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#include "pci_regs.h" // PCI_COMMAND
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#include "ioport.h" // PORT_ATA1_CMD_BASE
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#include "config.h" // CONFIG_*
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#include "xen.h" // usingXen
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#include "memmap.h" // add_e820
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#include "paravirt.h" // RamSize
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#include "dev-q35.h" // Q35_HOST_BRIDGE_PCIEXBAR_ADDR
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#include "list.h" // struct hlist_node
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/* PM Timer ticks per second (HZ) */
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#define PM_TIMER_FREQUENCY 3579545
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/* acpi enable, SCI: IRQ9 000b = irq9*/
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pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN);
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pmtimer_init(PORT_ACPI_PM_BASE + 0x08, PM_TIMER_FREQUENCY / 1000);
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pmtimer_setup(PORT_ACPI_PM_BASE + 0x08, PM_TIMER_FREQUENCY / 1000);
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static void storage_ide_init(struct pci_device *pci, void *arg)
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static void storage_ide_setup(struct pci_device *pci, void *arg)
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/* IDE: we map it as in ISA mode */
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pci_set_io_region_addr(pci, 0, PORT_ATA1_CMD_BASE, 0);
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/* PIIX3/PIIX4 IDE */
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static void piix_ide_init(struct pci_device *pci, void *arg)
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static void piix_ide_setup(struct pci_device *pci, void *arg)
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u16 bdf = pci->bdf;
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pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
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pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
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static void pic_ibm_init(struct pci_device *pci, void *arg)
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static void pic_ibm_setup(struct pci_device *pci, void *arg)
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/* PIC, IBM, MPIC & MPIC2 */
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pci_set_io_region_addr(pci, 0, 0x80800000 + 0x00040000, 0);
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static void apple_macio_init(struct pci_device *pci, void *arg)
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static void apple_macio_setup(struct pci_device *pci, void *arg)
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/* macio bridge */
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pci_set_io_region_addr(pci, 0, 0x80800000, 0);
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/* PIIX4 Power Management device (for ACPI) */
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static void piix4_pm_init(struct pci_device *pci, void *arg)
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static void piix4_pm_setup(struct pci_device *pci, void *arg)
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u16 bdf = pci->bdf;
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// acpi sci is hardwired to 9
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pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
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pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
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pmtimer_init(PORT_ACPI_PM_BASE + 0x08, PM_TIMER_FREQUENCY / 1000);
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pmtimer_setup(PORT_ACPI_PM_BASE + 0x08, PM_TIMER_FREQUENCY / 1000);
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/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_SMBUS */
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void ich9_smbus_init(struct pci_device *dev, void *arg)
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void ich9_smbus_setup(struct pci_device *dev, void *arg)
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u16 bdf = dev->bdf;
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/* map smbus into io space */
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static const struct pci_device_id pci_device_tbl[] = {
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/* PIIX3/PIIX4 PCI to ISA bridge */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
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piix_isa_bridge_init),
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piix_isa_bridge_setup),
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
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piix_isa_bridge_init),
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piix_isa_bridge_setup),
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC,
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mch_isa_bridge_init),
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mch_isa_bridge_setup),
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/* STORAGE IDE */
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PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
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PCI_CLASS_STORAGE_IDE, piix_ide_init),
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PCI_CLASS_STORAGE_IDE, piix_ide_setup),
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PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
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PCI_CLASS_STORAGE_IDE, piix_ide_init),
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PCI_CLASS_STORAGE_IDE, piix_ide_setup),
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PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
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/* PIC, IBM, MIPC & MPIC2 */
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PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
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PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
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/* PIIX4 Power Management device (for ACPI) */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_SMBUS,
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PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
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PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init),
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PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_setup),
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PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_setup),
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static void pci_enable_default_vga(void)
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struct pci_device *pci;
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if (is_pci_vga(pci)) {
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dprintf(1, "PCI: Using %02x:%02x.%x for primary VGA\n",
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pci_bdf_to_bus(pci->bdf), pci_bdf_to_dev(pci->bdf),
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pci_bdf_to_fn(pci->bdf));
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pci = pci_find_class(PCI_CLASS_DISPLAY_VGA);
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dprintf(1, "PCI: No VGA devices found\n");
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dprintf(1, "PCI: Enabling %02x:%02x.%x for primary VGA\n",
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pci_bdf_to_bus(pci->bdf), pci_bdf_to_dev(pci->bdf),
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pci_bdf_to_fn(pci->bdf));
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pci_config_maskw(pci->bdf, PCI_COMMAND, 0,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
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while (pci->parent) {
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dprintf(1, "PCI: Setting VGA enable on bridge %02x:%02x.%x\n",
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pci_bdf_to_bus(pci->bdf), pci_bdf_to_dev(pci->bdf),
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pci_bdf_to_fn(pci->bdf));
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pci_config_maskw(pci->bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_VGA);
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pci_config_maskw(pci->bdf, PCI_COMMAND, 0,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
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/****************************************************************
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* Platform device initialization
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****************************************************************/
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void i440fx_mem_addr_init(struct pci_device *dev, void *arg)
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void i440fx_mem_addr_setup(struct pci_device *dev, void *arg)
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if (RamSize <= 0x80000000)
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pcimem_start = 0x80000000;
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pci_slot_get_irq = piix_pci_slot_get_irq;
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void mch_mem_addr_init(struct pci_device *dev, void *arg)
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void mch_mem_addr_setup(struct pci_device *dev, void *arg)
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u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
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u32 size = Q35_HOST_BRIDGE_PCIEXBAR_SIZE;
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if ((pmem & PCI_PREF_RANGE_TYPE_MASK) != PCI_PREF_RANGE_TYPE_64)
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struct pci_region_entry *entry = r->list;
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struct pci_region_entry *entry;
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hlist_for_each_entry(entry, &r->list, node) {
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if (!entry->is64)
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static u64 pci_region_align(struct pci_region *r)
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// The first entry in the sorted list has the largest alignment
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return r->list->align;
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struct pci_region_entry *entry;
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hlist_for_each_entry(entry, &r->list, node) {
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// The first entry in the sorted list has the largest alignment
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static u64 pci_region_sum(struct pci_region *r)
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struct pci_region_entry *entry = r->list;
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struct pci_region_entry *entry;
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hlist_for_each_entry(entry, &r->list, node) {
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sum += entry->size;
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static void pci_region_migrate_64bit_entries(struct pci_region *from,
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struct pci_region *to)
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struct pci_region_entry **pprev = &from->list, **last = &to->list;
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struct pci_region_entry *entry = *pprev;
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pprev = &entry->next;
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struct hlist_node *n, **last = &to->list.first;
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struct pci_region_entry *entry;
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hlist_for_each_entry_safe(entry, n, &from->list, node) {
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// Move from source list to destination list.
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*pprev = entry->next;
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hlist_del(&entry->node);
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hlist_add(&entry->node, last);
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entry->is64 = is64;
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entry->type = type;
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// Insert into list in sorted order.
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struct pci_region_entry **pprev;
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for (pprev = &bus->r[type].list; *pprev; pprev = &(*pprev)->next) {
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struct pci_region_entry *pos = *pprev;
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struct hlist_node **pprev;
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struct pci_region_entry *pos;
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hlist_for_each_entry_pprev(pos, pprev, &bus->r[type].list, node) {
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if (pos->align < align || (pos->align == align && pos->size < size))
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entry->next = *pprev;
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hlist_add(&entry->node, pprev);
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static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r)
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struct pci_region_entry *entry = r->list;
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struct hlist_node *n;
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struct pci_region_entry *entry;
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hlist_for_each_entry_safe(entry, n, &r->list, node) {
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u64 addr = r->base;
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r->base += entry->size;
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if (entry->bar == -1)
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// Update bus base address if entry is a bridge region
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busses[entry->dev->secondary_bus].r[entry->type].base = addr;
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pci_region_map_one_entry(entry, addr);
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struct pci_region_entry *next = entry->next;
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hlist_del(&entry->node);
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if (pci_bios_init_root_regions(busses)) {
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struct pci_region r64_mem, r64_pref;
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r64_pref.list = NULL;
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r64_mem.list.first = NULL;
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r64_pref.list.first = NULL;
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pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_MEM],
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pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_PREFMEM],