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test_regress/t/t_wire_types.pl

 

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#!/usr/bin/perl

 

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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }

 

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# DESCRIPTION: Verilator: Verilog Test driver/expect definition

 

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#

 

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# Copyright 2003 by Wilson Snyder. This program is free software; you can

 

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# redistribute it and/or modify it under the terms of either the GNU

 

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# Lesser General Public License Version 3 or the Perl Artistic License

 

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# Version 2.0.

 

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$Self->{verilated_randReset} = 1;  # allow checking if we initialize vars to zero only when needed

 

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compile (

 

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         );

 

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execute (

 

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         check_finished=>1,

 

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     );

 

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ok(1);

 

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1;

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