~ubuntu-branches/ubuntu/trusty/binutils-msp430/trusty : revision 6

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diff --git a/bfd/archures.c b/bfd/archures.c

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index cd8500f..94f951a 100644

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--- a/bfd/archures.c

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+++ b/bfd/archures.c

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@@ -408,21 +408,8 @@ DESCRIPTION

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. bfd_arch_xstormy16,

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.#define bfd_mach_xstormy16 1

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. bfd_arch_msp430, {* Texas Instruments MSP430 architecture. *}

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-.#define bfd_mach_msp11 11

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-.#define bfd_mach_msp110 110

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-.#define bfd_mach_msp12 12

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-.#define bfd_mach_msp13 13

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-.#define bfd_mach_msp14 14

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-.#define bfd_mach_msp15 15

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-.#define bfd_mach_msp16 16

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-.#define bfd_mach_msp21 21

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-.#define bfd_mach_msp31 31

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-.#define bfd_mach_msp32 32

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-.#define bfd_mach_msp33 33

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-.#define bfd_mach_msp41 41

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-.#define bfd_mach_msp42 42

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-.#define bfd_mach_msp43 43

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-.#define bfd_mach_msp44 44

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+.#define bfd_mach_msp430 430

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+.#define bfd_mach_msp430x 431

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. bfd_arch_xc16x, {* Infineon's XC16X Series. *}

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.#define bfd_mach_xc16x 1

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.#define bfd_mach_xc16xl 2

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diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h

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index 2c795b6..e21ef7b 100644

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--- a/bfd/bfd-in2.h

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+++ b/bfd/bfd-in2.h

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@@ -2095,21 +2095,8 @@ enum bfd_architecture

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bfd_arch_xstormy16,

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#define bfd_mach_xstormy16 1

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bfd_arch_msp430, /* Texas Instruments MSP430 architecture. */

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-#define bfd_mach_msp11 11

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-#define bfd_mach_msp110 110

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-#define bfd_mach_msp12 12

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-#define bfd_mach_msp13 13

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-#define bfd_mach_msp14 14

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-#define bfd_mach_msp15 15

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-#define bfd_mach_msp16 16

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-#define bfd_mach_msp21 21

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-#define bfd_mach_msp31 31

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-#define bfd_mach_msp32 32

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-#define bfd_mach_msp33 33

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-#define bfd_mach_msp41 41

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-#define bfd_mach_msp42 42

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-#define bfd_mach_msp43 43

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-#define bfd_mach_msp44 44

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+#define bfd_mach_msp430 430

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+#define bfd_mach_msp430x 431

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bfd_arch_xc16x, /* Infineon's XC16X Series. */

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#define bfd_mach_xc16x 1

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#define bfd_mach_xc16xl 2

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@@ -4587,6 +4574,25 @@ This is the 5 bits of a value. */

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BFD_RELOC_MSP430_16_BYTE,

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BFD_RELOC_MSP430_2X_PCREL,

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BFD_RELOC_MSP430_RL_PCREL,

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+ BFD_RELOC_MSP430X_SRC_BYTE,

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+ BFD_RELOC_MSP430X_SRC,

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+ BFD_RELOC_MSP430X_DST_BYTE,

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+ BFD_RELOC_MSP430X_DST,

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+ BFD_RELOC_MSP430X_DST_2ND_BYTE,

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+ BFD_RELOC_MSP430X_DST_2ND,

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+ BFD_RELOC_MSP430X_PCREL_SRC_BYTE,

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+ BFD_RELOC_MSP430X_PCREL_SRC,

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+ BFD_RELOC_MSP430X_PCREL_DST_BYTE,

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+ BFD_RELOC_MSP430X_PCREL_DST,

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+ BFD_RELOC_MSP430X_PCREL_DST_2ND,

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+ BFD_RELOC_MSP430X_PCREL_DST_2ND_BYTE,

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+ BFD_RELOC_MSP430X_S_BYTE,

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+ BFD_RELOC_MSP430X_S,

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+ BFD_RELOC_MSP430X_D_BYTE,

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+ BFD_RELOC_MSP430X_D,

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+ BFD_RELOC_MSP430X_PCREL_D,

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+ BFD_RELOC_MSP430X_INDXD,

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+ BFD_RELOC_MSP430X_PCREL_INDXD,

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/* IQ2000 Relocations. */

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BFD_RELOC_IQ2000_OFFSET_16,

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diff --git a/bfd/cpu-msp430.c b/bfd/cpu-msp430.c

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index 63c301a..9e9fcdd 100644

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--- a/bfd/cpu-msp430.c

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+++ b/bfd/cpu-msp430.c

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@@ -23,86 +23,14 @@

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#include "bfd.h"

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#include "libbfd.h"

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-static const bfd_arch_info_type *compatible

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- PARAMS ((const bfd_arch_info_type *, const bfd_arch_info_type *));

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-

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-#define N(addr_bits, machine, print, default, next) \

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-{ \

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- 16, /* 16 bits in a word. */ \

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- addr_bits, /* Bits in an address. */ \

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- 8, /* 8 bits in a byte. */ \

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- bfd_arch_msp430, \

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- machine, /* Machine number. */ \

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- "msp430", /* Architecture name. */ \

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- print, /* Printable name. */ \

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- 1, /* Section align power. */ \

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- default, /* The default machine. */ \

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- compatible, \

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- bfd_default_scan, \

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- next \

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-}

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-

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-static const bfd_arch_info_type arch_info_struct[] =

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-{

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- /* msp430x11x. */

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- N (16, bfd_mach_msp11, "msp:11", FALSE, & arch_info_struct[1]),

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-

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- /* msp430x11x1. */

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- N (16, bfd_mach_msp110, "msp:110", FALSE, & arch_info_struct[2]),

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-

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- /* msp430x12x. */

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- N (16, bfd_mach_msp12, "msp:12", FALSE, & arch_info_struct[3]),

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-

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- /* msp430x13x. */

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- N (16, bfd_mach_msp13, "msp:13", FALSE, & arch_info_struct[4]),

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-

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- /* msp430x14x. */

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- N (16, bfd_mach_msp14, "msp:14", FALSE, & arch_info_struct[5]),

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-

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- /* msp430x15x. */

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- N (16, bfd_mach_msp15, "msp:15", FALSE, & arch_info_struct[6]),

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-

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- /* msp430x16x. */

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- N (16, bfd_mach_msp16, "msp:16", FALSE, & arch_info_struct[7]),

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-

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- /* msp430x21x. */

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- N (16, bfd_mach_msp21, "msp:21", FALSE, & arch_info_struct[8]),

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-

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- /* msp430x31x. */

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- N (16, bfd_mach_msp31, "msp:31", FALSE, & arch_info_struct[9]),

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-

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- /* msp430x32x. */

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- N (16, bfd_mach_msp32, "msp:32", FALSE, & arch_info_struct[10]),

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-

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- /* msp430x33x. */

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- N (16, bfd_mach_msp33, "msp:33", FALSE, & arch_info_struct[11]),

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-

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- /* msp430x41x. */

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- N (16, bfd_mach_msp41, "msp:41", FALSE, & arch_info_struct[12]),

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-

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- /* msp430x42x. */

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- N (16, bfd_mach_msp42, "msp:42", FALSE, & arch_info_struct[13]),

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-

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- /* msp430x43x. */

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- N (16, bfd_mach_msp43, "msp:43", FALSE, & arch_info_struct[14]),

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-

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- /* msp430x44x. */

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- N (16, bfd_mach_msp43, "msp:44", FALSE, NULL)

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-};

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-

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-const bfd_arch_info_type bfd_msp430_arch =

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- N (16, bfd_mach_msp14, "msp:14", TRUE, & arch_info_struct[0]);

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-

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/* This routine is provided two arch_infos and works out which MSP

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machine which would be compatible with both and returns a pointer

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- to its info structure. */

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-

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+ to its info structure. */

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static const bfd_arch_info_type *

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-compatible (a,b)

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- const bfd_arch_info_type * a;

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- const bfd_arch_info_type * b;

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+compatible (const bfd_arch_info_type *a,

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+ const bfd_arch_info_type *b)

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{

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- /* If a & b are for different architectures we can do nothing. */

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+ /* If a & b are for different architectures we can do nothing */

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if (a->arch != b->arch)

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return NULL;

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@@ -111,3 +39,35 @@ compatible (a,b)

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return a;

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}

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+

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+/* Architecture for MSP430X and MSP430XV2 */

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+static const bfd_arch_info_type bfd_msp430x_arch = {

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+ 16, /* 16 bits in a word */

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+ 20, /* 20 bits in an address */

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+ 8, /* 8 bits in a byte */

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+ bfd_arch_msp430,

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+ bfd_mach_msp430x, /* Machine number */

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+ "msp430", /* Architecture name. */

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+ "msp430:430X", /* Printable name */

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+ 1, /* Section align power */

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+ FALSE, /* The default machine */

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+ compatible,

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+ bfd_default_scan,

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+ 0

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+};

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+

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+/* Architecture for MSP430 */

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+const bfd_arch_info_type bfd_msp430_arch = {

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+ 16, /* 16 bits in a word */

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+ 16, /* 16 bits in an address */

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+ 8, /* 8 bits in a byte */

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+ bfd_arch_msp430,

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+ bfd_mach_msp430, /* Machine number */

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+ "msp430", /* Architecture name */

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+ "msp430:430", /* Printable name */

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+ 1, /* Section align power */

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+ TRUE, /* The default machine */

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+ compatible,

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+ bfd_default_scan,

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+ &bfd_msp430x_arch

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+};

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diff --git a/bfd/elf32-msp430.c b/bfd/elf32-msp430.c

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index 9a5fb2a..a2fc8c1 100644

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--- a/bfd/elf32-msp430.c

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+++ b/bfd/elf32-msp430.c

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@@ -90,7 +90,7 @@ static reloc_howto_type elf_msp430_howto_table[] =

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0xffff, /* dst_mask */

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FALSE), /* pcrel_offset */

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- /* A 16 bit absolute relocation for command address. */

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+ /* A 16 bit PC relative relocation for command address. */

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HOWTO (R_MSP430_16_PCREL, /* type */

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1, /* rightshift */

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1, /* size (0 = byte, 1 = short, 2 = long) */

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@@ -120,7 +120,7 @@ static reloc_howto_type elf_msp430_howto_table[] =

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0xffff, /* dst_mask */

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FALSE), /* pcrel_offset */

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- /* A 16 bit absolute relocation for command address. */

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+ /* A 16 bit PC relative relocation, byte operations. */

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HOWTO (R_MSP430_16_PCREL_BYTE,/* type */

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1, /* rightshift */

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1, /* size (0 = byte, 1 = short, 2 = long) */

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@@ -163,7 +163,292 @@ static reloc_howto_type elf_msp430_howto_table[] =

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FALSE, /* partial_inplace */

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0, /* src_mask */

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0xffff, /* dst_mask */

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- TRUE) /* pcrel_offset */

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+ TRUE), /* pcrel_offset */

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+

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+ /* A 20 bit msp430x absolute src operand relocation, byte operations */

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+ HOWTO (R_MSP430X_SRC_BYTE, /* type */

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+ 0, /* rightshift */

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+ 2, /* size (0 = byte, 1 = short, 2 = long) */

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+ 20, /* bitsize */

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+ FALSE, /* pc_relative */

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+ 0, /* bitpos */

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+ complain_overflow_dont,/* complain_on_overflow */

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+ bfd_elf_generic_reloc, /* special_function */

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+ "R_MSP430X_SRC_BYTE", /* name */

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+ FALSE, /* partial_inplace */

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+ 0xfffff, /* src_mask */

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+ 0, /* dst_mask */

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+ FALSE), /* pcrel_offset */

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+

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+ /* A 20 bit msp430x absolute src operand relocation */

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+ HOWTO (R_MSP430X_SRC, /* type */

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+ 0, /* rightshift */

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+ 2, /* size (0 = byte, 1 = short, 2 = long) */

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+ 20, /* bitsize */

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+ FALSE, /* pc_relative */

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+ 0, /* bitpos */

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+ complain_overflow_dont,/* complain_on_overflow */

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+ bfd_elf_generic_reloc, /* special_function */

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+ "R_MSP430X_SRC", /* name */

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+ FALSE, /* partial_inplace */

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+ 0xfffff, /* src_mask */

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+ 0, /* dst_mask */

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+ FALSE), /* pcrel_offset */

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+

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+ /* A 20 bit msp430x absolute dst operand relocation, src is register mode, byte operations */

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+ HOWTO (R_MSP430X_DST_BYTE, /* type */

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+ 0, /* rightshift */

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+ 2, /* size (0 = byte, 1 = short, 2 = long) */

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+ 20, /* bitsize */

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+ FALSE, /* pc_relative */

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+ 0, /* bitpos */

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+ complain_overflow_dont,/* complain_on_overflow */

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+ bfd_elf_generic_reloc, /* special_function */

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+ "R_MSP430X_DST_BYTE", /* name */

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+ FALSE, /* partial_inplace */

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+ 0, /* src_mask */

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+ 0xfffff, /* dst_mask */

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+ FALSE), /* pcrel_offset */

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+

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+ /* A 20 bit msp430x absolute dst operand relocation, src is register mode */

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+ HOWTO (R_MSP430X_DST, /* type */

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+ 0, /* rightshift */

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+ 2, /* size (0 = byte, 1 = short, 2 = long) */

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+ 20, /* bitsize */

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+ FALSE, /* pc_relative */

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+ 0, /* bitpos */

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+ complain_overflow_dont,/* complain_on_overflow */

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+ bfd_elf_generic_reloc, /* special_function */

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+ "R_MSP430X_DST", /* name */

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+ FALSE, /* partial_inplace */

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+ 0, /* src_mask */

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+ 0xfffff, /* dst_mask */

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+ FALSE), /* pcrel_offset */

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+

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+ /* A 20 bit msp430x absolute dst operand relocation, byte operations */

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+ HOWTO (R_MSP430X_DST_2ND_BYTE, /* type */

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+ 0, /* rightshift */

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+ 2, /* size (0 = byte, 1 = short, 2 = long) */

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+ 20, /* bitsize */

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+ FALSE, /* pc_relative */

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+ 0, /* bitpos */

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+ complain_overflow_dont,/* complain_on_overflow */

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+ bfd_elf_generic_reloc, /* special_function */

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+ "R_MSP430X_DST_2ND_BYTE", /* name */

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+ FALSE, /* partial_inplace */

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+ 0, /* src_mask */

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+ 0xfffff, /* dst_mask */

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+ FALSE), /* pcrel_offset */

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+

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+ /* A 20 bit msp430x absolute dst operand relocation */

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+ HOWTO (R_MSP430X_DST_2ND, /* type */

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+ 0, /* rightshift */

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+ 2, /* size (0 = byte, 1 = short, 2 = long) */

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+ 20, /* bitsize */

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+ FALSE, /* pc_relative */

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+ 0, /* bitpos */

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+ complain_overflow_dont,/* complain_on_overflow */

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+ bfd_elf_generic_reloc, /* special_function */

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+ "R_MSP430X_DST_2ND", /* name */

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+ FALSE, /* partial_inplace */

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+ 0, /* src_mask */

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+ 0xfffff, /* dst_mask */

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+ FALSE), /* pcrel_offset */

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+

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+ /* A 20 bit msp430x PC relative src operand relocation, byte operations */

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+ HOWTO (R_MSP430X_PCREL_SRC_BYTE, /* type */

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+ 0, /* rightshift */

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+ 2, /* size (0 = byte, 1 = short, 2 = long) */

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+ 20, /* bitsize */

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+ TRUE, /* pc_relative */

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+ 0, /* bitpos */

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+ complain_overflow_dont,/* complain_on_overflow */

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+ bfd_elf_generic_reloc, /* special_function */

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+ "R_MSP430X_PCREL_SRC_BYTE", /* name */

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+ FALSE, /* partial_inplace */

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+ 0xfffff, /* src_mask */

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+ 0, /* dst_mask */

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+ TRUE), /* pcrel_offset */

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+

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+ /* A 20 bit msp430x PC relative src operand relocation */

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+ HOWTO (R_MSP430X_PCREL_SRC, /* type */

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+ 0, /* rightshift */

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+ 2, /* size (0 = byte, 1 = short, 2 = long) */

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+ 20, /* bitsize */

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+ TRUE, /* pc_relative */

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+ 0, /* bitpos */

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+ complain_overflow_dont,/* complain_on_overflow */

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+ bfd_elf_generic_reloc, /* special_function */

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+ "R_MSP430X_PCREL_SRC", /* name */

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+ FALSE, /* partial_inplace */

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+ 0xfffff, /* src_mask */

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+ 0, /* dst_mask */

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+ TRUE), /* pcrel_offset */

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+

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+ /* A 20 bit msp430x PC relative dst operand relocation, src is register mode, byte operations */

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+ HOWTO (R_MSP430X_PCREL_DST_BYTE, /* type */

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+ 0, /* rightshift */

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+ 2, /* size (0 = byte, 1 = short, 2 = long) */

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+ 20, /* bitsize */

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+ TRUE, /* pc_relative */

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+ 0, /* bitpos */

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+ complain_overflow_dont,/* complain_on_overflow */

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+ bfd_elf_generic_reloc, /* special_function */

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+ "R_MSP430X_PCREL_DST_BYTE", /* name */

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+ FALSE, /* partial_inplace */

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+ 0, /* src_mask */

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+ 0xfffff, /* dst_mask */

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+ TRUE), /* pcrel_offset */

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+

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+ /* A 20 bit msp430x PC relative dst operand relocation, src is register mode */

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+ HOWTO (R_MSP430X_PCREL_DST, /* type */

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+ 0, /* rightshift */

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+ 2, /* size (0 = byte, 1 = short, 2 = long) */

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+ 20, /* bitsize */

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+ TRUE, /* pc_relative */

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+ 0, /* bitpos */

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+ complain_overflow_dont,/* complain_on_overflow */

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+ bfd_elf_generic_reloc, /* special_function */

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+ "R_MSP430X_PCREL_DST", /* name */

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+ FALSE, /* partial_inplace */

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+ 0, /* src_mask */

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+ 0xfffff, /* dst_mask */

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+ TRUE), /* pcrel_offset */

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+

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+ /* A 20 bit msp430x PC relative dst operand relocation, byte operations */

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+ HOWTO (R_MSP430X_PCREL_DST_2ND_BYTE, /* type */

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+ 0, /* rightshift */

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+ 2, /* size (0 = byte, 1 = short, 2 = long) */

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+ 20, /* bitsize */

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+ TRUE, /* pc_relative */

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+ 0, /* bitpos */

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+ complain_overflow_dont,/* complain_on_overflow */

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+ bfd_elf_generic_reloc, /* special_function */

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+ "R_MSP430X_PCREL_DST_2ND_BYTE", /* name */

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+ FALSE, /* partial_inplace */

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+ 0, /* src_mask */

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+ 0xfffff, /* dst_mask */

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+ TRUE), /* pcrel_offset */

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+

408

+ /* A 20 bit msp430x PC relative dst operand relocation */

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+ HOWTO (R_MSP430X_PCREL_DST_2ND, /* type */

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+ 0, /* rightshift */

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+ 2, /* size (0 = byte, 1 = short, 2 = long) */

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+ 20, /* bitsize */

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+ TRUE, /* pc_relative */

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+ 0, /* bitpos */

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+ complain_overflow_dont,/* complain_on_overflow */

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+ bfd_elf_generic_reloc, /* special_function */

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+ "R_MSP430X_PCREL_DST_2ND", /* name */

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+ FALSE, /* partial_inplace */

419

+ 0, /* src_mask */

420

+ 0xfffff, /* dst_mask */

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+ TRUE), /* pcrel_offset */

422

+

423

+ /* A 20 bit msp430x address instructions immediate src operand relocation */

424

+ HOWTO (R_MSP430X_S_BYTE, /* type */

425

+ 0, /* rightshift */

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+ 2, /* size (0 = byte, 1 = short, 2 = long) */

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+ 20, /* bitsize */

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+ FALSE, /* pc_relative */

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+ 0, /* bitpos */

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+ complain_overflow_dont,/* complain_on_overflow */

431

+ bfd_elf_generic_reloc, /* special_function */

432

+ "R_MSP430X_S_BYTE", /* name */

433

+ FALSE, /* partial_inplace */

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+ 0xfffff, /* src_mask */

435

+ 0, /* dst_mask */

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+ FALSE), /* pcrel_offset */

437

+

438

+ /* A 20 bit msp430x address instructions absolute src operand relocation */

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+ HOWTO (R_MSP430X_S, /* type */

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+ 0, /* rightshift */

441

+ 2, /* size (0 = byte, 1 = short, 2 = long) */

442

+ 20, /* bitsize */

443

+ FALSE, /* pc_relative */

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+ 0, /* bitpos */

445

+ complain_overflow_dont,/* complain_on_overflow */

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+ bfd_elf_generic_reloc, /* special_function */

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+ "R_MSP430X_S", /* name */

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+ FALSE, /* partial_inplace */

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+ 0xfffff, /* src_mask */

450

+ 0, /* dst_mask */

451

+ FALSE), /* pcrel_offset */

452

+

453

+ /* A 20 bit msp430x address instructions immediate dst operand relocation */

454

+ HOWTO (R_MSP430X_D_BYTE, /* type */

455

+ 0, /* rightshift */

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+ 2, /* size (0 = byte, 1 = short, 2 = long) */

457

+ 20, /* bitsize */

458

+ FALSE, /* pc_relative */

459

+ 0, /* bitpos */

460

+ complain_overflow_dont,/* complain_on_overflow */

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+ bfd_elf_generic_reloc, /* special_function */

462

+ "R_MSP430X_D_BYTE", /* name */

463

+ FALSE, /* partial_inplace */

464

+ 0, /* src_mask */

465

+ 0xfffff, /* dst_mask */

466

+ FALSE), /* pcrel_offset */

467

+

468

+ /* A 20 bit msp430x address instructions absolute dst operand relocation */

469

+ HOWTO (R_MSP430X_D, /* type */

470

+ 0, /* rightshift */

471

+ 2, /* size (0 = byte, 1 = short, 2 = long) */

472

+ 20, /* bitsize */

473

+ FALSE, /* pc_relative */

474

+ 0, /* bitpos */

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+ complain_overflow_dont,/* complain_on_overflow */

476

+ bfd_elf_generic_reloc, /* special_function */

477

+ "R_MSP430X_D", /* name */

478

+ FALSE, /* partial_inplace */

479

+ 0, /* src_mask */

480

+ 0xfffff, /* dst_mask */

481

+ FALSE), /* pcrel_offset */

482

+

483

+ /* A 20 bit msp430x address instructions absolute dst operand relocation */

484

+ HOWTO (R_MSP430X_PCREL_D, /* type */

485

+ 0, /* rightshift */

486

+ 2, /* size (0 = byte, 1 = short, 2 = long) */

487

+ 20, /* bitsize */

488

+ TRUE, /* pc_relative */

489

+ 0, /* bitpos */

490

+ complain_overflow_dont,/* complain_on_overflow */

491

+ bfd_elf_generic_reloc, /* special_function */

492

+ "R_MSP430X_PCREL_D", /* name */

493

+ FALSE, /* partial_inplace */

494

+ 0, /* src_mask */

495

+ 0xfffff, /* dst_mask */

496

+ TRUE), /* pcrel_offset */

497

+

498

+ /* A 16 bit msp430x relocation *** for msp430x calla 16-bit PC-relative index ***/

499

+ HOWTO (R_MSP430X_PCREL_INDXD, /* type */

500

+ 0, /* rightshift */

501

+ 1, /* size (0 = byte, 1 = short, 2 = long) */

502

+ 16, /* bitsize */

503

+ TRUE, /* pc_relative */

504

+ 0, /* bitpos */

505

+ complain_overflow_dont,/* complain_on_overflow */

506

+ bfd_elf_generic_reloc, /* special_function */

507

+ "R_MSP430X_PCREL_INDXD", /* name */

508

+ FALSE, /* partial_inplace */

509

+ 0xffff, /* src_mask */

510

+ 0xffff, /* dst_mask */

511

+ TRUE), /* pcrel_offset */

512

+

513

+ /* A 16 bit msp430x relocation *** for msp430x bra/calla 16-bit index ***/

514

+ HOWTO (R_MSP430X_INDXD, /* type */

515

+ 0, /* rightshift */

516

+ 1, /* size (0 = byte, 1 = short, 2 = long) */

517

+ 16, /* bitsize */

518

+ FALSE, /* pc_relative */

519

+ 0, /* bitpos */

520

+ complain_overflow_dont,/* complain_on_overflow */

521

+ bfd_elf_generic_reloc, /* special_function */

522

+ "R_MSP430X_INDXD", /* name */

523

+ FALSE, /* partial_inplace */

524

+ 0xffff, /* src_mask */

525

+ 0xffff, /* dst_mask */

526

+ FALSE), /* pcrel_offset */

527

};

528

529

/* Map BFD reloc types to MSP430 ELF reloc types. */

530

@@ -185,7 +470,29 @@ static const struct msp430_reloc_map msp430_reloc_map[] =

531

{BFD_RELOC_MSP430_16_PCREL_BYTE, R_MSP430_16_PCREL_BYTE},

532

{BFD_RELOC_MSP430_16_BYTE, R_MSP430_16_BYTE},

533

{BFD_RELOC_MSP430_2X_PCREL, R_MSP430_2X_PCREL},

534

- {BFD_RELOC_MSP430_RL_PCREL, R_MSP430_RL_PCREL}

535

+ {BFD_RELOC_MSP430_RL_PCREL, R_MSP430_RL_PCREL},

536

+

537

+ {BFD_RELOC_MSP430X_SRC_BYTE, R_MSP430X_SRC_BYTE},

538

+ {BFD_RELOC_MSP430X_SRC, R_MSP430X_SRC},

539

+ {BFD_RELOC_MSP430X_DST_BYTE, R_MSP430X_DST_BYTE},

540

+ {BFD_RELOC_MSP430X_DST, R_MSP430X_DST},

541

+ {BFD_RELOC_MSP430X_DST_2ND_BYTE, R_MSP430X_DST_2ND_BYTE},

542

+ {BFD_RELOC_MSP430X_DST_2ND, R_MSP430X_DST_2ND},

543

+

544

+ {BFD_RELOC_MSP430X_PCREL_SRC_BYTE, R_MSP430X_PCREL_SRC_BYTE},

545

+ {BFD_RELOC_MSP430X_PCREL_SRC, R_MSP430X_PCREL_SRC},

546

+ {BFD_RELOC_MSP430X_PCREL_DST_BYTE, R_MSP430X_PCREL_DST_BYTE},

547

+ {BFD_RELOC_MSP430X_PCREL_DST, R_MSP430X_PCREL_DST},

548

+ {BFD_RELOC_MSP430X_PCREL_DST_2ND_BYTE, R_MSP430X_PCREL_DST_2ND_BYTE},

549

+ {BFD_RELOC_MSP430X_PCREL_DST_2ND, R_MSP430X_PCREL_DST_2ND},

550

+

551

+ {BFD_RELOC_MSP430X_S_BYTE, R_MSP430X_S_BYTE},

552

+ {BFD_RELOC_MSP430X_S, R_MSP430X_S},

553

+ {BFD_RELOC_MSP430X_D_BYTE, R_MSP430X_D_BYTE},

554

+ {BFD_RELOC_MSP430X_D, R_MSP430X_D},

555

+ {BFD_RELOC_MSP430X_PCREL_D, R_MSP430X_PCREL_D},

556

+ {BFD_RELOC_MSP430X_INDXD, R_MSP430X_INDXD},

557

+ {BFD_RELOC_MSP430X_PCREL_INDXD, R_MSP430X_PCREL_INDXD},

558

};

559

560

static reloc_howto_type *

561

@@ -207,10 +514,7 @@ bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,

562

{

563

unsigned int i;

564

565

- for (i = 0;

566

- i < (sizeof (elf_msp430_howto_table)

567

- / sizeof (elf_msp430_howto_table[0]));

568

- i++)

569

+ for (i = 0; i < ARRAY_SIZE (elf_msp430_howto_table); i++)

570

if (elf_msp430_howto_table[i].name != NULL

571

&& strcasecmp (elf_msp430_howto_table[i].name, r_name) == 0)

572

return &elf_msp430_howto_table[i];

573

@@ -282,18 +586,44 @@ msp430_final_link_relocate (reloc_howto_type * howto, bfd * input_bfd,

574

{

575

bfd_reloc_status_type r = bfd_reloc_ok;

576

bfd_vma x;

577

- bfd_signed_vma srel;

578

+ bfd_signed_vma srel = 0;

579

580

- switch (howto->type)

581

+ if (howto->type > R_MSP430_32 && howto->type < R_MSP430_max)

582

{

583

- case R_MSP430_10_PCREL:

584

contents += rel->r_offset;

585

srel = (bfd_signed_vma) relocation;

586

srel += rel->r_addend;

587

- srel -= rel->r_offset;

588

+

589

+ if(howto->pc_relative)

590

+ {

591

+ srel -= rel->r_offset;

592

+ srel -= (input_section->output_section->vma +

593

+ input_section->output_offset);

594

+ }

595

+

596

+ switch (howto->type)

597

+ {

598

+ case R_MSP430X_PCREL_D: // PC relative dst operand of calla

599

+ case R_MSP430X_PCREL_INDXD: // 16-bit idx in mova/bra instruction PC relative (symbolic) mode operand

600

+ srel -= 2; // operand located 2 bytes after opcode

601

+ break;

602

+ case R_MSP430X_PCREL_SRC: // PC-relative 20-bit address operand

603

+ case R_MSP430X_PCREL_SRC_BYTE:

604

+ case R_MSP430X_PCREL_DST:

605

+ case R_MSP430X_PCREL_DST_BYTE:

606

+ srel -= 4; // operand located 4 bytes after opcode

607

+ break;

608

+ case R_MSP430X_PCREL_DST_2ND:

609

+ case R_MSP430X_PCREL_DST_2ND_BYTE:

610

+ srel -= 6; // operand located 6 bytes after opcode

611

+ break;

612

+ }

613

+ }

614

+

615

+ switch (howto->type)

616

+ {

617

+ case R_MSP430_10_PCREL:

618

srel -= 2; /* Branch instructions add 2 to the PC... */

619

- srel -= (input_section->output_section->vma +

620

- input_section->output_offset);

621

622

if (srel & 1)

623

return bfd_reloc_outofrange;

624

@@ -311,13 +641,7 @@ msp430_final_link_relocate (reloc_howto_type * howto, bfd * input_bfd,

625

break;

626

627

case R_MSP430_2X_PCREL:

628

- contents += rel->r_offset;

629

- srel = (bfd_signed_vma) relocation;

630

- srel += rel->r_addend;

631

- srel -= rel->r_offset;

632

srel -= 2; /* Branch instructions add 2 to the PC... */

633

- srel -= (input_section->output_section->vma +

634

- input_section->output_offset);

635

636

if (srel & 1)

637

return bfd_reloc_outofrange;

638

@@ -341,13 +665,7 @@ msp430_final_link_relocate (reloc_howto_type * howto, bfd * input_bfd,

639

640

case R_MSP430_16_PCREL:

641

case R_MSP430_RL_PCREL:

642

- contents += rel->r_offset;

643

- srel = (bfd_signed_vma) relocation;

644

- srel += rel->r_addend;

645

- srel -= rel->r_offset;

646

/* Only branch instructions add 2 to the PC... */

647

- srel -= (input_section->output_section->vma +

648

- input_section->output_offset);

649

650

if (srel & 1)

651

return bfd_reloc_outofrange;

652

@@ -356,35 +674,138 @@ msp430_final_link_relocate (reloc_howto_type * howto, bfd * input_bfd,

653

break;

654

655

case R_MSP430_16_PCREL_BYTE:

656

- contents += rel->r_offset;

657

- srel = (bfd_signed_vma) relocation;

658

- srel += rel->r_addend;

659

- srel -= rel->r_offset;

660

/* Only branch instructions add 2 to the PC... */

661

- srel -= (input_section->output_section->vma +

662

- input_section->output_offset);

663

664

bfd_put_16 (input_bfd, srel & 0xffff, contents);

665

break;

666

667

case R_MSP430_16_BYTE:

668

- contents += rel->r_offset;

669

- srel = (bfd_signed_vma) relocation;

670

- srel += rel->r_addend;

671

bfd_put_16 (input_bfd, srel & 0xffff, contents);

672

break;

673

674

case R_MSP430_16:

675

- contents += rel->r_offset;

676

- srel = (bfd_signed_vma) relocation;

677

- srel += rel->r_addend;

678

-

679

if (srel & 1)

680

return bfd_reloc_notsupported;

681

682

bfd_put_16 (input_bfd, srel & 0xffff, contents);

683

break;

684

685

+ case R_MSP430X_SRC: // address operand

686

+ case R_MSP430X_PCREL_SRC: // PC-relative address operand

687

+

688

+ // 20 bit reloc for msp430x

689

+ // src in Non-register mode extended instructions,

690

+ // imm/abs in bra instruction

691

+

692

+ // src(19:16) located at positions 10:7 of extension word

693

+ // src(15:0) located just after opcode

694

+

695

+ if (srel & 1) // odd address

696

+ return bfd_reloc_notsupported;

697

+ /* and fall trough, no break here!!! */

698

+ case R_MSP430X_SRC_BYTE: // byte instructions or immediate operand

699

+ case R_MSP430X_PCREL_SRC_BYTE:

700

+ x = bfd_get_16 (input_bfd, contents);

701

+ /* 4 most-significant bits */

702

+ x = (x & 0xf87f) | ((srel >> 9) & 0x0780);

703

+ bfd_put_16 (input_bfd, x, contents);

704

+ /* 16 least-significant bits */

705

+ bfd_put_16 (input_bfd, srel & 0xffff, contents + 4);

706

+ break;

707

+

708

+ case R_MSP430X_DST: // address operand

709

+ case R_MSP430X_PCREL_DST:

710

+

711

+ // 20 bit reloc for msp430x

712

+ // dst in Non-register mode extended instructions,

713

+ // imm/abs/20-bit idx in calla instruction

714

+

715

+ // dst(19:16) located at positions 3:0 of extension word

716

+ // dst(15:0) located just after opcode

717

+

718

+ if (srel & 1) // odd address

719

+ return bfd_reloc_notsupported;

720

+ /* and fall trough, no break here!!! */

721

+ case R_MSP430X_DST_BYTE: // byte instructions or immediate operand

722

+ case R_MSP430X_PCREL_DST_BYTE:

723

+ x = bfd_get_16 (input_bfd, contents);

724

+ /* 4 most-significant bits */

725

+ x = (x & 0xfff0) | ((srel >> 16) & 0x000f);

726

+ bfd_put_16 (input_bfd, x, contents);

727

+ /* 16 least-significant bits */

728

+ bfd_put_16 (input_bfd, srel & 0xffff, contents + 4);

729

+ break;

730

+

731

+ case R_MSP430X_DST_2ND: // address operand

732

+ case R_MSP430X_PCREL_DST_2ND:

733

+

734

+ // 20 bit reloc for msp430x

735

+ // dst in Non-register mode extended instructions,

736

+

737

+ // dst(19:16) located at positions 3:0 of extension word

738

+ // dst(15:0) located after src(15:0)

739

+

740

+ if (srel & 1) // odd address

741

+ return bfd_reloc_notsupported;

742

+ /* and fall trough, no break here!!! */

743

+ case R_MSP430X_DST_2ND_BYTE: // byte instructions or immediate operand

744

+ case R_MSP430X_PCREL_DST_2ND_BYTE:

745

+ x = bfd_get_16 (input_bfd, contents);

746

+ /* 4 most-significant bits */

747

+ x = (x & 0xfff0) | ((srel >> 16) & 0x000f);

748

+ bfd_put_16 (input_bfd, x, contents);

749

+ /* 16 least-significant bits */

750

+ bfd_put_16 (input_bfd, srel & 0xffff, contents + 6);

751

+ break;

752

+

753

+ case R_MSP430X_S: // absolute src operand of address instructions

754

+ // 20 bit reloc for msp430x

755

+

756

+ // src(19:16) located at positions 11:8 of opcode

757

+ // src(15:0) located just after opcode

758

+

759

+ if (srel & 1) //odd address

760

+ return bfd_reloc_notsupported;

761

+ /* and fall trough, no break here!!! */

762

+ case R_MSP430X_S_BYTE: // immediate src operand of address instructions

763

+ x = bfd_get_16 (input_bfd, contents);

764

+ /* 4 most-significant bits */

765

+ x = (x & 0xf0ff) | ((srel >> 8) & 0x0f00);

766

+ bfd_put_16 (input_bfd, x, contents);

767

+ /* 16 least-significant bits */

768

+ bfd_put_16 (input_bfd, srel & 0xffff, contents + 2);

769

+ break;

770

+

771

+ case R_MSP430X_D: // absolute dst operand of address instructions

772

+ case R_MSP430X_PCREL_D: // PC relative dst operand of calla

773

+ // 20 bit reloc for msp430x,

774

+

775

+ // dst(19:16) located at positions 3:0 of opcode

776

+ // dst(15:0) located just after opcode

777

+

778

+ if (srel & 1) //odd address

779

+ return bfd_reloc_notsupported;

780

+ /* and fall trough, no break here!!! */

781

+ case R_MSP430X_D_BYTE: //immediate dst operand of address instructions

782

+

783

+ x = bfd_get_16 (input_bfd, contents);

784

+ /* 4 most-significant bits */

785

+ x = (x & 0xfff0) | ((srel >> 16) & 0x000f);

786

+ bfd_put_16 (input_bfd, x, contents);

787

+ /* 16 least-significant bits */

788

+ bfd_put_16 (input_bfd, srel & 0xffff, contents + 2);

789

+ break;

790

+

791

+ case R_MSP430X_PCREL_INDXD: // 16-bit idx in mova/bra instruction PC relative (symbolic) mode operand

792

+

793

+ if (srel & 1) //odd address

794

+ return bfd_reloc_notsupported;

795

+ case R_MSP430X_INDXD: // 16-bit idx in calla/mova/bra instruction

796

+

797

+ x = srel & 0xffff;

798

+ bfd_put_16 (input_bfd, x, contents + 2); //16 least-significant bits

799

+ break;

800

+

801

default:

802

r = _bfd_final_link_relocate (howto, input_bfd, input_section,

803

contents, rel->r_offset,

804

@@ -517,150 +938,54 @@ elf32_msp430_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED,

805

number. */

806

807

static void

808

-bfd_elf_msp430_final_write_processing (bfd * abfd,

809

- bfd_boolean linker ATTRIBUTE_UNUSED)

810

+msp430_elf_backend_final_write_processing (bfd * abfd,

811

+ bfd_boolean linker ATTRIBUTE_UNUSED)

812

{

813

- unsigned long val;

814

+ Elf_Internal_Ehdr * i_ehdrp;

815

+ unsigned long flags;

816

817

+ i_ehdrp = elf_elfheader (abfd);

818

+ i_ehdrp->e_machine = EM_MSP430;

819

+ flags = 0;

820

switch (bfd_get_mach (abfd))

821

{

822

default:

823

- case bfd_mach_msp110:

824

- val = E_MSP430_MACH_MSP430x11x1;

825

- break;

826

-

827

- case bfd_mach_msp11:

828

- val = E_MSP430_MACH_MSP430x11;

829

- break;

830

-

831

- case bfd_mach_msp12:

832

- val = E_MSP430_MACH_MSP430x12;

833

- break;

834

-

835

- case bfd_mach_msp13:

836

- val = E_MSP430_MACH_MSP430x13;

837

- break;

838

-

839

- case bfd_mach_msp14:

840

- val = E_MSP430_MACH_MSP430x14;

841

- break;

842

-

843

- case bfd_mach_msp15:

844

- val = E_MSP430_MACH_MSP430x15;

845

- break;

846

-

847

- case bfd_mach_msp16:

848

- val = E_MSP430_MACH_MSP430x16;

849

- break;

850

-

851

- case bfd_mach_msp31:

852

- val = E_MSP430_MACH_MSP430x31;

853

- break;

854

-

855

- case bfd_mach_msp32:

856

- val = E_MSP430_MACH_MSP430x32;

857

- break;

858

-

859

- case bfd_mach_msp33:

860

- val = E_MSP430_MACH_MSP430x33;

861

- break;

862

-

863

- case bfd_mach_msp41:

864

- val = E_MSP430_MACH_MSP430x41;

865

- break;

866

-

867

- case bfd_mach_msp42:

868

- val = E_MSP430_MACH_MSP430x42;

869

- break;

870

-

871

- case bfd_mach_msp43:

872

- val = E_MSP430_MACH_MSP430x43;

873

+ case bfd_mach_msp430:

874

+ flags = EF_MSP430_ARCH_430;

875

break;

876

-

877

- case bfd_mach_msp44:

878

- val = E_MSP430_MACH_MSP430x44;

879

+ case bfd_mach_msp430x:

880

+ flags = EF_MSP430_ARCH_430X;

881

break;

882

}

883

-

884

- elf_elfheader (abfd)->e_machine = EM_MSP430;

885

- elf_elfheader (abfd)->e_flags &= ~EF_MSP430_MACH;

886

- elf_elfheader (abfd)->e_flags |= val;

887

+ i_ehdrp->e_flags = EF_MSP430_UNIARCH | flags;

888

}

889

890

/* Set the right machine number. */

891

892

static bfd_boolean

893

-elf32_msp430_object_p (bfd * abfd)

894

+msp430_elf_backend_object_p (bfd * abfd ATTRIBUTE_UNUSED)

895

{

896

- int e_set = bfd_mach_msp14;

897

-

898

- if (elf_elfheader (abfd)->e_machine == EM_MSP430

899

- || elf_elfheader (abfd)->e_machine == EM_MSP430_OLD)

900

- {

901

- int e_mach = elf_elfheader (abfd)->e_flags & EF_MSP430_MACH;

902

-

903

- switch (e_mach)

904

- {

905

- default:

906

- case E_MSP430_MACH_MSP430x11:

907

- e_set = bfd_mach_msp11;

908

- break;

909

-

910

- case E_MSP430_MACH_MSP430x11x1:

911

- e_set = bfd_mach_msp110;

912

- break;

913

-

914

- case E_MSP430_MACH_MSP430x12:

915

- e_set = bfd_mach_msp12;

916

- break;

917

-

918

- case E_MSP430_MACH_MSP430x13:

919

- e_set = bfd_mach_msp13;

920

- break;

921

-

922

- case E_MSP430_MACH_MSP430x14:

923

- e_set = bfd_mach_msp14;

924

- break;

925

-

926

- case E_MSP430_MACH_MSP430x15:

927

- e_set = bfd_mach_msp15;

928

- break;

929

-

930

- case E_MSP430_MACH_MSP430x16:

931

- e_set = bfd_mach_msp16;

932

- break;

933

-

934

- case E_MSP430_MACH_MSP430x31:

935

- e_set = bfd_mach_msp31;

936

- break;

937

-

938

- case E_MSP430_MACH_MSP430x32:

939

- e_set = bfd_mach_msp32;

940

- break;

941

-

942

- case E_MSP430_MACH_MSP430x33:

943

- e_set = bfd_mach_msp33;

944

- break;

945

-

946

- case E_MSP430_MACH_MSP430x41:

947

- e_set = bfd_mach_msp41;

948

- break;

949

-

950

- case E_MSP430_MACH_MSP430x42:

951

- e_set = bfd_mach_msp42;

952

- break;

953

-

954

- case E_MSP430_MACH_MSP430x43:

955

- e_set = bfd_mach_msp43;

956

- break;

957

-

958

- case E_MSP430_MACH_MSP430x44:

959

- e_set = bfd_mach_msp44;

960

- break;

961

- }

962

- }

963

-

964

- return bfd_default_set_arch_mach (abfd, bfd_arch_msp430, e_set);

965

+ Elf_Internal_Ehdr * i_ehdrp;

966

+ int bfd_mach;

967

+

968

+ i_ehdrp = elf_elfheader (abfd);

969

+ if (EM_MSP430 != i_ehdrp->e_machine)

970

+ return FALSE;

971

+ if (EF_MSP430_UNIARCH & i_ehdrp->e_flags) {

972

+ switch (i_ehdrp->e_flags & EF_MSP430_ARCH)

973

+ {

974

+ default:

975

+ case EF_MSP430_ARCH_430:

976

+ bfd_mach = bfd_mach_msp430;

977

+ break;

978

+ case EF_MSP430_ARCH_430X:

979

+ bfd_mach = bfd_mach_msp430x;

980

+ break;

981

+ }

982

+ } else {

983

+ bfd_mach = bfd_mach_msp430;

984

+ }

985

+ return bfd_default_set_arch_mach (abfd, bfd_arch_msp430, bfd_mach);

986

}

987

988

/* These functions handle relaxing for the msp430.

989

@@ -1167,13 +1492,12 @@ error_return:

990

#define TARGET_LITTLE_NAME "elf32-msp430"

991

992

#define elf_info_to_howto msp430_info_to_howto_rela

993

-#define elf_info_to_howto_rel NULL

994

#define elf_backend_relocate_section elf32_msp430_relocate_section

995

#define elf_backend_check_relocs elf32_msp430_check_relocs

996

#define elf_backend_can_gc_sections 1

997

-#define elf_backend_final_write_processing bfd_elf_msp430_final_write_processing

998

-#define elf_backend_object_p elf32_msp430_object_p

999

#define elf_backend_post_process_headers _bfd_elf_set_osabi

1000

#define bfd_elf32_bfd_relax_section msp430_elf_relax_section

1001

+#define elf_backend_final_write_processing msp430_elf_backend_final_write_processing

1002

+#define elf_backend_object_p msp430_elf_backend_object_p

1003

1004

#include "elf32-target.h"

1005

diff --git a/bfd/libbfd.h b/bfd/libbfd.h

1006

index 2e7df4f..b18acf2 100644

1007

--- a/bfd/libbfd.h

1008

+++ b/bfd/libbfd.h

1009

@@ -2179,6 +2179,25 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",

1010

"BFD_RELOC_MSP430_16_BYTE",

1011

"BFD_RELOC_MSP430_2X_PCREL",

1012

"BFD_RELOC_MSP430_RL_PCREL",

1013

+ "BFD_RELOC_MSP430X_SRC_BYTE",

1014

+ "BFD_RELOC_MSP430X_SRC",

1015

+ "BFD_RELOC_MSP430X_DST_BYTE",

1016

+ "BFD_RELOC_MSP430X_DST",

1017

+ "BFD_RELOC_MSP430X_DST_2ND_BYTE",

1018

+ "BFD_RELOC_MSP430X_DST_2ND",

1019

+ "BFD_RELOC_MSP430X_PCREL_SRC_BYTE",

1020

+ "BFD_RELOC_MSP430X_PCREL_SRC",

1021

+ "BFD_RELOC_MSP430X_PCREL_DST_BYTE",

1022

+ "BFD_RELOC_MSP430X_PCREL_DST",

1023

+ "BFD_RELOC_MSP430X_PCREL_DST_2ND",

1024

+ "BFD_RELOC_MSP430X_PCREL_DST_2ND_BYTE",

1025

+ "BFD_RELOC_MSP430X_S_BYTE",

1026

+ "BFD_RELOC_MSP430X_S",

1027

+ "BFD_RELOC_MSP430X_D_BYTE",

1028

+ "BFD_RELOC_MSP430X_D",

1029

+ "BFD_RELOC_MSP430X_PCREL_D",

1030

+ "BFD_RELOC_MSP430X_INDXD",

1031

+ "BFD_RELOC_MSP430X_PCREL_INDXD",

1032

"BFD_RELOC_IQ2000_OFFSET_16",

1033

"BFD_RELOC_IQ2000_OFFSET_21",

1034

"BFD_RELOC_IQ2000_UHI16",

1035

diff --git a/bfd/reloc.c b/bfd/reloc.c

1036

index 202a340..7b60036 100644

1037

--- a/bfd/reloc.c

1038

+++ b/bfd/reloc.c

1039

@@ -5247,6 +5247,44 @@ ENUMX

1040

BFD_RELOC_MSP430_2X_PCREL

1041

ENUMX

1042

BFD_RELOC_MSP430_RL_PCREL

1043

+ENUMX

1044

+ BFD_RELOC_MSP430X_SRC_BYTE

1045

+ENUMX

1046

+ BFD_RELOC_MSP430X_SRC

1047

+ENUMX

1048

+ BFD_RELOC_MSP430X_DST_BYTE

1049

+ENUMX

1050

+ BFD_RELOC_MSP430X_DST

1051

+ENUMX

1052

+ BFD_RELOC_MSP430X_DST_2ND_BYTE

1053

+ENUMX

1054

+ BFD_RELOC_MSP430X_DST_2ND

1055

+ENUMX

1056

+ BFD_RELOC_MSP430X_PCREL_SRC_BYTE

1057

+ENUMX

1058

+ BFD_RELOC_MSP430X_PCREL_SRC

1059

+ENUMX

1060

+ BFD_RELOC_MSP430X_PCREL_DST_BYTE

1061

+ENUMX

1062

+ BFD_RELOC_MSP430X_PCREL_DST

1063

+ENUMX

1064

+ BFD_RELOC_MSP430X_PCREL_DST_2ND

1065

+ENUMX

1066

+ BFD_RELOC_MSP430X_PCREL_DST_2ND_BYTE

1067

+ENUMX

1068

+ BFD_RELOC_MSP430X_S_BYTE

1069

+ENUMX

1070

+ BFD_RELOC_MSP430X_S

1071

+ENUMX

1072

+ BFD_RELOC_MSP430X_D_BYTE

1073

+ENUMX

1074

+ BFD_RELOC_MSP430X_D

1075

+ENUMX

1076

+ BFD_RELOC_MSP430X_PCREL_D

1077

+ENUMX

1078

+ BFD_RELOC_MSP430X_INDXD

1079

+ENUMX

1080

+ BFD_RELOC_MSP430X_PCREL_INDXD

1081

ENUMDOC

1082

msp430 specific relocation codes

1083

1084

diff --git a/gas/config/tc-msp430.c b/gas/config/tc-msp430.c

1085

index 98d90c6..583af27 100644

1086

--- a/gas/config/tc-msp430.c

1087

+++ b/gas/config/tc-msp430.c

1088

@@ -23,7 +23,6 @@

1089

1090

#include <limits.h>

1091

1092

-#define PUSH_1X_WORKAROUND

1093

#include "as.h"

1094

#include "subsegs.h"

1095

#include "opcode/msp430.h"

1096

@@ -69,6 +68,7 @@

1097

1098

int msp430_enable_relax;

1099

int msp430_enable_polys;

1100

+int msp430x_repeats; // It's not a right way to use global variable, but I don't know other way how to do it

1101

1102

/* GCC uses the some condition codes which we'll

1103

implement as new polymorph instructions.

1104

@@ -99,12 +99,13 @@ int msp430_enable_polys;

1105

Also, we add 'jump' instruction:

1106

jump UNCOND -> jmp br lab

1107

1108

- They will have fmt == 4, and insn_opnumb == number of instruction. */

1109

+ They will have opcode_format() == FMT_EMULATED_POLYMORPH_JUMP,

1110

+ and opcode_variant() == number of instruction. */

1111

1112

struct rcodes_s

1113

{

1114

char * name;

1115

- int index; /* Corresponding insn_opnumb. */

1116

+ int index; /* Corresponding opcode_variant(). */

1117

int sop; /* Opcode if jump length is short. */

1118

long lpos; /* Label position. */

1119

long lop0; /* Opcode 1 _word_ (16 bits). */

1120

@@ -143,7 +144,7 @@ static struct rcodes_s msp430_rcodes[] =

1121

struct hcodes_s

1122

{

1123

char * name;

1124

- int index; /* Corresponding insn_opnumb. */

1125

+ int index; /* Corresponding opcode_variant(). */

1126

int tlab; /* Number of labels in short mode. */

1127

int op0; /* Opcode for first word of short jump. */

1128

int op1; /* Opcode for second word of short jump. */

1129

@@ -228,116 +229,373 @@ relax_typeS md_relax_table[] =

1130

};

1131

1132

1133

-#define MAX_OP_LEN 256

1134

-

1135

-struct mcu_type_s

1136

+/** List known silicon errata with a description of the problem (where

1137

+ * this can be found). Errata descriptions are available in PDF files

1138

+ * that can be found on the device-specific web page at TI. Errata

1139

+ * numbers are consistent across the product line.

1140

+ *

1141

+ * Note that not all documented errata are currently recognized by the

1142

+ * assembler. In fact, most are completely ignored. Future work...

1143

+ *

1144

+ * Legacy errata descriptions are from previous versions of

1145

+ * binutils. */

1146

+typedef enum msp430_errata_e

1147

{

1148

- char * name;

1149

- int isa;

1150

- int mach;

1151

-};

1152

-

1153

-#define MSP430_ISA_11 11

1154

-#define MSP430_ISA_110 110

1155

-#define MSP430_ISA_12 12

1156

-#define MSP430_ISA_13 13

1157

-#define MSP430_ISA_14 14

1158

-#define MSP430_ISA_15 15

1159

-#define MSP430_ISA_16 16

1160

-#define MSP430_ISA_21 21

1161

-#define MSP430_ISA_31 31

1162

-#define MSP430_ISA_32 32

1163

-#define MSP430_ISA_33 33

1164

-#define MSP430_ISA_41 41

1165

-#define MSP430_ISA_42 42

1166

-#define MSP430_ISA_43 43

1167

-#define MSP430_ISA_44 44

1168

-

1169

-#define CHECK_RELOC_MSP430 ((imm_op || byte_op)?BFD_RELOC_MSP430_16_BYTE:BFD_RELOC_MSP430_16)

1170

-#define CHECK_RELOC_MSP430_PCREL ((imm_op || byte_op)?BFD_RELOC_MSP430_16_PCREL_BYTE:BFD_RELOC_MSP430_16_PCREL)

1171

-

1172

-static struct mcu_type_s mcu_types[] =

1173

-{

1174

- {"msp1", MSP430_ISA_11, bfd_mach_msp11},

1175

- {"msp2", MSP430_ISA_14, bfd_mach_msp14},

1176

- {"msp430x110", MSP430_ISA_11, bfd_mach_msp11},

1177

- {"msp430x112", MSP430_ISA_11, bfd_mach_msp11},

1178

- {"msp430x1101", MSP430_ISA_110, bfd_mach_msp110},

1179

- {"msp430x1111", MSP430_ISA_110, bfd_mach_msp110},

1180

- {"msp430x1121", MSP430_ISA_110, bfd_mach_msp110},

1181

- {"msp430x1122", MSP430_ISA_11, bfd_mach_msp110},

1182

- {"msp430x1132", MSP430_ISA_11, bfd_mach_msp110},

1183

-

1184

- {"msp430x122", MSP430_ISA_12, bfd_mach_msp12},

1185

- {"msp430x123", MSP430_ISA_12, bfd_mach_msp12},

1186

- {"msp430x1222", MSP430_ISA_12, bfd_mach_msp12},

1187

- {"msp430x1232", MSP430_ISA_12, bfd_mach_msp12},

1188

-

1189

- {"msp430x133", MSP430_ISA_13, bfd_mach_msp13},

1190

- {"msp430x135", MSP430_ISA_13, bfd_mach_msp13},

1191

- {"msp430x1331", MSP430_ISA_13, bfd_mach_msp13},

1192

- {"msp430x1351", MSP430_ISA_13, bfd_mach_msp13},

1193

- {"msp430x147", MSP430_ISA_14, bfd_mach_msp14},

1194

- {"msp430x148", MSP430_ISA_14, bfd_mach_msp14},

1195

- {"msp430x149", MSP430_ISA_14, bfd_mach_msp14},

1196

-

1197

- {"msp430x155", MSP430_ISA_15, bfd_mach_msp15},

1198

- {"msp430x156", MSP430_ISA_15, bfd_mach_msp15},

1199

- {"msp430x157", MSP430_ISA_15, bfd_mach_msp15},

1200

- {"msp430x167", MSP430_ISA_16, bfd_mach_msp16},

1201

- {"msp430x168", MSP430_ISA_16, bfd_mach_msp16},

1202

- {"msp430x169", MSP430_ISA_16, bfd_mach_msp16},

1203

- {"msp430x1610", MSP430_ISA_16, bfd_mach_msp16},

1204

- {"msp430x1611", MSP430_ISA_16, bfd_mach_msp16},

1205

- {"msp430x1612", MSP430_ISA_16, bfd_mach_msp16},

1206

-

1207

- {"msp430x2101", MSP430_ISA_21, bfd_mach_msp21},

1208

- {"msp430x2111", MSP430_ISA_21, bfd_mach_msp21},

1209

- {"msp430x2121", MSP430_ISA_21, bfd_mach_msp21},

1210

- {"msp430x2131", MSP430_ISA_21, bfd_mach_msp21},

1211

+ /* CPU4: PUSH #4, PUSH #8

1212

+ *

1213

+ * The single operand instruction PUSH cannot use the internal

1214

+ * constants (CG) 4 and 8. The other internal constants (0, 1, 2,

1215

+ * –1) can be used. The number of clock cycles is different:

1216

+ *

1217

+ * - PUSH #CG uses address mode 00, requiring 3 cycles, 1-word instruction

1218

+ * - PUSH #4/#8 uses address mode 11, requiring 5 cycles, 2-word instruction

1219

+ *

1220

+ * Workaround:

1221

+ * - Assembler generate code not referencing constant generator

1222

+ */

1223

+ ERRATUM_CPU4 = 4,

1224

+

1225

+ // CALL and PUSH with @SP+, @SP, and X(SP) uses the SP to calculate the address, then decrements it

1226

+ ERRATUM_CPU7 = 7,

1227

+

1228

+ /* CPU8: Using odd values in the SP register

1229

+ *

1230

+ * The SP can be written with odd values. In the original CPU, an

1231

+ * odd SP value could be combined with an odd offset (for example,

1232

+ * mov. #value, 5(SP)). In the new CPU, the SP can be written with

1233

+ * an odd value, but the first time the SP is used, the LSB is

1234

+ * forced to 0.

1235

+ *

1236

+ * Workaround:

1237

+ * - Do not use odd values with the SP.

1238

+ */

1239

+ ERRATUM_CPU8 = 8, /* UNHANDLED */

1240

+

1241

+ /* CPU11: Invalid status register after program counter access

1242

+ *

1243

+ * When addressing the program counter (PC) in register mode when

1244

+ * the PC is the destination, the Status Register (SR) may be

1245

+ * erroneous. The instructions BIS, BIC, and MOV do not affect SR

1246

+ * contents. Only CPU flags are affected. This bug does not apply to

1247

+ * LPMx control bits.

1248

+ *

1249

+ * Workaround: None

1250

+ */

1251

+ ERRATUM_CPU11 = 11, /* UNHANDLED */

1252

+

1253

+ /* CPU12: CMP or BIT with PC destination

1254

+ *

1255

+ * Any instruction immediately following a CMP(.B) or BIT(.B)

1256

+ * instruction when the PC is the destination address using register

1257

+ * mode is ignored or erroneously executed. When the following

1258

+ * instruction is longer than one word, the second word is fetched

1259

+ * by the CPU and decoded as the instruction, leading to

1260

+ * unpredictable behavior. Affected source-addressing modes are

1261

+ * indexed and indirect addressing modes.

1262

+ *

1263

+ * Example:

1264

+ * cmp &200,PC

1265

+ * add #4,R8

1266

+ * The add command is not executed.

1267

+ *

1268

+ * Workaround:

1269

+ * - Insert a NOP instruction after the BIT or CMP instruction. The

1270

+ * NOP is ignored, and program execution continues as expected.

1271

+ */

1272

+ ERRATUM_CPU12 = 12, /* UNHANDLED */

1273

+

1274

+ /* CPU13: Arithmetic operations and the SR

1275

+ *

1276

+ * Performing arithmetic operations with the Status Register (SR) as

1277

+ * the destination address does not update the SR as intended. The

1278

+ * result in SR can be invalid, leading to erroneous low-power mode

1279

+ * entry. Arithmetic operations are defined as all instructions that

1280

+ * modify the SR flag bits (RRA, SUB, XOR, and ADD, for example).

1281

+ *

1282

+ * Workaround: None

1283

+ */

1284

+ ERRATUM_CPU13 = 13, /* UNHANDLED */

1285

+

1286

+ /* CPU15: Modifying the Program Counter (PC) behaves differently

1287

+ * than in previous devices

1288

+ *

1289

+ * When using instructions with immediate or indirect addressing

1290

+ * mode to modify the PC, a different value compared to previous

1291

+ * devices must be added to get to the same destination.

1292

+ *

1293

+ * NOTE: The MOV instruction is not affected

1294

+ *

1295

+ * Example: Previous device (MSP430F4619)

1296

+ * label_1 ADD.W #Branch1-label_1-4h,PC

1297

+ * MSP430F5438:

1298

+ * label_1 ADD.W #Branch1-label_1-2h,PC

1299

+ *

1300

+ * Workaround:

1301

+ * - Additional NOP after the PC-modifying instruction; or

1302

+ * - Change the offset value in software

1303

+ */

1304

+ ERRATUM_CPU15 = 15, /* UNHANDLED */

1305

+

1306

+ /* CPU16 Indexed addressing with instructions calla, mova, and bra

1307

+ *

1308

+ * With indexed addressing mode and instructions calla, mova, and bra, it is not possible

1309

+ * to reach memory above 64k if the register content is < 64k.

1310

+ * Example: Assume R5 = FFFEh. The instruction calla 0004h(R5) results in a 20-bit call

1311

+ * of address 0002h instead of 10002h.

1312

+ *

1313

+ * Workaround:

1314

+ * - Use different addressing mode to reach memory above 64k.

1315

+ * - First use adda [index],[Rx] to calculate address in upper memory and then use

1316

+ * calla [Rx].

1317

+ */

1318

+ ERRATUM_CPU16 = 16, /* UNHANDLED */

1319

+

1320

+ /* CPU18: LPM instruction can corrupt PC/SR registers

1321

+ *

1322

+ * The PC and SR registers have the potential to be corrupted when:

1323

+ * - An instruction using register, absolute, indexed, indirect,

1324

+ * indirect auto-increment, or symbolic mode is used to set the

1325

+ * LPM bits (for example, BIS &xyh, SR).

1326

+ * and

1327

+ * - This instruction is followed by a CALL or CALLA instruction.

1328

+ *

1329

+ * Upon servicing an interrupt service routine, the program counter

1330

+ * (PC) is pushed twice onto the stack instead of the correct

1331

+ * operation where the PC, then the SR registers are pushed onto the

1332

+ * stack. This corrupts the SR and possibly the PC on RETI from the

1333

+ * ISR.

1334

+ *

1335

+ * Workaround:

1336

+ * - Insert a NOP or __no_operation() intrinsic function between the

1337

+ * instruction to enter low-power mode and the CALL or CALLA

1338

+ * instruction.

1339

+ */

1340

+ ERRATUM_CPU18 = 18, /* UNHANDLED */

1341

+

1342

+ /* CPU19: CPUOFF can change register values

1343

+ *

1344

+ * If a CPUOFF command is followed by an instruction with an

1345

+ * indirect addressed operand (for example, mov @R8, R9, and RET),

1346

+ * an unintentional register-read operation can occur during the

1347

+ * wakeup of the CPU. If the unintentional read occurs to a

1348

+ * read-sensitive register (for example, UCB0RXBUF or TAIV), which

1349

+ * changes its value or the value of other registers (IFGs), the bug

1350

+ * leads to lost interrupts or wrong register read values.

1351

+ *

1352

+ * Workaround:

1353

+ * - Insert a NOP instruction after each CPUOFF instruction.

1354

+ */

1355

+ ERRATUM_CPU19 = 19, /* UNHANDLED */

1356

+

1357

+ /* CPU20: An unexpected Vacant Memory Access Flag (VMAIFG) can be

1358

+ * triggered due to the CPU autoincrement of the MAB + 2

1359

+ * outside the range of a valid memory block.

1360

+ *

1361

+ * The VMAIFG is triggered if a PC-modifying instruction (for

1362

+ * example, ret, push, call, pop, jmp, br) is fetched from the last

1363

+ * address of a section of memory (for example, flash or RAM) that

1364

+ * is not contiguous to a higher valid section on the memory map.

1365

+ *

1366

+ * Workaround:

1367

+ * - If code is affected, edit the linker command file to make the

1368

+ * last four bytes of affected memory sections unavailable.

1369

+ */

1370

+ ERRATUM_CPU20 = 20, /* UNHANDLED */

1371

+

1372

+ /* NO DESCRIPTION */

1373

+ ERRATUM_CPU21 = 21, /* UNHANDLED */

1374

+

1375

+ /* NO DESCRIPTION */

1376

+ ERRATUM_CPU22 = 22, /* UNHANDLED */

1377

+

1378

+ /* NO DESCRIPTION */

1379

+ ERRATUM_CPU23 = 23, /* UNHANDLED */

1380

+

1381

+ /* CPU26: CALL SP does not behave as expected

1382

+ *

1383

+ * When the intention is to execute code from the stack, a CALL SP

1384

+ * instruction skips the first piece of data (instruction) on the

1385

+ * stack. The second piece of data at SP + 2 is used as the first

1386

+ * executable instruction.

1387

+ *

1388

+ * Workaround:

1389

+ * - Write the op code for a NOP as the first instruction on the

1390

+ * stack. Begin the intended subroutine at address SP + 2.

1391

+ */

1392

+ ERRATUM_CPU26 = 26, /* UNHANDLED */

1393

+

1394

+ /* CPU27: Program Counter (PC) is corrupted during the context save

1395

+ * of a nested interrupt

1396

+ *

1397

+ * When a low-power mode is entered within an interrupt service

1398

+ * routine that has enabled nested interrupts (by setting the GIE

1399

+ * bit), and the instruction that sets the low-power mode is

1400

+ * directly followed by a RETI instruction, an incorrect value of PC

1401

+ * + 2 is pushed to the stack during the context save. Hence, the

1402

+ * RETI instruction is not executed on return from the nested

1403

+ * interrupt, and the PC becomes corrupted.

1404

+ *

1405

+ * Workaround:

1406

+ * - Insert a NOP or __no_operation() intrinsic function between the

1407

+ * instruction that sets the lower power mode and the RETI

1408

+ * instruction.

1409

+ */

1410

+ ERRATUM_CPU27 = 27, /* UNHANDLED */

1411

+

1412

+ /* CPU28: PC is corrupted when using certain extended addressing

1413

+ * mode combinations

1414

+ *

1415

+ * An extended memory instruction that modifies the program counter

1416

+ * executes incorrectly when preceded by an extended memory

1417

+ * write-back instruction under the following conditions:

1418

+ *

1419

+ * - First instruction:

1420

+ * 2-operand instruction, extended mode using (register,index),

1421

+ * (register,absolute), or (register,symbolic) addressing modes

1422

+ * - Second instruction:

1423

+ * 2-operand instruction, extended mode using the (indirect,PC),

1424

+ * (indirect auto-increment,PC), or (indexed [with ind 0], PC)

1425

+ * addressing modes

1426

+ *

1427

+ * Example:

1428

+ * BISX.A R6,&AABCD

1429

+ * ANDX.A @R4+,PC

1430

+ *

1431

+ * Workaround:

1432

+ * - Insert a NOP or a __no_operation() intrinsic function between

1433

+ * the two instructions.

1434

+ * or

1435

+ * - Do not use an extended memory instruction to modify the PC.

1436

+ */

1437

+ ERRATUM_CPU28 = 28, /* UNHANDLED */

1438

+

1439

+ /* CPU29: Using a certain instruction sequence to enter low-power

1440

+ * mode(s) affects the instruction width of the first

1441

+ * instruction in an NMI ISR

1442

+ *

1443

+ * If there is a pending NMI request when the CPU enters a low-power

1444

+ * mode (LPMx) using an instruction of Indexed source addressing

1445

+ * mode, and that instruction is followed by a 20-bit wide

1446

+ * instruction of Register source and Destination addressing modes,

1447

+ * the first instruction of the ISR is executed as a 20-bit wide

1448

+ * instruction.

1449

+ *

1450

+ * Example:

1451

+ * main:

1452

+ * ...

1453

+ * MOV.W [indexed],SR ; Enter LPMx

1454

+ * MOVX.A [register],[register] ; 20-bit wide instruction

1455

+ * ...

1456

+ * ISR_start:

1457

+ * MOV.B [indexed],[register] ; ERROR - Executed as a 20-bit instruction!

1458

+ *

1459

+ * Note: [ ] indicates addressing mode

1460

+ *

1461

+ * Workaround:

1462

+ * - Insert a NOP or a __no_operation() intrinsic function following

1463

+ * the instruction that enters the LPMx using indexed addressing

1464

+ * mode.

1465

+ * or

1466

+ * - Use a NOP or a __no_operation() intrinsic function as first

1467

+ * instruction in the ISR.

1468

+ * or

1469

+ * - Do not use the indexed mode to enter LPMx.

1470

+ */

1471

+ ERRATUM_CPU29 = 29, /* UNHANDLED */

1472

1473

- {"msp430x311", MSP430_ISA_31, bfd_mach_msp31},

1474

- {"msp430x312", MSP430_ISA_31, bfd_mach_msp31},

1475

- {"msp430x313", MSP430_ISA_31, bfd_mach_msp31},

1476

- {"msp430x314", MSP430_ISA_31, bfd_mach_msp31},

1477

- {"msp430x315", MSP430_ISA_31, bfd_mach_msp31},

1478

- {"msp430x323", MSP430_ISA_32, bfd_mach_msp32},

1479

- {"msp430x325", MSP430_ISA_32, bfd_mach_msp32},

1480

- {"msp430x336", MSP430_ISA_33, bfd_mach_msp33},

1481

- {"msp430x337", MSP430_ISA_33, bfd_mach_msp33},

1482

-

1483

- {"msp430x412", MSP430_ISA_41, bfd_mach_msp41},

1484

- {"msp430x413", MSP430_ISA_41, bfd_mach_msp41},

1485

- {"msp430x415", MSP430_ISA_41, bfd_mach_msp41},

1486

- {"msp430x417", MSP430_ISA_41, bfd_mach_msp41},

1487

-

1488

- {"msp430xE423", MSP430_ISA_42, bfd_mach_msp42},

1489

- {"msp430xE425", MSP430_ISA_42, bfd_mach_msp42},

1490

- {"msp430xE427", MSP430_ISA_42, bfd_mach_msp42},

1491

-

1492

- {"msp430xW423", MSP430_ISA_42, bfd_mach_msp42},

1493

- {"msp430xW425", MSP430_ISA_42, bfd_mach_msp42},

1494

- {"msp430xW427", MSP430_ISA_42, bfd_mach_msp42},

1495

-

1496

- {"msp430xG437", MSP430_ISA_43, bfd_mach_msp43},

1497

- {"msp430xG438", MSP430_ISA_43, bfd_mach_msp43},

1498

- {"msp430xG439", MSP430_ISA_43, bfd_mach_msp43},

1499

-

1500

- {"msp430x435", MSP430_ISA_43, bfd_mach_msp43},

1501

- {"msp430x436", MSP430_ISA_43, bfd_mach_msp43},

1502

- {"msp430x437", MSP430_ISA_43, bfd_mach_msp43},

1503

- {"msp430x447", MSP430_ISA_44, bfd_mach_msp44},

1504

- {"msp430x448", MSP430_ISA_44, bfd_mach_msp44},

1505

- {"msp430x449", MSP430_ISA_44, bfd_mach_msp44},

1506

-

1507

- {NULL, 0, 0}

1508

+ /* CPU30: ADDA, SUBA, CMPA [immediate],PC behave as if immediate

1509

+ * value were offset by -2

1510

+ *

1511

+ * The extended address instructions ADDA, SUBA, and CMPA in

1512

+ * immediate addressing mode are represented by 4 bytes of opcode

1513

+ * (see the MSP430F5xx Family User's Guide (SLAU208) for more

1514

+ * details). In cases where the program counter (PC) is used as the

1515

+ * destination register, only 2 bytes of the current instruction's

1516

+ * 4-byte opcode are accounted for in the PC value. The resulting

1517

+ * operation executes as if the immediate value were offset by a

1518

+ * value of -2.

1519

+ *

1520

+ * Example:

1521

+ * Ideal: ADDA #Immediate-4, PC

1522

+ * ...is equivalent to...

1523

+ * Actual: ADDA #Immediate-2, PC

1524

+ * NOTE: The MOV instruction is not affected.

1525

+ *

1526

+ * Workaround:

1527

+ * - Modify immediate value in software to account for the offset of 2.

1528

+ * or

1529

+ * - Use extended 20-bit instructions (addx.a, subx.a, cmpx.a) instead.

1530

+ */

1531

+ ERRATUM_CPU30 = 30, /* UNHANDLED */

1532

+

1533

+ /* CPU40: PC is corrupted when executing jump/conditional jump

1534

+ * instruction that is followed by instruction with PC as

1535

+ * destination register or a data section

1536

+ *

1537

+ * If the value at the memory location immediately following a

1538

+ * jump/conditional jump instruction is 0X40h or 0X50h (where X =

1539

+ * don't care), which could either be an instruction opcode (for

1540

+ * instructions like RRCM, RRAM, RLAM, RRUM) with PC as destination

1541

+ * register or a data section (const data in flash memory or data

1542

+ * variable in RAM), then the PC value gets auto-incremented by 2

1543

+ * after the jump instruction is executed; thus branching to a wrong

1544

+ * address location in code and leading to wrong program execution.

1545

+ *

1546

+ * For example, a conditional jump instruction followed by data

1547

+ * section (0140h).

1548

+ *

1549

+ * @0x8012 Loop DEC.W R6

1550

+ * @0x8014 DEC.W R7

1551

+ * @0x8016 JNZ Loop

1552

+ * @0x8018 Value1 DW 0140h

1553

+ *

1554

+ * Workaround:

1555

+ * - In assembly, insert a NOP between the jump/conditional jump

1556

+ * instruction and program code with instruction that contains PC

1557

+ * as destination register or the data section.

1558

+ */

1559

+ ERRATUM_CPU40 = 40, /* UNHANDLED */

1560

+} msp430_errata_e;

1561

+

1562

+/* sed -e '1,/enum msp430_errata/d' -e '/^\}/,$d' tc-msp430.c \

1563

+ | grep '^ *ERRATUM_*' \

1564

+ | cut -d= -f1 \

1565

+ | sed 's@ *$@,@' */

1566

+static const int recognized_errata[] = {

1567

+ ERRATUM_CPU4,

1568

+ ERRATUM_CPU7,

1569

+ ERRATUM_CPU8,

1570

+ ERRATUM_CPU11,

1571

+ ERRATUM_CPU12,

1572

+ ERRATUM_CPU13,

1573

+ ERRATUM_CPU15,

1574

+ ERRATUM_CPU16,

1575

+ ERRATUM_CPU18,

1576

+ ERRATUM_CPU19,

1577

+ ERRATUM_CPU20,

1578

+ ERRATUM_CPU21,

1579

+ ERRATUM_CPU22,

1580

+ ERRATUM_CPU23,

1581

+ ERRATUM_CPU26,

1582

+ ERRATUM_CPU27,

1583

+ ERRATUM_CPU28,

1584

+ ERRATUM_CPU29,

1585

+ ERRATUM_CPU30,

1586

+ ERRATUM_CPU40,

1587

};

1588

1589

+#define CHECK_RELOC_MSP430 ((imm_op || op_width == BYTE_OP) ? BFD_RELOC_MSP430_16_BYTE : BFD_RELOC_MSP430_16)

1590

+#define CHECK_RELOC_MSP430_PCREL ((imm_op || op_width == BYTE_OP) ? BFD_RELOC_MSP430_16_PCREL_BYTE : BFD_RELOC_MSP430_16_PCREL)

1591

+#define CHECK_RELOC_MSP430X_SRC ((imm_op || op_width == BYTE_OP) ? BFD_RELOC_MSP430X_SRC_BYTE : BFD_RELOC_MSP430X_SRC)

1592

+#define CHECK_RELOC_MSP430X_PCREL_SRC ((imm_op || op_width == BYTE_OP) ? BFD_RELOC_MSP430X_PCREL_SRC_BYTE : BFD_RELOC_MSP430X_PCREL_SRC)

1593

+#define CHECK_RELOC_MSP430X_DST ((imm_op || op_width == BYTE_OP) ? BFD_RELOC_MSP430X_DST_BYTE : BFD_RELOC_MSP430X_DST)

1594

+#define CHECK_RELOC_MSP430X_PCREL_DST ((imm_op || op_width == BYTE_OP) ? BFD_RELOC_MSP430X_PCREL_DST_BYTE : BFD_RELOC_MSP430X_PCREL_DST)

1595

+#define CHECK_RELOC_MSP430X_DST_2ND ((imm_op || op_width == BYTE_OP) ? BFD_RELOC_MSP430X_DST_2ND_BYTE : BFD_RELOC_MSP430X_DST_2ND)

1596

+#define CHECK_RELOC_MSP430X_PCREL_DST_2ND ((imm_op || op_width == BYTE_OP) ? BFD_RELOC_MSP430X_PCREL_DST_2ND_BYTE : BFD_RELOC_MSP430X_PCREL_DST_2ND)

1597

1598

-static struct mcu_type_s default_mcu =

1599

- { "msp430x11", MSP430_ISA_11, bfd_mach_msp11 };

1600

-

1601

-static struct mcu_type_s * msp430_mcu = & default_mcu;

1602

+static int msp430_cpu = MSP430_CPU_MSP430;

1603

+static int msp430_mpy = MSP430_MPY_NONE;

1604

+static int *msp430_errata = 0;

1605

1606

/* Profiling capability:

1607

It is a performance hit to use gcc's profiling approach for this tiny target.

1608

@@ -446,32 +704,14 @@ pow2value (int y)

1609

static char *

1610

parse_exp (char * s, expressionS * op)

1611

{

1612

+ char * in_save = input_line_pointer;

1613

input_line_pointer = s;

1614

expression (op);

1615

+ s = input_line_pointer;

1616

+ input_line_pointer = in_save;

1617

if (op->X_op == O_absent)

1618

as_bad (_("missing operand"));

1619

- return input_line_pointer;

1620

-}

1621

-

1622

-

1623

-/* Delete spaces from s: X ( r 1 2) => X(r12). */

1624

-

1625

-static void

1626

-del_spaces (char * s)

1627

-{

1628

- while (*s)

1629

- {

1630

- if (ISSPACE (*s))

1631

- {

1632

- char *m = s + 1;

1633

-

1634

- while (ISSPACE (*m) && *m)

1635

- m++;

1636

- memmove (s, m, strlen (m) + 1);

1637

- }

1638

- else

1639

- s++;

1640

- }

1641

+ return s;

1642

}

1643

1644

static inline char *

1645

@@ -482,42 +722,46 @@ skip_space (char * s)

1646

return s;

1647

}

1648

1649

-/* Extract one word from FROM and copy it to TO. Delimiters are ",;\n" */

1650

-

1651

+/* Extract one word from the input. Delimiters are ",;\n" */

1652

static char *

1653

-extract_operand (char * from, char * to, int limit)

1654

+get_operand (void)

1655

{

1656

- int size = 0;

1657

-

1658

- /* Drop leading whitespace. */

1659

- from = skip_space (from);

1660

+ char* sp = input_line_pointer;

1661

+ char* end_ilp;

1662

+ char* dest;

1663

+ char* dp;

1664

+ int operand_length = 0;

1665

1666

- while (size < limit && *from)

1667

+ while (sp && ',' != *sp && ';' != *sp && '\n' != *sp)

1668

{

1669

- *(to + size) = *from;

1670

- if (*from == ',' || *from == ';' || *from == '\n')

1671

- break;

1672

- from++;

1673

- size++;

1674

+ if (! ISSPACE(*sp))

1675

+ ++operand_length;

1676

+ ++sp;

1677

}

1678

-

1679

- *(to + size) = 0;

1680

- del_spaces (to);

1681

-

1682

- from++;

1683

-

1684

- return from;

1685

+ end_ilp = sp;

1686

+ if (',' == *end_ilp)

1687

+ ++end_ilp;

1688

+

1689

+ dp = dest = xmalloc(operand_length + 1);

1690

+ sp = input_line_pointer;

1691

+ while (0 < operand_length) {

1692

+ if (! ISSPACE(*sp)) {

1693

+ *dp++ = *sp;

1694

+ --operand_length;

1695

+ }

1696

+ ++sp;

1697

+ }

1698

+ *dp = 0;

1699

+ input_line_pointer = end_ilp;

1700

+ return dest;

1701

}

1702

1703

static void

1704

msp430_profiler (int dummy ATTRIBUTE_UNUSED)

1705

{

1706

- char buffer[1024];

1707

- char f[32];

1708

- char * str = buffer;

1709

- char * flags = f;

1710

+ char * flag_token = 0;

1711

+ char * flags;

1712

int p_flags = 0;

1713

- char * halt;

1714

int ops = 0;

1715

int left;

1716

char * s;

1717

@@ -549,8 +793,7 @@ msp430_profiler (int dummy ATTRIBUTE_UNUSED)

1718

return;

1719

}

1720

1721

- input_line_pointer = extract_operand (input_line_pointer, flags, 32);

1722

-

1723

+ flags = flag_token = get_operand ();

1724

while (*flags)

1725

{

1726

switch (*flags)

1727

@@ -608,6 +851,7 @@ msp430_profiler (int dummy ATTRIBUTE_UNUSED)

1728

}

1729

flags++;

1730

}

1731

+ xfree (flag_token);

1732

1733

if (p_flags

1734

&& ( ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_ENTRY

1735

@@ -658,11 +902,11 @@ msp430_profiler (int dummy ATTRIBUTE_UNUSED)

1736

while (ops--)

1737

{

1738

/* Now get profiling info. */

1739

- halt = extract_operand (input_line_pointer, str, 1024);

1740

+ char *halt = get_operand ();

1741

/* Process like ".word xxx" directive. */

1742

- parse_exp (str, & exp);

1743

+ parse_exp (halt, & exp);

1744

emit_expr (& exp, 2);

1745

- input_line_pointer = halt;

1746

+ xfree(halt);

1747

}

1748

1749

/* Fill the rest with zeros. */

1750

@@ -675,79 +919,178 @@ msp430_profiler (int dummy ATTRIBUTE_UNUSED)

1751

subseg_set (seg, subseg);

1752

}

1753

1754

-static char *

1755

-extract_word (char * from, char * to, int limit)

1756

+struct tag_value_pair_t

1757

{

1758

- char *op_end;

1759

- int size = 0;

1760

+ const char *tag;

1761

+ unsigned long value;

1762

+};

1763

1764

- /* Drop leading whitespace. */

1765

- from = skip_space (from);

1766

- *to = 0;

1767

+static const struct tag_value_pair_t cpu_tag_value_map[] = {

1768

+ {"430", MSP430_CPU_MSP430},

1769

+ {"430x", MSP430_CPU_MSP430X},

1770

+ {"430xv2", MSP430_CPU_MSP430XV2},

1771

+ {0, 0}

1772

+};

1773

+

1774

+static const struct tag_value_pair_t mpy_tag_value_map[] = {

1775

+ {"none", MSP430_MPY_NONE},

1776

+ {"16", MSP430_MPY_16},

1777

+ {"16se", MSP430_MPY_16SE},

1778

+ {"32", MSP430_MPY_32},

1779

+ {"32dw", MSP430_MPY_32DW},

1780

+ {0, 0}

1781

+};

1782

1783

- /* Find the op code end. */

1784

- for (op_end = from; *op_end != 0 && is_part_of_name (*op_end);)

1785

+static const struct tag_value_pair_t *

1786

+find_pair_by_tag (const char *tag, const struct tag_value_pair_t *map)

1787

+{

1788

+ while (map->tag)

1789

{

1790

- to[size++] = *op_end++;

1791

- if (size + 1 >= limit)

1792

- break;

1793

+ if (0 == strcmp (tag, map->tag))

1794

+ return map;

1795

+ ++map;

1796

}

1797

+ return 0;

1798

+}

1799

1800

- to[size] = 0;

1801

- return op_end;

1802

+#if 0

1803

+static const struct tag_value_pair_t *

1804

+find_pair_by_value (unsigned long value, const struct tag_value_pair_t *map)

1805

+{

1806

+ while (map->tag)

1807

+ {

1808

+ if (map->value == value)

1809

+ return map;

1810

+ ++map;

1811

+ }

1812

+ return 0;

1813

}

1814

+#endif

1815

1816

-#define OPTION_MMCU 'm'

1817

-#define OPTION_RELAX 'Q'

1818

-#define OPTION_POLYMORPHS 'P'

1819

+enum {

1820

+ OPTION_MMCU = 'm',

1821

+ OPTION_RELAX = 'Q',

1822

+ OPTION_POLYMORPHS = 'P',

1823

+ OPTION_CPU = OPTION_MD_BASE + 0,

1824

+ OPTION_MPY,

1825

+ OPTION_ERRATA,

1826

+};

1827

+

1828

+static int

1829

+erratum_applies (int erratum)

1830

+{

1831

+ if (! msp430_errata)

1832

+ if (ERRATUM_CPU4 == erratum)

1833

+ return msp430_cpu < MSP430_CPU_MSP430X;

1834

+ return 0;

1835

+}

1836

+

1837

+static int

1838

+cpu_from_text (const char* text)

1839

+{

1840

+ const struct tag_value_pair_t* mp = find_pair_by_tag(text, cpu_tag_value_map);

1841

+ if (! mp)

1842

+ as_fatal (_("unrecognized cpu type %s"), text);

1843

+ return mp->value;

1844

+}

1845

+

1846

+static int

1847

+mpy_from_text (const char* text)

1848

+{

1849

+ const struct tag_value_pair_t* mp = find_pair_by_tag(text, mpy_tag_value_map);

1850

+ if (! mp)

1851

+ as_fatal (_("unrecognized hardware multiplier type %s"), text);

1852

+ return mp->value;

1853

+}

1854

1855

static void

1856

-msp430_set_arch (int dummy ATTRIBUTE_UNUSED)

1857

+set_arch_mach (int cpu,

1858

+ int mpy ATTRIBUTE_UNUSED)

1859

{

1860

- char *str = (char *) alloca (32); /* 32 for good measure. */

1861

+ unsigned long mach = bfd_mach_msp430;

1862

+ if (MSP430_CPU_MSP430X <= cpu)

1863

+ mach = bfd_mach_msp430x;

1864

+ bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);

1865

+}

1866

1867

- input_line_pointer = extract_word (input_line_pointer, str, 32);

1868

+/* Like get_symbol_end, but accepts sequences that start with

1869

+ * digits and doesn't strip out name ends */

1870

+static char

1871

+get_token_end (void)

1872

+{

1873

+ char c;

1874

1875

- md_parse_option (OPTION_MMCU, str);

1876

- bfd_set_arch_mach (stdoutput, TARGET_ARCH, msp430_mcu->mach);

1877

+ while (is_part_of_name (c = *input_line_pointer++))

1878

+ ;

1879

+ *--input_line_pointer = 0;

1880

+ return (c);

1881

}

1882

1883

static void

1884

-show_mcu_list (FILE * stream)

1885

+msp430_set_mcu (int dummy ATTRIBUTE_UNUSED)

1886

{

1887

- int i;

1888

+ SKIP_WHITESPACE();

1889

+ if (!is_end_of_line[(unsigned char) *input_line_pointer])

1890

+ {

1891

+ char* tag_start = input_line_pointer;

1892

+ int ch = get_token_end ();

1893

+ md_parse_option (OPTION_MMCU, tag_start);

1894

+ *input_line_pointer = ch;

1895

+ demand_empty_rest_of_line ();

1896

+ }

1897

+ else

1898

+ as_bad (_("missing value for arch"));

1899

+}

1900

+

1901

+static void

1902

+msp430_set (int option)

1903

+{

1904

+ char* tag = 0;

1905

+

1906

+ SKIP_WHITESPACE ();

1907

+ if (!is_end_of_line[(unsigned char) *input_line_pointer])

1908

+ {

1909

+ char *tag_start = input_line_pointer;

1910

+ char e = get_token_end ();

1911

+ int tag_len = input_line_pointer + 1 - tag_start;

1912

+ tag = (char *) xmalloc(tag_len);

1913

+ memcpy (tag, tag_start, tag_len);

1914

+ *input_line_pointer = e;

1915

+ demand_empty_rest_of_line ();

1916

+ }

1917

+

1918

+ switch (option)

1919

+ {

1920

+ case OPTION_CPU:

1921

+ if (! tag)

1922

+ as_bad (_("missing value for cpu"));

1923

+ msp430_cpu = cpu_from_text(tag);

1924

+ break;

1925

+ case OPTION_MPY:

1926

+ if (! tag)

1927

+ as_bad (_("missing value for mpy"));

1928

+ msp430_mpy = mpy_from_text(tag);

1929

+ break;

1930

+ default:

1931

+ abort();

1932

+ }

1933

1934

- fprintf (stream, _("Known MCU names:\n"));

1935

+ set_arch_mach (msp430_cpu, msp430_mpy);

1936

1937

- for (i = 0; mcu_types[i].name; i++)

1938

- fprintf (stream, _("\t %s\n"), mcu_types[i].name);

1939

+}

1940

1941

- fprintf (stream, "\n");

1942

+static void

1943

+msp430_set_errata (int dummy ATTRIBUTE_UNUSED)

1944

+{

1945

}

1946

1947

int

1948

md_parse_option (int c, char * arg)

1949

{

1950

- int i;

1951

-

1952

switch (c)

1953

{

1954

case OPTION_MMCU:

1955

- for (i = 0; mcu_types[i].name; ++i)

1956

- if (strcmp (mcu_types[i].name, arg) == 0)

1957

- break;

1958

-

1959

- if (!mcu_types[i].name)

1960

- {

1961

- show_mcu_list (stderr);

1962

- as_fatal (_("unknown MCU: %s\n"), arg);

1963

- }

1964

-

1965

- if (msp430_mcu == &default_mcu || msp430_mcu->mach == mcu_types[i].mach)

1966

- msp430_mcu = &mcu_types[i];

1967

- else

1968

- as_fatal (_("redefinition of mcu type %s' to %s'"),

1969

- msp430_mcu->name, mcu_types[i].name);

1970

+ //as_tsktsk(_("mcu option ignored"));

1971

return 1;

1972

break;

1973

1974

@@ -760,16 +1103,35 @@ md_parse_option (int c, char * arg)

1975

msp430_enable_polys = 1;

1976

return 1;

1977

break;

1978

+

1979

+ case OPTION_CPU:

1980

+ msp430_cpu = cpu_from_text(arg);

1981

+ return 1;

1982

+ break;

1983

+

1984

+ case OPTION_MPY:

1985

+ msp430_mpy = mpy_from_text(arg);

1986

+ return 1;

1987

+ break;

1988

+

1989

+ case OPTION_ERRATA:

1990

+ break;

1991

}

1992

1993

return 0;

1994

}

1995

1996

+static void

1997

+msp430_repeat_insn (int dummy ATTRIBUTE_UNUSED);

1998

1999

const pseudo_typeS md_pseudo_table[] =

2000

{

2001

- {"arch", msp430_set_arch, 0},

2002

+ {"arch", msp430_set_mcu, 0},

2003

{"profiler", msp430_profiler, 0},

2004

+ {"rpt", msp430_repeat_insn, 0},

2005

+ {"cpu", msp430_set, OPTION_CPU},

2006

+ {"mpy", msp430_set, OPTION_MPY},

2007

+ {"errata", msp430_set_errata, 0},

2008

{NULL, NULL, 0}

2009

};

2010

2011

@@ -780,6 +1142,9 @@ struct option md_longopts[] =

2012

{"mmcu", required_argument, NULL, OPTION_MMCU},

2013

{"mP", no_argument, NULL, OPTION_POLYMORPHS},

2014

{"mQ", no_argument, NULL, OPTION_RELAX},

2015

+ {"mcpu", required_argument, NULL, OPTION_CPU },

2016

+ {"mmpy", required_argument, NULL, OPTION_MPY },

2017

+ {"merrata", required_argument, NULL, OPTION_ERRATA },

2018

{NULL, no_argument, NULL, 0}

2019

};

2020

2021

@@ -789,33 +1154,13 @@ void

2022

md_show_usage (FILE * stream)

2023

{

2024

fprintf (stream,

2025

- _("MSP430 options:\n"

2026

- " -mmcu=[msp430-name] select microcontroller type\n"

2027

- " msp430x110 msp430x112\n"

2028

- " msp430x1101 msp430x1111\n"

2029

- " msp430x1121 msp430x1122 msp430x1132\n"

2030

- " msp430x122 msp430x123\n"

2031

- " msp430x1222 msp430x1232\n"

2032

- " msp430x133 msp430x135\n"

2033

- " msp430x1331 msp430x1351\n"

2034

- " msp430x147 msp430x148 msp430x149\n"

2035

- " msp430x155 msp430x156 msp430x157\n"

2036

- " msp430x167 msp430x168 msp430x169\n"

2037

- " msp430x1610 msp430x1611 msp430x1612\n"

2038

- " msp430x311 msp430x312 msp430x313 msp430x314 msp430x315\n"

2039

- " msp430x323 msp430x325\n"

2040

- " msp430x336 msp430x337\n"

2041

- " msp430x412 msp430x413 msp430x415 msp430x417\n"

2042

- " msp430xE423 msp430xE425 msp430E427\n"

2043

- " msp430xW423 msp430xW425 msp430W427\n"

2044

- " msp430xG437 msp430xG438 msp430G439\n"

2045

- " msp430x435 msp430x436 msp430x437\n"

2046

- " msp430x447 msp430x448 msp430x449\n"));

2047

- fprintf (stream,

2048

- _(" -mQ - enable relaxation at assembly time. DANGEROUS!\n"

2049

+ _("MSP430 as-specific options:\n"

2050

+ " -mmcu=[msp430-name] select microcontroller type (ignored)\n"

2051

+ " -mcpu={430,430x,430xv2} select cpu model\n"

2052

+ " -mmpy={none,16,16se,32,32dw} select hardware multiplier type\n"

2053

+ " -merrata=[cpuX,...] list relevant errata\n"

2054

+ " -mQ - enable relaxation at assembly time. DANGEROUS!\n"

2055

" -mP - enable polymorph instructions\n"));

2056

-

2057

- show_mcu_list (stream);

2058

}

2059

2060

symbolS *

2061

@@ -824,23 +1169,6 @@ md_undefined_symbol (char * name ATTRIBUTE_UNUSED)

2062

return 0;

2063

}

2064

2065

-static char *

2066

-extract_cmd (char * from, char * to, int limit)

2067

-{

2068

- int size = 0;

2069

-

2070

- while (*from && ! ISSPACE (*from) && *from != '.' && limit > size)

2071

- {

2072

- *(to + size) = *from;

2073

- from++;

2074

- size++;

2075

- }

2076

-

2077

- *(to + size) = 0;

2078

-

2079

- return from;

2080

-}

2081

-

2082

char *

2083

md_atof (int type, char * litP, int * sizeP)

2084

{

2085

@@ -850,13 +1178,13 @@ md_atof (int type, char * litP, int * sizeP)

2086

void

2087

md_begin (void)

2088

{

2089

- struct msp430_opcode_s * opcode;

2090

+ struct msp430_opcode_s const * opcode;

2091

msp430_hash = hash_new ();

2092

2093

for (opcode = msp430_opcodes; opcode->name; opcode++)

2094

hash_insert (msp430_hash, opcode->name, (char *) opcode);

2095

2096

- bfd_set_arch_mach (stdoutput, TARGET_ARCH, msp430_mcu->mach);

2097

+ set_arch_mach (msp430_cpu, msp430_mpy);

2098

}

2099

2100

static int

2101

@@ -880,13 +1208,74 @@ check_reg (char * t)

2102

return 0;

2103

}

2104

2105

+static void

2106

+msp430_substitute_CG(struct msp430_operand_s * op, int workaround)

2107

+{

2108

+ /* Substitute register mode with a constant generator if applicable. */

2109

+ if( op->mode != OP_EXP || ( op->exp.X_op != O_constant && op->exp.X_op != O_big ))

2110

+ return;

2111

+ if( op->am != 3 || op->reg != 0 ) // not #N

2112

+ return;

2113

+ int x = (short) op->exp.X_add_number; /* Extend sign. */

2114

+

2115

+ if (x == 0)

2116

+ {

2117

+ op->reg = 3;

2118

+ op->am = 0;

2119

+ op->ol = 0;

2120

+ op->mode = OP_REG;

2121

+ }

2122

+ else if (x == 1)

2123

+ {

2124

+ op->reg = 3;

2125

+ op->am = 1;

2126

+ op->ol = 0;

2127

+ op->mode = OP_REG;

2128

+ }

2129

+ else if (x == 2)

2130

+ {

2131

+ op->reg = 3;

2132

+ op->am = 2;

2133

+ op->ol = 0;

2134

+ op->mode = OP_REG;

2135

+ }

2136

+ else if (x == -1)

2137

+ {

2138

+ op->reg = 3;

2139

+ op->am = 3;

2140

+ op->ol = 0;

2141

+ op->mode = OP_REG;

2142

+ }

2143

+ else if (x == 4 && !workaround)

2144

+ {

2145

+ op->reg = 2;

2146

+ op->am = 2;

2147

+ op->ol = 0;

2148

+ op->mode = OP_REG;

2149

+ }

2150

+ else if (x == 8 && ! workaround)

2151

+ {

2152

+ op->reg = 2;

2153

+ op->am = 3;

2154

+ op->ol = 0;

2155

+ op->mode = OP_REG;

2156

+ }

2157

+}

2158

2159

static int

2160

msp430_srcoperand (struct msp430_operand_s * op,

2161

- char * l, int bin, int * imm_op)

2162

+ const char * operand_string, int * imm_op, int imm_min, int imm_max)

2163

{

2164

- char *__tl = l;

2165

+ char *l = "";

2166

+ char *__tl;

2167

2168

+ if (operand_string)

2169

+ {

2170

+ l = alloca(strlen(operand_string) + 1);

2171

+ strcpy(l, operand_string);

2172

+ }

2173

+ __tl = l;

2174

+

2175

/* Check if an immediate #VALUE. The hash sign should be only at the beginning! */

2176

if (*l == '#')

2177

{

2178

@@ -943,100 +1332,27 @@ msp430_srcoperand (struct msp430_operand_s * op,

2179

parse_exp (__tl, &(op->exp));

2180

if (op->exp.X_op == O_constant)

2181

{

2182

- int x = op->exp.X_add_number;

2183

+ offsetT x = op->exp.X_add_number;

2184

+ int is_negative = 0 > x;

2185

2186

- if (vshift == 0)

2187

- {

2188

- x = x & 0xffff;

2189

- op->exp.X_add_number = x;

2190

- }

2191

- else if (vshift == 1)

2192

+ if (0 <= vshift)

2193

{

2194

- x = (x >> 16) & 0xffff;

2195

- op->exp.X_add_number = x;

2196

- }

2197

- else if (vshift > 1)

2198

- {

2199

- if (x < 0)

2200

- op->exp.X_add_number = -1;

2201

+ unsigned int shift_bits = vshift * 16;

2202

+ if (shift_bits < (8 * sizeof (x)))

2203

+ x >>= shift_bits;

2204

+ else

2205

+ x = 0;

2206

+ if (0 == x)

2207

+ op->exp.X_add_number = is_negative ? -1 : 0;

2208

else

2209

- op->exp.X_add_number = 0; /* Nothing left. */

2210

+ op->exp.X_add_number = x & 0xFFFF;

2211

x = op->exp.X_add_number;

2212

}

2213

-

2214

- if (op->exp.X_add_number > 65535 || op->exp.X_add_number < -32768)

2215

+ if (x >= imm_max || x < imm_min)

2216

{

2217

- as_bad (_("value %d out of range. Use #lo() or #hi()"), x);

2218

+ as_bad (_("value %ld out of %d...%d (0x%X...0x%X) range."), (long int)x, imm_min, imm_max - 1, imm_min, imm_max - 1);

2219

return 1;

2220

}

2221

-

2222

- /* Now check constants. */

2223

- /* Substitute register mode with a constant generator if applicable. */

2224

-

2225

- x = (short) x; /* Extend sign. */

2226

-

2227

- if (x == 0)

2228

- {

2229

- op->reg = 3;

2230

- op->am = 0;

2231

- op->ol = 0;

2232

- op->mode = OP_REG;

2233

- }

2234

- else if (x == 1)

2235

- {

2236

- op->reg = 3;

2237

- op->am = 1;

2238

- op->ol = 0;

2239

- op->mode = OP_REG;

2240

- }

2241

- else if (x == 2)

2242

- {

2243

- op->reg = 3;

2244

- op->am = 2;

2245

- op->ol = 0;

2246

- op->mode = OP_REG;

2247

- }

2248

- else if (x == -1)

2249

- {

2250

- op->reg = 3;

2251

- op->am = 3;

2252

- op->ol = 0;

2253

- op->mode = OP_REG;

2254

- }

2255

- else if (x == 4)

2256

- {

2257

-#ifdef PUSH_1X_WORKAROUND

2258

- if (bin == 0x1200)

2259

- {

2260

- /* Remove warning as confusing.

2261

- as_warn (_("Hardware push bug workaround")); */

2262

- }

2263

- else

2264

-#endif

2265

- {

2266

- op->reg = 2;

2267

- op->am = 2;

2268

- op->ol = 0;

2269

- op->mode = OP_REG;

2270

- }

2271

- }

2272

- else if (x == 8)

2273

- {

2274

-#ifdef PUSH_1X_WORKAROUND

2275

- if (bin == 0x1200)

2276

- {

2277

- /* Remove warning as confusing.

2278

- as_warn (_("Hardware push bug workaround")); */

2279

- }

2280

- else

2281

-#endif

2282

- {

2283

- op->reg = 2;

2284

- op->am = 3;

2285

- op->ol = 0;

2286

- op->mode = OP_REG;

2287

- }

2288

- }

2289

}

2290

else if (op->exp.X_op == O_symbol)

2291

{

2292

@@ -1044,12 +1360,10 @@ msp430_srcoperand (struct msp430_operand_s * op,

2293

}

2294

else if (op->exp.X_op == O_big)

2295

{

2296

- short x;

2297

if (vshift != -1)

2298

{

2299

op->exp.X_op = O_constant;

2300

op->exp.X_add_number = 0xffff & generic_bignum[vshift];

2301

- x = op->exp.X_add_number;

2302

}

2303

else

2304

{

2305

@@ -1058,49 +1372,6 @@ msp430_srcoperand (struct msp430_operand_s * op,

2306

l);

2307

return 1;

2308

}

2309

-

2310

- if (x == 0)

2311

- {

2312

- op->reg = 3;

2313

- op->am = 0;

2314

- op->ol = 0;

2315

- op->mode = OP_REG;

2316

- }

2317

- else if (x == 1)

2318

- {

2319

- op->reg = 3;

2320

- op->am = 1;

2321

- op->ol = 0;

2322

- op->mode = OP_REG;

2323

- }

2324

- else if (x == 2)

2325

- {

2326

- op->reg = 3;

2327

- op->am = 2;

2328

- op->ol = 0;

2329

- op->mode = OP_REG;

2330

- }

2331

- else if (x == -1)

2332

- {

2333

- op->reg = 3;

2334

- op->am = 3;

2335

- op->ol = 0;

2336

- op->mode = OP_REG;

2337

- }

2338

- else if (x == 4)

2339

- {

2340

- op->reg = 2;

2341

- op->am = 2;

2342

- op->ol = 0;

2343

- op->mode = OP_REG;

2344

- }

2345

- else if (x == 8)

2346

- {

2347

- op->reg = 2;

2348

- op->am = 3;

2349

- op->ol = 0;

2350

- op->mode = OP_REG;

2351

- }

2352

}

2353

/* Redundant (yet) check. */

2354

else if (op->exp.X_op == O_register)

2355

@@ -1127,7 +1398,7 @@ msp430_srcoperand (struct msp430_operand_s * op,

2356

{

2357

int x = op->exp.X_add_number;

2358

2359

- if (x > 65535 || x < -32768)

2360

+ if (x >= imm_max || x < imm_min)

2361

{

2362

as_bad (_("value out of range: %d"), x);

2363

return 1;

2364

@@ -1262,7 +1533,7 @@ msp430_srcoperand (struct msp430_operand_s * op,

2365

{

2366

int x = op->exp.X_add_number;

2367

2368

- if (x > 65535 || x < -32768)

2369

+ if (x > imm_max || x < imm_min)

2370

{

2371

as_bad (_("value out of range: %d"), x);

2372

return 1;

2373

@@ -1338,10 +1609,10 @@ msp430_srcoperand (struct msp430_operand_s * op,

2374

2375

2376

static int

2377

-msp430_dstoperand (struct msp430_operand_s * op, char * l, int bin)

2378

+msp430_dstoperand (struct msp430_operand_s * op, const char * l, int imm_min, int imm_max)

2379

{

2380

int dummy;

2381

- int ret = msp430_srcoperand (op, l, bin, & dummy);

2382

+ int ret = msp430_srcoperand (op, l, & dummy, imm_min, imm_max);

2383

2384

if (ret)

2385

return ret;

2386

@@ -1373,39 +1644,139 @@ msp430_dstoperand (struct msp430_operand_s * op, char * l, int bin)

2387

return 0;

2388

}

2389

2390

+static void

2391

+msp430_repeat_insn (int dummy ATTRIBUTE_UNUSED)

2392

+{

2393

+ char *operand = 0;

2394

+ struct msp430_operand_s op;

2395

+ int imm_op = 0;

2396

+ char *line = input_line_pointer;

2397

+

2398

+ if (msp430_cpu < MSP430_CPU_MSP430X)

2399

+ {

2400

+ as_bad (_("Repeatable instructions require 430X-based mcu"));

2401

+ goto done;

2402

+ }

2403

+

2404

+ if (msp430x_repeats)

2405

+ as_warn (_("two consecutive .rpt pseudo-ops. Previous .rpt discarded"));

2406

+

2407

+ if (!*line || *line == '\n')

2408

+ {

2409

+ as_bad (_("rpt pseudo-op requires 1 operand"));

2410

+ goto done;

2411

+ }

2412

+

2413

+ memset (&op, 0, sizeof (op));

2414

+ operand = get_operand ();

2415

+

2416

+ if (msp430_srcoperand(&op, operand, &imm_op, 1, 15) != 0)

2417

+ goto done;

2418

+

2419

+ if ( !(op.mode == OP_REG && op.am == 0) // Rn

2420

+ && !(op.mode == OP_EXP && op.am == 3) // #N

2421

+ )

2422

+ {

2423

+ as_bad (_("rpt pseudo-op requires immediate or register operand"));

2424

+ goto done;

2425

+ }

2426

+

2427

+ if (op.am == 0) // rpt Rn

2428

+ msp430x_repeats = (((1 << 7) | op.reg) << 1) | 1; // last bit as .rpt flag

2429

+ else // rpt #N

2430

+ msp430x_repeats = ((op.exp.X_add_number - 1) << 1) | 1; // last bit as .rpt flag

2431

+

2432

+ done:

2433

+ if (operand)

2434

+ xfree(operand);

2435

+}

2436

2437

/* Parse instruction operands.

2438

Return binary opcode. */

2439

2440

static unsigned int

2441

-msp430_operands (struct msp430_opcode_s * opcode, char * line)

2442

+msp430_operands (struct msp430_opcode_s const * opcode, char * line)

2443

{

2444

int bin = opcode->bin_opcode; /* Opcode mask. */

2445

int __is = 0;

2446

- char l1[MAX_OP_LEN], l2[MAX_OP_LEN];

2447

- char *frag;

2448

- int where;

2449

+ char *l1 = 0;

2450

+ char *l2 = 0;

2451

+ char *frag = 0;

2452

+ int where = 0;

2453

struct msp430_operand_s op1, op2;

2454

int res = 0;

2455

static short ZEROS = 0;

2456

- int byte_op, imm_op;

2457

-

2458

+ int imm_op;

2459

+ opwidth_t op_width = DEFAULT_OP;

2460

+

2461

/* Opcode is the one from opcodes table

2462

line contains something like

2463

[.w] @r2+, 5(R1)

2464

or

2465

- .b @r2+, 5(R1). */

2466

+ .b @r2+, 5(R1)

2467

+ or

2468

+ .a @r2+, 5(R1) */

2469

2470

/* Check if byte or word operation. */

2471

+

2472

if (*line == '.' && TOLOWER (*(line + 1)) == 'b')

2473

{

2474

- bin |= BYTE_OPERATION;

2475

- byte_op = 1;

2476

+ op_width = BYTE_OP;

2477

+ }

2478

+ else if (*line == '.' && TOLOWER (*(line + 1)) == 'w')

2479

+ {

2480

+ op_width = WORD_OP;

2481

+ }

2482

+ else if (*line == '.' && TOLOWER (*(line + 1)) == 'a')

2483

+ {

2484

+ op_width = ADDR_OP;

2485

}

2486

- else

2487

- byte_op = 0;

2488

2489

- /* skip .[bwBW]. */

2490

+ if ((op_width == WORD_OP && !(opcode_modifier(opcode) & MOD_W))

2491

+ || (op_width == BYTE_OP && !(opcode_modifier(opcode) & MOD_B))

2492

+ || (op_width == ADDR_OP && !(opcode_modifier(opcode) & MOD_A))

2493

+ )

2494

+ {

2495

+ static char* const modifier[] = { "", ".w", ".b", ".a" };

2496

+ as_bad (_("%s not allowed with %s instruction"),

2497

+ modifier[op_width], opcode->name);

2498

+ return 0;

2499

+ }

2500

+

2501

+ if ( opcode_format(opcode) == FMT_X_DOUBLE_OPERAND

2502

+ || opcode_format(opcode) == FMT_X_SINGLE_OPERAND

2503

+ || opcode_format(opcode) == FMT_X_EMULATED

2504

+ )

2505

+ {

2506

+ switch(op_width)

2507

+ {

2508

+ case DEFAULT_OP:

2509

+ case WORD_OP:

2510

+ bin |= NON_ADDR_OPERATION;

2511

+ break;

2512

+ case BYTE_OP:

2513

+ bin |= NON_ADDR_OPERATION;

2514

+ bin |= BYTE_OPERATION_X;

2515

+ break;

2516

+ case ADDR_OP:

2517

+ bin |= BYTE_OPERATION_X;

2518

+ break;

2519

+ }

2520

+ }

2521

+ else

2522

+ {

2523

+ if(msp430x_repeats)

2524

+ {

2525

+ as_bad (_("%s instruction is not repeatable"), opcode->name);

2526

+ return 0;

2527

+ }

2528

+

2529

+ if ( opcode_format(opcode) < FMT_X && op_width == BYTE_OP ) // 430 instructions

2530

+ {

2531

+ bin |= BYTE_OPERATION;

2532

+ }

2533

+ }

2534

+ /* skip .[abwABW]. */

2535

while (! ISSPACE (*line) && *line)

2536

line++;

2537

2538

@@ -1416,29 +1787,29 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)

2539

return 0;

2540

}

2541

2542

- memset (l1, 0, sizeof (l1));

2543

- memset (l2, 0, sizeof (l2));

2544

+ input_line_pointer = line;

2545

+

2546

memset (&op1, 0, sizeof (op1));

2547

memset (&op2, 0, sizeof (op2));

2548

2549

imm_op = 0;

2550

2551

- switch (opcode->fmt)

2552

+ switch (opcode_format(opcode))

2553

{

2554

- case 0: /* Emulated. */

2555

- switch (opcode->insn_opnumb)

2556

+ case FMT_EMULATED: /* Emulated. */

2557

+ switch (opcode_variant(opcode))

2558

{

2559

- case 0:

2560

- /* Set/clear bits instructions. */

2561

+ case V_NOOP:

2562

+ /* Set/clear SR bits instructions, ret, nop */

2563

__is = 2;

2564

frag = frag_more (__is);

2565

bfd_putl16 ((bfd_vma) bin, frag);

2566

dwarf2_emit_insn (__is);

2567

break;

2568

- case 1:

2569

+ case V_NONE:

2570

/* Something which works with destination operand. */

2571

- line = extract_operand (line, l1, sizeof (l1));

2572

- res = msp430_dstoperand (&op1, l1, opcode->bin_opcode);

2573

+ l1 = get_operand ();

2574

+ res = msp430_dstoperand (&op1, l1, -(1<<15), (1<<16) );

2575

if (res)

2576

break;

2577

2578

@@ -1463,14 +1834,13 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)

2579

}

2580

break;

2581

2582

- case 2:

2583

+ case V_SHIFT:

2584

{

2585

/* Shift instruction. */

2586

- line = extract_operand (line, l1, sizeof (l1));

2587

- strncpy (l2, l1, sizeof (l2));

2588

- l2[sizeof (l2) - 1] = '\0';

2589

- res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op);

2590

- res += msp430_dstoperand (&op2, l2, opcode->bin_opcode);

2591

+ l1 = get_operand ();

2592

+ res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<15), (1<<16));

2593

+ msp430_substitute_CG(&op1, 0);

2594

+ res += msp430_dstoperand (&op2, l1, -(1<<15), (1<<16));

2595

2596

if (res)

2597

break; /* An error occurred. All warnings were done before. */

2598

@@ -1498,7 +1868,12 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)

2599

2600

if (op2.mode == OP_EXP)

2601

{

2602

- imm_op = 0;

2603

+ /*

2604

+ x(Rn). x can be odd in non-byte operations

2605

+ except x(R2) = x(0) = &TONI and x(PC) = TONI

2606

+ */

2607

+ imm_op = (op2.mode == 1 && op2.reg != 2 && op2.reg != 0);

2608

+

2609

bfd_putl16 ((bfd_vma) ZEROS, frag + 2 + ((__is == 3) ? 2 : 0));

2610

2611

if (op2.reg) /* Not PC relative. */

2612

@@ -1510,16 +1885,20 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)

2613

}

2614

break;

2615

}

2616

- case 3:

2617

+ case V_BR:

2618

/* Branch instruction => mov dst, r0. */

2619

- line = extract_operand (line, l1, sizeof (l1));

2620

-

2621

- res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op);

2622

+ l1 = get_operand ();

2623

+ res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<15), (1<<16));

2624

+ msp430_substitute_CG(&op1, 0);

2625

if (res)

2626

break;

2627

2628

- byte_op = 0;

2629

- imm_op = 0;

2630

+ if (op1.mode == 1 && (op1.reg == 2 || op1.reg == 0))

2631

+ /*

2632

+ x(Rn). x can be odd in non-byte operations

2633

+ except x(R2) = x(0) = &EDE and x(PC) = EDE

2634

+ */

2635

+ imm_op = 0;

2636

2637

bin |= ((op1.reg << 8) | (op1.am << 4));

2638

__is = 1 + op1.ol;

2639

@@ -1544,11 +1923,12 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)

2640

}

2641

break;

2642

2643

- case 1: /* Format 1, double operand. */

2644

- line = extract_operand (line, l1, sizeof (l1));

2645

- line = extract_operand (line, l2, sizeof (l2));

2646

- res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op);

2647

- res += msp430_dstoperand (&op2, l2, opcode->bin_opcode);

2648

+ case FMT_DOUBLE_OPERAND: /* Format 1, double operand. */

2649

+ l1 = get_operand ();

2650

+ l2 = get_operand ();

2651

+ res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<15), (1<<16));

2652

+ msp430_substitute_CG(&op1, 0);

2653

+ res += msp430_dstoperand (&op2, l2, -(1<<15), (1<<16));

2654

2655

if (res)

2656

break; /* Error occurred. All warnings were done before. */

2657

@@ -1576,7 +1956,12 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)

2658

2659

if (op2.mode == OP_EXP)

2660

{

2661

- imm_op = 0;

2662

+ /*

2663

+ x(Rn). x can be odd in non-byte operations

2664

+ except x(R2) = x(0) = &TONI and x(PC) = TONI

2665

+ */

2666

+ imm_op = (op2.mode == 1 && op2.reg != 2 && op2.reg != 0);

2667

+

2668

bfd_putl16 ((bfd_vma) ZEROS, frag + 2 + ((__is == 3) ? 2 : 0));

2669

2670

if (op2.reg) /* Not PC relative. */

2671

@@ -1588,8 +1973,8 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)

2672

}

2673

break;

2674

2675

- case 2: /* Single-operand mostly instr. */

2676

- if (opcode->insn_opnumb == 0)

2677

+ case FMT_SINGLE_OPERAND: /* Single-operand mostly instr. */

2678

+ if (opcode_variant(opcode) == V_RETI)

2679

{

2680

/* reti instruction. */

2681

frag = frag_more (2);

2682

@@ -1598,10 +1983,11 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)

2683

break;

2684

}

2685

2686

- line = extract_operand (line, l1, sizeof (l1));

2687

- res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op);

2688

+ l1 = get_operand ();

2689

+ res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<15), (1<<16));

2690

if (res)

2691

break; /* Error in operand. */

2692

+ msp430_substitute_CG(&op1, erratum_applies(ERRATUM_CPU4) && (opcode->bin_opcode == 0x1200));

2693

2694

bin |= op1.reg | (op1.am << 4);

2695

__is = 1 + op1.ol;

2696

@@ -1623,8 +2009,8 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)

2697

}

2698

break;

2699

2700

- case 3: /* Conditional jumps instructions. */

2701

- line = extract_operand (line, l1, sizeof (l1));

2702

+ case FMT_JUMP: /* Conditional jumps instructions. */

2703

+ l1 = get_operand ();

2704

/* l1 is a label. */

2705

if (l1[0])

2706

{

2707

@@ -1693,11 +2079,13 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)

2708

else if (*l1 == '$')

2709

{

2710

as_bad (_("instruction requires label sans '$'"));

2711

+ break;

2712

}

2713

else

2714

{

2715

as_bad (_

2716

("instruction requires label or value in range -511:512"));

2717

+ break;

2718

}

2719

dwarf2_emit_insn (2 * __is);

2720

break;

2721

@@ -1709,14 +2097,14 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)

2722

}

2723

break;

2724

2725

- case 4: /* Extended jumps. */

2726

+ case FMT_EMULATED_POLYMORPH_JUMP: /* Extended jumps. */

2727

if (!msp430_enable_polys)

2728

{

2729

as_bad (_("polymorphs are not enabled. Use -mP option to enable."));

2730

break;

2731

}

2732

2733

- line = extract_operand (line, l1, sizeof (l1));

2734

+ l1 = get_operand ();

2735

if (l1[0])

2736

{

2737

char *m = l1;

2738

@@ -1730,7 +2118,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)

2739

if (exp.X_op == O_symbol)

2740

{

2741

/* Relaxation required. */

2742

- struct rcodes_s rc = msp430_rcodes[opcode->insn_opnumb];

2743

+ struct rcodes_s rc = msp430_rcodes[opcode_variant(opcode)];

2744

2745

/* The parameter to dwarf2_emit_insn is actually the offset to the start

2746

of the insn from the fix piece of instruction that was emitted.

2747

@@ -1751,13 +2139,13 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)

2748

as_bad (_("instruction requires label"));

2749

break;

2750

2751

- case 5: /* Emulated extended branches. */

2752

+ case FMT_EMULATED_LONG_POLYMORPH_JUMP: /* Emulated extended branches. */

2753

if (!msp430_enable_polys)

2754

{

2755

as_bad (_("polymorphs are not enabled. Use -mP option to enable."));

2756

break;

2757

}

2758

- line = extract_operand (line, l1, sizeof (l1));

2759

+ l1 = get_operand ();

2760

if (l1[0])

2761

{

2762

char * m = l1;

2763

@@ -1771,7 +2159,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)

2764

if (exp.X_op == O_symbol)

2765

{

2766

/* Relaxation required. */

2767

- struct hcodes_s hc = msp430_hcodes[opcode->insn_opnumb];

2768

+ struct hcodes_s hc = msp430_hcodes[opcode_variant(opcode)];

2769

2770

frag = frag_more (8);

2771

dwarf2_emit_insn (0);

2772

@@ -1790,42 +2178,716 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)

2773

as_bad (_("instruction requires label"));

2774

break;

2775

2776

+ case FMT_X_DOUBLE_OPERAND: /* Extended Format 1 ( double operand). */

2777

+ l1 = get_operand ();

2778

+ l2 = get_operand ();

2779

+ res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<19), (1<<20));

2780

+ msp430_substitute_CG(&op1, 0);

2781

+ res += msp430_dstoperand (&op2, l2, -(1<<19), (1<<20));

2782

+

2783

+ if (res)

2784

+ break; /* Error occurred. All warnings were done before. */

2785

+

2786

+ if (msp430x_repeats)

2787

+ {

2788

+ if (op1.mode != OP_REG || op2.mode != OP_REG)

2789

+ {

2790

+ as_bad(_("Repeated instruction must have register mode operands"));

2791

+ break;

2792

+ }

2793

+ bin |= msp430x_repeats >> 1;

2794

+ msp430x_repeats = 0;

2795

+ }

2796

+

2797

+ bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7)) << 16;

2798

+

2799

+ __is = 2 + op1.ol + op2.ol; /* insn size in words, opcode is 2 words wide. */

2800

+ frag = frag_more (2 * __is);

2801

+ where = frag - frag_now->fr_literal;

2802

+ bfd_putl32 ((bfd_vma) bin, frag);

2803

+ dwarf2_emit_insn (2 * __is);

2804

+

2805

+ if (op1.mode == OP_EXP)

2806

+ {

2807

+ bfd_putl16 ((bfd_vma) ZEROS, frag + 4);

2808

+

2809

+ if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */

2810

+ fix_new_exp (frag_now, where, 2,

2811

+ &(op1.exp), FALSE, CHECK_RELOC_MSP430X_SRC);

2812

+ else

2813

+ fix_new_exp (frag_now, where , 2,

2814

+ &(op1.exp), TRUE, CHECK_RELOC_MSP430X_PCREL_SRC);

2815

+ }

2816

+

2817

+ if (op2.mode == OP_EXP)

2818

+ {

2819

+ /*

2820

+ x(Rn). x can be odd in non-byte operations

2821

+ except x(R2) = x(0) = &TONI and x(PC) = TONI

2822

+ */

2823

+ imm_op = (op2.mode == 1 && op2.reg != 2 && op2.reg != 0);

2824

+ bfd_putl16 ((bfd_vma) ZEROS, frag + 4 + ((__is == 4) ? 2 : 0));

2825

+

2826

+ if (op1.mode == OP_EXP)

2827

+ {

2828

+ if (op2.reg) /* Not PC relative. */

2829

+ fix_new_exp (frag_now, where, 2,

2830

+ &(op2.exp), FALSE, CHECK_RELOC_MSP430X_DST_2ND);

2831

+ else

2832

+ fix_new_exp (frag_now, where, 2,

2833

+ &(op2.exp), TRUE, CHECK_RELOC_MSP430X_PCREL_DST_2ND);

2834

+ }

2835

+ else

2836

+ {

2837

+ if (op2.reg) /* Not PC relative. */

2838

+ fix_new_exp (frag_now, where, 2,

2839

+ &(op2.exp), FALSE, CHECK_RELOC_MSP430X_DST);

2840

+ else

2841

+ fix_new_exp (frag_now, where, 2,

2842

+ &(op2.exp), TRUE, CHECK_RELOC_MSP430X_PCREL_DST);

2843

+ }

2844

+ }

2845

+ break;

2846

+

2847

+ case FMT_X_SINGLE_OPERAND: /* Extended format 2 (single-operand). */

2848

+ l1 = get_operand ();

2849

+ res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<19), (1<<20));

2850

+ msp430_substitute_CG(&op1, 0);

2851

+ if (res)

2852

+ break; /* Error in operand. */

2853

+

2854

+ if (opcode_variant(opcode) != V_PUSHX && op1.mode == OP_EXP && op1.am == 3) // #N

2855

+ {

2856

+ as_bad (_("bad operand [%s]"), l1);

2857

+ break;

2858

+ }

2859

+

2860

+ if (msp430x_repeats)

2861

+ {

2862

+ if (op1.mode != OP_REG)

2863

+ {

2864

+ as_bad(_("Repeated instruction must have register mode operand"));

2865

+ break;

2866

+ }

2867

+ bin |= msp430x_repeats >> 1;

2868

+ msp430x_repeats = 0;

2869

+ }

2870

+

2871

+ if(opcode_variant(opcode) == V_SWPSXT && op_width == ADDR_OP)

2872

+ { // sxtx.a | swpbx.a opcode

2873

+ bin ^= BYTE_OPERATION_X;

2874

+ }

2875

+

2876

+ bin |= (op1.reg | (op1.am << 4)) << 16;

2877

+ __is = 2 + op1.ol; /* insn size in words, opcode is 2 words wide. */

2878

+ frag = frag_more (2 * __is);

2879

+ where = frag - frag_now->fr_literal;

2880

+ bfd_putl32 ((bfd_vma) bin, frag);

2881

+ dwarf2_emit_insn (2 * __is);

2882

+

2883

+ if (op1.mode == OP_EXP)

2884

+ {

2885

+ bfd_putl16 ((bfd_vma) ZEROS, frag + 4);

2886

+

2887

+ if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */

2888

+ fix_new_exp (frag_now, where, 2,

2889

+ &(op1.exp), FALSE, CHECK_RELOC_MSP430X_DST);

2890

+ else

2891

+ fix_new_exp (frag_now, where, 2,

2892

+ &(op1.exp), TRUE, CHECK_RELOC_MSP430X_PCREL_DST);

2893

+ }

2894

+ break;

2895

+

2896

+ case FMT_X_EXCEPTION:

2897

+ /* calla, pushm, popm, rrcm, rrum, rram, rlam */

2898

+ bin = opcode->bin_opcode; // remove WB/AL bits

2899

+ l1 = get_operand ();

2900

+ switch(opcode_variant(opcode))

2901

+ {

2902

+ case V_CALLA: // calla

2903

+ res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<19), (1<<20));

2904

+ if (res)

2905

+ break; /* Error in operand. */

2906

+ __is = 1 + op1.ol;

2907

+ frag = frag_more(__is * 2);

2908

+

2909

+ if (op1.mode == OP_REG)

2910

+ {

2911

+ bin |= op1.reg;

2912

+ switch (op1.am)

2913

+ {

2914

+ case 0: // Rdst

2915

+ bin |= 0x0040;

2916

+ break;

2917

+ case 2: // @Rdst

2918

+ bin |= 0x0060;

2919

+ break;

2920

+ case 3: // @Rdst+

2921

+ bin |= 0x0070;

2922

+ break;

2923

+ }

2924

+ bin |= op1.reg;

2925

+ bfd_putl16 ((bfd_vma) bin, frag);

2926

+ dwarf2_emit_insn (__is * 2);

2927

+ }

2928

+ else if (op1.mode == OP_EXP)

2929

+ {

2930

+ bfd_putl16 ((bfd_vma) ZEROS, frag + 2);

2931

+ where = frag - frag_now->fr_literal;

2932

+ switch (op1.am)

2933

+ {

2934

+ case 1:

2935

+ switch(op1.reg)

2936

+ {

2937

+ case 0: // x(PC) = EDE

2938

+ bin |= 0x0090;

2939

+ bfd_putl16 ((bfd_vma) bin, frag);

2940

+ fix_new_exp (frag_now, where, 2,

2941

+ &(op1.exp), TRUE, BFD_RELOC_MSP430X_PCREL_D);

2942

+ break;

2943

+ case 2: // &abs20

2944

+ bin |= 0x0080;

2945

+ bfd_putl16 ((bfd_vma) bin, frag);

2946

+ fix_new_exp (frag_now, where, 2,

2947

+ &(op1.exp), FALSE, BFD_RELOC_MSP430X_D);

2948

+ break;

2949

+ default: //z16(Rdst)

2950

+ bin |= 0x0050 | op1.reg;

2951

+ bfd_putl16 ((bfd_vma) bin, frag);

2952

+ fix_new_exp (frag_now, where, 2,

2953

+ &(op1.exp), FALSE, BFD_RELOC_MSP430X_INDXD);

2954

+ break;

2955

+ }

2956

+ break;

2957

+ case 3: // calla #imm

2958

+ bin |= 0x00b0;

2959

+ bfd_putl16 ((bfd_vma) bin, frag);

2960

+ fix_new_exp (frag_now, where, 2,

2961

+ &(op1.exp), FALSE, BFD_RELOC_MSP430X_D);

2962

+ break;

2963

+ }

2964

+ dwarf2_emit_insn (__is * 2);

2965

+ }

2966

+ break;

2967

+ case V_ROTM: // rxxm

2968

+ l2 = get_operand ();

2969

+ res = msp430_srcoperand (&op1, l1, &imm_op, 1, 5);

2970

+ res += msp430_dstoperand (&op2, l2, -(1<<19), (1<<20));

2971

+ if(res)

2972

+ break; /* An error occurred. All warnings were done before. */

2973

+

2974

+ if(op_width != ADDR_OP)

2975

+ bin |= (1 << 4);

2976

+

2977

+ if(op1.mode != OP_EXP || op1.am != 3) // not #imm

2978

+ {

2979

+ as_bad (_("bad operand [%s]"), l1);

2980

+ break;

2981

+ }

2982

+

2983

+ bin |= ((op1.exp.X_add_number - 1) & 0x0003) << 10;

2984

+

2985

+ if(op2.mode != OP_REG)

2986

+ {

2987

+ as_bad (_("bad operand [%s]"), l2);

2988

+ break;

2989

+ }

2990

+ bin |= op2.reg;

2991

+

2992

+ frag = frag_more (2);

2993

+ bfd_putl16 ((bfd_vma) bin, frag);

2994

+ dwarf2_emit_insn (2);

2995

+ break;

2996

+ case V_PUSHM:

2997

+ case V_POPM:

2998

+ l2 = get_operand ();

2999

+ res = msp430_srcoperand (&op1, l1, &imm_op, 1, 17);

3000

+ res += msp430_dstoperand (&op2, l2, -(1<<19), (1<<20));

3001

+ if(res)

3002

+ break; /* An error occurred. All warnings were done before. */

3003

+

3004

+

3005

+ if(imm_op == 0)

3006

+ {

3007

+ as_bad (_("bad operand [%s]"), l1);

3008

+ break;

3009

+ }

3010

+

3011

+ if(op_width != ADDR_OP)

3012

+ {

3013

+ bin |= (1 << 8);

3014

+ }

3015

+ bin |= ((op1.exp.X_add_number - 1) & 0x000F) << 4;

3016

+

3017

+ if(op2.mode != OP_REG)

3018

+ {

3019

+ as_bad (_("bad operand [%s]"), l2);

3020

+ break;

3021

+ }

3022

+ if(opcode_variant(opcode) == V_POPM)

3023

+ {

3024

+ /* popm */

3025

+ bin |= (op2.reg - op1.exp.X_add_number + 1) & 0x000F;

3026

+ }

3027

+ else

3028

+ {

3029

+ /* pushm */

3030

+ bin |= op2.reg;

3031

+ }

3032

+

3033

+ frag = frag_more (2);

3034

+ bfd_putl16 ((bfd_vma) bin, frag);

3035

+ dwarf2_emit_insn (2);

3036

+ break;

3037

+ }

3038

+ break;

3039

+ case FMT_X_ADDRESS:

3040

+ /* mova, adda, suba, cmpa */

3041

+ l1 = get_operand ();

3042

+ l2 = get_operand ();

3043

+ res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<19), (1<<20));

3044

+ res += msp430_dstoperand (&op2, l2, -(1<<19), (1<<20));

3045

+ if (res)

3046

+ break; /* Error in operand. */

3047

+

3048

+ __is = 1 + op1.ol + op2.ol;

3049

+ frag = frag_more(__is * 2);

3050

+ where = frag - frag_now->fr_literal;

3051

+ bin = opcode->bin_opcode; // remove WB/AL bits

3052

+ if( opcode_variant(opcode) == V_MOVA)

3053

+ {

3054

+ if (op1.mode == OP_REG && op1.am == 0)

3055

+ { // Rsrc

3056

+ if(op2.mode == OP_REG && op2.am == 0)

3057

+ {

3058

+ // mova Rsrc, Rdst

3059

+ bin |= 0x00c0 | op1.reg << 8 | op2.reg;

3060

+ bfd_putl16 ((bfd_vma) bin, frag);

3061

+ dwarf2_emit_insn (__is * 2);

3062

+ }

3063

+ else if(op2.mode == OP_EXP && op2.am == 1 && op2.reg == 2)

3064

+ {

3065

+ // mova Rsrc, &abs20

3066

+ bin |= 0x0060 | op1.reg << 8;

3067

+ bfd_putl16 ((bfd_vma) bin, frag);

3068

+ dwarf2_emit_insn (__is * 2);

3069

+ bfd_putl16 ((bfd_vma) ZEROS, frag + 2);

3070

+ fix_new_exp (frag_now, where, 2,

3071

+ &(op2.exp), FALSE, BFD_RELOC_MSP430X_D);

3072

+ }

3073

+ else if(op2.mode == OP_EXP && op2.am == 1 && op2.reg == 0)

3074

+ {

3075

+ bin |= 0x0070 | op1.reg << 8;

3076

+ bfd_putl16 ((bfd_vma) bin, frag);

3077

+ dwarf2_emit_insn (__is * 2);

3078

+ bfd_putl16 ((bfd_vma) ZEROS, frag + 2);

3079

+ fix_new_exp (frag_now, where, 2,

3080

+ &(op2.exp), TRUE, BFD_RELOC_MSP430X_PCREL_D);

3081

+ }

3082

+ else if(op2.mode == OP_EXP && op2.am == 1)

3083

+ {

3084

+ // mova Rsrc, z16(Rdst)

3085

+ bin |= 0x0070 | op1.reg << 8 | op2.reg;

3086

+ bfd_putl16 ((bfd_vma) bin, frag);

3087

+ dwarf2_emit_insn (__is * 2);

3088

+ bfd_putl16 ((bfd_vma) ZEROS, frag + 2);

3089

+ if(op2.reg == 0)

3090

+ // mova Rsrc, TONI == mova Rsrc, z16(PC)

3091

+ fix_new_exp (frag_now, where, 2,

3092

+ &(op2.exp), TRUE, BFD_RELOC_MSP430X_PCREL_INDXD);

3093

+ else

3094

+ fix_new_exp (frag_now, where, 2,

3095

+ &(op2.exp), FALSE, BFD_RELOC_MSP430X_INDXD);

3096

+ }

3097

+ else

3098

+ as_bad (_("destination operand address mode not allowed with mova instruction"));

3099

+

3100

+ }

3101

+ else if (op2.mode == OP_REG && op2.am == 0)

3102

+ { // Rdst

3103

+ if(op1.mode == OP_REG && op1.am == 2)

3104

+ {

3105

+ // mova @Rsrc, Rdst

3106

+ bin |= 0x0000 | op1.reg << 8 | op2.reg;

3107

+ bfd_putl16 ((bfd_vma) bin, frag);

3108

+ dwarf2_emit_insn (__is * 2);

3109

+ }

3110

+ else if (op1.mode == OP_REG && op1.am == 3)

3111

+ {

3112

+ // mova @Rsrc+, Rdst

3113

+ bin |= 0x0010 | op1.reg << 8 | op2.reg;

3114

+ bfd_putl16 ((bfd_vma) bin, frag);

3115

+ dwarf2_emit_insn (__is * 2);

3116

+ }

3117

+ else if (op1.mode == OP_EXP && op1.am == 1 && op1.reg == 2)

3118

+ {

3119

+ if (op1.reg == 2)

3120

+ {

3121

+ // mova &abs20, Rdst

3122

+ bin |= 0x0020 | op2.reg;

3123

+ bfd_putl16 ((bfd_vma) bin, frag);

3124

+ dwarf2_emit_insn (__is * 2);

3125

+ bfd_putl16 ((bfd_vma) ZEROS, frag + 2);

3126

+ fix_new_exp (frag_now, where, 2,

3127

+ &(op1.exp), FALSE, BFD_RELOC_MSP430X_S);

3128

+ }

3129

+ else

3130

+ {

3131

+ // mova z16(Rsrc), Rdst

3132

+ bin |= 0x0030 | op1.reg << 8 | op2.reg;

3133

+ bfd_putl16 ((bfd_vma) bin, frag);

3134

+ dwarf2_emit_insn (__is * 2);

3135

+ bfd_putl16 ((bfd_vma) ZEROS, frag + 2);

3136

+ if (op1.reg == 0)

3137

+ // mova TONI, Rdst

3138

+ fix_new_exp (frag_now, where, 2,

3139

+ &(op1.exp), FALSE, BFD_RELOC_MSP430X_PCREL_INDXD);

3140

+ else

3141

+ fix_new_exp (frag_now, where, 2,

3142

+ &(op1.exp), FALSE, BFD_RELOC_MSP430X_INDXD);

3143

+ }

3144

+ }

3145

+ else if (op1.mode == OP_EXP && op1.am == 3)

3146

+ {

3147

+ // mova #imm20, Rdst

3148

+ bin |= 0x0080 | op2.reg;

3149

+ bfd_putl16 ((bfd_vma) bin, frag);

3150

+ dwarf2_emit_insn (__is * 2);

3151

+ bfd_putl16 ((bfd_vma) ZEROS, frag + 2);

3152

+ if (op2.reg == 0)

3153

+ fix_new_exp (frag_now, where, 2,

3154

+ &(op1.exp), FALSE, BFD_RELOC_MSP430X_S);

3155

+ else

3156

+ fix_new_exp (frag_now, where, 2,

3157

+ &(op1.exp), FALSE, BFD_RELOC_MSP430X_S_BYTE);

3158

+ }

3159

+ else

3160

+ as_bad (_("source operand address mode not allowed with mova instruction"));

3161

+ }

3162

+ break;

3163

+ }

3164

+ else

3165

+ /* adda, suba, cmpa */

3166

+ {

3167

+ if(op2.mode == OP_REG && op2.am == 0)

3168

+ {

3169

+ if (op1.mode == OP_REG && op1.am == 0)

3170

+ { // Rsrc, Rdst

3171

+ bin |= 0x0040 | op1.reg << 8 | op2.reg;

3172

+ bfd_putl16 ((bfd_vma) bin, frag);

3173

+ dwarf2_emit_insn (__is * 2);

3174

+ }

3175

+ else if (op1.mode == OP_EXP && op1.am == 3)

3176

+ {

3177

+ // #imm20, Rdst

3178

+ bin |= 0x0080 | op2.reg;

3179

+ bfd_putl16 ((bfd_vma) bin, frag);

3180

+ dwarf2_emit_insn (__is * 2);

3181

+ bfd_putl16 ((bfd_vma) ZEROS, frag + 2);

3182

+ if (op2.reg == 0)

3183

+ fix_new_exp (frag_now, where, 2,

3184

+ &(op1.exp), FALSE, BFD_RELOC_MSP430X_S);

3185

+ else

3186

+ fix_new_exp (frag_now, where, 2,

3187

+ &(op1.exp), FALSE, BFD_RELOC_MSP430X_S_BYTE);

3188

+ }

3189

+ else

3190

+ as_bad (_("source operand address mode not allowed with %s instruction"), opcode->name);

3191

+ }

3192

+ else

3193

+ as_bad (_("destination operand address mode not allowed with %s instruction"), opcode->name);

3194

+ break;

3195

+ }

3196

+ break;

3197

+

3198

+ case FMT_X_EMULATED: /* Extended emulated. */

3199

+ switch (opcode_variant(opcode))

3200

+ {

3201

+ case V_NONE:

3202

+ /* single operand instruction emulated with Extended type 1 (double operand) instructions. */

3203

+ l1 = get_operand ();

3204

+ res = msp430_dstoperand (&op1, l1, -(1<<19), (1<<20) );

3205

+ if (res)

3206

+ break;

3207

+

3208

+ if (msp430x_repeats)

3209

+ {

3210

+ if ((bin >> 20) && 0x3 == 1)

3211

+ {

3212

+ as_bad (_("%s instruction is not repeatable"), opcode->name);

3213

+ break;

3214

+ }

3215

+ if (op1.mode != OP_REG)

3216

+ {

3217

+ as_bad(_("Repeated instruction must have register mode operand"));

3218

+ break;

3219

+ }

3220

+ bin |= msp430x_repeats >> 1;

3221

+ msp430x_repeats = 0;

3222

+ }

3223

+

3224

+ bin |= (op1.reg | (op1.am << 7)) << 16;

3225

+ __is = 2 + op1.ol;

3226

+ frag = frag_more (2 * __is);

3227

+ where = frag - frag_now->fr_literal;

3228

+ bfd_putl32 ((bfd_vma) bin, frag);

3229

+ dwarf2_emit_insn (2 * __is);

3230

+

3231

+ if (op1.mode == OP_EXP)

3232

+ {

3233

+ /*

3234

+ x(Rn). x can be odd in non-byte operations

3235

+ except x(R2) = x(0) = &TONI and x(PC) = TONI

3236

+ */

3237

+ imm_op = (op2.mode == 1 && op2.reg != 2 && op2.reg != 0);

3238

+

3239

+ bfd_putl16 ((bfd_vma) ZEROS, frag + 4);

3240

+ if (op1.reg || (op1.reg == 0 && op1.am == 3))

3241

+ fix_new_exp (frag_now, where, 2,

3242

+ &(op1.exp), FALSE, CHECK_RELOC_MSP430X_DST);

3243

+ else

3244

+ fix_new_exp (frag_now, where, 2,

3245

+ &(op1.exp), TRUE, CHECK_RELOC_MSP430X_PCREL_DST);

3246

+ }

3247

+ break;

3248

+ case V_X_SHIFT:

3249

+ {

3250

+ /* Shift instruction. */

3251

+ l1 = get_operand ();

3252

+ res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<19), (1<<20));

3253

+ msp430_substitute_CG(&op1, 0);

3254

+ res += msp430_dstoperand (&op2, l1, -(1<<19), (1<<20));

3255

+

3256

+ if (res)

3257

+ break; /* An error occurred. All warnings were done before. */

3258

+

3259

+ if (msp430x_repeats)

3260

+ {

3261

+ if (op2.mode != OP_REG)

3262

+ {

3263

+ as_bad(_("Repeated instruction must have register mode operands"));

3264

+ break;

3265

+ }

3266

+ bin |= msp430x_repeats >> 1;

3267

+ msp430x_repeats = 0;

3268

+ }

3269

+

3270

+ bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7)) << 16;

3271

+

3272

+ __is = 2 + op1.ol + op2.ol; /* insn size in words. */

3273

+ frag = frag_more (2 * __is);

3274

+ where = frag - frag_now->fr_literal;

3275

+ bfd_putl32 ((bfd_vma) bin, frag);

3276

+ dwarf2_emit_insn (2 * __is);

3277

+

3278

+ if (op1.mode == OP_EXP)

3279

+ {

3280

+ bfd_putl16 ((bfd_vma) ZEROS, frag + 4);

3281

+

3282

+ if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */

3283

+ fix_new_exp (frag_now, where, 2,

3284

+ &(op1.exp), FALSE, CHECK_RELOC_MSP430X_SRC);

3285

+ else

3286

+ fix_new_exp (frag_now, where, 2,

3287

+ &(op1.exp), TRUE, CHECK_RELOC_MSP430X_PCREL_SRC);

3288

+ }

3289

+

3290

+ if (op2.mode == OP_EXP)

3291

+ {

3292

+ /*

3293

+ x(Rn). x can be odd in non-byte operations

3294

+ except x(R2) = x(0) = &TONI and x(PC) = TONI

3295

+ */

3296

+ imm_op = (op2.mode == 1 && op2.reg != 2 && op2.reg != 0);

3297

+

3298

+ bfd_putl16 ((bfd_vma) ZEROS, frag + 4 + ((__is == 4) ? 2 : 0));

3299

+ if (op1.mode == OP_EXP)

3300

+ {

3301

+

3302

+ if (op2.reg) /* Not PC relative. */

3303

+ fix_new_exp (frag_now, where, 2,

3304

+ &(op2.exp), FALSE, CHECK_RELOC_MSP430X_DST_2ND);

3305

+ else

3306

+ fix_new_exp (frag_now, where, 2,

3307

+ &(op2.exp), TRUE, CHECK_RELOC_MSP430X_PCREL_DST_2ND);

3308

+ }

3309

+ else

3310

+ {

3311

+

3312

+ if (op2.reg) /* Not PC relative. */

3313

+ fix_new_exp (frag_now, where, 2,

3314

+ &(op2.exp), FALSE, CHECK_RELOC_MSP430X_DST);

3315

+ else

3316

+ fix_new_exp (frag_now, where, 2,

3317

+ &(op2.exp), TRUE, CHECK_RELOC_MSP430X_PCREL_DST);

3318

+ }

3319

+ }

3320

+ }

3321

+ break;

3322

+ case V_RETA:

3323

+ /* reta */

3324

+ if (msp430x_repeats)

3325

+ {

3326

+ as_bad (_("%s instruction is not repeatable"), opcode->name);

3327

+ break;

3328

+ }

3329

+ bin = opcode->bin_opcode; // remove WB/AL bits

3330

+ frag = frag_more (2);

3331

+ bfd_putl16 ((bfd_vma) bin, frag);

3332

+ dwarf2_emit_insn (2);

3333

+ break;

3334

+ case V_EMU_ADDR: // incda, decda, tsta

3335

+ if (msp430x_repeats)

3336

+ {

3337

+ as_bad (_("%s instruction is not repeatable"), opcode->name);

3338

+ break;

3339

+ }

3340

+ bin = opcode->bin_opcode; // remove WB/AL bits

3341

+ l1 = get_operand ();

3342

+ res = msp430_dstoperand (&op1, l1, -(1<<19), (1<<20) );

3343

+ if (res)

3344

+ break;

3345

+

3346

+ if(op1.mode == OP_REG && op1.am == 0)

3347

+ {

3348

+ frag = frag_more(2);

3349

+ bin |= op1.reg;

3350

+ bfd_putl16 ((bfd_vma) bin, frag);

3351

+ dwarf2_emit_insn (2);

3352

+ }

3353

+ else

3354

+ as_bad (_("destination operand address mode not allowed with %s instruction"), opcode->name);

3355

+ break;

3356

+ case V_BRA: // bra, emulated with Address type instruction

3357

+ if (msp430x_repeats)

3358

+ {

3359

+ as_bad (_("%s instruction is not repeatable"), opcode->name);

3360

+ break;

3361

+ }

3362

+

3363

+ bin = opcode->bin_opcode; // remove WB/AL bits

3364

+ l1 = get_operand ();

3365

+ res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<19), (1<<20));

3366

+ if (res)

3367

+ break; /* Error in operand. */

3368

+

3369

+ __is = 1 + op1.ol;

3370

+ frag = frag_more(__is * 2);

3371

+ where = frag - frag_now->fr_literal;

3372

+ if (op1.mode == OP_REG && op1.am == 0)

3373

+ {

3374

+ // mova Rsrc, PC

3375

+ bin |= 0x00C0 | op1.reg << 8;

3376

+ bfd_putl16 ((bfd_vma) bin, frag);

3377

+ dwarf2_emit_insn (__is * 2);

3378

+ }

3379

+ else if(op1.mode == OP_REG && op1.am == 2)

3380

+ {

3381

+ // mova @Rsrc, PC

3382

+ bin |= 0x0000 | op1.reg << 8;

3383

+ bfd_putl16 ((bfd_vma) bin, frag);

3384

+ dwarf2_emit_insn (__is * 2);

3385

+ }

3386

+ else if (op1.mode == OP_REG && op1.am == 3)

3387

+ {

3388

+ // mova @Rsrc+, PC

3389

+ bin |= 0x0010 | op1.reg << 8;

3390

+ bfd_putl16 ((bfd_vma) bin, frag);

3391

+ dwarf2_emit_insn (__is * 2);

3392

+ }

3393

+ else if (op1.mode == OP_EXP && op1.am == 1)

3394

+ {

3395

+ if (op1.reg == 2)

3396

+ {

3397

+ // mova &abs20, PC

3398

+ bin |= 0x0020;

3399

+ bfd_putl16 ((bfd_vma) bin, frag);

3400

+ dwarf2_emit_insn (__is * 2);

3401

+ bfd_putl16 ((bfd_vma) ZEROS, frag + 2);

3402

+ fix_new_exp (frag_now, where, 2,

3403

+ &(op1.exp), FALSE, BFD_RELOC_MSP430X_S);

3404

+ }

3405

+ else

3406

+ {

3407

+ // mova z16(Rsrc), PC

3408

+ bin |= 0x0030 | op1.reg << 8;

3409

+ bfd_putl16 ((bfd_vma) bin, frag);

3410

+ dwarf2_emit_insn (__is * 2);

3411

+ bfd_putl16 ((bfd_vma) ZEROS, frag + 2);

3412

+ if (op1.reg == 0)

3413

+ // mova z16(PC), PC = mova TONI, PC

3414

+ fix_new_exp (frag_now, where, 2,

3415

+ &(op1.exp), TRUE, BFD_RELOC_MSP430X_PCREL_INDXD);

3416

+ else

3417

+ fix_new_exp (frag_now, where, 2,

3418

+ &(op1.exp), FALSE, BFD_RELOC_MSP430X_INDXD);

3419

+ }

3420

+ }

3421

+ else if (op1.mode == OP_EXP && op1.am == 3)

3422

+ {

3423

+ // mova #imm20, Rdst

3424

+ bin |= 0x0080;

3425

+ bfd_putl16 ((bfd_vma) bin, frag);

3426

+ dwarf2_emit_insn (__is * 2);

3427

+ bfd_putl16 ((bfd_vma) ZEROS, frag + 2);

3428

+ fix_new_exp (frag_now, where, 2,

3429

+ &(op1.exp), FALSE, BFD_RELOC_MSP430X_S);

3430

+ }

3431

+ else

3432

+ as_bad (_("source operand address mode not allowed with bra instruction"));

3433

+ }

3434

+ break;

3435

+

3436

default:

3437

as_bad (_("Illegal instruction or not implemented opcode."));

3438

}

3439

3440

- input_line_pointer = line;

3441

+ if (l1)

3442

+ xfree(l1);

3443

+ if (l2)

3444

+ xfree(l2);

3445

+

3446

return 0;

3447

}

3448

3449

void

3450

md_assemble (char * str)

3451

{

3452

- struct msp430_opcode_s * opcode;

3453

- char cmd[32];

3454

- unsigned int i = 0;

3455

-

3456

- str = skip_space (str); /* Skip leading spaces. */

3457

- str = extract_cmd (str, cmd, sizeof (cmd));

3458

-

3459

- while (cmd[i] && i < sizeof (cmd))

3460

- {

3461

- char a = TOLOWER (cmd[i]);

3462

- cmd[i] = a;

3463

- i++;

3464

- }

3465

-

3466

- if (!cmd[0])

3467

+ struct msp430_opcode_s const * opcode;

3468

+ char* cmda;

3469

+ char* cmd;

3470

+ int i = 0;

3471

+ int cmd_length;

3472

+

3473

+ while (ISSPACE (*str))

3474

+ ++str;

3475

+ cmd = str;

3476

+ while (*str && (! ISSPACE (*str)) && '.' != *str)

3477

+ ++str;

3478

+ cmd_length = str - cmd;

3479

+ if (0 == cmd_length)

3480

{

3481

as_bad (_("can't find opcode "));

3482

return;

3483

}

3484

3485

- opcode = (struct msp430_opcode_s *) hash_find (msp430_hash, cmd);

3486

+ cmda = alloca(1+cmd_length);

3487

+ do {

3488

+ cmda[i] = TOLOWER(cmd[i]);

3489

+ } while (++i < cmd_length);

3490

+ cmda[i] = 0;

3491

+

3492

+ opcode = (struct msp430_opcode_s const *) hash_find (msp430_hash, cmda);

3493

3494

if (opcode == NULL)

3495

{

3496

- as_bad (_("unknown opcode `%s'"), cmd);

3497

+ as_bad (_("unknown opcode `%s'"), cmda);

3498

+ return;

3499

+ }

3500

+

3501

+ if (msp430_cpu < MSP430_CPU_MSP430X && opcode_format(opcode) >= FMT_X)

3502

+ {

3503

+ as_bad (_("Extended instruction (%s) requires 430X-based mcu"), opcode->name);

3504

return;

3505

}

3506

3507

@@ -1963,6 +3025,26 @@ md_apply_fix (fixS * fixp, valueT * valuep, segT seg)

3508

3509

switch (fixp->fx_r_type)

3510

{

3511

+ case BFD_RELOC_MSP430X_PCREL_D:

3512

+ case BFD_RELOC_MSP430X_PCREL_INDXD:

3513

+ value -= 2; // operand located 2 bytes after opcode

3514

+ break;

3515

+ case BFD_RELOC_MSP430X_PCREL_SRC:

3516

+ case BFD_RELOC_MSP430X_PCREL_SRC_BYTE:

3517

+ case BFD_RELOC_MSP430X_PCREL_DST:

3518

+ case BFD_RELOC_MSP430X_PCREL_DST_BYTE:

3519

+ value -= 4; // operand located 4 bytes after opcode

3520

+ break;

3521

+ case BFD_RELOC_MSP430X_PCREL_DST_2ND:

3522

+ case BFD_RELOC_MSP430X_PCREL_DST_2ND_BYTE:

3523

+ value -= 6; // operand located 6 bytes after opcode

3524

+ break;

3525

+ default:

3526

+ break;

3527

+ }

3528

+

3529

+ switch (fixp->fx_r_type)

3530

+ {

3531

case BFD_RELOC_MSP430_10_PCREL:

3532

if (value & 1)

3533

as_bad_where (fixp->fx_file, fixp->fx_line,

3534

@@ -1987,7 +3069,7 @@ md_apply_fix (fixS * fixp, valueT * valuep, segT seg)

3535

_("odd address operand: %ld"), value);

3536

3537

/* Nothing to be corrected here. */

3538

- if (value < -32768 || value > 65536)

3539

+ if (value < -32768 || value > 65535)

3540

as_bad_where (fixp->fx_file, fixp->fx_line,

3541

_("operand out of range: %ld"), value);

3542

3543

@@ -1997,7 +3079,7 @@ md_apply_fix (fixS * fixp, valueT * valuep, segT seg)

3544

3545

case BFD_RELOC_MSP430_16_PCREL_BYTE:

3546

/* Nothing to be corrected here. */

3547

- if (value < -32768 || value > 65536)

3548

+ if (value < -32768 || value > 65535)

3549

as_bad_where (fixp->fx_file, fixp->fx_line,

3550

_("operand out of range: %ld"), value);

3551

3552

@@ -2016,6 +3098,76 @@ md_apply_fix (fixS * fixp, valueT * valuep, segT seg)

3553

bfd_putl16 ((bfd_vma) value, where);

3554

break;

3555

3556

+ case BFD_RELOC_MSP430X_SRC:

3557

+ case BFD_RELOC_MSP430X_PCREL_SRC:

3558

+ if (value & 1)

3559

+ as_bad_where (fixp->fx_file, fixp->fx_line,

3560

+ _("odd operand: %ld"), value);

3561

+ case BFD_RELOC_MSP430X_SRC_BYTE:

3562

+ case BFD_RELOC_MSP430X_PCREL_SRC_BYTE:

3563

+ value &= 0xfffff;

3564

+ bfd_putl16 ((bfd_vma)(bfd_getl16 (where) & 0xf87f) | ((value >> 9) & 0x0780), where);

3565

+ /* 16 least-significant bits */

3566

+ bfd_putl16 ((bfd_vma) (value & 0xffff), where + 4);

3567

+ break;

3568

+ case BFD_RELOC_MSP430X_DST:

3569

+ case BFD_RELOC_MSP430X_PCREL_DST:

3570

+ if (value & 1)

3571

+ as_bad_where (fixp->fx_file, fixp->fx_line,

3572

+ _("odd operand: %ld"), value);

3573

+ case BFD_RELOC_MSP430X_DST_BYTE:

3574

+ case BFD_RELOC_MSP430X_PCREL_DST_BYTE:

3575

+ bfd_putl16 ((bfd_vma)(bfd_getl16 (where) & 0xfff0) | ((value >> 16) & 0x000f), where);

3576

+ /* 16 least-significant bits */

3577

+ value &= 0xfffff;

3578

+ bfd_putl16 ((bfd_vma) (value & 0xffff), where + 4);

3579

+ break;

3580

+ case BFD_RELOC_MSP430X_DST_2ND:

3581

+ case BFD_RELOC_MSP430X_PCREL_DST_2ND:

3582

+ if (value & 1)

3583

+ as_bad_where (fixp->fx_file, fixp->fx_line,

3584

+ _("odd operand: %ld"), value);

3585

+ case BFD_RELOC_MSP430X_DST_2ND_BYTE:

3586

+ case BFD_RELOC_MSP430X_PCREL_DST_2ND_BYTE:

3587

+ value &= 0xfffff;

3588

+ bfd_putl16 ((bfd_vma)(bfd_getl16 (where) & 0xfff0) | ((value >> 16) & 0x000f), where);

3589

+ /* 16 least-significant bits */

3590

+ bfd_putl16 ((bfd_vma) (value & 0xffff), where + 6);

3591

+ break;

3592

+ case BFD_RELOC_MSP430X_S:

3593

+ if (value & 1)

3594

+ as_bad_where (fixp->fx_file, fixp->fx_line,

3595

+ _("odd operand: %ld"), value);

3596

+ case BFD_RELOC_MSP430X_S_BYTE:

3597

+ value &= 0xfffff;

3598

+ bfd_putl16 ((bfd_vma)(bfd_getl16 (where) & 0xf0ff) | ((value >> 8) & 0x0f00), where);

3599

+ /* 16 least-significant bits */

3600

+ bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);

3601

+ break;

3602

+ case BFD_RELOC_MSP430X_D:

3603

+ case BFD_RELOC_MSP430X_PCREL_D:

3604

+ if (value & 1)

3605

+ as_bad_where (fixp->fx_file, fixp->fx_line,

3606

+ _("odd operand: %ld"), value);

3607

+ case BFD_RELOC_MSP430X_D_BYTE:

3608

+ value &= 0xfffff;

3609

+ bfd_putl16 ((bfd_vma)(bfd_getl16 (where) & 0xfff0) | ((value >> 16) & 0x000f), where);

3610

+ /* 16 least-significant bits */

3611

+ bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);

3612

+ break;

3613

+ case BFD_RELOC_MSP430X_PCREL_INDXD:

3614

+ if (value & 1)

3615

+ as_bad_where (fixp->fx_file, fixp->fx_line,

3616

+ _("odd operand: %ld"), value);

3617

+ case BFD_RELOC_MSP430X_INDXD:

3618

+ if (value < -32768 || value > 65535)

3619

+ as_bad_where (fixp->fx_file, fixp->fx_line,

3620

+ _("operand out of range: %ld"), value);

3621

+

3622

+ value &= 0xffff; /* Get rid of extended sign. */

3623

+ bfd_putl16 ((bfd_vma) value, where + 2);

3624

+ break;

3625

+

3626

default:

3627

as_fatal (_("line %d: unknown relocation type: 0x%x"),

3628

fixp->fx_line, fixp->fx_r_type);

3629

diff --git a/gas/testsuite/gas/msp430/opcode.d b/gas/testsuite/gas/msp430/opcode.d

3630

index 22df51c..297d3e1 100644

3631

--- a/gas/testsuite/gas/msp430/opcode.d

3632

+++ b/gas/testsuite/gas/msp430/opcode.d

3633

@@ -5,41 +5,49 @@

3634

3635

Disassembly of section .text:

3636

0+000 <[^>]*> 1b f3 and #1, r11 ;r3 As==01

3637

-0+002 <[^>]*> 3a e3 inv r10 ;

3638

+0+002 <[^>]*> 3a e3 inv r10

3639

0+004 <[^>]*> 3b e0 ff 00 xor #255, r11 ;#0x00ff

3640

0+008 <[^>]*> 3c d2 bis #8, r12 ;r2 As==11

3641

0+00a <[^>]*> 3d b0 10 00 bit #16, r13 ;#0x0010

3642

0+00e <[^>]*> 3e c0 a0 00 bic #160, r14 ;#0x00a0

3643

-0+012 <[^>]*> 0f 93 cmp #0, r15 ;r3 As==00

3644

-0+014 <[^>]*> 1a 83 dec r10 ;

3645

-0+016 <[^>]*> 0b 73 sbc r11 ;

3646

-0+018 <[^>]*> 1c 53 inc r12 ;

3647

+0+012 <[^>]*> 0f 93 tst r15

3648

+0+014 <[^>]*> 1a 83 dec r10

3649

+0+016 <[^>]*> 0b 73 sbc r11

3650

+0+018 <[^>]*> 1c 53 inc r12

3651

0+01a <[^>]*> 2d 63 addc #2, r13 ;r3 As==10

3652

-0+01c <[^>]*> 0e 12 push r14 ;

3653

-0+01e <[^>]*> 3f 41 pop r15 ;

3654

-0+020 <[^>]*> 8a 11 sxt r10 ;

3655

-0+022 <[^>]*> 0b 11 rra r11 ;

3656

-0+024 <[^>]*> 8c 10 swpb r12 ;

3657

-0+026 <[^>]*> 0d 10 rrc r13 ;

3658

+0+01c <[^>]*> 0e 12 push r14

3659

+0+01e <[^>]*> 3f 41 pop r15

3660

+0+020 <[^>]*> 8a 11 sxt r10

3661

+0+022 <[^>]*> 0b 11 rra r11

3662

+0+024 <[^>]*> 8c 10 swpb r12

3663

+0+026 <[^>]*> 0d 10 rrc r13

3664

0+028 <[^>]*> 30 41 ret

3665

0+02a <[^>]*> 31 40 00 00 mov #0, r1 ;#0x0000

3666

-0+02e <[^>]*> b0 12 00 00 call #0 ;#0x0000

3667

-0+032 <[^>]*> 1e 42 00 00 mov &0x0000,r14 ;0x0000

3668

-0+036 <[^>]*> 0f 4e mov r14, r15 ;

3669

-0+038 <[^>]*> 0f 5f rla r15 ;

3670

-0+03a <[^>]*> 0f 7f subc r15, r15 ;

3671

-0+03c <[^>]*> 3f e3 inv r15 ;

3672

-0+03e <[^>]*> b0 12 00 00 call #0 ;#0x0000

3673

-0+042 <[^>]*> 82 4e 00 00 mov r14, &0x0000 ;

3674

-0+046 <[^>]*> 82 4f 00 00 mov r15, &0x0000 ;

3675

-0+04a <[^>]*> 1e 42 00 00 mov &0x0000,r14 ;0x0000

3676

-0+04e <[^>]*> 0f 4e mov r14, r15 ;

3677

-0+050 <[^>]*> 0f 5f rla r15 ;

3678

-0+052 <[^>]*> 0f 7f subc r15, r15 ;

3679

-0+054 <[^>]*> 3f e3 inv r15 ;

3680

-0+056 <[^>]*> b0 12 00 00 call #0 ;#0x0000

3681

-0+05a <[^>]*> 82 4e 00 00 mov r14, &0x0000 ;

3682

-0+05e <[^>]*> 82 4f 00 00 mov r15, &0x0000 ;

3683

+0+02e <[^>]*> b0 12 00 00 call #0x0000

3684

+0+032 <[^>]*> 1e 42 00 00 mov &0x0000,r14

3685

+0+036 <[^>]*> 0f 4e mov r14, r15

3686

+0+038 <[^>]*> 0f 5f rla r15

3687

+0+03a <[^>]*> 0f 7f subc r15, r15

3688

+0+03c <[^>]*> 3f e3 inv r15

3689

+0+03e <[^>]*> b0 12 00 00 call #0x0000

3690

+0+042 <[^>]*> 82 4e 00 00 mov r14, &0x0000

3691

+0+046 <[^>]*> 82 4f 00 00 mov r15, &0x0000

3692

+0+04a <[^>]*> 1e 42 00 00 mov &0x0000,r14

3693

+0+04e <[^>]*> 0f 4e mov r14, r15

3694

+0+050 <[^>]*> 0f 5f rla r15

3695

+0+052 <[^>]*> 0f 7f subc r15, r15

3696

+0+054 <[^>]*> 3f e3 inv r15

3697

+0+056 <[^>]*> b0 12 00 00 call #0x0000

3698

+0+05a <[^>]*> 82 4e 00 00 mov r14, &0x0000

3699

+0+05e <[^>]*> 82 4f 00 00 mov r15, &0x0000

3700

0+062 <[^>]*> 3f 40 f0 00 mov #240, r15 ;#0x00f0

3701

-0+066 <[^>]*> 30 40 00 00 br #0x0000 ;

3702

-0+06a <[^>]*> 92 52 00 02 72 01 add &0x0200,&0x0172 ;0x0200

3703

+0+066 <[^>]*> 30 40 00 00 br #0x0000

3704

+0+06a <[^>]*> 92 52 00 02 72 01 add &0x0200,&0x0172

3705

+0+070 <extract> 3a 40 f0 de mov #-8464, r10 ;#0xdef0

3706

+0+074 <extract\+0x4> 3b 40 bc 9a mov #-25924,r11 ;#0x9abc

3707

+0+078 <extract\+0x8> 3c 40 78 56 mov #22136, r12 ;#0x5678

3708

+0+07c <extract\+0xc> 3d 40 34 12 mov #4660, r13 ;#0x1234

3709

+0+080 <extract0> 3a 40 7b 00 mov #123, r10 ;#0x007b

3710

+0+084 <extract0\+0x4> 0b 43 clr r11

3711

+0+086 <extract0\+0x6> 0c 43 clr r12

3712

+0+088 <extract0\+0x8> 0d 43 clr r13

3713

diff --git a/gas/testsuite/gas/msp430/opcode.s b/gas/testsuite/gas/msp430/opcode.s

3714

index b85a463..8fa444f 100644

3715

--- a/gas/testsuite/gas/msp430/opcode.s

3716

+++ b/gas/testsuite/gas/msp430/opcode.s

3717

@@ -55,3 +55,19 @@ main:

3718

;; This next instruction triggered a bug which

3719

;; was fixed by a patch to msp430-dis.c on Jan 2, 2004

3720

add &0x200, &0x172

3721

+

3722

+.global extract

3723

+ .type extract,@function

3724

+extract:

3725

+ mov #llo(0x123456789abcdef0), r10

3726

+ mov #lhi(0x123456789abcdef0), r11

3727

+ mov #hlo(0x123456789abcdef0), r12

3728

+ mov #hhi(0x123456789abcdef0), r13

3729

+

3730

+.global extract0

3731

+ .type extract,@function

3732

+extract0:

3733

+ mov #llo(123), r10

3734

+ mov #lhi(123), r11

3735

+ mov #hlo(123), r12

3736

+ mov #hhi(123), r13

3737

diff --git a/include/elf/msp430.h b/include/elf/msp430.h

3738

index 44f5c51..1eeb56b 100644

3739

--- a/include/elf/msp430.h

3740

+++ b/include/elf/msp430.h

3741

@@ -23,24 +23,6 @@

3742

3743

#include "elf/reloc-macros.h"

3744

3745

-/* Processor specific flags for the ELF header e_flags field. */

3746

-#define EF_MSP430_MACH 0xff

3747

-

3748

-#define E_MSP430_MACH_MSP430x11 11

3749

-#define E_MSP430_MACH_MSP430x11x1 110

3750

-#define E_MSP430_MACH_MSP430x12 12

3751

-#define E_MSP430_MACH_MSP430x13 13

3752

-#define E_MSP430_MACH_MSP430x14 14

3753

-#define E_MSP430_MACH_MSP430x15 15

3754

-#define E_MSP430_MACH_MSP430x16 16

3755

-#define E_MSP430_MACH_MSP430x31 31

3756

-#define E_MSP430_MACH_MSP430x32 32

3757

-#define E_MSP430_MACH_MSP430x33 33

3758

-#define E_MSP430_MACH_MSP430x41 41

3759

-#define E_MSP430_MACH_MSP430x42 42

3760

-#define E_MSP430_MACH_MSP430x43 43

3761

-#define E_MSP430_MACH_MSP430x44 44

3762

-

3763

/* Relocations. */

3764

START_RELOC_NUMBERS (elf_msp430_reloc_type)

3765

RELOC_NUMBER (R_MSP430_NONE, 0)

3766

@@ -52,7 +34,71 @@ START_RELOC_NUMBERS (elf_msp430_reloc_type)

3767

RELOC_NUMBER (R_MSP430_16_PCREL_BYTE, 6)

3768

RELOC_NUMBER (R_MSP430_2X_PCREL, 7)

3769

RELOC_NUMBER (R_MSP430_RL_PCREL, 8)

3770

+ RELOC_NUMBER (R_MSP430X_SRC_BYTE, 9)

3771

+ RELOC_NUMBER (R_MSP430X_SRC, 10)

3772

+ RELOC_NUMBER (R_MSP430X_DST_BYTE, 11)

3773

+ RELOC_NUMBER (R_MSP430X_DST, 12)

3774

+ RELOC_NUMBER (R_MSP430X_DST_2ND_BYTE, 13)

3775

+ RELOC_NUMBER (R_MSP430X_DST_2ND, 14)

3776

+ RELOC_NUMBER (R_MSP430X_PCREL_SRC_BYTE, 15)

3777

+ RELOC_NUMBER (R_MSP430X_PCREL_SRC, 16)

3778

+ RELOC_NUMBER (R_MSP430X_PCREL_DST_BYTE, 17)

3779

+ RELOC_NUMBER (R_MSP430X_PCREL_DST, 18)

3780

+ RELOC_NUMBER (R_MSP430X_PCREL_DST_2ND, 19)

3781

+ RELOC_NUMBER (R_MSP430X_PCREL_DST_2ND_BYTE, 20)

3782

+ RELOC_NUMBER (R_MSP430X_S_BYTE, 21)

3783

+ RELOC_NUMBER (R_MSP430X_S, 22)

3784

+ RELOC_NUMBER (R_MSP430X_D_BYTE, 23)

3785

+ RELOC_NUMBER (R_MSP430X_D, 24)

3786

+ RELOC_NUMBER (R_MSP430X_PCREL_D, 25)

3787

+ RELOC_NUMBER (R_MSP430X_INDXD, 26)

3788

+ RELOC_NUMBER (R_MSP430X_PCREL_INDXD, 27)

3789

3790

END_RELOC_NUMBERS (R_MSP430_max)

3791

3792

+/* TODO: Define a set of flags that are appropriate for storage in the e_flags field.

3793

+ * Potential members include:

3794

+ * - Whether CPUX instructions are present

3795

+ * - Whether hardware multiply register references are present (which kind)

3796

+ * - The code addressing mode

3797

+ * - The data addressing mode

3798

+ */

3799

+

3800

+/* Pre-uniarch versions of binutils stored machine types in the

3801

+ * e_flags field, with values up to 471 decimal. Now we store the

3802

+ * machine type in the e_mach field, and use e_flags to identify the

3803

+ * characteristics of the code.

3804

+ *

3805

+ * Use the following flag to indicate that this object file uses the

3806

+ * uniarch flag layout. */

3807

+#define EF_MSP430_UNIARCH 0x10000000

3808

+

3809

+#define EF_MSP430_ARCH_430 0x00000000

3810

+#define EF_MSP430_ARCH_430X 0x00000001

3811

+#define EF_MSP430_ARCH 0x000000FF

3812

+#if 0

3813

+/* These are symbol-associated, not archive-associated, attributes.

3814

+ * Not sure what to do with them. */

3815

+#define EF_MSP430_CPU_430 0x00000000

3816

+#define EF_MSP430_CPU_430X 0x00000200

3817

+#define EF_MSP430_CPU_430XV2 0x00000300

3818

+#define EF_MSP430_CPU 0x00000300

3819

+#define EF_MSP430_MPY_NONE 0x00000000

3820

+#define EF_MSP430_MPY_16 0x00001000

3821

+#define EF_MSP430_MPY_16_SE (0x00008000 + EF_MSP430_MPY_16)

3822

+#define EF_MSP430_MPY_32 0x00002000

3823

+#define EF_MSP430_MPY_32_DW (0x00008000 + EF_MSP430_MPY_32)

3824

+#define EF_MSP430_MPY_CLASS 0x00003000

3825

+#define EF_MSP430_MPY 0x0000F000

3826

+#define EF_MSP430_CODE_NEAR 0x00010000

3827

+#define EF_MSP430_CODE_FAR 0x00020000

3828

+#define EF_MSP430_CODE_MIXED 0x00030000

3829

+#define EF_MSP430_CODE 0x00030000

3830

+#define EF_MSP430_DATA_NEAR 0x00040000

3831

+#define EF_MSP430_DATA_FAR 0x00080000

3832

+#define EF_MSP430_DATA_MIXED 0x000c0000

3833

+#define EF_MSP430_DATA 0x000c0000

3834

+#define EF_MSP430_A20 0x000F0000

3835

+#endif

3836

+

3837

#endif /* _ELF_MSP430_H */

3838

diff --git a/include/opcode/msp430.h b/include/opcode/msp430.h

3839

index d3bf130..c281a49 100644

3840

--- a/include/opcode/msp430.h

3841

+++ b/include/opcode/msp430.h

3842

@@ -26,7 +26,7 @@ struct msp430_operand_s

3843

int ol; /* Operand length words. */

3844

int am; /* Addr mode. */

3845

int reg; /* Register. */

3846

- int mode; /* Pperand mode. */

3847

+ int mode; /* Operand mode. */

3848

#define OP_REG 0

3849

#define OP_EXP 1

3850

#ifndef DASM_SECTION

3851

@@ -34,91 +34,252 @@ struct msp430_operand_s

3852

#endif

3853

};

3854

3855

-#define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */

3856

+#define BYTE_OPERATION (1 << 6) /* Byte operation flag for 430 instructions. */

3857

+#define BYTE_OPERATION_X (1 << 22) /* Byte operation flag for 430x instructions. */

3858

+#define NON_ADDR_OPERATION (1 << 6) /* Address operation flag for 430x instructions. */

3859

+

3860

+typedef enum

3861

+{

3862

+ DEFAULT_OP, // instruction has no modifier

3863

+ WORD_OP, // .w

3864

+ BYTE_OP, // .b

3865

+ ADDR_OP // .a

3866

+}

3867

+opwidth_t;

3868

+

3869

+/** Bit-markers for type of CPU present. */

3870

+typedef enum msp430_cpu_e

3871

+{

3872

+ MSP430_CPU_MSP430 = 0x0000,

3873

+ MSP430_CPU_MSP430X = 0x0002,

3874

+ MSP430_CPU_MSP430XV2 = 0x0003,

3875

+ MSP430_CPU = 0x0003,

3876

+} msp430_cpu_e;

3877

+

3878

+/** Bit-markers for type of hardware multiplier present. */

3879

+typedef enum msp430_mpy_e

3880

+{

3881

+ MSP430_MPY_NONE = 0x0000,

3882

+ MSP430_MPY_16 = 0x0010,

3883

+ MSP430_MPY_16SE = 0x0011,

3884

+ MSP430_MPY_32 = 0x0020,

3885

+ MSP430_MPY_32DW = 0x0022,

3886

+ MSP430_MPY = 0x0030

3887

+} msp430_mpy_e;

3888

+

3889

+typedef enum

3890

+{

3891

+ FMT_EMULATED = 0,

3892

+ FMT_DOUBLE_OPERAND,

3893

+ FMT_SINGLE_OPERAND,

3894

+ FMT_JUMP,

3895

+ FMT_EMULATED_POLYMORPH_JUMP,

3896

+ FMT_EMULATED_LONG_POLYMORPH_JUMP,

3897

+ FMT_X_DOUBLE_OPERAND,

3898

+ FMT_X_SINGLE_OPERAND,

3899

+ FMT_X_EXCEPTION,

3900

+ FMT_X_EMULATED,

3901

+ FMT_X_ADDRESS,

3902

+

3903

+ FMT_X = FMT_X_DOUBLE_OPERAND,

3904

+ FMT_MASK = 0x000f,

3905

+

3906

+ /* allowed modifiers: .b, .w, .a */

3907

+ MOD_NONE = 0,

3908

+ MOD_W = 1 << 4,

3909

+ MOD_B = 1 << 5,

3910

+ MOD_A = 1 << 6,

3911

+ MOD_MASK = 0x0070,

3912

+

3913

+ /* opcode variant */

3914

+ VAR_MASK = 0x0380,

3915

+}

3916

+format_t;

3917

+

3918

+#define OP_V(x) (x << 7)

3919

3920

struct msp430_opcode_s

3921

{

3922

char *name;

3923

- int fmt;

3924

- int insn_opnumb;

3925

- int bin_opcode;

3926

- int bin_mask;

3927

+ format_t fmt;

3928

+ unsigned int insn_opnumb;

3929

+ unsigned int bin_opcode;

3930

+ unsigned int bin_mask;

3931

};

3932

3933

-#define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask }

3934

+#define opcode_format(opcode) (opcode->fmt & FMT_MASK)

3935

+#define opcode_modifier(opcode) (opcode->fmt & MOD_MASK)

3936

+#define opcode_variant(opcode) ((opcode->fmt & VAR_MASK) >> 7)

3937

+

3938

+/* opcode variants: */

3939

+enum

3940

+{

3941

+ V_NONE = 0, // ordinary instruction

3942

+

3943

+ /* FMT_EMULATED: */

3944

+ V_NOOP, // no operands: set/clear bit instructions, reti

3945

+ V_SHIFT, // shift instructions

3946

+ V_BR, // br instruction

3947

+

3948

+ /* FMT_SINGLE_OPERAND: */

3949

+ V_RETI = 1, // reti

3950

+ V_CALL = 2, // hex operand in disassembly

3951

+

3952

+ /* FMT_X_SINGLE_OPERAND: */

3953

+ // V_NONE - #N operand disallowed

3954

+ V_SWPSXT = 1, // #N operand disallowed, special A/L, B/W bits case with .a modifier

3955

+ V_PUSHX, // #N operand allowed

3956

3957

-static struct msp430_opcode_s msp430_opcodes[] =

3958

+ /* FMT_X_EXCEPTIONS: */

3959

+ V_CALLA = 0, // calla

3960

+ V_ROTM, // two operands, rotations

3961

+ V_POPM, // two operands, popm

3962

+ V_PUSHM, // two operands, pushm

3963

+

3964

+ /* FMT_X_EMULATED: */

3965

+ // V_NONE - substituted by 430x double operand instruction

3966

+ V_X_SHIFT, // shifts

3967

+ V_RETA, // reta, short instruction, no operands

3968

+ V_EMU_ADDR, // substituted by address instruction other than mova

3969

+ V_BRA, // bra, substituted by mova address instruction == format II exception instruction

3970

+ // clra emulated by msp430 instruction

3971

+

3972

+ /* FMT_X_ADDRESS: */

3973

+ V_MOVA = 1, // mova, more address modes allowed

3974

+};

3975

+

3976

+#define MSP_INSN(name, format, opnumb, bin, mask) { #name, format, opnumb, bin, mask }

3977

+

3978

+static struct msp430_opcode_s const msp430_opcodes[] =

3979

{

3980

- MSP_INSN (and, 1, 2, 0xf000, 0xf000),

3981

- MSP_INSN (inv, 0, 1, 0xe330, 0xfff0),

3982

- MSP_INSN (xor, 1, 2, 0xe000, 0xf000),

3983

- MSP_INSN (setz, 0, 0, 0xd322, 0xffff),

3984

- MSP_INSN (setc, 0, 0, 0xd312, 0xffff),

3985

- MSP_INSN (eint, 0, 0, 0xd232, 0xffff),

3986

- MSP_INSN (setn, 0, 0, 0xd222, 0xffff),

3987

- MSP_INSN (bis, 1, 2, 0xd000, 0xf000),

3988

- MSP_INSN (clrz, 0, 0, 0xc322, 0xffff),

3989

- MSP_INSN (clrc, 0, 0, 0xc312, 0xffff),

3990

- MSP_INSN (dint, 0, 0, 0xc232, 0xffff),

3991

- MSP_INSN (clrn, 0, 0, 0xc222, 0xffff),

3992

- MSP_INSN (bic, 1, 2, 0xc000, 0xf000),

3993

- MSP_INSN (bit, 1, 2, 0xb000, 0xf000),

3994

- MSP_INSN (dadc, 0, 1, 0xa300, 0xff30),

3995

- MSP_INSN (dadd, 1, 2, 0xa000, 0xf000),

3996

- MSP_INSN (tst, 0, 1, 0x9300, 0xff30),

3997

- MSP_INSN (cmp, 1, 2, 0x9000, 0xf000),

3998

- MSP_INSN (decd, 0, 1, 0x8320, 0xff30),

3999

- MSP_INSN (dec, 0, 1, 0x8310, 0xff30),

4000

- MSP_INSN (sub, 1, 2, 0x8000, 0xf000),

4001

- MSP_INSN (sbc, 0, 1, 0x7300, 0xff30),

4002

- MSP_INSN (subc, 1, 2, 0x7000, 0xf000),

4003

- MSP_INSN (adc, 0, 1, 0x6300, 0xff30),

4004

- MSP_INSN (rlc, 0, 2, 0x6000, 0xf000),

4005

- MSP_INSN (addc, 1, 2, 0x6000, 0xf000),

4006

- MSP_INSN (incd, 0, 1, 0x5320, 0xff30),

4007

- MSP_INSN (inc, 0, 1, 0x5310, 0xff30),

4008

- MSP_INSN (rla, 0, 2, 0x5000, 0xf000),

4009

- MSP_INSN (add, 1, 2, 0x5000, 0xf000),

4010

- MSP_INSN (nop, 0, 0, 0x4303, 0xffff),

4011

- MSP_INSN (clr, 0, 1, 0x4300, 0xff30),

4012

- MSP_INSN (ret, 0, 0, 0x4130, 0xff30),

4013

- MSP_INSN (pop, 0, 1, 0x4130, 0xff30),

4014

- MSP_INSN (br, 0, 3, 0x4000, 0xf000),

4015

- MSP_INSN (mov, 1, 2, 0x4000, 0xf000),

4016

- MSP_INSN (jmp, 3, 1, 0x3c00, 0xfc00),

4017

- MSP_INSN (jl, 3, 1, 0x3800, 0xfc00),

4018

- MSP_INSN (jge, 3, 1, 0x3400, 0xfc00),

4019

- MSP_INSN (jn, 3, 1, 0x3000, 0xfc00),

4020

- MSP_INSN (jc, 3, 1, 0x2c00, 0xfc00),

4021

- MSP_INSN (jhs, 3, 1, 0x2c00, 0xfc00),

4022

- MSP_INSN (jnc, 3, 1, 0x2800, 0xfc00),

4023

- MSP_INSN (jlo, 3, 1, 0x2800, 0xfc00),

4024

- MSP_INSN (jz, 3, 1, 0x2400, 0xfc00),

4025

- MSP_INSN (jeq, 3, 1, 0x2400, 0xfc00),

4026

- MSP_INSN (jnz, 3, 1, 0x2000, 0xfc00),

4027

- MSP_INSN (jne, 3, 1, 0x2000, 0xfc00),

4028

- MSP_INSN (reti, 2, 0, 0x1300, 0xffc0),

4029

- MSP_INSN (call, 2, 1, 0x1280, 0xffc0),

4030

- MSP_INSN (push, 2, 1, 0x1200, 0xff80),

4031

- MSP_INSN (sxt, 2, 1, 0x1180, 0xffc0),

4032

- MSP_INSN (rra, 2, 1, 0x1100, 0xff80),

4033

- MSP_INSN (swpb, 2, 1, 0x1080, 0xffc0),

4034

- MSP_INSN (rrc, 2, 1, 0x1000, 0xff80),

4035

+ MSP_INSN (and, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0xf000, 0xfffff000),

4036

+ MSP_INSN (inv, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0xe330, 0xfffffff0),

4037

+ MSP_INSN (xor, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0xe000, 0xfffff000),

4038

+ MSP_INSN (setz, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0xd322, 0xffffffff),

4039

+ MSP_INSN (setc, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0xd312, 0xffffffff),

4040

+ MSP_INSN (eint, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0xd232, 0xffffffff),

4041

+ MSP_INSN (setn, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0xd222, 0xffffffff),

4042

+ MSP_INSN (bis, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0xd000, 0xfffff000),

4043

+ MSP_INSN (clrz, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0xc322, 0xffffffff),

4044

+ MSP_INSN (clrc, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0xc312, 0xffffffff),

4045

+ MSP_INSN (dint, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0xc232, 0xffffffff),

4046

+ MSP_INSN (clrn, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0xc222, 0xffffffff),

4047

+ MSP_INSN (bic, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0xc000, 0xfffff000),

4048

+ MSP_INSN (bit, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0xb000, 0xfffff000),

4049

+ MSP_INSN (dadc, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0xa300, 0xffffff30),

4050

+ MSP_INSN (dadd, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0xa000, 0xfffff000),

4051

+ MSP_INSN (tst, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x9300, 0xffffff30),

4052

+ MSP_INSN (cmp, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0x9000, 0xfffff000),

4053

+ MSP_INSN (decd, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x8320, 0xffffff30),

4054

+ MSP_INSN (dec, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x8310, 0xffffff30),

4055

+ MSP_INSN (sub, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0x8000, 0xfffff000),

4056

+ MSP_INSN (sbc, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x7300, 0xffffff30),

4057

+ MSP_INSN (subc, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0x7000, 0xfffff000),

4058

+ MSP_INSN (adc, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x6300, 0xffffff30),

4059

+ MSP_INSN (rlc, FMT_EMULATED | MOD_W|MOD_B | OP_V(V_SHIFT), 2, 0x6000, 0xfffff000),

4060

+ MSP_INSN (addc, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0x6000, 0xfffff000),

4061

+ MSP_INSN (incd, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x5320, 0xffffff30),

4062

+ MSP_INSN (inc, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x5310, 0xffffff30),

4063

+ MSP_INSN (rla, FMT_EMULATED | MOD_W|MOD_B | OP_V(V_SHIFT), 2, 0x5000, 0xfffff000),

4064

+ MSP_INSN (add, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0x5000, 0xfffff000),

4065

+ MSP_INSN (nop, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0x4303, 0xffffffff),

4066

+ MSP_INSN (clr, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x4300, 0xffffff30),

4067

+ MSP_INSN (clra, FMT_EMULATED | MOD_NONE | OP_V(0), 1, 0x4300, 0xffffff30), // MOV #0, Rdst

4068

+ MSP_INSN (ret, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0x4130, 0xffffffff),

4069

+ MSP_INSN (pop, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x4130, 0xffffff30),

4070

+ MSP_INSN (br, FMT_EMULATED | MOD_NONE | OP_V(V_BR), 1, 0x4000, 0xfffff08f),

4071

+ MSP_INSN (mov, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0x4000, 0xfffff000),

4072

+

4073

+ MSP_INSN (jmp, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x3c00, 0xfffffc00),

4074

+ MSP_INSN (jl, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x3800, 0xfffffc00),

4075

+ MSP_INSN (jge, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x3400, 0xfffffc00),

4076

+ MSP_INSN (jn, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x3000, 0xfffffc00),

4077

+ MSP_INSN (jc, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x2c00, 0xfffffc00),

4078

+ MSP_INSN (jhs, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x2c00, 0xfffffc00),

4079

+ MSP_INSN (jnc, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x2800, 0xfffffc00),

4080

+ MSP_INSN (jlo, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x2800, 0xfffffc00),

4081

+ MSP_INSN (jz, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x2400, 0xfffffc00),

4082

+ MSP_INSN (jeq, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x2400, 0xfffffc00),

4083

+ MSP_INSN (jnz, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x2000, 0xfffffc00),

4084

+ MSP_INSN (jne, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x2000, 0xfffffc00),

4085

+

4086

+ MSP_INSN (reti, FMT_SINGLE_OPERAND | MOD_NONE | OP_V(V_RETI), 0, 0x1300, 0xffffffc0),

4087

+ MSP_INSN (call, FMT_SINGLE_OPERAND | MOD_NONE | OP_V(V_CALL), 1, 0x1280, 0xffffffc0),

4088

+ MSP_INSN (push, FMT_SINGLE_OPERAND | MOD_W|MOD_B | OP_V(0), 1, 0x1200, 0xffffff80),

4089

+ MSP_INSN (sxt, FMT_SINGLE_OPERAND | MOD_NONE | OP_V(0), 1, 0x1180, 0xffffffc0),

4090

+ MSP_INSN (rra, FMT_SINGLE_OPERAND | MOD_W|MOD_B | OP_V(0), 1, 0x1100, 0xffffff80),

4091

+ MSP_INSN (swpb, FMT_SINGLE_OPERAND | MOD_NONE | OP_V(0), 1, 0x1080, 0xffffffc0),

4092

+ MSP_INSN (rrc, FMT_SINGLE_OPERAND | MOD_W|MOD_B | OP_V(0), 1, 0x1000, 0xffffff80),

4093

+

4094

+

4095

+ /* emulated instructions placed just before instruction emulated by for disassembly search */

4096

+ MSP_INSN (popx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x41301800, 0xff30f800), // MOVX @SP+, dst

4097

+ MSP_INSN (clrx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x43001800, 0xff30f800), // MOVX #0, dst

4098

+ MSP_INSN (movx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0x40001800, 0xf000f800),

4099

+ MSP_INSN (incx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x53101800, 0xff30f800), // ADDX #1, dst

4100

+ MSP_INSN (incdx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x53201800, 0xff30f800), // ADDX #2, dst

4101

+ MSP_INSN (rlax, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(V_X_SHIFT), 1, 0x50001800, 0xf000f800), // ADDX dst, dst

4102

+ MSP_INSN (addx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0x50001800, 0xf000f800),

4103

+ MSP_INSN (adcx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x63001800, 0xff30f800), // ADDCX #0, dst

4104

+ MSP_INSN (rlcx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(V_X_SHIFT), 1, 0x60001800, 0xf000f800), // ADDCX dst, dst

4105

+ MSP_INSN (addcx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0x60001800, 0xf000f800),

4106

+ MSP_INSN (sbcx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x73001800, 0xff30f800), // SUBCX #0, dst

4107

+ MSP_INSN (subcx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0x70001800, 0xf000f800),

4108

+ MSP_INSN (decx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x83101800, 0xff30f800), // SUBX #1, dst

4109

+ MSP_INSN (decdx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x83201800, 0xff30f800), // SUBX #2, dst

4110

+ MSP_INSN (subx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0x80001800, 0xf000f800),

4111

+ MSP_INSN (tstx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x93001800, 0xff30f800), // CMPX #0, dst

4112

+ MSP_INSN (cmpx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0x90001800, 0xf000f800),

4113

+ MSP_INSN (dadcx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0xa3001800, 0xff30f800), // DADDX #0, dst

4114

+ MSP_INSN (daddx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0xa0001800, 0xf000f800),

4115

+ MSP_INSN (bitx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0xb0001800, 0xf000f800),

4116

+ MSP_INSN (bicx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0xc0001800, 0xf000f800),

4117

+ MSP_INSN (bisx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0xd0001800, 0xf000f800),

4118

+ MSP_INSN (invx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0xe3301800, 0xff30f800), // XORX #-1, dst

4119

+ MSP_INSN (xorx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0xe0001800, 0xf000f800),

4120

+ MSP_INSN (andx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0xf0001800, 0xf000f800),

4121

+

4122

+ MSP_INSN (rrcx, FMT_X_SINGLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x10001800, 0xff80f800),

4123

+ MSP_INSN (swpbx, FMT_X_SINGLE_OPERAND | MOD_W|MOD_A | OP_V(V_SWPSXT), 1, 0x10801800, 0xffc0f800),

4124

+ MSP_INSN (rrax, FMT_X_SINGLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x11001800, 0xff80f800),

4125

+ MSP_INSN (sxtx, FMT_X_SINGLE_OPERAND | MOD_W|MOD_A | OP_V(V_SWPSXT), 1, 0x11801800, 0xffc0f800),

4126

+ MSP_INSN (pushx, FMT_X_SINGLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(V_PUSHX), 1, 0x12001800, 0xff80f800),

4127

+

4128

+ MSP_INSN (calla, FMT_X_EXCEPTION | MOD_NONE | OP_V(V_CALLA), 1, 0x1300, 0xffffff00),

4129

+ MSP_INSN (pushm, FMT_X_EXCEPTION | MOD_W|MOD_A | OP_V(V_PUSHM), 2, 0x1400, 0xfffffe00),

4130

+ MSP_INSN (popm, FMT_X_EXCEPTION | MOD_W|MOD_A | OP_V(V_POPM), 2, 0x1600, 0xfffffe00),

4131

+ MSP_INSN (rrcm, FMT_X_EXCEPTION | MOD_W|MOD_A | OP_V(V_ROTM), 2, 0x0040, 0xfffff3e0),

4132

+ MSP_INSN (rram, FMT_X_EXCEPTION | MOD_W|MOD_A | OP_V(V_ROTM), 2, 0x0140, 0xfffff3e0),

4133

+ MSP_INSN (rlam, FMT_X_EXCEPTION | MOD_W|MOD_A | OP_V(V_ROTM), 2, 0x0240, 0xfffff3e0),

4134

+ MSP_INSN (rrum, FMT_X_EXCEPTION | MOD_W|MOD_A | OP_V(V_ROTM), 2, 0x0340, 0xfffff3e0),

4135

+

4136

+ /* Address. */

4137

+ MSP_INSN (incda, FMT_X_EMULATED | MOD_NONE | OP_V(V_EMU_ADDR), 1, 0x03e0, 0xfffffff0), // ADDA #2, Rdst = ADDA R3, Rdst

4138

+ MSP_INSN (adda, FMT_X_ADDRESS | MOD_NONE | OP_V(0), 2, 0x00a0, 0xfffff0b0),

4139

+ MSP_INSN (tsta, FMT_X_EMULATED | MOD_NONE | OP_V(V_EMU_ADDR), 1, 0x03d0, 0xfffffff0), // CMPA #0, Rdst = CMPA R3, Rdst

4140

+ MSP_INSN (cmpa, FMT_X_ADDRESS | MOD_NONE | OP_V(0), 2, 0x0090, 0xfffff0b0),

4141

+ MSP_INSN (decda, FMT_X_EMULATED | MOD_NONE | OP_V(V_EMU_ADDR), 1, 0x03f0, 0xfffffff0), // SUBA #2, Rdst = SUBA R3, Rdst

4142

+ MSP_INSN (suba, FMT_X_ADDRESS | MOD_NONE | OP_V(0), 2, 0x00b0, 0xfffff0b0),

4143

+ MSP_INSN (reta, FMT_X_EMULATED | MOD_NONE | OP_V(V_RETA), 0, 0x0110, 0xffffffff), // MOVA @SP+, PC

4144

+ MSP_INSN (bra, FMT_X_EMULATED | MOD_NONE | OP_V(V_BRA), 1, 0x0000, 0xfffff0cf), // MOVA dst, PC

4145

+ MSP_INSN (bra, FMT_X_EMULATED | MOD_NONE | OP_V(V_BRA), 1, 0x0080, 0xfffff0bf), // MOVA #imm20, PC; MOVA Rsrc, Rdst

4146

+ MSP_INSN (mova, FMT_X_ADDRESS | MOD_NONE | OP_V(V_MOVA), 1, 0x0000, 0xfffff000),

4147

+

4148

/* Simple polymorphs. */

4149

- MSP_INSN (beq, 4, 0, 0, 0xffff),

4150

- MSP_INSN (bne, 4, 1, 0, 0xffff),

4151

- MSP_INSN (blt, 4, 2, 0, 0xffff),

4152

- MSP_INSN (bltu, 4, 3, 0, 0xffff),

4153

- MSP_INSN (bge, 4, 4, 0, 0xffff),

4154

- MSP_INSN (bgeu, 4, 5, 0, 0xffff),

4155

- MSP_INSN (bltn, 4, 6, 0, 0xffff),

4156

- MSP_INSN (jump, 4, 7, 0, 0xffff),

4157

- /* Long polymorphs. */

4158

- MSP_INSN (bgt, 5, 0, 0, 0xffff),

4159

- MSP_INSN (bgtu, 5, 1, 0, 0xffff),

4160

- MSP_INSN (bleu, 5, 2, 0, 0xffff),

4161

- MSP_INSN (ble, 5, 3, 0, 0xffff),

4162

+ MSP_INSN (beq, FMT_EMULATED_POLYMORPH_JUMP | MOD_NONE | OP_V(0), 1, 0, 0xffff),

4163

+ MSP_INSN (bne, FMT_EMULATED_POLYMORPH_JUMP | MOD_NONE | OP_V(1), 1, 0, 0xffff),

4164

+ MSP_INSN (blt, FMT_EMULATED_POLYMORPH_JUMP | MOD_NONE | OP_V(2), 1, 0, 0xffff),

4165

+ MSP_INSN (bltu, FMT_EMULATED_POLYMORPH_JUMP | MOD_NONE | OP_V(3), 1, 0, 0xffff),

4166

+ MSP_INSN (bge, FMT_EMULATED_POLYMORPH_JUMP | MOD_NONE | OP_V(4), 1, 0, 0xffff),

4167

+ MSP_INSN (bgeu, FMT_EMULATED_POLYMORPH_JUMP | MOD_NONE | OP_V(5), 1, 0, 0xffff),

4168

+ MSP_INSN (bltn, FMT_EMULATED_POLYMORPH_JUMP | MOD_NONE | OP_V(6), 1, 0, 0xffff),

4169

+ MSP_INSN (jump, FMT_EMULATED_POLYMORPH_JUMP | MOD_NONE | OP_V(7), 1, 0, 0xffff),

4170

4171

+ /* Long polymorphs. */

4172

+ MSP_INSN (bgt, FMT_EMULATED_LONG_POLYMORPH_JUMP | MOD_NONE | OP_V(0), 1, 0, 0xffff),

4173

+ MSP_INSN (bgtu, FMT_EMULATED_LONG_POLYMORPH_JUMP | MOD_NONE | OP_V(1), 1, 0, 0xffff),

4174

+ MSP_INSN (bleu, FMT_EMULATED_LONG_POLYMORPH_JUMP | MOD_NONE | OP_V(2), 1, 0, 0xffff),

4175

+ MSP_INSN (ble, FMT_EMULATED_LONG_POLYMORPH_JUMP | MOD_NONE | OP_V(3), 1, 0, 0xffff),

4176

/* End of instruction set. */

4177

{ NULL, 0, 0, 0, 0 }

4178

};

4179

diff --git a/ld/Makefile.am b/ld/Makefile.am

4180

index b392e14..f3c0130 100644

4181

--- a/ld/Makefile.am

4182

+++ b/ld/Makefile.am

4183

@@ -328,65 +328,7 @@ ALL_EMULATION_SOURCES = \

4184

emipspe.c \

4185

emn10200.c \

4186

emn10300.c \

4187

- emsp430x110.c \

4188

- emsp430x1101.c \

4189

- emsp430x1111.c \

4190

- emsp430x112.c \

4191

- emsp430x1121.c \

4192

- emsp430x1122.c \

4193

- emsp430x1132.c \

4194

- emsp430x122.c \

4195

- emsp430x1222.c \

4196

- emsp430x123.c \

4197

- emsp430x1232.c \

4198

- emsp430x133.c \

4199

- emsp430x1331.c \

4200

- emsp430x135.c \

4201

- emsp430x1351.c \

4202

- emsp430x147.c \

4203

- emsp430x148.c \

4204

- emsp430x149.c \

4205

- emsp430x155.c \

4206

- emsp430x156.c \

4207

- emsp430x157.c \

4208

- emsp430x1610.c \

4209

- emsp430x1611.c \

4210

- emsp430x1612.c \

4211

- emsp430x167.c \

4212

- emsp430x168.c \

4213

- emsp430x169.c \

4214

- emsp430x2101.c \

4215

- emsp430x2111.c \

4216

- emsp430x2121.c \

4217

- emsp430x2131.c \

4218

- emsp430x311.c \

4219

- emsp430x312.c \

4220

- emsp430x313.c \

4221

- emsp430x314.c \

4222

- emsp430x315.c \

4223

- emsp430x323.c \

4224

- emsp430x325.c \

4225

- emsp430x336.c \

4226

- emsp430x337.c \

4227

- emsp430x412.c \

4228

- emsp430x413.c \

4229

- emsp430x415.c \

4230

- emsp430x417.c \

4231

- emsp430x435.c \

4232

- emsp430x436.c \

4233

- emsp430x437.c \

4234

- emsp430x447.c \

4235

- emsp430x448.c \

4236

- emsp430x449.c \

4237

- emsp430xE423.c \

4238

- emsp430xE425.c \

4239

- emsp430xE427.c \

4240

- emsp430xG437.c \

4241

- emsp430xG438.c \

4242

- emsp430xG439.c \

4243

- emsp430xW423.c \

4244

- emsp430xW425.c \

4245

- emsp430xW427.c \

4246

+ emsp430.c \

4247

enews.c \

4248

ens32knbsd.c \

4249

eor32.c \

4250

@@ -1396,242 +1338,10 @@ emn10300.c: $(srcdir)/emulparams/mn10300.sh \

4251

$(srcdir)/emulparams/mn10200.sh \

4252

$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}

4253

${GENSCRIPTS} mn10300 "$(tdir_mn10300)"

4254

-emsp430x110.c: $(srcdir)/emulparams/msp430all.sh \

4255

+emsp430.c: $(srcdir)/emulparams/msp430uni.sh \

4256

$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4257

${GEN_DEPENDS}

4258

- ${GENSCRIPTS} msp430x110 "$(tdir_msp430x110)" msp430all

4259

-emsp430x1101.c: $(srcdir)/emulparams/msp430all.sh \

4260

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4261

- ${GEN_DEPENDS}

4262

- ${GENSCRIPTS} msp430x1101 "$(tdir_msp430x1101)" msp430all

4263

-emsp430x1111.c: $(srcdir)/emulparams/msp430all.sh \

4264

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4265

- ${GEN_DEPENDS}

4266

- ${GENSCRIPTS} msp430x1111 "$(tdir_msp430x1111)" msp430all

4267

-emsp430x112.c: $(srcdir)/emulparams/msp430all.sh \

4268

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4269

- ${GEN_DEPENDS}

4270

- ${GENSCRIPTS} msp430x112 "$(tdir_msp430x112)" msp430all

4271

-emsp430x1121.c: $(srcdir)/emulparams/msp430all.sh \

4272

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4273

- ${GEN_DEPENDS}

4274

- ${GENSCRIPTS} msp430x1121 "$(tdir_msp430x1121)" msp430all

4275

-emsp430x1122.c: $(srcdir)/emulparams/msp430all.sh \

4276

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4277

- ${GEN_DEPENDS}

4278

- ${GENSCRIPTS} msp430x1122 "$(tdir_msp430x1122)" msp430all

4279

-emsp430x1132.c: $(srcdir)/emulparams/msp430all.sh \

4280

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4281

- ${GEN_DEPENDS}

4282

- ${GENSCRIPTS} msp430x1132 "$(tdir_msp430x1132)" msp430all

4283

-emsp430x122.c: $(srcdir)/emulparams/msp430all.sh \

4284

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4285

- ${GEN_DEPENDS}

4286

- ${GENSCRIPTS} msp430x122 "$(tdir_msp430x122)" msp430all

4287

-emsp430x1222.c: $(srcdir)/emulparams/msp430all.sh \

4288

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4289

- ${GEN_DEPENDS}

4290

- ${GENSCRIPTS} msp430x1222 "$(tdir_msp430x1222)" msp430all

4291

-emsp430x123.c: $(srcdir)/emulparams/msp430all.sh \

4292

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4293

- ${GEN_DEPENDS}

4294

- ${GENSCRIPTS} msp430x123 "$(tdir_msp430x123)" msp430all

4295

-emsp430x1232.c: $(srcdir)/emulparams/msp430all.sh \

4296

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4297

- ${GEN_DEPENDS}

4298

- ${GENSCRIPTS} msp430x1232 "$(tdir_msp430x1232)" msp430all

4299

-emsp430x133.c: $(srcdir)/emulparams/msp430all.sh \

4300

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4301

- ${GEN_DEPENDS}

4302

- ${GENSCRIPTS} msp430x133 "$(tdir_msp430x133)" msp430all

4303

-emsp430x1331.c: $(srcdir)/emulparams/msp430all.sh \

4304

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4305

- ${GEN_DEPENDS}

4306

- ${GENSCRIPTS} msp430x1331 "$(tdir_msp430x1331)" msp430all

4307

-emsp430x135.c: $(srcdir)/emulparams/msp430all.sh \

4308

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4309

- ${GEN_DEPENDS}

4310

- ${GENSCRIPTS} msp430x135 "$(tdir_msp430x135)" msp430all

4311

-emsp430x1351.c: $(srcdir)/emulparams/msp430all.sh \

4312

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4313

- ${GEN_DEPENDS}

4314

- ${GENSCRIPTS} msp430x1351 "$(tdir_msp430x1351)" msp430all

4315

-emsp430x147.c: $(srcdir)/emulparams/msp430all.sh \

4316

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4317

- ${GEN_DEPENDS}

4318

- ${GENSCRIPTS} msp430x147 "$(tdir_msp430x147)" msp430all

4319

-emsp430x148.c: $(srcdir)/emulparams/msp430all.sh \

4320

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4321

- ${GEN_DEPENDS}

4322

- ${GENSCRIPTS} msp430x148 "$(tdir_msp430x148)" msp430all

4323

-emsp430x149.c: $(srcdir)/emulparams/msp430all.sh \

4324

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4325

- ${GEN_DEPENDS}

4326

- ${GENSCRIPTS} msp430x149 "$(tdir_msp430x149)" msp430all

4327

-emsp430x155.c: $(srcdir)/emulparams/msp430all.sh \

4328

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4329

- ${GEN_DEPENDS}

4330

- ${GENSCRIPTS} msp430x155 "$(tdir_msp430x155)" msp430all

4331

-emsp430x156.c: $(srcdir)/emulparams/msp430all.sh \

4332

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4333

- ${GEN_DEPENDS}

4334

- ${GENSCRIPTS} msp430x156 "$(tdir_msp430x156)" msp430all

4335

-emsp430x157.c: $(srcdir)/emulparams/msp430all.sh \

4336

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4337

- ${GEN_DEPENDS}

4338

- ${GENSCRIPTS} msp430x157 "$(tdir_msp430x157)" msp430all

4339

-emsp430x1610.c: $(srcdir)/emulparams/msp430all.sh \

4340

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4341

- ${GEN_DEPENDS}

4342

- ${GENSCRIPTS} msp430x1610 "$(tdir_msp430x1610)" msp430all

4343

-emsp430x1611.c: $(srcdir)/emulparams/msp430all.sh \

4344

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4345

- ${GEN_DEPENDS}

4346

- ${GENSCRIPTS} msp430x1611 "$(tdir_msp430x1611)" msp430all

4347

-emsp430x1612.c: $(srcdir)/emulparams/msp430all.sh \

4348

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4349

- ${GEN_DEPENDS}

4350

- ${GENSCRIPTS} msp430x1612 "$(tdir_msp430x1612)" msp430all

4351

-emsp430x167.c: $(srcdir)/emulparams/msp430all.sh \

4352

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4353

- ${GEN_DEPENDS}

4354

- ${GENSCRIPTS} msp430x167 "$(tdir_msp430x167)" msp430all

4355

-emsp430x168.c: $(srcdir)/emulparams/msp430all.sh \

4356

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4357

- ${GEN_DEPENDS}

4358

- ${GENSCRIPTS} msp430x168 "$(tdir_msp430x168)" msp430all

4359

-emsp430x169.c: $(srcdir)/emulparams/msp430all.sh \

4360

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4361

- ${GEN_DEPENDS}

4362

- ${GENSCRIPTS} msp430x169 "$(tdir_msp430x169)" msp430all

4363

-emsp430x2101.c: $(srcdir)/emulparams/msp430all.sh \

4364

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4365

- ${GEN_DEPENDS}

4366

- ${GENSCRIPTS} msp430x2101 "$(tdir_msp430x2101)" msp430all

4367

-emsp430x2111.c: $(srcdir)/emulparams/msp430all.sh \

4368

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4369

- ${GEN_DEPENDS}

4370

- ${GENSCRIPTS} msp430x2111 "$(tdir_msp430x2111)" msp430all

4371

-emsp430x2121.c: $(srcdir)/emulparams/msp430all.sh \

4372

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4373

- ${GEN_DEPENDS}

4374

- ${GENSCRIPTS} msp430x2121 "$(tdir_msp430x2121)" msp430all

4375

-emsp430x2131.c: $(srcdir)/emulparams/msp430all.sh \

4376

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4377

- ${GEN_DEPENDS}

4378

- ${GENSCRIPTS} msp430x2131 "$(tdir_msp430x2131)" msp430all

4379

-emsp430x311.c: $(srcdir)/emulparams/msp430all.sh \

4380

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4381

- ${GEN_DEPENDS}

4382

- ${GENSCRIPTS} msp430x311 "$(tdir_msp430x311)" msp430all

4383

-emsp430x312.c: $(srcdir)/emulparams/msp430all.sh \

4384

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4385

- ${GEN_DEPENDS}

4386

- ${GENSCRIPTS} msp430x312 "$(tdir_msp430x312)" msp430all

4387

-emsp430x313.c: $(srcdir)/emulparams/msp430all.sh \

4388

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4389

- ${GEN_DEPENDS}

4390

- ${GENSCRIPTS} msp430x313 "$(tdir_msp430x313)" msp430all

4391

-emsp430x314.c: $(srcdir)/emulparams/msp430all.sh \

4392

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4393

- ${GEN_DEPENDS}

4394

- ${GENSCRIPTS} msp430x314 "$(tdir_msp430x314)" msp430all

4395

-emsp430x315.c: $(srcdir)/emulparams/msp430all.sh \

4396

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4397

- ${GEN_DEPENDS}

4398

- ${GENSCRIPTS} msp430x315 "$(tdir_msp430x315)" msp430all

4399

-emsp430x323.c: $(srcdir)/emulparams/msp430all.sh \

4400

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4401

- ${GEN_DEPENDS}

4402

- ${GENSCRIPTS} msp430x323 "$(tdir_msp430x323)" msp430all

4403

-emsp430x325.c: $(srcdir)/emulparams/msp430all.sh \

4404

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4405

- ${GEN_DEPENDS}

4406

- ${GENSCRIPTS} msp430x325 "$(tdir_msp430x325)" msp430all

4407

-emsp430x336.c: $(srcdir)/emulparams/msp430all.sh \

4408

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4409

- ${GEN_DEPENDS}

4410

- ${GENSCRIPTS} msp430x336 "$(tdir_msp430x336)" msp430all

4411

-emsp430x337.c: $(srcdir)/emulparams/msp430all.sh \

4412

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4413

- ${GEN_DEPENDS}

4414

- ${GENSCRIPTS} msp430x337 "$(tdir_msp430x337)" msp430all

4415

-emsp430x412.c: $(srcdir)/emulparams/msp430all.sh \

4416

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4417

- ${GEN_DEPENDS}

4418

- ${GENSCRIPTS} msp430x412 "$(tdir_msp430x412)" msp430all

4419

-emsp430x413.c: $(srcdir)/emulparams/msp430all.sh \

4420

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4421

- ${GEN_DEPENDS}

4422

- ${GENSCRIPTS} msp430x413 "$(tdir_msp430x413)" msp430all

4423

-emsp430x415.c: $(srcdir)/emulparams/msp430all.sh \

4424

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4425

- ${GEN_DEPENDS}

4426

- ${GENSCRIPTS} msp430x415 "$(tdir_msp430x415)" msp430all

4427

-emsp430x417.c: $(srcdir)/emulparams/msp430all.sh \

4428

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4429

- ${GEN_DEPENDS}

4430

- ${GENSCRIPTS} msp430x417 "$(tdir_msp430x417)" msp430all

4431

-emsp430x435.c: $(srcdir)/emulparams/msp430all.sh \

4432

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4433

- ${GEN_DEPENDS}

4434

- ${GENSCRIPTS} msp430x435 "$(tdir_msp430x435)" msp430all

4435

-emsp430x436.c: $(srcdir)/emulparams/msp430all.sh \

4436

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4437

- ${GEN_DEPENDS}

4438

- ${GENSCRIPTS} msp430x436 "$(tdir_msp430x436)" msp430all

4439

-emsp430x437.c: $(srcdir)/emulparams/msp430all.sh \

4440

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4441

- ${GEN_DEPENDS}

4442

- ${GENSCRIPTS} msp430x437 "$(tdir_msp430x437)" msp430all

4443

-emsp430x447.c: $(srcdir)/emulparams/msp430all.sh \

4444

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4445

- ${GEN_DEPENDS}

4446

- ${GENSCRIPTS} msp430x447 "$(tdir_msp430x447)" msp430all

4447

-emsp430x448.c: $(srcdir)/emulparams/msp430all.sh \

4448

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4449

- ${GEN_DEPENDS}

4450

- ${GENSCRIPTS} msp430x448 "$(tdir_msp430x448)" msp430all

4451

-emsp430x449.c: $(srcdir)/emulparams/msp430all.sh \

4452

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4453

- ${GEN_DEPENDS}

4454

- ${GENSCRIPTS} msp430x449 "$(tdir_msp430x449)" msp430all

4455

-emsp430xE423.c: $(srcdir)/emulparams/msp430all.sh \

4456

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4457

- ${GEN_DEPENDS}

4458

- ${GENSCRIPTS} msp430xE423 "$(tdir_msp430xE423)" msp430all

4459

-emsp430xE425.c: $(srcdir)/emulparams/msp430all.sh \

4460

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4461

- ${GEN_DEPENDS}

4462

- ${GENSCRIPTS} msp430xE425 "$(tdir_msp430xE425)" msp430all

4463

-emsp430xE427.c: $(srcdir)/emulparams/msp430all.sh \

4464

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4465

- ${GEN_DEPENDS}

4466

- ${GENSCRIPTS} msp430xE427 "$(tdir_msp430xE427)" msp430all

4467

-emsp430xG437.c: $(srcdir)/emulparams/msp430all.sh \

4468

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4469

- ${GEN_DEPENDS}

4470

- ${GENSCRIPTS} msp430xG437 "$(tdir_msp430xG437)" msp430all

4471

-emsp430xG438.c: $(srcdir)/emulparams/msp430all.sh \

4472

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4473

- ${GEN_DEPENDS}

4474

- ${GENSCRIPTS} msp430xG438 "$(tdir_msp430xG438)" msp430all

4475

-emsp430xG439.c: $(srcdir)/emulparams/msp430all.sh \

4476

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4477

- ${GEN_DEPENDS}

4478

- ${GENSCRIPTS} msp430xG439 "$(tdir_msp430xG439)" msp430all

4479

-emsp430xW423.c: $(srcdir)/emulparams/msp430all.sh \

4480

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4481

- ${GEN_DEPENDS}

4482

- ${GENSCRIPTS} msp430xW423 "$(tdir_msp430xW423)" msp430all

4483

-emsp430xW425.c: $(srcdir)/emulparams/msp430all.sh \

4484

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4485

- ${GEN_DEPENDS}

4486

- ${GENSCRIPTS} msp430xW425 "$(tdir_msp430xW425)" msp430all

4487

-emsp430xW427.c: $(srcdir)/emulparams/msp430all.sh \

4488

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4489

- ${GEN_DEPENDS}

4490

- ${GENSCRIPTS} msp430xW427 "$(tdir_msp430xW427)" msp430all

4491

+ ${GENSCRIPTS} msp430 "$(tdir_msp430)" msp430uni

4492

enews.c: $(srcdir)/emulparams/news.sh \

4493

$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}

4494

${GENSCRIPTS} news "$(tdir_news)"

4495

diff --git a/ld/Makefile.in b/ld/Makefile.in

4496

index 9c546d7..557ebb0 100644

4497

--- a/ld/Makefile.in

4498

+++ b/ld/Makefile.in

4499

@@ -634,65 +634,7 @@ ALL_EMULATION_SOURCES = \

4500

emipspe.c \

4501

emn10200.c \

4502

emn10300.c \

4503

- emsp430x110.c \

4504

- emsp430x1101.c \

4505

- emsp430x1111.c \

4506

- emsp430x112.c \

4507

- emsp430x1121.c \

4508

- emsp430x1122.c \

4509

- emsp430x1132.c \

4510

- emsp430x122.c \

4511

- emsp430x1222.c \

4512

- emsp430x123.c \

4513

- emsp430x1232.c \

4514

- emsp430x133.c \

4515

- emsp430x1331.c \

4516

- emsp430x135.c \

4517

- emsp430x1351.c \

4518

- emsp430x147.c \

4519

- emsp430x148.c \

4520

- emsp430x149.c \

4521

- emsp430x155.c \

4522

- emsp430x156.c \

4523

- emsp430x157.c \

4524

- emsp430x1610.c \

4525

- emsp430x1611.c \

4526

- emsp430x1612.c \

4527

- emsp430x167.c \

4528

- emsp430x168.c \

4529

- emsp430x169.c \

4530

- emsp430x2101.c \

4531

- emsp430x2111.c \

4532

- emsp430x2121.c \

4533

- emsp430x2131.c \

4534

- emsp430x311.c \

4535

- emsp430x312.c \

4536

- emsp430x313.c \

4537

- emsp430x314.c \

4538

- emsp430x315.c \

4539

- emsp430x323.c \

4540

- emsp430x325.c \

4541

- emsp430x336.c \

4542

- emsp430x337.c \

4543

- emsp430x412.c \

4544

- emsp430x413.c \

4545

- emsp430x415.c \

4546

- emsp430x417.c \

4547

- emsp430x435.c \

4548

- emsp430x436.c \

4549

- emsp430x437.c \

4550

- emsp430x447.c \

4551

- emsp430x448.c \

4552

- emsp430x449.c \

4553

- emsp430xE423.c \

4554

- emsp430xE425.c \

4555

- emsp430xE427.c \

4556

- emsp430xG437.c \

4557

- emsp430xG438.c \

4558

- emsp430xG439.c \

4559

- emsp430xW423.c \

4560

- emsp430xW425.c \

4561

- emsp430xW427.c \

4562

+ emsp430.c \

4563

enews.c \

4564

ens32knbsd.c \

4565

eor32.c \

4566

@@ -1250,65 +1192,7 @@ distclean-compile:

4567

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emmo.Po@am__quote@

4568

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emn10200.Po@am__quote@

4569

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emn10300.Po@am__quote@

4570

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x110.Po@am__quote@

4571

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1101.Po@am__quote@

4572

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1111.Po@am__quote@

4573

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x112.Po@am__quote@

4574

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1121.Po@am__quote@

4575

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1122.Po@am__quote@

4576

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1132.Po@am__quote@

4577

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x122.Po@am__quote@

4578

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1222.Po@am__quote@

4579

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x123.Po@am__quote@

4580

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1232.Po@am__quote@

4581

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x133.Po@am__quote@

4582

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1331.Po@am__quote@

4583

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x135.Po@am__quote@

4584

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1351.Po@am__quote@

4585

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x147.Po@am__quote@

4586

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x148.Po@am__quote@

4587

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x149.Po@am__quote@

4588

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x155.Po@am__quote@

4589

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x156.Po@am__quote@

4590

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x157.Po@am__quote@

4591

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1610.Po@am__quote@

4592

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1611.Po@am__quote@

4593

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1612.Po@am__quote@

4594

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x167.Po@am__quote@

4595

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x168.Po@am__quote@

4596

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x169.Po@am__quote@

4597

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x2101.Po@am__quote@

4598

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x2111.Po@am__quote@

4599

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x2121.Po@am__quote@

4600

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x2131.Po@am__quote@

4601

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x311.Po@am__quote@

4602

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x312.Po@am__quote@

4603

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x313.Po@am__quote@

4604

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x314.Po@am__quote@

4605

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x315.Po@am__quote@

4606

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x323.Po@am__quote@

4607

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x325.Po@am__quote@

4608

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x336.Po@am__quote@

4609

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x337.Po@am__quote@

4610

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x412.Po@am__quote@

4611

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x413.Po@am__quote@

4612

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x415.Po@am__quote@

4613

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x417.Po@am__quote@

4614

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x435.Po@am__quote@

4615

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x436.Po@am__quote@

4616

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x437.Po@am__quote@

4617

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x447.Po@am__quote@

4618

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x448.Po@am__quote@

4619

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x449.Po@am__quote@

4620

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xE423.Po@am__quote@

4621

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xE425.Po@am__quote@

4622

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xE427.Po@am__quote@

4623

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xG437.Po@am__quote@

4624

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xG438.Po@am__quote@

4625

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xG439.Po@am__quote@

4626

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xW423.Po@am__quote@

4627

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xW425.Po@am__quote@

4628

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xW427.Po@am__quote@

4629

+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430.Po@am__quote@

4630

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/enews.Po@am__quote@

4631

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ens32knbsd.Po@am__quote@

4632

@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eor32.Po@am__quote@

4633

@@ -2839,242 +2723,10 @@ emn10300.c: $(srcdir)/emulparams/mn10300.sh \

4634

$(srcdir)/emulparams/mn10200.sh \

4635

$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}

4636

${GENSCRIPTS} mn10300 "$(tdir_mn10300)"

4637

-emsp430x110.c: $(srcdir)/emulparams/msp430all.sh \

4638

+emsp430.c: $(srcdir)/emulparams/msp430uni.sh \

4639

$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4640

${GEN_DEPENDS}

4641

- ${GENSCRIPTS} msp430x110 "$(tdir_msp430x110)" msp430all

4642

-emsp430x1101.c: $(srcdir)/emulparams/msp430all.sh \

4643

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4644

- ${GEN_DEPENDS}

4645

- ${GENSCRIPTS} msp430x1101 "$(tdir_msp430x1101)" msp430all

4646

-emsp430x1111.c: $(srcdir)/emulparams/msp430all.sh \

4647

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4648

- ${GEN_DEPENDS}

4649

- ${GENSCRIPTS} msp430x1111 "$(tdir_msp430x1111)" msp430all

4650

-emsp430x112.c: $(srcdir)/emulparams/msp430all.sh \

4651

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4652

- ${GEN_DEPENDS}

4653

- ${GENSCRIPTS} msp430x112 "$(tdir_msp430x112)" msp430all

4654

-emsp430x1121.c: $(srcdir)/emulparams/msp430all.sh \

4655

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4656

- ${GEN_DEPENDS}

4657

- ${GENSCRIPTS} msp430x1121 "$(tdir_msp430x1121)" msp430all

4658

-emsp430x1122.c: $(srcdir)/emulparams/msp430all.sh \

4659

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4660

- ${GEN_DEPENDS}

4661

- ${GENSCRIPTS} msp430x1122 "$(tdir_msp430x1122)" msp430all

4662

-emsp430x1132.c: $(srcdir)/emulparams/msp430all.sh \

4663

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4664

- ${GEN_DEPENDS}

4665

- ${GENSCRIPTS} msp430x1132 "$(tdir_msp430x1132)" msp430all

4666

-emsp430x122.c: $(srcdir)/emulparams/msp430all.sh \

4667

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4668

- ${GEN_DEPENDS}

4669

- ${GENSCRIPTS} msp430x122 "$(tdir_msp430x122)" msp430all

4670

-emsp430x1222.c: $(srcdir)/emulparams/msp430all.sh \

4671

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4672

- ${GEN_DEPENDS}

4673

- ${GENSCRIPTS} msp430x1222 "$(tdir_msp430x1222)" msp430all

4674

-emsp430x123.c: $(srcdir)/emulparams/msp430all.sh \

4675

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4676

- ${GEN_DEPENDS}

4677

- ${GENSCRIPTS} msp430x123 "$(tdir_msp430x123)" msp430all

4678

-emsp430x1232.c: $(srcdir)/emulparams/msp430all.sh \

4679

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4680

- ${GEN_DEPENDS}

4681

- ${GENSCRIPTS} msp430x1232 "$(tdir_msp430x1232)" msp430all

4682

-emsp430x133.c: $(srcdir)/emulparams/msp430all.sh \

4683

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4684

- ${GEN_DEPENDS}

4685

- ${GENSCRIPTS} msp430x133 "$(tdir_msp430x133)" msp430all

4686

-emsp430x1331.c: $(srcdir)/emulparams/msp430all.sh \

4687

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4688

- ${GEN_DEPENDS}

4689

- ${GENSCRIPTS} msp430x1331 "$(tdir_msp430x1331)" msp430all

4690

-emsp430x135.c: $(srcdir)/emulparams/msp430all.sh \

4691

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4692

- ${GEN_DEPENDS}

4693

- ${GENSCRIPTS} msp430x135 "$(tdir_msp430x135)" msp430all

4694

-emsp430x1351.c: $(srcdir)/emulparams/msp430all.sh \

4695

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4696

- ${GEN_DEPENDS}

4697

- ${GENSCRIPTS} msp430x1351 "$(tdir_msp430x1351)" msp430all

4698

-emsp430x147.c: $(srcdir)/emulparams/msp430all.sh \

4699

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4700

- ${GEN_DEPENDS}

4701

- ${GENSCRIPTS} msp430x147 "$(tdir_msp430x147)" msp430all

4702

-emsp430x148.c: $(srcdir)/emulparams/msp430all.sh \

4703

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4704

- ${GEN_DEPENDS}

4705

- ${GENSCRIPTS} msp430x148 "$(tdir_msp430x148)" msp430all

4706

-emsp430x149.c: $(srcdir)/emulparams/msp430all.sh \

4707

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4708

- ${GEN_DEPENDS}

4709

- ${GENSCRIPTS} msp430x149 "$(tdir_msp430x149)" msp430all

4710

-emsp430x155.c: $(srcdir)/emulparams/msp430all.sh \

4711

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4712

- ${GEN_DEPENDS}

4713

- ${GENSCRIPTS} msp430x155 "$(tdir_msp430x155)" msp430all

4714

-emsp430x156.c: $(srcdir)/emulparams/msp430all.sh \

4715

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4716

- ${GEN_DEPENDS}

4717

- ${GENSCRIPTS} msp430x156 "$(tdir_msp430x156)" msp430all

4718

-emsp430x157.c: $(srcdir)/emulparams/msp430all.sh \

4719

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4720

- ${GEN_DEPENDS}

4721

- ${GENSCRIPTS} msp430x157 "$(tdir_msp430x157)" msp430all

4722

-emsp430x1610.c: $(srcdir)/emulparams/msp430all.sh \

4723

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4724

- ${GEN_DEPENDS}

4725

- ${GENSCRIPTS} msp430x1610 "$(tdir_msp430x1610)" msp430all

4726

-emsp430x1611.c: $(srcdir)/emulparams/msp430all.sh \

4727

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4728

- ${GEN_DEPENDS}

4729

- ${GENSCRIPTS} msp430x1611 "$(tdir_msp430x1611)" msp430all

4730

-emsp430x1612.c: $(srcdir)/emulparams/msp430all.sh \

4731

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4732

- ${GEN_DEPENDS}

4733

- ${GENSCRIPTS} msp430x1612 "$(tdir_msp430x1612)" msp430all

4734

-emsp430x167.c: $(srcdir)/emulparams/msp430all.sh \

4735

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4736

- ${GEN_DEPENDS}

4737

- ${GENSCRIPTS} msp430x167 "$(tdir_msp430x167)" msp430all

4738

-emsp430x168.c: $(srcdir)/emulparams/msp430all.sh \

4739

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4740

- ${GEN_DEPENDS}

4741

- ${GENSCRIPTS} msp430x168 "$(tdir_msp430x168)" msp430all

4742

-emsp430x169.c: $(srcdir)/emulparams/msp430all.sh \

4743

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4744

- ${GEN_DEPENDS}

4745

- ${GENSCRIPTS} msp430x169 "$(tdir_msp430x169)" msp430all

4746

-emsp430x2101.c: $(srcdir)/emulparams/msp430all.sh \

4747

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4748

- ${GEN_DEPENDS}

4749

- ${GENSCRIPTS} msp430x2101 "$(tdir_msp430x2101)" msp430all

4750

-emsp430x2111.c: $(srcdir)/emulparams/msp430all.sh \

4751

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4752

- ${GEN_DEPENDS}

4753

- ${GENSCRIPTS} msp430x2111 "$(tdir_msp430x2111)" msp430all

4754

-emsp430x2121.c: $(srcdir)/emulparams/msp430all.sh \

4755

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4756

- ${GEN_DEPENDS}

4757

- ${GENSCRIPTS} msp430x2121 "$(tdir_msp430x2121)" msp430all

4758

-emsp430x2131.c: $(srcdir)/emulparams/msp430all.sh \

4759

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4760

- ${GEN_DEPENDS}

4761

- ${GENSCRIPTS} msp430x2131 "$(tdir_msp430x2131)" msp430all

4762

-emsp430x311.c: $(srcdir)/emulparams/msp430all.sh \

4763

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4764

- ${GEN_DEPENDS}

4765

- ${GENSCRIPTS} msp430x311 "$(tdir_msp430x311)" msp430all

4766

-emsp430x312.c: $(srcdir)/emulparams/msp430all.sh \

4767

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4768

- ${GEN_DEPENDS}

4769

- ${GENSCRIPTS} msp430x312 "$(tdir_msp430x312)" msp430all

4770

-emsp430x313.c: $(srcdir)/emulparams/msp430all.sh \

4771

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4772

- ${GEN_DEPENDS}

4773

- ${GENSCRIPTS} msp430x313 "$(tdir_msp430x313)" msp430all

4774

-emsp430x314.c: $(srcdir)/emulparams/msp430all.sh \

4775

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4776

- ${GEN_DEPENDS}

4777

- ${GENSCRIPTS} msp430x314 "$(tdir_msp430x314)" msp430all

4778

-emsp430x315.c: $(srcdir)/emulparams/msp430all.sh \

4779

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4780

- ${GEN_DEPENDS}

4781

- ${GENSCRIPTS} msp430x315 "$(tdir_msp430x315)" msp430all

4782

-emsp430x323.c: $(srcdir)/emulparams/msp430all.sh \

4783

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4784

- ${GEN_DEPENDS}

4785

- ${GENSCRIPTS} msp430x323 "$(tdir_msp430x323)" msp430all

4786

-emsp430x325.c: $(srcdir)/emulparams/msp430all.sh \

4787

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4788

- ${GEN_DEPENDS}

4789

- ${GENSCRIPTS} msp430x325 "$(tdir_msp430x325)" msp430all

4790

-emsp430x336.c: $(srcdir)/emulparams/msp430all.sh \

4791

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4792

- ${GEN_DEPENDS}

4793

- ${GENSCRIPTS} msp430x336 "$(tdir_msp430x336)" msp430all

4794

-emsp430x337.c: $(srcdir)/emulparams/msp430all.sh \

4795

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \

4796

- ${GEN_DEPENDS}

4797

- ${GENSCRIPTS} msp430x337 "$(tdir_msp430x337)" msp430all

4798

-emsp430x412.c: $(srcdir)/emulparams/msp430all.sh \

4799

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4800

- ${GEN_DEPENDS}

4801

- ${GENSCRIPTS} msp430x412 "$(tdir_msp430x412)" msp430all

4802

-emsp430x413.c: $(srcdir)/emulparams/msp430all.sh \

4803

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4804

- ${GEN_DEPENDS}

4805

- ${GENSCRIPTS} msp430x413 "$(tdir_msp430x413)" msp430all

4806

-emsp430x415.c: $(srcdir)/emulparams/msp430all.sh \

4807

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4808

- ${GEN_DEPENDS}

4809

- ${GENSCRIPTS} msp430x415 "$(tdir_msp430x415)" msp430all

4810

-emsp430x417.c: $(srcdir)/emulparams/msp430all.sh \

4811

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4812

- ${GEN_DEPENDS}

4813

- ${GENSCRIPTS} msp430x417 "$(tdir_msp430x417)" msp430all

4814

-emsp430x435.c: $(srcdir)/emulparams/msp430all.sh \

4815

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4816

- ${GEN_DEPENDS}

4817

- ${GENSCRIPTS} msp430x435 "$(tdir_msp430x435)" msp430all

4818

-emsp430x436.c: $(srcdir)/emulparams/msp430all.sh \

4819

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4820

- ${GEN_DEPENDS}

4821

- ${GENSCRIPTS} msp430x436 "$(tdir_msp430x436)" msp430all

4822

-emsp430x437.c: $(srcdir)/emulparams/msp430all.sh \

4823

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4824

- ${GEN_DEPENDS}

4825

- ${GENSCRIPTS} msp430x437 "$(tdir_msp430x437)" msp430all

4826

-emsp430x447.c: $(srcdir)/emulparams/msp430all.sh \

4827

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4828

- ${GEN_DEPENDS}

4829

- ${GENSCRIPTS} msp430x447 "$(tdir_msp430x447)" msp430all

4830

-emsp430x448.c: $(srcdir)/emulparams/msp430all.sh \

4831

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4832

- ${GEN_DEPENDS}

4833

- ${GENSCRIPTS} msp430x448 "$(tdir_msp430x448)" msp430all

4834

-emsp430x449.c: $(srcdir)/emulparams/msp430all.sh \

4835

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4836

- ${GEN_DEPENDS}

4837

- ${GENSCRIPTS} msp430x449 "$(tdir_msp430x449)" msp430all

4838

-emsp430xE423.c: $(srcdir)/emulparams/msp430all.sh \

4839

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4840

- ${GEN_DEPENDS}

4841

- ${GENSCRIPTS} msp430xE423 "$(tdir_msp430xE423)" msp430all

4842

-emsp430xE425.c: $(srcdir)/emulparams/msp430all.sh \

4843

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4844

- ${GEN_DEPENDS}

4845

- ${GENSCRIPTS} msp430xE425 "$(tdir_msp430xE425)" msp430all

4846

-emsp430xE427.c: $(srcdir)/emulparams/msp430all.sh \

4847

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4848

- ${GEN_DEPENDS}

4849

- ${GENSCRIPTS} msp430xE427 "$(tdir_msp430xE427)" msp430all

4850

-emsp430xG437.c: $(srcdir)/emulparams/msp430all.sh \

4851

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4852

- ${GEN_DEPENDS}

4853

- ${GENSCRIPTS} msp430xG437 "$(tdir_msp430xG437)" msp430all

4854

-emsp430xG438.c: $(srcdir)/emulparams/msp430all.sh \

4855

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4856

- ${GEN_DEPENDS}

4857

- ${GENSCRIPTS} msp430xG438 "$(tdir_msp430xG438)" msp430all

4858

-emsp430xG439.c: $(srcdir)/emulparams/msp430all.sh \

4859

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4860

- ${GEN_DEPENDS}

4861

- ${GENSCRIPTS} msp430xG439 "$(tdir_msp430xG439)" msp430all

4862

-emsp430xW423.c: $(srcdir)/emulparams/msp430all.sh \

4863

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4864

- ${GEN_DEPENDS}

4865

- ${GENSCRIPTS} msp430xW423 "$(tdir_msp430xW423)" msp430all

4866

-emsp430xW425.c: $(srcdir)/emulparams/msp430all.sh \

4867

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4868

- ${GEN_DEPENDS}

4869

- ${GENSCRIPTS} msp430xW425 "$(tdir_msp430xW425)" msp430all

4870

-emsp430xW427.c: $(srcdir)/emulparams/msp430all.sh \

4871

- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \

4872

- ${GEN_DEPENDS}

4873

- ${GENSCRIPTS} msp430xW427 "$(tdir_msp430xW427)" msp430all

4874

+ ${GENSCRIPTS} msp430 "$(tdir_msp430)" msp430uni

4875

enews.c: $(srcdir)/emulparams/news.sh \

4876

$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}

4877

${GENSCRIPTS} news "$(tdir_news)"

4878

diff --git a/ld/configure.tgt b/ld/configure.tgt

4879

index 7528cb5..98c4022 100644

4880

--- a/ld/configure.tgt

4881

+++ b/ld/configure.tgt

4882

@@ -433,8 +433,7 @@ mn10300-*-*) targ_emul=mn10300

4883

;;

4884

mt-*elf) targ_emul=elf32mt

4885

;;

4886

-msp430-*-*) targ_emul=msp430x110

4887

- targ_extra_emuls="msp430x112 msp430x1101 msp430x1111 msp430x1121 msp430x1122 msp430x1132 msp430x122 msp430x123 msp430x1222 msp430x1232 msp430x133 msp430x135 msp430x1331 msp430x1351 msp430x147 msp430x148 msp430x149 msp430x155 msp430x156 msp430x157 msp430x167 msp430x168 msp430x169 msp430x1610 msp430x1611 msp430x1612 msp430x2101 msp430x2111 msp430x2121 msp430x2131 msp430x311 msp430x312 msp430x313 msp430x314 msp430x315 msp430x323 msp430x325 msp430x336 msp430x337 msp430x412 msp430x413 msp430x415 msp430x417 msp430xE423 msp430xE425 msp430xE427 msp430xW423 msp430xW425 msp430xW427 msp430xG437 msp430xG438 msp430xG439 msp430x435 msp430x436 msp430x437 msp430x447 msp430x448 msp430x449"

4888

+msp430-*-*) targ_emul=msp430

4889

;;

4890

ns32k-pc532-mach* | ns32k-pc532-ux*) targ_emul=pc532macha ;;

4891

ns32k-*-netbsd* | ns32k-pc532-lites*) targ_emul=ns32knbsd

4892

diff --git a/ld/emulparams/msp430all.sh b/ld/emulparams/msp430all.sh

4893

deleted file mode 100644

4894

index 57d21c2..0000000

4895

--- a/ld/emulparams/msp430all.sh

4896

+++ /dev/null

4897

@@ -1,553 +0,0 @@

4898

-#!/bin/sh

4899

-

4900

-# This called by genscripts_extra.sh

4901

-

4902

-MSP430_NAME=${EMULATION_NAME}

4903

-

4904

-SCRIPT_NAME=elf32msp430

4905

-TEMPLATE_NAME=generic

4906

-EXTRA_EM_FILE=genelf

4907

-OUTPUT_FORMAT="elf32-msp430"

4908

-MACHINE=

4909

-MAXPAGESIZE=1

4910

-EMBEDDED=yes

4911

-

4912

-if [ "${MSP430_NAME}" = "msp430x110" ] ; then

4913

-ARCH=msp:11

4914

-ROM_START=0xfc00

4915

-ROM_SIZE=0x3e0

4916

-RAM_START=0x0200

4917

-RAM_SIZE=128

4918

-STACK=0x280

4919

-fi

4920

-

4921

-if [ "${MSP430_NAME}" = "msp430x1101" ] ; then

4922

-ARCH=msp:110

4923

-ROM_START=0xfc00

4924

-ROM_SIZE=0x3e0

4925

-RAM_START=0x0200

4926

-RAM_SIZE=128

4927

-STACK=0x280

4928

-fi

4929

-

4930

-if [ "${MSP430_NAME}" = "msp430x1111" ] ; then

4931

-ARCH=msp:110

4932

-ROM_START=0xf800

4933

-ROM_SIZE=0x07e0

4934

-RAM_START=0x0200

4935

-RAM_SIZE=128

4936

-STACK=0x280

4937

-fi

4938

-

4939

-if [ "${MSP430_NAME}" = "msp430x112" ] ; then

4940

-ARCH=msp:11

4941

-ROM_START=0xf000

4942

-ROM_SIZE=0xfe0

4943

-RAM_START=0x0200

4944

-RAM_SIZE=256

4945

-STACK=0x300

4946

-fi

4947

-

4948

-if [ "${MSP430_NAME}" = "msp430x1121" ] ; then

4949

-ARCH=msp:110

4950

-ROM_START=0xf000

4951

-ROM_SIZE=0x0fe0

4952

-RAM_START=0x0200

4953

-RAM_SIZE=256

4954

-STACK=0x300

4955

-fi

4956

-

4957

-if [ "${MSP430_NAME}" = "msp430x1122" ] ; then

4958

-ARCH=msp:110

4959

-ROM_START=0xf000

4960

-ROM_SIZE=0x0fe0

4961

-RAM_START=0x0200

4962

-RAM_SIZE=256

4963

-STACK=0x300

4964

-fi

4965

-

4966

-if [ "${MSP430_NAME}" = "msp430x1132" ] ; then

4967

-ARCH=msp:110

4968

-ROM_START=0xe000

4969

-ROM_SIZE=0x1fe0

4970

-RAM_START=0x0200

4971

-RAM_SIZE=256

4972

-STACK=0x300

4973

-fi

4974

-

4975

-if [ "${MSP430_NAME}" = "msp430x122" ] ; then

4976

-ARCH=msp:12

4977

-ROM_START=0xf000

4978

-ROM_SIZE=0xfe0

4979

-RAM_START=0x0200

4980

-RAM_SIZE=256

4981

-STACK=0x300

4982

-fi

4983

-

4984

-if [ "${MSP430_NAME}" = "msp430x1222" ] ; then

4985

-ARCH=msp:12

4986

-ROM_START=0xf000

4987

-ROM_SIZE=0xfe0

4988

-RAM_START=0x0200

4989

-RAM_SIZE=256

4990

-STACK=0x300

4991

-fi

4992

-

4993

-if [ "${MSP430_NAME}" = "msp430x123" ] ; then

4994

-ARCH=msp:12

4995

-ROM_START=0xe000

4996

-ROM_SIZE=0x1fe0

4997

-RAM_START=0x0200

4998

-RAM_SIZE=256

4999

-STACK=0x300

5000

-fi

5001

-

5002

-if [ "${MSP430_NAME}" = "msp430x1232" ] ; then

5003

-ARCH=msp:12

5004

-ROM_START=0xe000

5005

-ROM_SIZE=0x1fe0

5006

-RAM_START=0x0200

5007

-RAM_SIZE=256

5008

-STACK=0x300

5009

-fi

5010

-

5011

-if [ "${MSP430_NAME}" = "msp430x133" ] ; then

5012

-ARCH=msp:13

5013

-ROM_START=0xe000

5014

-ROM_SIZE=0x1fe0

5015

-RAM_START=0x0200

5016

-RAM_SIZE=256

5017

-STACK=0x300

5018

-fi

5019

-

5020

-if [ "${MSP430_NAME}" = "msp430x1331" ] ; then

5021

-ARCH=msp:13

5022

-ROM_START=0xe000

5023

-ROM_SIZE=0x1fe0

5024

-RAM_START=0x0200

5025

-RAM_SIZE=256

5026

-STACK=0x300

5027

-fi

5028

-

5029

-if [ "${MSP430_NAME}" = "msp430x135" ] ; then

5030

-ARCH=msp:13

5031

-ROM_START=0xc000

5032

-ROM_SIZE=0x3fe0

5033

-RAM_START=0x0200

5034

-RAM_SIZE=512

5035

-STACK=0x400

5036

-fi

5037

-

5038

-if [ "${MSP430_NAME}" = "msp430x1351" ] ; then

5039

-ARCH=msp:13

5040

-ROM_START=0xc000

5041

-ROM_SIZE=0x3fe0

5042

-RAM_START=0x0200

5043

-RAM_SIZE=512

5044

-STACK=0x400

5045

-fi

5046

-

5047

-if [ "${MSP430_NAME}" = "msp430x147" ] ; then

5048

-ARCH=msp:14

5049

-ROM_START=0x8000

5050

-ROM_SIZE=0x7fe0

5051

-RAM_START=0x0200

5052

-RAM_SIZE=1K

5053

-STACK=0x600

5054

-fi

5055

-

5056

-if [ "${MSP430_NAME}" = "msp430x148" ] ; then

5057

-ARCH=msp:14

5058

-ROM_START=0x4000

5059

-ROM_SIZE=0xbfe0

5060

-RAM_START=0x0200

5061

-RAM_SIZE=0x0800

5062

-STACK=0xa00

5063

-fi

5064

-

5065

-if [ "${MSP430_NAME}" = "msp430x149" ] ; then

5066

-ARCH=msp:14

5067

-ROM_START=0x1100

5068

-ROM_SIZE=0xeee0

5069

-RAM_START=0x0200

5070

-RAM_SIZE=0x0800

5071

-STACK=0xa00

5072

-fi

5073

-

5074

-if [ "${MSP430_NAME}" = "msp430x155" ] ; then

5075

-ARCH=msp:15

5076

-ROM_START=0xc000

5077

-ROM_SIZE=0x3fe0

5078

-RAM_START=0x0200

5079

-RAM_SIZE=512

5080

-STACK=0x400

5081

-fi

5082

-

5083

-if [ "${MSP430_NAME}" = "msp430x156" ] ; then

5084

-ARCH=msp:15

5085

-ROM_START=0xa000

5086

-ROM_SIZE=0x5fe0

5087

-RAM_START=0x0200

5088

-RAM_SIZE=512

5089

-STACK=0x400

5090

-fi

5091

-

5092

-if [ "${MSP430_NAME}" = "msp430x157" ] ; then

5093

-ARCH=msp:15

5094

-ROM_START=0x8000

5095

-ROM_SIZE=0x7fe0

5096

-RAM_START=0x0200

5097

-RAM_SIZE=1K

5098

-STACK=0x600

5099

-fi

5100

-

5101

-if [ "${MSP430_NAME}" = "msp430x167" ] ; then

5102

-ARCH=msp:16

5103

-ROM_START=0x8000

5104

-ROM_SIZE=0x7fe0

5105

-RAM_START=0x0200

5106

-RAM_SIZE=1K

5107

-STACK=0x600

5108

-fi

5109

-

5110

-if [ "${MSP430_NAME}" = "msp430x168" ] ; then

5111

-ARCH=msp:16

5112

-ROM_START=0x4000

5113

-ROM_SIZE=0xbfe0

5114

-RAM_START=0x0200

5115

-RAM_SIZE=0x0800

5116

-STACK=0xa00

5117

-fi

5118

-

5119

-if [ "${MSP430_NAME}" = "msp430x169" ] ; then

5120

-ARCH=msp:16

5121

-ROM_START=0x1100

5122

-ROM_SIZE=0xeee0

5123

-RAM_START=0x0200

5124

-RAM_SIZE=0x0800

5125

-STACK=0xa00

5126

-fi

5127

-

5128

-if [ "${MSP430_NAME}" = "msp430x1610" ] ; then

5129

-ARCH=msp:16

5130

-ROM_START=0x8000

5131

-ROM_SIZE=0x7fe0

5132

-RAM_START=0x1100

5133

-RAM_SIZE=0x1400

5134

-STACK=0x2500

5135

-fi

5136

-

5137

-if [ "${MSP430_NAME}" = "msp430x1611" ] ; then

5138

-ARCH=msp:16

5139

-ROM_START=0x4000

5140

-ROM_SIZE=0xbfe0

5141

-RAM_START=0x1100

5142

-RAM_SIZE=0x2800

5143

-STACK=0x3900

5144

-fi

5145

-

5146

-if [ "${MSP430_NAME}" = "msp430x1612" ] ; then

5147

-ARCH=msp:16

5148

-ROM_START=0x2500

5149

-ROM_SIZE=0xdae0

5150

-RAM_START=0x1100

5151

-RAM_SIZE=0x1400

5152

-STACK=0x2500

5153

-fi

5154

-

5155

-if [ "${MSP430_NAME}" = "msp430x2101" ] ; then

5156

-ARCH=msp:21

5157

-ROM_START=0xFC00

5158

-ROM_SIZE=0x03e0

5159

-RAM_START=0x0200

5160

-RAM_SIZE=128

5161

-STACK=0x280

5162

-fi

5163

-

5164

-if [ "${MSP430_NAME}" = "msp430x2111" ] ; then

5165

-ARCH=msp:21

5166

-ROM_START=0xF800

5167

-ROM_SIZE=0x07e0

5168

-RAM_START=0x0200

5169

-RAM_SIZE=128

5170

-STACK=0x280

5171

-fi

5172

-

5173

-if [ "${MSP430_NAME}" = "msp430x2121" ] ; then

5174

-ARCH=msp:21

5175

-ROM_START=0xf000

5176

-ROM_SIZE=0x0fe0

5177

-RAM_START=0x0200

5178

-RAM_SIZE=256

5179

-STACK=0x300

5180

-fi

5181

-

5182

-if [ "${MSP430_NAME}" = "msp430x2131" ] ; then

5183

-ARCH=msp:21

5184

-ROM_START=0xe000

5185

-ROM_SIZE=0x1fe0

5186

-RAM_START=0x0200

5187

-RAM_SIZE=256

5188

-STACK=0x300

5189

-fi

5190

-

5191

-if [ "${MSP430_NAME}" = "msp430x311" ] ; then

5192

-ARCH=msp:31

5193

-SCRIPT_NAME=elf32msp430_3

5194

-ROM_START=0xf800

5195

-ROM_SIZE=0x07e0

5196

-RAM_START=0x0200

5197

-RAM_SIZE=128

5198

-STACK=0x280

5199

-fi

5200

-

5201

-if [ "${MSP430_NAME}" = "msp430x312" ] ; then

5202

-ARCH=msp:31

5203

-SCRIPT_NAME=elf32msp430_3

5204

-ROM_START=0xf000

5205

-ROM_SIZE=0x0fe0

5206

-RAM_START=0x0200

5207

-RAM_SIZE=256

5208

-STACK=0x300

5209

-fi

5210

-

5211

-if [ "${MSP430_NAME}" = "msp430x313" ] ; then

5212

-ARCH=msp:31

5213

-SCRIPT_NAME=elf32msp430_3

5214

-ROM_START=0xe000

5215

-ROM_SIZE=0x1fe0

5216

-RAM_START=0x0200

5217

-RAM_SIZE=256

5218

-STACK=0x300

5219

-fi

5220

-

5221

-if [ "${MSP430_NAME}" = "msp430x314" ] ; then

5222

-ARCH=msp:31

5223

-SCRIPT_NAME=elf32msp430_3

5224

-ROM_START=0xd000

5225

-ROM_SIZE=0x2fe0

5226

-RAM_START=0x0200

5227

-RAM_SIZE=512

5228

-STACK=0x400

5229

-fi

5230

-

5231

-if [ "${MSP430_NAME}" = "msp430x315" ] ; then

5232

-ARCH=msp:31

5233

-SCRIPT_NAME=elf32msp430_3

5234

-ROM_START=0xc000

5235

-ROM_SIZE=0x3fe0

5236

-RAM_START=0x0200

5237

-RAM_SIZE=512

5238

-STACK=0x400

5239

-fi

5240

-

5241

-if [ "${MSP430_NAME}" = "msp430x323" ] ; then

5242

-ARCH=msp:32

5243

-SCRIPT_NAME=elf32msp430_3

5244

-ROM_START=0xe000

5245

-ROM_SIZE=0x1fe0

5246

-RAM_START=0x0200

5247

-RAM_SIZE=256

5248

-STACK=0x300

5249

-fi

5250

-

5251

-if [ "${MSP430_NAME}" = "msp430x325" ] ; then

5252

-ARCH=msp:32

5253

-SCRIPT_NAME=elf32msp430_3

5254

-ROM_START=0xc000

5255

-ROM_SIZE=0x3fe0

5256

-RAM_START=0x0200

5257

-RAM_SIZE=512

5258

-STACK=0x400

5259

-fi

5260

-

5261

-if [ "${MSP430_NAME}" = "msp430x336" ] ; then

5262

-ARCH=msp:33

5263

-SCRIPT_NAME=elf32msp430_3

5264

-ROM_START=0xa000

5265

-ROM_SIZE=0x5fe0

5266

-RAM_START=0x0200

5267

-RAM_SIZE=1024

5268

-STACK=0x600

5269

-fi

5270

-

5271

-if [ "${MSP430_NAME}" = "msp430x337" ] ; then

5272

-ARCH=msp:33

5273

-SCRIPT_NAME=elf32msp430_3

5274

-ROM_START=0x8000

5275

-ROM_SIZE=0x7fe0

5276

-RAM_START=0x0200

5277

-RAM_SIZE=1024

5278

-STACK=0x600

5279

-fi

5280

-

5281

-if [ "${MSP430_NAME}" = "msp430x412" ] ; then

5282

-ARCH=msp:41

5283

-ROM_START=0xf000

5284

-ROM_SIZE=0x0fe0

5285

-RAM_START=0x0200

5286

-RAM_SIZE=256

5287

-STACK=0x300

5288

-fi

5289

-

5290

-if [ "${MSP430_NAME}" = "msp430x413" ] ; then

5291

-ARCH=msp:41

5292

-ROM_START=0xe000

5293

-ROM_SIZE=0x1fe0

5294

-RAM_START=0x0200

5295

-RAM_SIZE=256

5296

-STACK=0x300

5297

-fi

5298

-

5299

-if [ "${MSP430_NAME}" = "msp430x415" ] ; then

5300

-ARCH=msp:41

5301

-ROM_START=0xc000

5302

-ROM_SIZE=0x3fe0

5303

-RAM_START=0x0200

5304

-RAM_SIZE=512

5305

-STACK=0x400

5306

-fi

5307

-

5308

-if [ "${MSP430_NAME}" = "msp430x417" ] ; then

5309

-ARCH=msp:41

5310

-ROM_START=0x8000

5311

-ROM_SIZE=0x7fe0

5312

-RAM_START=0x0200

5313

-RAM_SIZE=1024

5314

-STACK=0x600

5315

-fi

5316

-

5317

-if [ "${MSP430_NAME}" = "msp430x435" ] ; then

5318

-ARCH=msp:43

5319

-ROM_START=0xc000

5320

-ROM_SIZE=0x3fe0

5321

-RAM_START=0x0200

5322

-RAM_SIZE=512

5323

-STACK=0x400

5324

-fi

5325

-

5326

-if [ "${MSP430_NAME}" = "msp430x436" ] ; then

5327

-ARCH=msp:43

5328

-ROM_START=0xa000

5329

-ROM_SIZE=0x5fe0

5330

-RAM_START=0x0200

5331

-RAM_SIZE=1024

5332

-STACK=0x600

5333

-fi

5334

-

5335

-if [ "${MSP430_NAME}" = "msp430x437" ] ; then

5336

-ARCH=msp:43

5337

-ROM_START=0x8000

5338

-ROM_SIZE=0x7fe0

5339

-RAM_START=0x0200

5340

-RAM_SIZE=1024

5341

-STACK=0x600

5342

-fi

5343

-

5344

-if [ "${MSP430_NAME}" = "msp430x447" ] ; then

5345

-ARCH=msp:44

5346

-ROM_START=0x8000

5347

-ROM_SIZE=0x7fe0

5348

-RAM_START=0x0200

5349

-RAM_SIZE=1024

5350

-STACK=0x600

5351

-fi

5352

-

5353

-if [ "${MSP430_NAME}" = "msp430x448" ] ; then

5354

-ARCH=msp:44

5355

-ROM_START=0x4000

5356

-ROM_SIZE=0xbfe0

5357

-RAM_START=0x0200

5358

-RAM_SIZE=0x0800

5359

-STACK=0xa00

5360

-fi

5361

-

5362

-if [ "${MSP430_NAME}" = "msp430x449" ] ; then

5363

-ARCH=msp:44

5364

-ROM_START=0x1100

5365

-ROM_SIZE=0xeee0

5366

-RAM_START=0x0200

5367

-RAM_SIZE=0x0800

5368

-STACK=0xa00

5369

-fi

5370

-

5371

-if [ "${MSP430_NAME}" = "msp430xE423" ] ; then

5372

-ARCH=msp:42

5373

-ROM_START=0xe000

5374

-ROM_SIZE=0x1fe0

5375

-RAM_START=0x0200

5376

-RAM_SIZE=256

5377

-STACK=0x300

5378

-fi

5379

-

5380

-if [ "${MSP430_NAME}" = "msp430xE425" ] ; then

5381

-ARCH=msp:42

5382

-ROM_START=0xc000

5383

-ROM_SIZE=0x3fe0

5384

-RAM_START=0x0200

5385

-RAM_SIZE=512

5386

-STACK=0x400

5387

-fi

5388

-

5389

-if [ "${MSP430_NAME}" = "msp430xE427" ] ; then

5390

-ARCH=msp:42

5391

-ROM_START=0x8000

5392

-ROM_SIZE=0x7fe0

5393

-RAM_START=0x0200

5394

-RAM_SIZE=1024

5395

-STACK=0x600

5396

-fi

5397

-

5398

-if [ "${MSP430_NAME}" = "msp430xG437" ] ; then

5399

-ARCH=msp:43

5400

-ROM_START=0x8000

5401

-ROM_SIZE=0x7fe0

5402

-RAM_START=0x0200

5403

-RAM_SIZE=1024

5404

-STACK=0x600

5405

-fi

5406

-

5407

-if [ "${MSP430_NAME}" = "msp430xG438" ] ; then

5408

-ARCH=msp:43

5409

-ROM_START=0x4000

5410

-ROM_SIZE=0xbef0

5411

-RAM_START=0x0200

5412

-RAM_SIZE=0x0800

5413

-STACK=0xa00

5414

-fi

5415

-

5416

-if [ "${MSP430_NAME}" = "msp430xG439" ] ; then

5417

-ARCH=msp:43

5418

-ROM_START=0x1100

5419

-ROM_SIZE=0xeee0

5420

-RAM_START=0x0200

5421

-RAM_SIZE=0x0800

5422

-STACK=0xa00

5423

-fi

5424

-

5425

-if [ "${MSP430_NAME}" = "msp430xW423" ] ; then

5426

-ARCH=msp:42

5427

-ROM_START=0xe000

5428

-ROM_SIZE=0x1fe0

5429

-RAM_START=0x0200

5430

-RAM_SIZE=256

5431

-STACK=0x300

5432

-fi

5433

-

5434

-if [ "${MSP430_NAME}" = "msp430xW425" ] ; then

5435

-ARCH=msp:42

5436

-ROM_START=0xc000

5437

-ROM_SIZE=0x3fe0

5438

-RAM_START=0x0200

5439

-RAM_SIZE=512

5440

-STACK=0x400

5441

-fi

5442

-

5443

-if [ "${MSP430_NAME}" = "msp430xW427" ] ; then

5444

-ARCH=msp:42

5445

-ROM_START=0x8000

5446

-ROM_SIZE=0x7fe0

5447

-RAM_START=0x0200

5448

-RAM_SIZE=0x400

5449

-STACK=0x600

5450

-fi

5451

diff --git a/ld/emulparams/msp430uni.sh b/ld/emulparams/msp430uni.sh

5452

new file mode 100644

5453

index 0000000..ac7473f

5454

--- /dev/null

5455

+++ b/ld/emulparams/msp430uni.sh

5456

@@ -0,0 +1,13 @@

5457

+#!/bin/sh

5458

+

5459

+# This called by genscripts_extra.sh

5460

+

5461

+MSP430_NAME=${EMULATION_NAME}

5462

+SCRIPT_NAME=elf32msp430

5463

+TEMPLATE_NAME=generic

5464

+EXTRA_EM_FILE=msp430

5465

+OUTPUT_FORMAT="elf32-msp430"

5466

+MACHINE=

5467

+MAXPAGESIZE=1

5468

+EMBEDDED=yes

5469

+

5470

diff --git a/ld/emultempl/msp430.em b/ld/emultempl/msp430.em

5471

new file mode 100644

5472

index 0000000..f4586f8

5473

--- /dev/null

5474

+++ b/ld/emultempl/msp430.em

5475

@@ -0,0 +1,107 @@

5476

+# This shell script emits a C file. -*- C -*-

5477

5478

+#

5479

+# This file is part of the GNU Binutils.

5480

+#

5481

+# This program is free software; you can redistribute it and/or modify

5482

+# it under the terms of the GNU General Public License as published by

5483

+# the Free Software Foundation; either version 3 of the License, or

5484

+# (at your option) any later version.

5485

+#

5486

+# This program is distributed in the hope that it will be useful,

5487

+# but WITHOUT ANY WARRANTY; without even the implied warranty of

5488

+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

5489

+# GNU General Public License for more details.

5490

+#

5491

+# You should have received a copy of the GNU General Public License

5492

+# along with this program; if not, write to the Free Software

5493

+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,

5494

+# MA 02110-1301, USA.

5495

+#

5496

+

5497

+# Adapt genelf.em for MSP430

5498

+# This file is sourced from generic.em

5499

+#

5500

+fragment <<EOF

5501

+#include "elf-bfd.h"

5502

+#include "libbfd.h"

5503

+#include "elf/msp430.h"

5504

+

5505

+EOF

5506

+source_em ${srcdir}/emultempl/elf-generic.em

5507

+fragment <<EOF

5508

+

5509

+static void

5510

+gld${EMULATION_NAME}_after_open (void)

5511

+{

5512

+ bfd *ibfd;

5513

+ asection *sec;

5514

+ asymbol **syms;

5515

+

5516

+ after_open_default ();

5517

+

5518

+ if (link_info.relocatable)

5519

+ for (ibfd = link_info.input_bfds; ibfd != NULL; ibfd = ibfd->link_next)

5520

+ if ((syms = bfd_get_outsymbols (ibfd)) != NULL

5521

+ && bfd_get_flavour (ibfd) == bfd_target_elf_flavour)

5522

+ for (sec = ibfd->sections; sec != NULL; sec = sec->next)

5523

+ if ((sec->flags & (SEC_GROUP | SEC_LINKER_CREATED)) == SEC_GROUP)

5524

+ {

5525

+ struct bfd_elf_section_data *sec_data = elf_section_data (sec);

5526

+ elf_group_id (sec) = syms[sec_data->this_hdr.sh_info - 1];

5527

+ }

5528

+}

5529

+

5530

+static void

5531

+gld${EMULATION_NAME}_before_allocation (void)

5532

+{

5533

+ if (link_info.relocatable

5534

+ && !_bfd_elf_size_group_sections (&link_info))

5535

+ einfo ("%X%P: can not size group sections: %E\n");

5536

+ before_allocation_default ();

5537

+}

5538

+

5539

+static void

5540

+gld${EMULATION_NAME}_after_allocation (void)

5541

+{

5542

+ gld${EMULATION_NAME}_map_segments (FALSE);

5543

+}

5544

+

5545

+static void

5546

+gld${EMULATION_NAME}_finish (void)

5547

+{

5548

+ bfd *obfd = link_info.output_bfd;

5549

+ Elf_Internal_Ehdr *o_ehdrp = elf_elfheader (obfd);

5550

+ unsigned long flags = 0;

5551

+ bfd *ibfd;

5552

+

5553

+ for (ibfd = link_info.input_bfds; ibfd != NULL; ibfd = ibfd->link_next) {

5554

+ Elf_Internal_Ehdr * i_ehdrp = elf_elfheader (ibfd);

5555

+

5556

+ if (EF_MSP430_UNIARCH & i_ehdrp->e_flags)

5557

+ flags |= i_ehdrp->e_flags;

5558

+ }

5559

+ if (EF_MSP430_UNIARCH & flags) {

5560

+ int bfd_mach;

5561

+ switch (flags & EF_MSP430_ARCH)

5562

+ {

5563

+ default:

5564

+ case EF_MSP430_ARCH_430:

5565

+ bfd_mach = bfd_mach_msp430;

5566

+ break;

5567

+ case EF_MSP430_ARCH_430X:

5568

+ bfd_mach = bfd_mach_msp430x;

5569

+ break;

5570

+ }

5571

+ bfd_default_set_arch_mach (obfd, bfd_arch_msp430, bfd_mach);

5572

+ o_ehdrp->e_flags = flags;

5573

+ }

5574

+ finish_default();

5575

+}

5576

+EOF

5577

+# Put these extra routines in ld_${EMULATION_NAME}_emulation

5578

+#

5579

+LDEMUL_AFTER_OPEN=gld${EMULATION_NAME}_after_open

5580

+LDEMUL_BEFORE_ALLOCATION=gld${EMULATION_NAME}_before_allocation

5581

+LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation

5582

+LDEMUL_FINISH=gld${EMULATION_NAME}_finish

5583

diff --git a/ld/scripttempl/elf32msp430.sc b/ld/scripttempl/elf32msp430.sc

5584

index cbffe48..cb3e754 100644

5585

--- a/ld/scripttempl/elf32msp430.sc

5586

+++ b/ld/scripttempl/elf32msp430.sc

5587

@@ -1,37 +1,11 @@

5588

#!/bin/sh

5589

5590

-HEAP_SECTION_MSP430=" "

5591

-HEAP_MEMORY_MSP430=" "

5592

-

5593

-if test ${GOT_HEAP_MSP-0} -ne 0

5594

-then

5595

-HEAP_SECTION_MSP430=".heap ${RELOCATING-0} :

5596

- {

5597

- ${RELOCATING+ PROVIDE (__heap_data_start = .) ; }

5598

- *(.heap*)

5599

- ${RELOCATING+ PROVIDE (_heap_data_end = .) ; }

5600

- ${RELOCATING+. = ALIGN(2);}

5601

- ${RELOCATING+ PROVIDE (__heap_bottom = .) ; }

5602

- ${RELOCATING+ PROVIDE (__heap_top = ${HEAP_START} + ${HEAP_LENGTH}) ; }

5603

- } ${RELOCATING+ > heap}"

5604

-HEAP_MEMORY_MSP430="heap(rwx) : ORIGIN = $HEAP_START, LENGTH = $HEAP_LENGTH"

5605

-fi

5606

-

5607

-

5608

cat <<EOF

5609

-OUTPUT_FORMAT("${OUTPUT_FORMAT}","${OUTPUT_FORMAT}","${OUTPUT_FORMAT}")

5610

-OUTPUT_ARCH(${ARCH})

5611

+OUTPUT_FORMAT("${OUTPUT_FORMAT}")

5612

+OUTPUT_ARCH("${MSP430_NAME}")

5613

5614

-MEMORY

5615

-{

5616

- text (rx) : ORIGIN = $ROM_START, LENGTH = $ROM_SIZE

5617

- data (rwx) : ORIGIN = $RAM_START, LENGTH = $RAM_SIZE

5618

- vectors (rw) : ORIGIN = 0xffe0, LENGTH = 0x20

5619

- bootloader(rx) : ORIGIN = 0x0c00, LENGTH = 1K

5620

- infomem(rx) : ORIGIN = 0x1000, LENGTH = 256

5621

- infomemnobits(rx) : ORIGIN = 0x1000, LENGTH = 256

5622

- ${HEAP_MEMORY_MSP430}

5623

-}

5624

+${RELOCATING+INCLUDE "memory.x"}

5625

+${RELOCATING+INCLUDE "periph.x"}

5626

5627

SECTIONS

5628

{

5629

@@ -98,109 +72,104 @@ SECTIONS

5630

/* Internal text space. */

5631

.text :

5632

{

5633

- ${RELOCATING+. = ALIGN(2);}

5634

- *(.init)

5635

- *(.init0) /* Start here after reset. */

5636

- *(.init1)

5637

- *(.init2) /* Copy data loop */

5638

- *(.init3)

5639

- *(.init4) /* Clear bss */

5640

- *(.init5)

5641

- *(.init6) /* C++ constructors. */

5642

- *(.init7)

5643

- *(.init8)

5644

- *(.init9) /* Call main(). */

5645

+ ${RELOCATING+ . = ALIGN(2);}

5646

+ KEEP(*(.init))

5647

+ *(.init0) /* Start here after reset. */

5648

+ *(.init1) /* User definable. */

5649

+ *(.init2) /* Initialize stack. */

5650

+ *(.init3) /* Initialize hardware, user definable. */

5651

+ *(.init4) /* Copy data to .data, clear bss. */

5652

+ *(.init5) /* User definable. */

5653

+ *(.init6) /* C++ constructors. */

5654

+ *(.init7) /* User definable. */

5655

+ *(.init8) /* User definable. */

5656

+ *(.init9) /* Call main(). */

5657

+ *(.fini9) /* Falls into here after main(). User definable. */

5658

+ *(.fini8) /* User definable. */

5659

+ *(.fini7) /* User definable. */

5660

+ *(.fini6) /* C++ destructors. */

5661

+ *(.fini5) /* User definable. */

5662

+ *(.fini4) /* User definable. */

5663

+ *(.fini3) /* User definable. */

5664

+ *(.fini2) /* User definable. */

5665

+ *(.fini1) /* User definable. */

5666

+ *(.fini0) /* Infinite loop after program termination. */

5667

+ KEEP(*(.fini))

5668

5669

+ ${CONSTRUCTING+ . = ALIGN(2); }

5670

${CONSTRUCTING+ __ctors_start = . ; }

5671

- ${CONSTRUCTING+ *(.ctors) }

5672

+ ${CONSTRUCTING+ KEEP(*(.ctors)) }

5673

${CONSTRUCTING+ __ctors_end = . ; }

5674

${CONSTRUCTING+ __dtors_start = . ; }

5675

- ${CONSTRUCTING+ *(.dtors) }

5676

+ ${CONSTRUCTING+ KEEP(*(.dtors)) }

5677

${CONSTRUCTING+ __dtors_end = . ; }

5678

5679

- ${RELOCATING+. = ALIGN(2);}

5680

+ ${RELOCATING+ . = ALIGN(2);}

5681

*(.text)

5682

- ${RELOCATING+. = ALIGN(2);}

5683

+ ${RELOCATING+ . = ALIGN(2);}

5684

*(.text.*)

5685

5686

- ${RELOCATING+. = ALIGN(2);}

5687

- *(.fini9) /* */

5688

- *(.fini8)

5689

- *(.fini7)

5690

- *(.fini6) /* C++ destructors. */

5691

- *(.fini5)

5692

- *(.fini4)

5693

- *(.fini3)

5694

- *(.fini2)

5695

- *(.fini1)

5696

- *(.fini0) /* Infinite loop after program termination. */

5697

- *(.fini)

5698

+ ${RELOCATING+ _etext = .;}

5699

+ } ${RELOCATING+ > REGION_TEXT}

5700

5701

- _etext = .;

5702

- } ${RELOCATING+ > text}

5703

-

5704

- .data ${RELOCATING-0} : ${RELOCATING+AT (ADDR (.text) + SIZEOF (.text))}

5705

+ .data ${RELOCATING-0} :

5706

{

5707

+ ${RELOCATING+ . = ALIGN(2);}

5708

${RELOCATING+ PROVIDE (__data_start = .) ; }

5709

- ${RELOCATING+. = ALIGN(2);}

5710

*(.data)

5711

- ${RELOCATING+. = ALIGN(2);}

5712

+ *(SORT_BY_ALIGNMENT(.data.*))

5713

+ ${RELOCATING+ . = ALIGN(2);}

5714

*(.gnu.linkonce.d*)

5715

- ${RELOCATING+. = ALIGN(2);}

5716

+ ${RELOCATING+ . = ALIGN(2);}

5717

${RELOCATING+ _edata = . ; }

5718

- } ${RELOCATING+ > data}

5719

+ } ${RELOCATING+ > REGION_DATA AT > REGION_TEXT}

5720

+ ${RELOCATING+ PROVIDE (__data_load_start = LOADADDR(.data) ); }

5721

+ ${RELOCATING+ PROVIDE (__data_size = SIZEOF(.data) ); }

5722

5723

- /* Bootloader. */

5724

- .bootloader ${RELOCATING-0} :

5725

- {

5726

- ${RELOCATING+ PROVIDE (__boot_start = .) ; }

5727

- *(.bootloader)

5728

- ${RELOCATING+. = ALIGN(2);}

5729

- *(.bootloader.*)

5730

- } ${RELOCATING+ > bootloader}

5731

-

5732

- /* Information memory. */

5733

- .infomem ${RELOCATING-0} :

5734

- {

5735

- *(.infomem)

5736

- ${RELOCATING+. = ALIGN(2);}

5737

- *(.infomem.*)

5738

- } ${RELOCATING+ > infomem}

5739

-

5740

- /* Information memory (not loaded into MPU). */

5741

- .infomemnobits ${RELOCATING-0} :

5742

- {

5743

- *(.infomemnobits)

5744

- ${RELOCATING+. = ALIGN(2);}

5745

- *(.infomemnobits.*)

5746

- } ${RELOCATING+ > infomemnobits}

5747

-

5748

- .bss ${RELOCATING+ SIZEOF(.data) + ADDR(.data)} :

5749

+ .bss ${RELOCATING-0} :

5750

{

5751

${RELOCATING+ PROVIDE (__bss_start = .) ; }

5752

*(.bss)

5753

+ *(SORT_BY_ALIGNMENT(.bss.*))

5754

*(COMMON)

5755

${RELOCATING+ PROVIDE (__bss_end = .) ; }

5756

${RELOCATING+ _end = . ; }

5757

- } ${RELOCATING+ > data}

5758

+ } ${RELOCATING+ > REGION_DATA}

5759

+ ${RELOCATING+ PROVIDE (__bss_size = SIZEOF(.bss) ); }

5760

5761

- .noinit ${RELOCATING+ SIZEOF(.bss) + ADDR(.bss)} :

5762

+ .noinit ${RELOCATING-0} :

5763

{

5764

${RELOCATING+ PROVIDE (__noinit_start = .) ; }

5765

*(.noinit)

5766

+ *(.noinit.*)

5767

*(COMMON)

5768

${RELOCATING+ PROVIDE (__noinit_end = .) ; }

5769

${RELOCATING+ _end = . ; }

5770

- } ${RELOCATING+ > data}

5771

+ } ${RELOCATING+ > REGION_DATA}

5772

+

5773

+ /* Information memory. */

5774

+ .infomem ${RELOCATING-0} :

5775

+ {

5776

+ *(.infomem)

5777

+ ${RELOCATING+ . = ALIGN(2);}

5778

+ *(.infomem.*)

5779

+ } ${RELOCATING+ > infomem}

5780

5781

.vectors ${RELOCATING-0}:

5782

{

5783

${RELOCATING+ PROVIDE (__vectors_start = .) ; }

5784

- *(.vectors*)

5785

+ KEEP(*(.vectors*))

5786

${RELOCATING+ _vectors_end = . ; }

5787

} ${RELOCATING+ > vectors}

5788

5789

- ${HEAP_SECTION_MSP430}

5790

+ .fartext :

5791

+ {

5792

+ ${RELOCATING+ . = ALIGN(2);}

5793

+ *(.fartext)

5794

+ ${RELOCATING+ . = ALIGN(2);}

5795

+ *(.fartext.*)

5796

+ ${RELOCATING+ _efartext = .;}

5797

+ } ${RELOCATING+ > REGION_FAR_ROM}

5798

5799

/* Stabs for profiling information*/

5800

.profiler 0 : { *(.profiler) }

5801

@@ -239,11 +208,14 @@ SECTIONS

5802

.debug_loc 0 : { *(.debug_loc) }

5803

.debug_macinfo 0 : { *(.debug_macinfo) }

5804

5805

- PROVIDE (__stack = ${STACK}) ;

5806

- PROVIDE (__data_start_rom = _etext) ;

5807

- PROVIDE (__data_end_rom = _etext + SIZEOF (.data)) ;

5808

- PROVIDE (__noinit_start_rom = _etext + SIZEOF (.data)) ;

5809

- PROVIDE (__noinit_end_rom = _etext + SIZEOF (.data) + SIZEOF (.noinit)) ;

5810

- PROVIDE (__subdevice_has_heap = ${GOT_HEAP_MSP-0}) ;

5811

+ /* DWARF 3 */

5812

+ .debug_pubtypes 0 : { *(.debug_pubtypes) }

5813

+ .debug_ranges 0 : { *(.debug_ranges) }

5814

+

5815

+ ${RELOCATING+ PROVIDE (__stack = ORIGIN(ram) + LENGTH(ram));}

5816

+ ${RELOCATING+ PROVIDE (__data_start_rom = _etext);}

5817

+ ${RELOCATING+ PROVIDE (__data_end_rom = _etext + SIZEOF (.data));}

5818

+ ${RELOCATING+ PROVIDE (__noinit_start_rom = _etext + SIZEOF (.data));}

5819

+ ${RELOCATING+ PROVIDE (__noinit_end_rom = _etext + SIZEOF (.data) + SIZEOF (.noinit));}

5820

}

5821

EOF

5822

diff --git a/ld/scripttempl/elf32msp430_3.sc b/ld/scripttempl/elf32msp430_3.sc

5823

deleted file mode 100644

5824

index 15eb517..0000000

5825

--- a/ld/scripttempl/elf32msp430_3.sc

5826

+++ /dev/null

5827

@@ -1,192 +0,0 @@

5828

-cat <<EOF

5829

-OUTPUT_FORMAT("${OUTPUT_FORMAT}","${OUTPUT_FORMAT}","${OUTPUT_FORMAT}")

5830

-OUTPUT_ARCH(${ARCH})

5831

-

5832

-MEMORY

5833

-{

5834

- text (rx) : ORIGIN = $ROM_START, LENGTH = $ROM_SIZE

5835

- data (rwx) : ORIGIN = $RAM_START, LENGTH = $RAM_SIZE

5836

- vectors (rw) : ORIGIN = 0xffe0, LENGTH = 0x20

5837

-}

5838

-

5839

-SECTIONS

5840

-{

5841

- /* Read-only sections, merged into text segment. */

5842

- ${TEXT_DYNAMIC+${DYNAMIC}}

5843

- .hash ${RELOCATING-0} : { *(.hash) }

5844

- .dynsym ${RELOCATING-0} : { *(.dynsym) }

5845

- .dynstr ${RELOCATING-0} : { *(.dynstr) }

5846

- .gnu.version ${RELOCATING-0} : { *(.gnu.version) }

5847

- .gnu.version_d ${RELOCATING-0} : { *(.gnu.version_d) }

5848

- .gnu.version_r ${RELOCATING-0} : { *(.gnu.version_r) }

5849

-

5850

- .rel.init ${RELOCATING-0} : { *(.rel.init) }

5851

- .rela.init ${RELOCATING-0} : { *(.rela.init) }

5852

- .rel.text ${RELOCATING-0} :

5853

- {

5854

- *(.rel.text)

5855

- ${RELOCATING+*(.rel.text.*)}

5856

- ${RELOCATING+*(.rel.gnu.linkonce.t*)}

5857

- }

5858

- .rela.text ${RELOCATING-0} :

5859

- {

5860

- *(.rela.text)

5861

- ${RELOCATING+*(.rela.text.*)}

5862

- ${RELOCATING+*(.rela.gnu.linkonce.t*)}

5863

- }

5864

- .rel.fini ${RELOCATING-0} : { *(.rel.fini) }

5865

- .rela.fini ${RELOCATING-0} : { *(.rela.fini) }

5866

- .rel.rodata ${RELOCATING-0} :

5867

- {

5868

- *(.rel.rodata)

5869

- ${RELOCATING+*(.rel.rodata.*)}

5870

- ${RELOCATING+*(.rel.gnu.linkonce.r*)}

5871

- }

5872

- .rela.rodata ${RELOCATING-0} :

5873

- {

5874

- *(.rela.rodata)

5875

- ${RELOCATING+*(.rela.rodata.*)}

5876

- ${RELOCATING+*(.rela.gnu.linkonce.r*)}

5877

- }

5878

- .rel.data ${RELOCATING-0} :

5879

- {

5880

- *(.rel.data)

5881

- ${RELOCATING+*(.rel.data.*)}

5882

- ${RELOCATING+*(.rel.gnu.linkonce.d*)}

5883

- }

5884

- .rela.data ${RELOCATING-0} :

5885

- {

5886

- *(.rela.data)

5887

- ${RELOCATING+*(.rela.data.*)}

5888

- ${RELOCATING+*(.rela.gnu.linkonce.d*)}

5889

- }

5890

- .rel.ctors ${RELOCATING-0} : { *(.rel.ctors) }

5891

- .rela.ctors ${RELOCATING-0} : { *(.rela.ctors) }

5892

- .rel.dtors ${RELOCATING-0} : { *(.rel.dtors) }

5893

- .rela.dtors ${RELOCATING-0} : { *(.rela.dtors) }

5894

- .rel.got ${RELOCATING-0} : { *(.rel.got) }

5895

- .rela.got ${RELOCATING-0} : { *(.rela.got) }

5896

- .rel.bss ${RELOCATING-0} : { *(.rel.bss) }

5897

- .rela.bss ${RELOCATING-0} : { *(.rela.bss) }

5898

- .rel.plt ${RELOCATING-0} : { *(.rel.plt) }

5899

- .rela.plt ${RELOCATING-0} : { *(.rela.plt) }

5900

-

5901

- /* Internal text space. */

5902

- .text :

5903

- {

5904

- ${RELOCATING+. = ALIGN(2);}

5905

- *(.init)

5906

- *(.init0) /* Start here after reset. */

5907

- *(.init1)

5908

- *(.init2)

5909

- *(.init3)

5910

- *(.init4)

5911

- *(.init5)

5912

- *(.init6) /* C++ constructors. */

5913

- *(.init7)

5914

- *(.init8)

5915

- *(.init9) /* Call main(). */

5916

-

5917

- ${CONSTRUCTING+ __ctors_start = . ; }

5918

- ${CONSTRUCTING+ *(.ctors) }

5919

- ${CONSTRUCTING+ __ctors_end = . ; }

5920

- ${CONSTRUCTING+ __dtors_start = . ; }

5921

- ${CONSTRUCTING+ *(.dtors) }

5922

- ${CONSTRUCTING+ __dtors_end = . ; }

5923

-

5924

- ${RELOCATING+. = ALIGN(2);}

5925

- *(.text)

5926

- ${RELOCATING+. = ALIGN(2);}

5927

- *(.text.*)

5928

-

5929

- ${RELOCATING+. = ALIGN(2);}

5930

- *(.fini9)

5931

- *(.fini8)

5932

- *(.fini7)

5933

- *(.fini6) /* C++ destructors. */

5934

- *(.fini5)

5935

- *(.fini4)

5936

- *(.fini3)

5937

- *(.fini2)

5938

- *(.fini1)

5939

- *(.fini0) /* Infinite loop after program termination. */

5940

- *(.fini)

5941

-

5942

- ${RELOCATING+ _etext = . ; }

5943

- } ${RELOCATING+ > text}

5944

-

5945

- .data ${RELOCATING-0} : ${RELOCATING+AT (ADDR (.text) + SIZEOF (.text))}

5946

- {

5947

- ${RELOCATING+ PROVIDE (__data_start = .) ; }

5948

- *(.data)

5949

- *(.gnu.linkonce.d*)

5950

- ${RELOCATING+. = ALIGN(2);}

5951

- ${RELOCATING+ _edata = . ; }

5952

- } ${RELOCATING+ > data}

5953

-

5954

- .bss ${RELOCATING+ SIZEOF(.data) + ADDR(.data)} :

5955

- {

5956

- ${RELOCATING+ PROVIDE (__bss_start = .) ; }

5957

- *(.bss)

5958

- *(COMMON)

5959

- ${RELOCATING+ PROVIDE (__bss_end = .) ; }

5960

- ${RELOCATING+ _end = . ; }

5961

- } ${RELOCATING+ > data}

5962

-

5963

- .noinit ${RELOCATING+ SIZEOF(.bss) + ADDR(.bss)} :

5964

- {

5965

- ${RELOCATING+ PROVIDE (__noinit_start = .) ; }

5966

- *(.noinit)

5967

- *(COMMON)

5968

- ${RELOCATING+ PROVIDE (__noinit_end = .) ; }

5969

- ${RELOCATING+ _end = . ; }

5970

- } ${RELOCATING+ > data}

5971

-

5972

- .vectors ${RELOCATING-0}:

5973

- {

5974

- ${RELOCATING+ PROVIDE (__vectors_start = .) ; }

5975

- *(.vectors*)

5976

- ${RELOCATING+ _vectors_end = . ; }

5977

- } ${RELOCATING+ > vectors}

5978

-

5979

- /* Stabs debugging sections. */

5980

- .stab 0 : { *(.stab) }

5981

- .stabstr 0 : { *(.stabstr) }

5982

- .stab.excl 0 : { *(.stab.excl) }

5983

- .stab.exclstr 0 : { *(.stab.exclstr) }

5984

- .stab.index 0 : { *(.stab.index) }

5985

- .stab.indexstr 0 : { *(.stab.indexstr) }

5986

- .comment 0 : { *(.comment) }

5987

-

5988

- /* DWARF debug sections.

5989

- Symbols in the DWARF debugging sections are relative to the beginning

5990

- of the section so we begin them at 0. */

5991

-

5992

- /* DWARF 1 */

5993

- .debug 0 : { *(.debug) }

5994

- .line 0 : { *(.line) }

5995

-

5996

- /* GNU DWARF 1 extensions */

5997

- .debug_srcinfo 0 : { *(.debug_srcinfo) }

5998

- .debug_sfnames 0 : { *(.debug_sfnames) }

5999

-

6000

- /* DWARF 1.1 and DWARF 2 */

6001

- .debug_aranges 0 : { *(.debug_aranges) }

6002

- .debug_pubnames 0 : { *(.debug_pubnames) }

6003

-

6004

- /* DWARF 2 */

6005

- .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }

6006

- .debug_abbrev 0 : { *(.debug_abbrev) }

6007

- .debug_line 0 : { *(.debug_line) }

6008

- .debug_frame 0 : { *(.debug_frame) }

6009

- .debug_str 0 : { *(.debug_str) }

6010

- .debug_loc 0 : { *(.debug_loc) }

6011

- .debug_macinfo 0 : { *(.debug_macinfo) }

6012

-

6013

- PROVIDE (__stack = ${STACK}) ;

6014

- PROVIDE (__data_start_rom = _etext) ;

6015

- PROVIDE (__data_end_rom = _etext + SIZEOF (.data)) ;

6016

- PROVIDE (__noinit_start_rom = _etext + SIZEOF (.data)) ;

6017

- PROVIDE (__noinit_end_rom = _etext + SIZEOF (.data) + SIZEOF (.noinit)) ;

6018

-}

6019

-EOF

6020

diff --git a/opcodes/msp430-dis.c b/opcodes/msp430-dis.c

6021

index 9d7edbe..a00c718 100644

6022

--- a/opcodes/msp430-dis.c

6023

+++ b/opcodes/msp430-dis.c

6024

@@ -52,12 +52,153 @@ msp430dis_opcode (bfd_vma addr, disassemble_info *info)

6025

return bfd_getl16 (buffer);

6026

}

6027

6028

+static unsigned short

6029

+msp430dis_operand (bfd_vma addr, disassemble_info *info, int reg, int am, int *cmd_len)

6030

+{

6031

+ static int const op_length [][5] =

6032

+ {

6033

+ // am | reg 0 1 2 3 >3

6034

+ /* 0 */ { 0, 0, 0, 0, 0 }, // Rn

6035

+ /* 1 */ { 2, 2, 2, 0, 2 }, // x(Rn)

6036

+ /* 2 */ { 0, 0, 0, 0, 0 }, // @Rn

6037

+ /* 3 */ { 2, 0, 0, 0, 0 }, // @Rn+

6038

+ };

6039

+ if (reg >= (int)(sizeof(op_length[0]) / sizeof(op_length[0][0])))

6040

+ reg = sizeof(op_length[0]) / sizeof(op_length[0][0])- 1;

6041

+

6042

+ if (op_length[am][reg])

6043

+ {

6044

+ bfd_byte buffer[2];

6045

+ int status = info->read_memory_func (addr, buffer, 2, info);

6046

+ if (status != 0)

6047

+ {

6048

+ info->memory_error_func (status, addr, info);

6049

+ return -1;

6050

+ }

6051

+ *cmd_len += 2;

6052

+ return bfd_getl16 (buffer);

6053

+ }

6054

+ return 0;

6055

+}

6056

+

6057

+typedef enum

6058

+{

6059

+ OP_20BIT,

6060

+ OP_16BIT,

6061

+ OP_20BIT_HEX,

6062

+ OP_16BIT_HEX,

6063

+ OP_DECIMAL,

6064

+} operand_t;

6065

+

6066

+static void

6067

+msp430x_decode_operand(int reg, int am, int addr, int dst, operand_t size, char *op, char *comm)

6068

+{

6069

+ if (op) // if operand not hidden in emulated instruction

6070

+ switch (am)

6071

+ {

6072

+ case 0: // Rn

6073

+ if (reg == 3)

6074

+ {

6075

+ sprintf (op, "#0"); // constant #0

6076

+ sprintf (comm, "r3 As==00");

6077

+ }

6078

+ else

6079

+ {

6080

+ sprintf (op, "r%d", reg);

6081

+ }

6082

+ break;

6083

+ case 1: // x(Rn)

6084

+ if (reg == 0) // Symbolic, ADDR

6085

+ {

6086

+ if (size == OP_20BIT || size == OP_20BIT_HEX)

6087

+ sprintf (op, "0x%05x", dst & 0xfffff);

6088

+ else

6089

+ sprintf (op, "0x%04x", dst & 0xffff);

6090

+ sprintf (comm, "PC rel. 0x%05x", ((int)addr + dst) & 0xfffff);

6091

+ }

6092

+ else if (reg == 2) // Absolute, &ADDR

6093

+ {

6094

+ if (size == OP_20BIT || size == OP_20BIT_HEX)

6095

+ sprintf (op, "&0x%05x", dst & 0xfffff);

6096

+ else

6097

+ sprintf (op, "&0x%04x", dst & 0xffff);

6098

+ }

6099

+ else if (reg == 3) // constant #1

6100

+ {

6101

+ sprintf (op, "#1");

6102

+ sprintf (comm, "r3 As==01");

6103

+ }

6104

+ else // Indexed, x(Rn)

6105

+ {

6106

+ sprintf (op, "%d(r%d)", dst, reg);

6107

+ if (size == OP_20BIT || size == OP_20BIT_HEX)

6108

+ sprintf (comm, "0x%05x(r%d)", dst & 0xfffff, reg);

6109

+ else

6110

+ sprintf (comm, "0x%04x(r%d)", dst & 0xffff, reg);

6111

+ }

6112

+ break;

6113

+ case 2: // @Rn

6114

+ if (reg == 2) // constant #4

6115

+ {

6116

+ sprintf (op, "#4");

6117

+ sprintf (comm, "r2 As==10");

6118

+ }

6119

+ else if(reg == 3) // constant #2

6120

+ {

6121

+ sprintf (op, "#2");

6122

+ sprintf (comm, "r3 As==10");

6123

+ }

6124

+ else

6125

+ {

6126

+ sprintf (op, "@r%d", reg);

6127

+ }

6128

+ break;

6129

+ case 3: // @Rn+

6130

+ switch (reg)

6131

+ {

6132

+ case 0: // immediate, #N

6133

+ switch (size)

6134

+ {

6135

+ case OP_16BIT:

6136

+ sprintf (op, "#%d", dst);

6137

+ sprintf (comm, "#0x%04x", dst & 0xffff);

6138

+ break;

6139

+ case OP_16BIT_HEX:

6140

+ sprintf (op, "#0x%04x", dst & 0xffff);

6141

+ break;

6142

+ case OP_20BIT:

6143

+ sprintf (op, "#%d", dst);

6144

+ sprintf (comm, "#0x%05x", dst & 0xfffff);

6145

+ break;

6146

+ case OP_20BIT_HEX:

6147

+ sprintf (op, "#0x%05x", dst & 0xfffff);

6148

+ break;

6149

+ default: // #n in rxxm

6150

+ sprintf (op, "#%d", dst);

6151

+ break;

6152

+ }

6153

+ break;

6154

+ case 2: // constant #8

6155

+ sprintf (op, "#8");

6156

+ sprintf (comm, "r2 As==11");

6157

+ break;

6158

+ case 3: // constant #-1

6159

+ sprintf (op, "#-1");

6160

+ sprintf (comm, "r3 As==11");

6161

+ break;

6162

+ default:

6163

+ sprintf (op, "@r%d+", reg);

6164

+ break;

6165

+ }

6166

+ break;

6167

+ }

6168

+}

6169

+

6170

static int

6171

-msp430_nooperands (struct msp430_opcode_s *opcode,

6172

+msp430_nooperands (struct msp430_opcode_s const *opcode,

6173

bfd_vma addr ATTRIBUTE_UNUSED,

6174

unsigned short insn ATTRIBUTE_UNUSED,

6175

- char *comm,

6176

- int *cycles)

6177

+ char *comm)

6178

{

6179

/* Pop with constant. */

6180

if (insn == 0x43b2)

6181

@@ -65,18 +206,16 @@ msp430_nooperands (struct msp430_opcode_s *opcode,

6182

if (insn == opcode->bin_opcode)

6183

return 2;

6184

6185

- if (opcode->fmt == 0)

6186

+ if (opcode_format(opcode) == FMT_EMULATED)

6187

{

6188

if ((insn & 0x0f00) != 3 || (insn & 0x0f00) != 2)

6189

return 0;

6190

6191

strcpy (comm, "emulated...");

6192

- *cycles = 1;

6193

}

6194

else

6195

{

6196

strcpy (comm, "return from interupt");

6197

- *cycles = 5;

6198

}

6199

6200

return 2;

6201

@@ -84,16 +223,14 @@ msp430_nooperands (struct msp430_opcode_s *opcode,

6202

6203

static int

6204

msp430_singleoperand (disassemble_info *info,

6205

- struct msp430_opcode_s *opcode,

6206

+ struct msp430_opcode_s const *opcode,

6207

bfd_vma addr,

6208

unsigned short insn,

6209

char *op,

6210

- char *comm,

6211

- int *cycles)

6212

+ char *comm)

6213

{

6214

int regs = 0, regd = 0;

6215

int ad = 0, as = 0;

6216

- int where = 0;

6217

int cmd_len = 2;

6218

short dst = 0;

6219

6220

@@ -102,9 +239,9 @@ msp430_singleoperand (disassemble_info *info,

6221

as = (insn & 0x0030) >> 4;

6222

ad = (insn & 0x0080) >> 7;

6223

6224

- switch (opcode->fmt)

6225

+ switch (opcode_format(opcode))

6226

{

6227

- case 0: /* Emulated work with dst register. */

6228

+ case FMT_EMULATED: /* Emulated work with dst register. */

6229

if (regs != 2 && regs != 3 && regs != 1)

6230

return 0;

6231

6232

@@ -116,167 +253,23 @@ msp430_singleoperand (disassemble_info *info,

6233

if ((opcode->bin_opcode & 0xff00) == 0x5300 && as == 3)

6234

return 0;

6235

6236

- if (ad == 0)

6237

- {

6238

- *cycles = 1;

6239

-

6240

- /* Register. */

6241

- if (regd == 0)

6242

- {

6243

- *cycles += 1;

6244

- sprintf (op, "r0");

6245

- }

6246

- else if (regd == 1)

6247

- sprintf (op, "r1");

6248

-

6249

- else if (regd == 2)

6250

- sprintf (op, "r2");

6251

-

6252

- else

6253

- sprintf (op, "r%d", regd);

6254

- }

6255

- else /* ad == 1 msp430dis_opcode. */

6256

- {

6257

- if (regd == 0)

6258

- {

6259

- /* PC relative. */

6260

- dst = msp430dis_opcode (addr + 2, info);

6261

- cmd_len += 2;

6262

- *cycles = 4;

6263

- sprintf (op, "0x%04x", dst);

6264

- sprintf (comm, "PC rel. abs addr 0x%04x",

6265

- PS ((short) (addr + 2) + dst));

6266

- }

6267

- else if (regd == 2)

6268

- {

6269

- /* Absolute. */

6270

- dst = msp430dis_opcode (addr + 2, info);

6271

- cmd_len += 2;

6272

- *cycles = 4;

6273

- sprintf (op, "&0x%04x", PS (dst));

6274

- }

6275

- else

6276

- {

6277

- dst = msp430dis_opcode (addr + 2, info);

6278

- cmd_len += 2;

6279

- *cycles = 4;

6280

- sprintf (op, "%d(r%d)", dst, regd);

6281

- }

6282

- }

6283

+ dst = msp430dis_operand (addr + cmd_len, info, regd, ad, &cmd_len);

6284

+ msp430x_decode_operand (regd, ad, addr + cmd_len, dst, OP_16BIT, op, comm);

6285

break;

6286

6287

- case 2: /* rrc, push, call, swpb, rra, sxt, push, call, reti etc... */

6288

- if (as == 0)

6289

- {

6290

- if (regd == 3)

6291

- {

6292

- /* Constsnts. */

6293

- sprintf (op, "#0");

6294

- sprintf (comm, "r3 As==00");

6295

- }

6296

- else

6297

- {

6298

- /* Register. */

6299

- sprintf (op, "r%d", regd);

6300

- }

6301

- *cycles = 1;

6302

- }

6303

- else if (as == 2)

6304

- {

6305

- *cycles = 1;

6306

- if (regd == 2)

6307

- {

6308

- sprintf (op, "#4");

6309

- sprintf (comm, "r2 As==10");

6310

- }

6311

- else if (regd == 3)

6312

- {

6313

- sprintf (op, "#2");

6314

- sprintf (comm, "r3 As==10");

6315

- }

6316

- else

6317

- {

6318

- *cycles = 3;

6319

- /* Indexed register mode @Rn. */

6320

- sprintf (op, "@r%d", regd);

6321

- }

6322

- }

6323

- else if (as == 3)

6324

- {

6325

- *cycles = 1;

6326

- if (regd == 2)

6327

- {

6328

- sprintf (op, "#8");

6329

- sprintf (comm, "r2 As==11");

6330

- }

6331

- else if (regd == 3)

6332

- {

6333

- sprintf (op, "#-1");

6334

- sprintf (comm, "r3 As==11");

6335

- }

6336

- else if (regd == 0)

6337

- {

6338

- *cycles = 3;

6339

- /* absolute. @pc+ */

6340

- dst = msp430dis_opcode (addr + 2, info);

6341

- cmd_len += 2;

6342

- sprintf (op, "#%d", dst);

6343

- sprintf (comm, "#0x%04x", PS (dst));

6344

- }

6345

- else

6346

- {

6347

- *cycles = 3;

6348

- sprintf (op, "@r%d+", regd);

6349

- }

6350

- }

6351

- else if (as == 1)

6352

- {

6353

- *cycles = 4;

6354

- if (regd == 0)

6355

- {

6356

- /* PC relative. */

6357

- dst = msp430dis_opcode (addr + 2, info);

6358

- cmd_len += 2;

6359

- sprintf (op, "0x%04x", PS (dst));

6360

- sprintf (comm, "PC rel. 0x%04x",

6361

- PS ((short) addr + 2 + dst));

6362

- }

6363

- else if (regd == 2)

6364

- {

6365

- /* Absolute. */

6366

- dst = msp430dis_opcode (addr + 2, info);

6367

- cmd_len += 2;

6368

- sprintf (op, "&0x%04x", PS (dst));

6369

- }

6370

- else if (regd == 3)

6371

- {

6372

- *cycles = 1;

6373

- sprintf (op, "#1");

6374

- sprintf (comm, "r3 As==01");

6375

- }

6376

- else

6377

- {

6378

- /* Indexd. */

6379

- dst = msp430dis_opcode (addr + 2, info);

6380

- cmd_len += 2;

6381

- sprintf (op, "%d(r%d)", dst, regd);

6382

- }

6383

- }

6384

+ case FMT_SINGLE_OPERAND: /* rrc, push, call, swpb, rra, sxt, push, call, reti etc... */

6385

+ dst = msp430dis_operand (addr + cmd_len, info, regd, as, &cmd_len);

6386

+ if(opcode_variant(opcode) != V_CALL)

6387

+ msp430x_decode_operand (regd, as, addr + cmd_len, dst, OP_16BIT, op, comm);

6388

+ else

6389

+ msp430x_decode_operand (regd, as, addr + cmd_len, dst, OP_16BIT_HEX, op, comm);

6390

break;

6391

6392

- case 3: /* Jumps. */

6393

- where = insn & 0x03ff;

6394

- if (where & 0x200)

6395

- where |= ~0x03ff;

6396

- if (where > 512 || where < -511)

6397

- return 0;

6398

-

6399

- where *= 2;

6400

- sprintf (op, "$%+-8d", where + 2);

6401

- sprintf (comm, "abs 0x%x", PS ((short) (addr) + 2 + where));

6402

- *cycles = 2;

6403

+ case FMT_JUMP: /* Jumps. */

6404

+ dst = (short)((insn & 0x03ff) << 6) >> 5; // sign extension, word addr to byte addr conversion

6405

+ sprintf (op, "$%+-8d", dst + 2);

6406

+ sprintf (comm, "abs 0x%x", PS ((short) (addr) + 2 + dst));

6407

return 2;

6408

- break;

6409

default:

6410

cmd_len = 0;

6411

}

6412

@@ -286,26 +279,26 @@ msp430_singleoperand (disassemble_info *info,

6413

6414

static int

6415

msp430_doubleoperand (disassemble_info *info,

6416

- struct msp430_opcode_s *opcode,

6417

+ struct msp430_opcode_s const *opcode,

6418

bfd_vma addr,

6419

unsigned short insn,

6420

char *op1,

6421

char *op2,

6422

char *comm1,

6423

- char *comm2,

6424

- int *cycles)

6425

+ char *comm2)

6426

{

6427

int regs = 0, regd = 0;

6428

int ad = 0, as = 0;

6429

int cmd_len = 2;

6430

- short dst = 0;

6431

+ short ops;

6432

+ short opd;

6433

6434

regd = insn & 0x0f;

6435

regs = (insn & 0x0f00) >> 8;

6436

as = (insn & 0x0030) >> 4;

6437

ad = (insn & 0x0080) >> 7;

6438

6439

- if (opcode->fmt == 0)

6440

+ if (opcode_format(opcode) == FMT_EMULATED)

6441

{

6442

/* Special case: rla and rlc are the only 2 emulated instructions that

6443

fall into two operand instructions. */

6444

@@ -320,347 +313,354 @@ msp430_doubleoperand (disassemble_info *info,

6445

if (regd != regs || as != ad)

6446

return 0; /* May be 'data' section. */

6447

6448

- if (ad == 0)

6449

- {

6450

- /* Register mode. */

6451

- if (regd == 3)

6452

- {

6453

- strcpy (comm1, _("Illegal as emulation instr"));

6454

- return -1;

6455

- }

6456

-

6457

- sprintf (op1, "r%d", regd);

6458

- *cycles = 1;

6459

- }

6460

- else /* ad == 1 */

6461

+ if (ad == 0 && regd == 3) // #N

6462

{

6463

- if (regd == 0)

6464

- {

6465

- /* PC relative, Symbolic. */

6466

- dst = msp430dis_opcode (addr + 2, info);

6467

- cmd_len += 4;

6468

- *cycles = 6;

6469

- sprintf (op1, "0x%04x", PS (dst));

6470

- sprintf (comm1, "PC rel. 0x%04x",

6471

- PS ((short) addr + 2 + dst));

6472

-

6473

- }

6474

- else if (regd == 2)

6475

- {

6476

- /* Absolute. */

6477

- dst = msp430dis_opcode (addr + 2, info);

6478

- /* If the 'src' field is not the same as the dst

6479

- then this is not an rla instruction. */

6480

- if (dst != msp430dis_opcode (addr + 4, info))

6481

- return 0;

6482

- cmd_len += 4;

6483

- *cycles = 6;

6484

- sprintf (op1, "&0x%04x", PS (dst));

6485

- }

6486

- else

6487

- {

6488

- /* Indexed. */

6489

- dst = msp430dis_opcode (addr + 2, info);

6490

- cmd_len += 4;

6491

- *cycles = 6;

6492

- sprintf (op1, "%d(r%d)", dst, regd);

6493

- }

6494

+ strcpy (comm1, _("Illegal as emulation instr"));

6495

+ return -1;

6496

}

6497

+ ops = msp430dis_operand (addr + cmd_len, info, regs, as, &cmd_len);

6498

+ opd = msp430dis_operand (addr + cmd_len, info, regd, ad, &cmd_len);

6499

+ /* If the 'src' field is not the same as the dst

6500

+ then this is not an rla instruction. */

6501

+ if (ops != opd)

6502

+ return 0;

6503

+ msp430x_decode_operand (regs, as, addr + cmd_len, ops, OP_16BIT, op1, comm1);

6504

6505

*op2 = 0;

6506

*comm2 = 0;

6507

return cmd_len;

6508

}

6509

-

6510

/* Two operands exactly. */

6511

+

6512

if (ad == 0 && regd == 3)

6513

{

6514

/* R2/R3 are illegal as dest: may be data section. */

6515

strcpy (comm1, _("Illegal as 2-op instr"));

6516

return -1;

6517

}

6518

+ ops = msp430dis_operand (addr + cmd_len, info, regs, as, &cmd_len);

6519

+ msp430x_decode_operand (regs, as, addr + cmd_len, ops, OP_16BIT, op1, comm1);

6520

6521

- /* Source. */

6522

- if (as == 0)

6523

- {

6524

- *cycles = 1;

6525

- if (regs == 3)

6526

- {

6527

- /* Constsnts. */

6528

- sprintf (op1, "#0");

6529

- sprintf (comm1, "r3 As==00");

6530

- }

6531

- else

6532

- {

6533

- /* Register. */

6534

- sprintf (op1, "r%d", regs);

6535

- }

6536

- }

6537

- else if (as == 2)

6538

- {

6539

- *cycles = 1;

6540

+ opd = msp430dis_operand (addr + cmd_len, info, regd, ad, &cmd_len);

6541

+ msp430x_decode_operand (regd, ad, addr + cmd_len, opd, OP_16BIT, op2, comm2);

6542

+ return cmd_len;

6543

+}

6544

6545

- if (regs == 2)

6546

- {

6547

- sprintf (op1, "#4");

6548

- sprintf (comm1, "r2 As==10");

6549

- }

6550

- else if (regs == 3)

6551

- {

6552

- sprintf (op1, "#2");

6553

- sprintf (comm1, "r3 As==10");

6554

- }

6555

- else

6556

- {

6557

- *cycles = 2;

6558

+static int

6559

+msp430_branchinstr (disassemble_info *info,

6560

+ struct msp430_opcode_s const *opcode ATTRIBUTE_UNUSED,

6561

+ bfd_vma addr ATTRIBUTE_UNUSED,

6562

+ unsigned short insn,

6563

+ char *op1,

6564

+ char *comm1)

6565

+{

6566

+ int regs = (insn & 0x0f00) >> 8;

6567

+ int as = (insn & 0x0030) >> 4;

6568

+ int cmd_len = 2;

6569

+ short dst;

6570

6571

- /* Indexed register mode @Rn. */

6572

- sprintf (op1, "@r%d", regs);

6573

- }

6574

- if (!regs)

6575

- *cycles = 3;

6576

- }

6577

- else if (as == 3)

6578

+ dst = msp430dis_operand (addr + cmd_len, info, regs, as, &cmd_len);

6579

+ msp430x_decode_operand(regs, as, addr + cmd_len, dst, OP_16BIT_HEX, op1, comm1);

6580

+

6581

+ return cmd_len;

6582

+}

6583

+

6584

+static opwidth_t

6585

+msp430x_opwidth(unsigned int insn)

6586

+{

6587

+ insn &= NON_ADDR_OPERATION | BYTE_OPERATION_X;

6588

+

6589

+ if(insn == (NON_ADDR_OPERATION | BYTE_OPERATION_X))

6590

+ return BYTE_OP;

6591

+ if(insn == NON_ADDR_OPERATION)

6592

+ return WORD_OP;

6593

+ if(insn == BYTE_OPERATION_X)

6594

+ return ADDR_OP;

6595

+

6596

+ return 0; // reserved

6597

+}

6598

+

6599

+static int

6600

+msp430x_singleoperand (disassemble_info *info,

6601

+ struct msp430_opcode_s const *opcode,

6602

+ bfd_vma addr,

6603

+ unsigned int insn,

6604

+ char *op,

6605

+ char *comm,

6606

+ int *repeats)

6607

+{

6608

+ int reg = (insn >> 16) & 0xf;

6609

+ int am = (insn >> 20) & 0x3;

6610

+ int cmd_len = 4;

6611

+ int dst = 0;

6612

+

6613

+ if ( opcode_variant(opcode) < V_PUSHX )

6614

+ if ((am == 3 && reg == 0) // #N operand

6615

+ || (am == 0 && reg == 3) // R3 is illegal as dest: may be data section.

6616

+ )

6617

+ {

6618

+ strcpy (comm, _("Illegal as 1-op instr"));

6619

+ return -1;

6620

+ }

6621

+

6622

+ // extract repeat count if any

6623

+ if ( am == 0 ) // extension word for register mode

6624

{

6625

- if (regs == 2)

6626

- {

6627

- sprintf (op1, "#8");

6628

- sprintf (comm1, "r2 As==11");

6629

- *cycles = 1;

6630

- }

6631

- else if (regs == 3)

6632

- {

6633

- sprintf (op1, "#-1");

6634

- sprintf (comm1, "r3 As==11");

6635

- *cycles = 1;

6636

- }

6637

- else if (regs == 0)

6638

- {

6639

- *cycles = 3;

6640

- /* Absolute. @pc+. */

6641

- dst = msp430dis_opcode (addr + 2, info);

6642

- cmd_len += 2;

6643

- sprintf (op1, "#%d", dst);

6644

- sprintf (comm1, "#0x%04x", PS (dst));

6645

- }

6646

- else

6647

- {

6648

- *cycles = 2;

6649

- sprintf (op1, "@r%d+", regs);

6650

- }

6651

- }

6652

- else if (as == 1)

6653

- {

6654

- if (regs == 0)

6655

- {

6656

- *cycles = 4;

6657

- /* PC relative. */

6658

- dst = msp430dis_opcode (addr + 2, info);

6659

- cmd_len += 2;

6660

- sprintf (op1, "0x%04x", PS (dst));

6661

- sprintf (comm1, "PC rel. 0x%04x",

6662

- PS ((short) addr + 2 + dst));

6663

- }

6664

- else if (regs == 2)

6665

- {

6666

- *cycles = 2;

6667

- /* Absolute. */

6668

- dst = msp430dis_opcode (addr + 2, info);

6669

- cmd_len += 2;

6670

- sprintf (op1, "&0x%04x", PS (dst));

6671

- sprintf (comm1, "0x%04x", PS (dst));

6672

- }

6673

- else if (regs == 3)

6674

- {

6675

- *cycles = 1;

6676

- sprintf (op1, "#1");

6677

- sprintf (comm1, "r3 As==01");

6678

- }

6679

- else

6680

- {

6681

- *cycles = 3;

6682

- /* Indexed. */

6683

- dst = msp430dis_opcode (addr + 2, info);

6684

- cmd_len += 2;

6685

- sprintf (op1, "%d(r%d)", dst, regs);

6686

- }

6687

+ if (insn & 0x008f) // repetitions

6688

+ {

6689

+ if (insn & 0x0080)

6690

+ *repeats = insn & 0xf; // positive number is Rn

6691

+ else

6692

+ *repeats = 0 - (insn & 0xf); // negative number is #N

6693

+ }

6694

}

6695

6696

- /* Destination. Special care needed on addr + XXXX. */

6697

+ // extract operands

6698

+ dst = msp430dis_operand(addr + cmd_len, info, reg, am, &cmd_len) | ((insn & 0x0000000f) << 16);

6699

+ dst = (dst << 12) >> 12; // sign extension

6700

+ msp430x_decode_operand(reg, am, addr + cmd_len, dst, OP_20BIT, op, comm);

6701

+

6702

+ return cmd_len;

6703

+}

6704

+

6705

+static int

6706

+msp430x_exception (disassemble_info *info,

6707

+ struct msp430_opcode_s const *opcode,

6708

+ bfd_vma addr,

6709

+ unsigned int insn,

6710

+ char *op1,

6711

+ char *op2,

6712

+ char *comm1,

6713

+ char *comm2,

6714

+ opwidth_t *op_width)

6715

+{

6716

+ int reg = 0;

6717

+ int cmd_len = 2;

6718

+ int n = 0;

6719

+ int dst = 0;

6720

+

6721

+ reg = insn & 0xf;

6722

6723

- if (ad == 0)

6724

+ switch(opcode_variant(opcode))

6725

{

6726

- /* Register. */

6727

- if (regd == 0)

6728

- {

6729

- *cycles += 1;

6730

- sprintf (op2, "r0");

6731

- }

6732

- else if (regd == 1)

6733

- sprintf (op2, "r1");

6734

+ case V_CALLA:

6735

+ switch((insn >> 4) & 0xf)

6736

+ {

6737

+ case 4: // Rdst

6738

+ msp430x_decode_operand(reg, 0, 0, 0, 0, op1, comm1);

6739

+ break;

6740

+ case 5: // x(Rdst)

6741

+ dst = (short)msp430dis_operand(addr + cmd_len, info, reg, 1, &cmd_len);

6742

+ msp430x_decode_operand(reg, 1, addr + cmd_len, dst, OP_16BIT, op1, comm1);

6743

+ break;

6744

+ case 6: // @Rdst

6745

+ msp430x_decode_operand(reg, 2, 0, 0, 0, op1, comm1);

6746

+ break;

6747

+ case 7: // @Rdst+

6748

+ msp430x_decode_operand(reg, 3, 0, 0, 0, op1, comm1);

6749

+ break;

6750

+ case 8: // &abs20

6751

+ dst = msp430dis_operand(addr + cmd_len, info, 2, 1, &cmd_len) | ((insn & 0x000f) << 16);

6752

+ msp430x_decode_operand(2, 1, addr + cmd_len, dst, OP_20BIT_HEX, op1, comm1);

6753

+ break;

6754

+ case 9: // EDE

6755

+ dst = msp430dis_operand(addr + cmd_len, info, 0, 1, &cmd_len) | ((insn & 0x000f) << 16);

6756

+ msp430x_decode_operand(0, 1, addr + cmd_len, dst, OP_20BIT, op1, comm1);

6757

+ break;

6758

+ case 0xb: // #imm20

6759

+ dst = msp430dis_operand(addr + cmd_len, info, 0, 3, &cmd_len) | ((insn & 0x000f) << 16);

6760

+ msp430x_decode_operand(0, 3, addr + cmd_len, dst, OP_20BIT_HEX, op1, comm1);

6761

+ break;

6762

+ }

6763

+ break;

6764

+ case V_PUSHM:

6765

+ n = ((insn >> 4) & 0xf) + 1;

6766

+ msp430x_decode_operand(0, 3, 0, n, OP_DECIMAL, op1, comm1); // #N

6767

+ msp430x_decode_operand(reg, 0, 0, 0, 0, op2, comm2); // Rdst

6768

+ if ((insn & 0x0100) == 0)

6769

+ *op_width = ADDR_OP;

6770

+ break;

6771

+ case V_POPM:

6772

+ n = ((insn >> 4) & 0xf) + 1;

6773

+ reg = (reg + n - 1) & 0xf;

6774

+ msp430x_decode_operand(0, 3, 0, n, OP_DECIMAL, op1, comm1); // #N

6775

+ msp430x_decode_operand(reg, 0, 0, 0, 0, op2, comm2); // Rdst

6776

+ if ((insn & 0x0100) == 0)

6777

+ *op_width = ADDR_OP;

6778

+ break;

6779

+ case V_ROTM:

6780

+ n = ((insn >> 10) & 0x3) + 1;

6781

+ msp430x_decode_operand(0, 3, 0, n, OP_DECIMAL, op1, comm1); // #N

6782

+ msp430x_decode_operand(reg, 0, 0, 0, 0, op2, comm2); // Rdst

6783

+ if ((insn & 0x0010) == 0)

6784

+ *op_width = ADDR_OP;

6785

+ break;

6786

+ default:

6787

+ break;

6788

+ }

6789

+ return cmd_len;

6790

+}

6791

+

6792

+static int

6793

+msp430x_doubleoperand (disassemble_info *info,

6794

+ struct msp430_opcode_s const *opcode,

6795

+ bfd_vma addr,

6796

+ unsigned int insn,

6797

+ char *op1,

6798

+ char *op2,

6799

+ char *comm1,

6800

+ char *comm2,

6801

+ opwidth_t *op_width,

6802

+ int *repeats)

6803

+{

6804

+ int regs, regd;

6805

+ int as, ad;

6806

+ int ops, opd;

6807

+ int cmd_len = 4;

6808

6809

- else if (regd == 2)

6810

- sprintf (op2, "r2");

6811

+ regd = (insn >> 16) & 0xf;

6812

+ regs = (insn >> 24) & 0xf;

6813

+ as = (insn >> 20) & 0x3;

6814

+ ad = (insn >> 23) & 0x1;

6815

6816

- else

6817

- sprintf (op2, "r%d", regd);

6818

+ if (ad == 0 && regd == 3)

6819

+ {

6820

+ // R3 is illegal as dest: may be data section.

6821

+ if (comm1)

6822

+ strcpy (comm1, _("Illegal as 2-op instr"));

6823

+ else if (comm2)

6824

+ strcpy (comm2, _("Illegal as 2-op instr"));

6825

+ return -1;

6826

}

6827

- else /* ad == 1. */

6828

+ *op_width = msp430x_opwidth(insn);

6829

+

6830

+ // extract repeat count if any

6831

+ if ( as == 0 && ad == 0 ) // extension word for register mode

6832

{

6833

- * cycles += 3;

6834

-

6835

- if (regd == 0)

6836

- {

6837

- /* PC relative. */

6838

- *cycles += 1;

6839

- dst = msp430dis_opcode (addr + cmd_len, info);

6840

- sprintf (op2, "0x%04x", PS (dst));

6841

- sprintf (comm2, "PC rel. 0x%04x",

6842

- PS ((short) addr + cmd_len + dst));

6843

- cmd_len += 2;

6844

- }

6845

- else if (regd == 2)

6846

- {

6847

- /* Absolute. */

6848

- dst = msp430dis_opcode (addr + cmd_len, info);

6849

- cmd_len += 2;

6850

- sprintf (op2, "&0x%04x", PS (dst));

6851

- }

6852

- else

6853

- {

6854

- dst = msp430dis_opcode (addr + cmd_len, info);

6855

- cmd_len += 2;

6856

- sprintf (op2, "%d(r%d)", dst, regd);

6857

- }

6858

+ if (insn & 0x008f) // repetitions

6859

+ {

6860

+ if (insn & 0x0080)

6861

+ *repeats = insn & 0xf; // positive number is Rn

6862

+ else

6863

+ *repeats = 0 - (insn & 0xf); // negative number is #N

6864

+ }

6865

}

6866

+ // extract operands

6867

+ ops = msp430dis_operand(addr + cmd_len, info, regs, as, &cmd_len) | ((insn & 0x00000780) << 9);

6868

+ ops = (ops << 12) >> 12; // sign extension

6869

+ msp430x_decode_operand(regs, as, addr + cmd_len, ops, OP_20BIT, op1, comm1);

6870

+

6871

+ opd = msp430dis_operand(addr + cmd_len, info, regd, ad, &cmd_len) | ((insn & 0x0000000f) << 16);

6872

+ opd = (opd << 12) >> 12; // sign extension

6873

+ if (opcode_variant(opcode) == V_X_SHIFT

6874

+ && ((0 == (as | ad) && ops != opd) /* non-register extension different ops */

6875

+ || regs != regd)) /* register extension different regs */

6876

+ return 0; // different operand => not emulated shift

6877

+

6878

+ msp430x_decode_operand(regd, ad, addr + cmd_len, opd, OP_20BIT, op2, comm2);

6879

6880

return cmd_len;

6881

}

6882

6883

static int

6884

-msp430_branchinstr (disassemble_info *info,

6885

- struct msp430_opcode_s *opcode ATTRIBUTE_UNUSED,

6886

- bfd_vma addr ATTRIBUTE_UNUSED,

6887

+msp430x_address (disassemble_info *info,

6888

+ bfd_vma addr,

6889

unsigned short insn,

6890

char *op1,

6891

+ char *op2,

6892

char *comm1,

6893

- int *cycles)

6894

+ char *comm2)

6895

{

6896

- int regs = 0, regd = 0;

6897

- int as = 0;

6898

int cmd_len = 2;

6899

- short dst = 0;

6900

-

6901

- regd = insn & 0x0f;

6902

- regs = (insn & 0x0f00) >> 8;

6903

- as = (insn & 0x0030) >> 4;

6904

-

6905

- if (regd != 0) /* Destination register is not a PC. */

6906

- return 0;

6907

-

6908

- /* dst is a source register. */

6909

- if (as == 0)

6910

+ int dst = 0;

6911

+ typedef struct

6912

{

6913

- /* Constants. */

6914

- if (regs == 3)

6915

- {

6916

- *cycles = 1;

6917

- sprintf (op1, "#0");

6918

- sprintf (comm1, "r3 As==00");

6919

- }

6920

- else

6921

- {

6922

- /* Register. */

6923

- *cycles = 1;

6924

- sprintf (op1, "r%d", regs);

6925

- }

6926

+ int as, regs;

6927

+ int ad, regd;

6928

+ int length;

6929

}

6930

- else if (as == 2)

6931

+ operands_t;

6932

+

6933

+ static operands_t const operands_table[] =

6934

{

6935

- if (regs == 2)

6936

- {

6937

- *cycles = 2;

6938

- sprintf (op1, "#4");

6939

- sprintf (comm1, "r2 As==10");

6940

- }

6941

- else if (regs == 3)

6942

- {

6943

- *cycles = 1;

6944

- sprintf (op1, "#2");

6945

- sprintf (comm1, "r3 As==10");

6946

- }

6947

- else

6948

- {

6949

- /* Indexed register mode @Rn. */

6950

- *cycles = 2;

6951

- sprintf (op1, "@r%d", regs);

6952

- }

6953

- }

6954

- else if (as == 3)

6955

+ { 2, -1, 0, -1, 0 }, // 0 @Rsrc, Rdst

6956

+ { 3, -1, 0, -1, 0 }, // 1 @Rsrc+, Rdst

6957

+ { 1, 2, 0, -1, 2 }, // 2 &abs20, Rdst

6958

+ { 1, -1, 0, -1, 2 }, // 3 x(Rsrc), Rdst

6959

+ { 0, 0, 0, 0, 0 }, // 4

6960

+ { 0, 0, 0, 0, 0 }, // 5

6961

+ { 0, -1, 1, 2, 2 }, // 6 Rsrc, &abs20

6962

+ { 0, -1, 1, -1, 2 }, // 7 Rsrc, x(Rdst)

6963

+ { 3, 0, 0, -1, 2 }, // 8 #imm20, Rdst

6964

+ { 3, 0, 0, -1, 2 }, // 9 #imm20, Rdst

6965

+ { 3, 0, 0, -1, 2 }, // a #imm20, Rdst

6966

+ { 3, 0, 0, -1, 2 }, // b #imm20, Rdst

6967

+ { 0, -1, 0, -1, 0 }, // c Rsrc, Rdst

6968

+ { 0, -1, 0, -1, 0 }, // d Rsrc, Rdst

6969

+ { 0, -1, 0, -1, 0 }, // e Rsrc, Rdst

6970

+ { 0, -1, 0, -1, 0 }, // f Rsrc, Rdst

6971

+ };

6972

+

6973

+ operands_t operands = operands_table[(insn >> 4) & 0xf];

6974

+ if(((insn >> 4) & 0xf) == 6)

6975

+ dst = msp430dis_opcode (addr + cmd_len, info) | ((insn & 0x000f) << 16);

6976

+ else if(((insn >> 4) & 0xb) == 3)

6977

+ dst = (short)msp430dis_opcode (addr + cmd_len, info);

6978

+ else if(operands.length != 0)

6979

+ dst = msp430dis_opcode(addr + cmd_len, info) | ((insn & 0x0f00) << 8);

6980

+

6981

+ if(operands.regs == -1)

6982

+ operands.regs = (insn >> 8 ) & 0x000f;

6983

+ if(operands.regd == -1)

6984

+ operands.regd = (insn >> 0 ) & 0x000f;

6985

+

6986

+ if (operands.regd == 3)

6987

{

6988

- if (regs == 2)

6989

- {

6990

- *cycles = 1;

6991

- sprintf (op1, "#8");

6992

- sprintf (comm1, "r2 As==11");

6993

- }

6994

- else if (regs == 3)

6995

- {

6996

- *cycles = 1;

6997

- sprintf (op1, "#-1");

6998

- sprintf (comm1, "r3 As==11");

6999

- }

7000

- else if (regs == 0)

7001

- {

7002

- /* Absolute. @pc+ */

7003

- *cycles = 3;

7004

- dst = msp430dis_opcode (addr + 2, info);

7005

- cmd_len += 2;

7006

- sprintf (op1, "#0x%04x", PS (dst));

7007

- }

7008

- else

7009

- {

7010

- *cycles = 2;

7011

- sprintf (op1, "@r%d+", regs);

7012

- }

7013

+ // R3 is illegal as dest: may be data section.

7014

+ if (comm1)

7015

+ strcpy (comm1, _("Illegal as address instr"));

7016

+ else if (comm2)

7017

+ strcpy (comm2, _("Illegal as address instr"));

7018

+ return -1;

7019

}

7020

- else if (as == 1)

7021

- {

7022

- * cycles = 3;

7023

+ // extract operands

7024

+ msp430x_decode_operand(operands.regs, operands.as, addr + cmd_len, dst,

7025

+ ((insn >> 4) & 0xf) == 3 ? OP_16BIT_HEX : OP_20BIT_HEX, op1, comm1);

7026

+ msp430x_decode_operand(operands.regd, operands.ad, addr + cmd_len, dst,

7027

+ ((insn >> 4) & 0xf) == 7 ? OP_16BIT_HEX : OP_20BIT_HEX, op2, comm2);

7028

+ return cmd_len + operands.length;

7029

+}

7030

7031

- if (regs == 0)

7032

- {

7033

- /* PC relative. */

7034

- dst = msp430dis_opcode (addr + 2, info);

7035

- cmd_len += 2;

7036

- (*cycles)++;

7037

- sprintf (op1, "0x%04x", PS (dst));

7038

- sprintf (comm1, "PC rel. 0x%04x",

7039

- PS ((short) addr + 2 + dst));

7040

- }

7041

- else if (regs == 2)

7042

- {

7043

- /* Absolute. */

7044

- dst = msp430dis_opcode (addr + 2, info);

7045

- cmd_len += 2;

7046

- sprintf (op1, "&0x%04x", PS (dst));

7047

- }

7048

- else if (regs == 3)

7049

- {

7050

- (*cycles)--;

7051

- sprintf (op1, "#1");

7052

- sprintf (comm1, "r3 As==01");

7053

- }

7054

- else

7055

- {

7056

- /* Indexd. */

7057

- dst = msp430dis_opcode (addr + 2, info);

7058

- cmd_len += 2;

7059

- sprintf (op1, "%d(r%d)", dst, regs);

7060

- }

7061

- }

7062

+static int

7063

+msp430x_emulated (disassemble_info *info,

7064

+ struct msp430_opcode_s const *opcode,

7065

+ bfd_vma addr,

7066

+ unsigned int insn,

7067

+ char *op1,

7068

+ char *comm1,

7069

+ opwidth_t *op_width,

7070

+ int *repeats)

7071

+{

7072

7073

- return cmd_len;

7074

+ switch(opcode_variant(opcode))

7075

+ {

7076

+ case V_NONE:

7077

+ case V_X_SHIFT:

7078

+ // emulated by double operand instruction

7079

+ return msp430x_doubleoperand(info, opcode, addr, insn, (char *)0, op1,

7080

+ (char *)0, comm1, op_width, repeats);

7081

+ case V_RETA: // reta, substituted by mova

7082

+ return 2;

7083

+ case V_EMU_ADDR: // substituted by other address instruction

7084

+ return msp430x_address(info, addr, insn, (char *)0, op1,

7085

+ (char *)0, comm1);

7086

+ case V_BRA: // bra, substituted by mova

7087

+ return msp430x_address(info, addr, insn, op1, (char *)0,

7088

+ comm1, (char *)0);

7089

+ default:

7090

+ break;

7091

+ }

7092

+ return 0;

7093

}

7094

7095

int

7096

@@ -668,22 +668,32 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)

7097

{

7098

void *stream = info->stream;

7099

fprintf_ftype prin = info->fprintf_func;

7100

- struct msp430_opcode_s *opcode;

7101

+ struct msp430_opcode_s const *opcode;

7102

char op1[32], op2[32], comm1[64], comm2[64];

7103

int cmd_len = 0;

7104

- unsigned short insn;

7105

- int cycles = 0;

7106

- char *bc = "";

7107

- char dinfo[32]; /* Debug purposes. */

7108

-

7109

+ unsigned int insn;

7110

+ int repeats = 0;

7111

+ int cpu = (bfd_mach_msp430x == info->mach) ? MSP430_CPU_MSP430X : MSP430_CPU_MSP430;

7112

+

7113

+ opwidth_t op_width = DEFAULT_OP; // word instruction by default

7114

+ static char const *width_modifier[] =

7115

+ {"", "", ".b", ".a" };

7116

+

7117

insn = msp430dis_opcode (addr, info);

7118

- sprintf (dinfo, "0x%04x", insn);

7119

7120

- if (((int) addr & 0xffff) > 0xffdf)

7121

+#if 0

7122

+ if ( (core == CORE_430 && ((int) addr & 0xffff) >= 0xffe0)

7123

+ || ( core == CORE_430X && (((int) addr & 0xfffff) >= 0xffc0) && ((int) addr & 0xfffff) < 0x10000)

7124

+ || ( core == CORE_430X2 && (((int) addr & 0xfffff) >= 0xff80) && ((int) addr & 0xfffff) < 0x10000)

7125

+ )

7126

{

7127

(*prin) (stream, "interrupt service routine at 0x%04x", 0xffff & insn);

7128

return 2;

7129

}

7130

+#endif

7131

+

7132

+ if (cpu >= MSP430_CPU_MSP430X && ((insn & 0xf800) == 0x1800)) // Extended instruction

7133

+ insn |= msp430dis_opcode(addr + 2, info) << 16;

7134

7135

*comm1 = 0;

7136

*comm2 = 0;

7137

@@ -691,62 +701,107 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)

7138

for (opcode = msp430_opcodes; opcode->name; opcode++)

7139

{

7140

if ((insn & opcode->bin_mask) == opcode->bin_opcode

7141

- && opcode->bin_opcode != 0x9300)

7142

+// && opcode->bin_opcode != 0x9300 // was disasm tst instruction as cmp #0, dst?

7143

+ )

7144

{

7145

*op1 = 0;

7146

*op2 = 0;

7147

*comm1 = 0;

7148

*comm2 = 0;

7149

7150

- /* r0 as destination. Ad should be zero. */

7151

- if (opcode->insn_opnumb == 3 && (insn & 0x000f) == 0

7152

- && (0x0080 & insn) == 0)

7153

+ /* unsupported instruction */

7154

+ if(opcode_format(opcode) >= FMT_X && cpu < MSP430_CPU_MSP430X)

7155

+ break;

7156

+

7157

+ /* r0 as destination. Ad should be zero. Rdst=0 and Ad=0 are encoded in opcode & opcode_mask */

7158

+ if (opcode_format(opcode) == FMT_EMULATED && opcode_variant(opcode) == V_BR)

7159

{

7160

cmd_len =

7161

- msp430_branchinstr (info, opcode, addr, insn, op1, comm1,

7162

- &cycles);

7163

+ msp430_branchinstr (info, opcode, addr, insn, op1, comm1);

7164

if (cmd_len)

7165

break;

7166

}

7167

-

7168

- switch (opcode->insn_opnumb)

7169

- {

7170

- case 0:

7171

- cmd_len = msp430_nooperands (opcode, addr, insn, comm1, &cycles);

7172

- break;

7173

- case 2:

7174

- cmd_len =

7175

- msp430_doubleoperand (info, opcode, addr, insn, op1, op2,

7176

- comm1, comm2, &cycles);

7177

- if (insn & BYTE_OPERATION)

7178

- bc = ".b";

7179

- break;

7180

- case 1:

7181

- cmd_len =

7182

- msp430_singleoperand (info, opcode, addr, insn, op1, comm1,

7183

- &cycles);

7184

- if (insn & BYTE_OPERATION && opcode->fmt != 3)

7185

- bc = ".b";

7186

- break;

7187

- default:

7188

- break;

7189

- }

7190

+ if(opcode_format(opcode) < FMT_X)

7191

+ switch (opcode->insn_opnumb)

7192

+ {

7193

+ case 0:

7194

+ cmd_len = msp430_nooperands (opcode, addr, insn, comm1);

7195

+ break;

7196

+ case 2:

7197

+ cmd_len =

7198

+ msp430_doubleoperand (info, opcode, addr, insn, op1, op2,

7199

+ comm1, comm2);

7200

+ if (insn & BYTE_OPERATION)

7201

+ op_width = BYTE_OP;

7202

+ break;

7203

+ case 1:

7204

+ cmd_len =

7205

+ msp430_singleoperand (info, opcode, addr, insn, op1, comm1);

7206

+ if (insn & BYTE_OPERATION && opcode_format(opcode) != FMT_JUMP)

7207

+ op_width = BYTE_OP;

7208

+ break;

7209

+ default:

7210

+ break;

7211

+ }

7212

+ else // 430x instruction

7213

+ switch(opcode_format(opcode))

7214

+ {

7215

+ case FMT_X_SINGLE_OPERAND:

7216

+ if( opcode_variant(opcode) == V_SWPSXT // swpbx, sxtx

7217

+ && (insn & (NON_ADDR_OPERATION | BYTE_OPERATION_X)) == 0) // .a, special case

7218

+ insn ^= BYTE_OPERATION_X; // make A/L, B/W as ordinary

7219

+

7220

+ op_width = msp430x_opwidth(insn);

7221

+

7222

+ if( opcode_variant(opcode) == V_SWPSXT && op_width == BYTE_OP) // swpbx, sxtx

7223

+ strcpy (comm1, _("Illegal A/L, B/W bits setting"));

7224

+

7225

+ cmd_len = msp430x_singleoperand (info, opcode, addr, insn, op1, comm1,

7226

+ &repeats);

7227

+ break;

7228

+ case FMT_X_EXCEPTION:

7229

+ cmd_len = msp430x_exception (info, opcode, addr, insn, op1, op2,

7230

+ comm1, comm2, &op_width);

7231

+ break;

7232

+ case FMT_X_DOUBLE_OPERAND:

7233

+ cmd_len = msp430x_doubleoperand (info, opcode, addr, insn, op1, op2,

7234

+ comm1, comm2, &op_width, &repeats);

7235

+ break;

7236

+ case FMT_X_EMULATED:

7237

+ cmd_len = msp430x_emulated (info, opcode, addr, insn, op1,

7238

+ comm1, &op_width, &repeats);

7239

+ break;

7240

+

7241

+ case FMT_X_ADDRESS:

7242

+ cmd_len = msp430x_address (info, addr, insn, op1, op2,

7243

+ comm1, comm2);

7244

+ break;

7245

+ default:

7246

+ break;

7247

+ }

7248

}

7249

7250

if (cmd_len)

7251

break;

7252

}

7253

7254

- dinfo[5] = 0;

7255

-

7256

if (cmd_len < 1)

7257

{

7258

/* Unknown opcode, or invalid combination of operands. */

7259

- (*prin) (stream, ".word 0x%04x; ????", PS (insn));

7260

+ (*prin) (stream, ".word 0x%04x; ????\t%s%s", PS (insn), comm1, comm2);

7261

return 2;

7262

}

7263

7264

- (*prin) (stream, "%s%s", opcode->name, bc);

7265

+

7266

+ if (repeats)

7267

+ {

7268

+ if (repeats < 0)

7269

+ (*prin) (stream, ".rpt\t#%d\n\t\t\t\t", 0 - repeats);

7270

+ else

7271

+ (*prin) (stream, ".rpt\tr%d\n\t\t\t\t", repeats);

7272

+ }

7273

+

7274

+ (*prin) (stream, "%s%s", opcode->name, width_modifier[op_width]);

7275

7276

if (*op1)

7277

(*prin) (stream, "\t%s", op1);

7278

@@ -765,23 +820,11 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)

7279

7280

if (*comm1 || *comm2)

7281

(*prin) (stream, ";");

7282

- else if (cycles)

7283

- {

7284

- if (*op2)

7285

- (*prin) (stream, ";");

7286

- else

7287

- {

7288

- if (strlen (op1) < 7)

7289

- (*prin) (stream, ";");

7290

- else

7291

- (*prin) (stream, "\t;");

7292

- }

7293

- }

7294

if (*comm1)

7295

(*prin) (stream, "%s", comm1);

7296

if (*comm1 && *comm2)

7297

- (*prin) (stream, ",");

7298

+ (*prin) (stream, ", ");

7299

if (*comm2)

7300

- (*prin) (stream, " %s", comm2);

7301

+ (*prin) (stream, "%s", comm2);

7302

return cmd_len;

7303

}