160
164
// Generally used methodology in verilog code is
161
165
// one module per file, so folding at module definition is useless.
162
166
// fold_at_brace/parenthese -
163
// Folding of long port lists can be convenient.
167
// Folding of long port lists can be convenient.
164
168
bool foldAtModule = styler.GetPropertyInt("fold.verilog.flags", 0) != 0;
165
169
bool foldAtBrace = 1;
166
170
bool foldAtParenthese = 1;
168
172
unsigned int endPos = startPos + length;
169
173
int visibleChars = 0;
170
174
int lineCurrent = styler.GetLine(startPos);
235
239
if (style == SCE_V_WORD && stylePrev != SCE_V_WORD) {
236
240
unsigned int j = i;
237
if (styler.Match(j, "case") ||
238
styler.Match(j, "casex") ||
239
styler.Match(j, "casez") ||
240
styler.Match(j, "function") ||
241
styler.Match(j, "fork") ||
242
styler.Match(j, "table") ||
243
styler.Match(j, "task") ||
244
styler.Match(j, "specify") ||
245
styler.Match(j, "primitive") ||
246
styler.Match(j, "module") && foldAtModule ||
241
if (styler.Match(j, "case") ||
242
styler.Match(j, "casex") ||
243
styler.Match(j, "casez") ||
244
styler.Match(j, "function") ||
245
styler.Match(j, "fork") ||
246
styler.Match(j, "table") ||
247
styler.Match(j, "task") ||
248
styler.Match(j, "generate") ||
249
styler.Match(j, "specify") ||
250
styler.Match(j, "primitive") ||
251
(styler.Match(j, "module") && foldAtModule) ||
247
252
styler.Match(j, "begin")) {
249
} else if (styler.Match(j, "endcase") ||
254
} else if (styler.Match(j, "endcase") ||
250
255
styler.Match(j, "endfunction") ||
251
256
styler.Match(j, "join") ||
252
257
styler.Match(j, "endtask") ||
258
styler.Match(j, "endgenerate") ||
253
259
styler.Match(j, "endtable") ||
254
260
styler.Match(j, "endspecify") ||
255
261
styler.Match(j, "endprimitive") ||
256
styler.Match(j, "endmodule") && foldAtModule ||
257
styler.Match(j, "end") && !IsAWordChar(styler.SafeGetCharAt(j+3))) {
262
(styler.Match(j, "endmodule") && foldAtModule) ||
263
(styler.Match(j, "end") && !IsAWordChar(styler.SafeGetCharAt(j+3)))) {