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Viewing changes to oprofile/org.eclipse.linuxtools.oprofile.core.tests/resources/test_info.xml

  • Committer: Package Import Robot
  • Author(s): Jakub Adam
  • Date: 2012-06-29 12:07:30 UTC
  • Revision ID: package-import@ubuntu.com-20120629120730-bfri1xys1i71dpn6
Tags: upstream-1.0.0
Import upstream version 1.0.0

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oprofile/org.eclipse.linuxtools.oprofile.core.tests/resources/test_info.xml
 
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<?xml version="1.0" encoding="UTF-8"?>
 
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<info>
 
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        <num-counters>2</num-counters>
 
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        <cpu-frequency>800</cpu-frequency>
 
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        <defaults>
 
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                <sample-dir>/var/lib/oprofile/samples/</sample-dir>
 
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                <lock-file>/var/lib/oprofile/lock</lock-file>
 
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                <log-file>/var/lib/oprofile/samples/oprofiled.log</log-file>
 
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                <dump-status>/var/lib/oprofile/complete_dump</dump-status>
 
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        </defaults>
 
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        <timer-mode>true</timer-mode>
 
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        <event-list counter="0">
 
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                <event>
 
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                        <name>CPU_CLK_UNHALTED</name>
 
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                        <description>Clock cycles when not halted</description>
 
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                        <value>60</value>
 
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                        <minimum>6000</minimum>
 
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                        <unit-mask>
 
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                                <type>exclusive</type>
 
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                                <default>0</default>
 
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                                <mask>
 
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                                        <value>0</value>
 
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                                        <description>Unhalted core cycles</description>
 
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                                </mask>
 
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                                <mask>
 
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                                        <value>1</value>
 
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                                        <description>Unhalted bus cycles</description>
 
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                                </mask>
 
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                                <mask>
 
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                                        <value>2</value>
 
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                                        <description>Unhalted bus cycles of this core while the other core is halted</description>
 
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                                </mask>
 
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                        </unit-mask>
 
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                </event>
 
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                <event>
 
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                        <name>INST_RETIRED_ANY_P</name>
 
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                        <description>number of instructions retired</description>
 
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                        <value>192</value>
 
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                        <minimum>6000</minimum>
 
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                        <unit-mask>
 
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                                <type>mandatory</type>
 
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                                <default>0</default>
 
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                                <mask>
 
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                                        <value>0</value>
 
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                                        <description>No unit mask</description>
 
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                                </mask>
 
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                        </unit-mask>
 
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                </event>
 
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                <event>
 
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                        <name>DTLB_MISSES</name>
 
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                        <description>DTLB miss events</description>
 
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                        <value>8</value>
 
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                        <minimum>500</minimum>
 
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                        <unit-mask>
 
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                                <type>bitmask</type>
 
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                                <default>15</default>
 
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                                <mask>
 
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                                        <value>1</value>
 
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                                        <description>ANY        Memory accesses that missed the DTLB.</description>
 
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                                </mask>
 
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                                <mask>
 
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                                        <value>2</value>
 
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                                        <description>MISS_LD    DTLB misses due to load operations.</description>
 
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                                </mask>
 
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                                <mask>
 
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                                        <value>4</value>
 
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                                        <description>L0_MISS_LD L0 DTLB misses due to load operations.</description>
 
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                                </mask>
 
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                                <mask>
 
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                                        <value>8</value>
 
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                                        <description>MISS_ST    TLB misses due to store operations.</description>
 
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                                </mask>
 
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                        </unit-mask>
 
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                </event>
 
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        </event-list>
 
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        <event-list counter="1">
 
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                <event>
 
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                        <name>L2_M_LINES_IN</name>
 
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                        <description>number of modified lines allocated in L2</description>
 
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                        <value>37</value>
 
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                        <minimum>500</minimum>
 
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                        <unit-mask>
 
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                                <type>exclusive</type>
 
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                                <default>64</default>
 
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                                <mask>
 
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                                        <value>192</value>
 
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                                        <description>All cores</description>
 
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                                </mask>
 
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                                <mask>
 
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                                        <value>64</value>
 
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                                        <description>This core</description>
 
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                                </mask>
 
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                        </unit-mask>
 
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                </event>
 
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                <event>
 
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                        <name>L2_LINES_OUT</name>
 
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                        <description>number of recovered lines from L2</description>
 
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                        <value>38</value>
 
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                        <minimum>500</minimum>
 
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                        <unit-mask>
 
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                                <type>bitmask</type>
 
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                                <default>112</default>
 
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                                <mask>
 
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                                        <value>192</value>
 
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                                        <description>core: all cores</description>
 
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                                </mask>
 
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                                <mask>
 
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                                        <value>64</value>
 
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                                        <description>core: this core</description>
 
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                                </mask>
 
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                                <mask>
 
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                                        <value>48</value>
 
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                                        <description>prefetch: all inclusive</description>
 
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                                </mask>
 
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                                <mask>
 
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                                        <value>16</value>
 
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                                        <description>prefetch: Hardware prefetch only</description>
 
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                                </mask>
 
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                                <mask>
 
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                                        <value>0</value>
 
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                                        <description>prefetch: exclude hardware prefetch</description>
 
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                                </mask>
 
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                        </unit-mask>
 
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                </event>
 
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                <event>
 
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                        <name>EIST_TRANS_ALL</name>
 
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                        <description>Intel(tm) Enhanced SpeedStep(r) Technology transitions</description>
 
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                        <value>58</value>
 
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                        <minimum>500</minimum>
 
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                        <unit-mask>
 
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                                <type>notavalidtype</type>
 
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                                <default>1</default>
 
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                                <mask>
 
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                                        <value>1</value>
 
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                                        <description>No unit mask</description>
 
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                                </mask>
 
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                        </unit-mask>
 
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                </event>
 
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        </event-list>
 
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</info>
 
 
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