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- Committer: Package Import Robot
- Author(s): Matthias Klose
- Date: 2014-02-24 11:40:55 UTC
- Revision ID: package-import@ubuntu.com-20140224114055-dwt8qdeb2j8qtlf8
Tags: 4.8.2-16ubuntu3
* Update the ibm branch to SVN 20140224 (r208054).
* Re-add gcc-4.8 dependency on libgcc-4.8-dev. LP: #1283850.
* Re-add gcc-4.8 dependency on libgcc-4.8-dev. LP: #1283850.
added
removed
debian/patches/gcc-ppc64el.diff
1
# DP: Changes from the ibm/gcc-4_8-branch (20140221)
1
# DP: Changes from the ibm/gcc-4_8-branch (20140223)
2
2
3
3
LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@206665 \
4
svn://gcc.gnu.org/svn/gcc/branches/ibm/gcc-4_8-branch@207920 \
4
svn://gcc.gnu.org/svn/gcc/branches/ibm/gcc-4_8-branch@208054 \
5
5
| filterdiff --remove-timestamps --addoldprefix=a/src/ --addnewprefix=b/src/
6
6
7
7
--- a/src/libitm/configure
5917
5917
+#include "bool2.h"
5918
5918
--- a/src/gcc/testsuite/ChangeLog.ibm
5919
5919
+++ b/src/gcc/testsuite/ChangeLog.ibm
5920
@@ -0,0 +1,522 @@
5920
@@ -0,0 +1,562 @@
5921
+2014-02-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
5922
+
5923
+ Backport from mainline 208049
5924
+ 2014-02-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
5925
+
5926
+ * gcc.dg/vmx/lde.c: New test.
5927
+ * gcc.dg/vmx/lde-be-order.c: New test.
5928
+ * gcc.dg/vmx/ste.c: New test.
5929
+ * gcc.dg/vmx/ste-be-order.c: New test.
5930
+
5931
+2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
5932
+
5933
+ Backport from mainline 208021
5934
+ 2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
5935
+
5936
+ * gcc.dg/vmx/vsums.c: Check entire result vector.
5937
+ * gcc.dg/vmx/vsums-be-order.c: Likewise.
5938
+
5939
+2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
5940
+
5941
+ Backport from mainline 208019
5942
+ 2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
5943
+
5944
+ * gcc.dg/vmx/ld.c: New test.
5945
+ * gcc.dg/vmx/ld-be-order.c: New test.
5946
+ * gcc.dg/vmx/ld-vsx.c: New test.
5947
+ * gcc.dg/vmx/ld-vsx-be-order.c: New test.
5948
+ * gcc.dg/vmx/ldl.c: New test.
5949
+ * gcc.dg/vmx/ldl-be-order.c: New test.
5950
+ * gcc.dg/vmx/ldl-vsx.c: New test.
5951
+ * gcc.dg/vmx/ldl-vsx-be-order.c: New test.
5952
+ * gcc.dg/vmx/st.c: New test.
5953
+ * gcc.dg/vmx/st-be-order.c: New test.
5954
+ * gcc.dg/vmx/st-vsx.c: New test.
5955
+ * gcc.dg/vmx/st-vsx-be-order.c: New test.
5956
+ * gcc.dg/vmx/stl.c: New test.
5957
+ * gcc.dg/vmx/stl-be-order.c: New test.
5958
+ * gcc.dg/vmx/stl-vsx.c: New test.
5959
+ * gcc.dg/vmx/stl-vsx-be-order.c: New test.
5960
+
5921
5961
+2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com>
5922
5962
+
5923
5963
+ Backport from mainline r207808.
6597
6637
! PR47293 NAN not correctly read
6598
6638
character(len=200) :: str
6599
6639
real(16) :: r
6640
--- a/src/gcc/testsuite/gcc.dg/vmx/stl-be-order.c
6641
+++ b/src/gcc/testsuite/gcc.dg/vmx/stl-be-order.c
6642
@@ -0,0 +1,83 @@
6643
+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
6644
+
6645
+#include "harness.h"
6646
+
6647
+static unsigned char svuc[16] __attribute__ ((aligned (16)));
6648
+static signed char svsc[16] __attribute__ ((aligned (16)));
6649
+static unsigned char svbc[16] __attribute__ ((aligned (16)));
6650
+static unsigned short svus[8] __attribute__ ((aligned (16)));
6651
+static signed short svss[8] __attribute__ ((aligned (16)));
6652
+static unsigned short svbs[8] __attribute__ ((aligned (16)));
6653
+static unsigned short svp[8] __attribute__ ((aligned (16)));
6654
+static unsigned int svui[4] __attribute__ ((aligned (16)));
6655
+static signed int svsi[4] __attribute__ ((aligned (16)));
6656
+static unsigned int svbi[4] __attribute__ ((aligned (16)));
6657
+static float svf[4] __attribute__ ((aligned (16)));
6658
+
6659
+static void check_arrays ()
6660
+{
6661
+ unsigned int i;
6662
+ for (i = 0; i < 16; ++i)
6663
+ {
6664
+ check (svuc[i] == i, "svuc");
6665
+ check (svsc[i] == i - 8, "svsc");
6666
+ check (svbc[i] == ((i % 2) ? 0xff : 0), "svbc");
6667
+ }
6668
+ for (i = 0; i < 8; ++i)
6669
+ {
6670
+ check (svus[i] == i, "svus");
6671
+ check (svss[i] == i - 4, "svss");
6672
+ check (svbs[i] == ((i % 2) ? 0xffff : 0), "svbs");
6673
+ check (svp[i] == i, "svp");
6674
+ }
6675
+ for (i = 0; i < 4; ++i)
6676
+ {
6677
+ check (svui[i] == i, "svui");
6678
+ check (svsi[i] == i - 2, "svsi");
6679
+ check (svbi[i] == ((i % 2) ? 0xffffffff : 0), "svbi");
6680
+ check (svf[i] == i * 1.0f, "svf");
6681
+ }
6682
+}
6683
+
6684
+static void test ()
6685
+{
6686
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
6687
+ vector unsigned char vuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
6688
+ vector signed char vsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};
6689
+ vector bool char vbc = {255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0};
6690
+ vector unsigned short vus = {7,6,5,4,3,2,1,0};
6691
+ vector signed short vss = {3,2,1,0,-1,-2,-3,-4};
6692
+ vector bool short vbs = {65535,0,65535,0,65535,0,65535,0};
6693
+ vector pixel vp = {7,6,5,4,3,2,1,0};
6694
+ vector unsigned int vui = {3,2,1,0};
6695
+ vector signed int vsi = {1,0,-1,-2};
6696
+ vector bool int vbi = {0xffffffff,0,0xffffffff,0};
6697
+ vector float vf = {3.0,2.0,1.0,0.0};
6698
+#else
6699
+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
6700
+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
6701
+ vector bool char vbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};
6702
+ vector unsigned short vus = {0,1,2,3,4,5,6,7};
6703
+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
6704
+ vector bool short vbs = {0,65535,0,65535,0,65535,0,65535};
6705
+ vector pixel vp = {0,1,2,3,4,5,6,7};
6706
+ vector unsigned int vui = {0,1,2,3};
6707
+ vector signed int vsi = {-2,-1,0,1};
6708
+ vector bool int vbi = {0,0xffffffff,0,0xffffffff};
6709
+ vector float vf = {0.0,1.0,2.0,3.0};
6710
+#endif
6711
+
6712
+ vec_stl (vuc, 0, (vector unsigned char *)svuc);
6713
+ vec_stl (vsc, 0, (vector signed char *)svsc);
6714
+ vec_stl (vbc, 0, (vector bool char *)svbc);
6715
+ vec_stl (vus, 0, (vector unsigned short *)svus);
6716
+ vec_stl (vss, 0, (vector signed short *)svss);
6717
+ vec_stl (vbs, 0, (vector bool short *)svbs);
6718
+ vec_stl (vp, 0, (vector pixel *)svp);
6719
+ vec_stl (vui, 0, (vector unsigned int *)svui);
6720
+ vec_stl (vsi, 0, (vector signed int *)svsi);
6721
+ vec_stl (vbi, 0, (vector bool int *)svbi);
6722
+ vec_stl (vf, 0, (vector float *)svf);
6723
+
6724
+ check_arrays ();
6725
+}
6600
6726
--- a/src/gcc/testsuite/gcc.dg/vmx/perm-be-order.c
6601
6727
+++ b/src/gcc/testsuite/gcc.dg/vmx/perm-be-order.c
6602
6728
@@ -0,0 +1,74 @@
6742
6868
+#endif
6743
6869
+}
6744
6870
+
6871
--- a/src/gcc/testsuite/gcc.dg/vmx/ldl.c
6872
+++ b/src/gcc/testsuite/gcc.dg/vmx/ldl.c
6873
@@ -0,0 +1,91 @@
6874
+#include "harness.h"
6875
+
6876
+static unsigned char svuc[16] __attribute__ ((aligned (16)));
6877
+static signed char svsc[16] __attribute__ ((aligned (16)));
6878
+static unsigned char svbc[16] __attribute__ ((aligned (16)));
6879
+static unsigned short svus[8] __attribute__ ((aligned (16)));
6880
+static signed short svss[8] __attribute__ ((aligned (16)));
6881
+static unsigned short svbs[8] __attribute__ ((aligned (16)));
6882
+static unsigned short svp[8] __attribute__ ((aligned (16)));
6883
+static unsigned int svui[4] __attribute__ ((aligned (16)));
6884
+static signed int svsi[4] __attribute__ ((aligned (16)));
6885
+static unsigned int svbi[4] __attribute__ ((aligned (16)));
6886
+static float svf[4] __attribute__ ((aligned (16)));
6887
+
6888
+static void init ()
6889
+{
6890
+ unsigned int i;
6891
+ for (i = 0; i < 16; ++i)
6892
+ {
6893
+ svuc[i] = i;
6894
+ svsc[i] = i - 8;
6895
+ svbc[i] = (i % 2) ? 0xff : 0;
6896
+ }
6897
+ for (i = 0; i < 8; ++i)
6898
+ {
6899
+ svus[i] = i;
6900
+ svss[i] = i - 4;
6901
+ svbs[i] = (i % 2) ? 0xffff : 0;
6902
+ svp[i] = i;
6903
+ }
6904
+ for (i = 0; i < 4; ++i)
6905
+ {
6906
+ svui[i] = i;
6907
+ svsi[i] = i - 2;
6908
+ svbi[i] = (i % 2) ? 0xffffffff : 0;
6909
+ svf[i] = i * 1.0f;
6910
+ }
6911
+}
6912
+
6913
+static void test ()
6914
+{
6915
+ vector unsigned char evuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
6916
+ vector signed char evsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
6917
+ vector bool char evbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};
6918
+ vector unsigned short evus = {0,1,2,3,4,5,6,7};
6919
+ vector signed short evss = {-4,-3,-2,-1,0,1,2,3};
6920
+ vector bool short evbs = {0,65535,0,65535,0,65535,0,65535};
6921
+ vector pixel evp = {0,1,2,3,4,5,6,7};
6922
+ vector unsigned int evui = {0,1,2,3};
6923
+ vector signed int evsi = {-2,-1,0,1};
6924
+ vector bool int evbi = {0,0xffffffff,0,0xffffffff};
6925
+ vector float evf = {0.0,1.0,2.0,3.0};
6926
+
6927
+ vector unsigned char vuc;
6928
+ vector signed char vsc;
6929
+ vector bool char vbc;
6930
+ vector unsigned short vus;
6931
+ vector signed short vss;
6932
+ vector bool short vbs;
6933
+ vector pixel vp;
6934
+ vector unsigned int vui;
6935
+ vector signed int vsi;
6936
+ vector bool int vbi;
6937
+ vector float vf;
6938
+
6939
+ init ();
6940
+
6941
+ vuc = vec_ldl (0, (vector unsigned char *)svuc);
6942
+ vsc = vec_ldl (0, (vector signed char *)svsc);
6943
+ vbc = vec_ldl (0, (vector bool char *)svbc);
6944
+ vus = vec_ldl (0, (vector unsigned short *)svus);
6945
+ vss = vec_ldl (0, (vector signed short *)svss);
6946
+ vbs = vec_ldl (0, (vector bool short *)svbs);
6947
+ vp = vec_ldl (0, (vector pixel *)svp);
6948
+ vui = vec_ldl (0, (vector unsigned int *)svui);
6949
+ vsi = vec_ldl (0, (vector signed int *)svsi);
6950
+ vbi = vec_ldl (0, (vector bool int *)svbi);
6951
+ vf = vec_ldl (0, (vector float *)svf);
6952
+
6953
+ check (vec_all_eq (vuc, evuc), "vuc");
6954
+ check (vec_all_eq (vsc, evsc), "vsc");
6955
+ check (vec_all_eq (vbc, evbc), "vbc");
6956
+ check (vec_all_eq (vus, evus), "vus");
6957
+ check (vec_all_eq (vss, evss), "vss");
6958
+ check (vec_all_eq (vbs, evbs), "vbs");
6959
+ check (vec_all_eq (vp, evp ), "vp" );
6960
+ check (vec_all_eq (vui, evui), "vui");
6961
+ check (vec_all_eq (vsi, evsi), "vsi");
6962
+ check (vec_all_eq (vbi, evbi), "vbi");
6963
+ check (vec_all_eq (vf, evf ), "vf" );
6964
+}
6965
--- a/src/gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c
6966
+++ b/src/gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c
6967
@@ -0,0 +1,34 @@
6968
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
6969
+/* { dg-require-effective-target powerpc_vsx_ok } */
6970
+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */
6971
+
6972
+#include "harness.h"
6973
+
6974
+static unsigned long svul[2] __attribute__ ((aligned (16)));
6975
+static double svd[2] __attribute__ ((aligned (16)));
6976
+
6977
+static void check_arrays ()
6978
+{
6979
+ unsigned int i;
6980
+ for (i = 0; i < 2; ++i)
6981
+ {
6982
+ check (svul[i] == i, "svul");
6983
+ check (svd[i] == i * 1.0, "svd");
6984
+ }
6985
+}
6986
+
6987
+static void test ()
6988
+{
6989
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
6990
+ vector unsigned long vul = {1,0};
6991
+ vector double vd = {1.0,0.0};
6992
+#else
6993
+ vector unsigned long vul = {0,1};
6994
+ vector double vd = {0.0,1.0};
6995
+#endif
6996
+
6997
+ vec_stl (vul, 0, (vector unsigned long *)svul);
6998
+ vec_stl (vd, 0, (vector double *)svd);
6999
+
7000
+ check_arrays ();
7001
+}
6745
7002
--- a/src/gcc/testsuite/gcc.dg/vmx/vsums.c
6746
7003
+++ b/src/gcc/testsuite/gcc.dg/vmx/vsums.c
6747
7004
@@ -0,0 +1,12 @@
6751
7008
+{
6752
7009
+ vector signed int va = {-7,11,-13,17};
6753
7010
+ vector signed int vb = {0,0,0,128};
7011
+ vector signed int evd = {0,0,0,136};
6754
7012
+
6755
7013
+ vector signed int vd = vec_sums (va, vb);
6756
+ signed int r = vec_extract (vd, 3);
6757
7014
+
6758
+ check (r == 136, "sums");
7015
+ check (vec_all_eq (vd, evd), "sums");
6759
7016
+}
6760
7017
--- a/src/gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c
6761
7018
+++ b/src/gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c
6914
7171
+ check (vec_all_eq (vsir, vsier), "vsi");
6915
7172
+ check (vec_all_eq (vfr, vfer ), "vf");
6916
7173
+}
7174
--- a/src/gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c
7175
+++ b/src/gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c
7176
@@ -0,0 +1,40 @@
7177
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
7178
+/* { dg-require-effective-target powerpc_vsx_ok } */
7179
+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */
7180
+
7181
+#include "harness.h"
7182
+
7183
+static unsigned long svul[2] __attribute__ ((aligned (16)));
7184
+static double svd[2] __attribute__ ((aligned (16)));
7185
+
7186
+static void init ()
7187
+{
7188
+ unsigned int i;
7189
+ for (i = 0; i < 2; ++i)
7190
+ {
7191
+ svul[i] = i;
7192
+ svd[i] = i * 1.0;
7193
+ }
7194
+}
7195
+
7196
+static void test ()
7197
+{
7198
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
7199
+ vector unsigned long evul = {1,0};
7200
+ vector double evd = {1.0,0.0};
7201
+#else
7202
+ vector unsigned long evul = {0,1};
7203
+ vector double evd = {0.0,1.0};
7204
+#endif
7205
+
7206
+ vector unsigned long vul;
7207
+ vector double vd;
7208
+
7209
+ init ();
7210
+
7211
+ vul = vec_ldl (0, (vector unsigned long *)svul);
7212
+ vd = vec_ldl (0, (vector double *)svd);
7213
+
7214
+ check (vec_all_eq (vul, evul), "vul");
7215
+ check (vec_all_eq (vd, evd ), "vd" );
7216
+}
6917
7217
--- a/src/gcc/testsuite/gcc.dg/vmx/merge-be-order.c
6918
7218
+++ b/src/gcc/testsuite/gcc.dg/vmx/merge-be-order.c
6919
7219
@@ -0,0 +1,96 @@
7150
7450
+ ((vector short){7, 0, 0, 0, 0, 0, 0, 0})),
7151
7451
+ "vec_set");
7152
7452
+}
7453
--- a/src/gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c
7454
+++ b/src/gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c
7455
@@ -0,0 +1,40 @@
7456
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
7457
+/* { dg-require-effective-target powerpc_vsx_ok } */
7458
+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */
7459
+
7460
+#include "harness.h"
7461
+
7462
+static unsigned long svul[2] __attribute__ ((aligned (16)));
7463
+static double svd[2] __attribute__ ((aligned (16)));
7464
+
7465
+static void init ()
7466
+{
7467
+ unsigned int i;
7468
+ for (i = 0; i < 2; ++i)
7469
+ {
7470
+ svul[i] = i;
7471
+ svd[i] = i * 1.0;
7472
+ }
7473
+}
7474
+
7475
+static void test ()
7476
+{
7477
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
7478
+ vector unsigned long evul = {1,0};
7479
+ vector double evd = {1.0,0.0};
7480
+#else
7481
+ vector unsigned long evul = {0,1};
7482
+ vector double evd = {0.0,1.0};
7483
+#endif
7484
+
7485
+ vector unsigned long vul;
7486
+ vector double vd;
7487
+
7488
+ init ();
7489
+
7490
+ vul = vec_ld (0, (vector unsigned long *)svul);
7491
+ vd = vec_ld (0, (vector double *)svd);
7492
+
7493
+ check (vec_all_eq (vul, evul), "vul");
7494
+ check (vec_all_eq (vd, evd ), "vd" );
7495
+}
7153
7496
--- a/src/gcc/testsuite/gcc.dg/vmx/extract.c
7154
7497
+++ b/src/gcc/testsuite/gcc.dg/vmx/extract.c
7155
7498
@@ -0,0 +1,21 @@
7313
7656
+ check (vec_all_eq (vussur1, vussuer1), "vussur1");
7314
7657
+ check (vec_all_eq (vussur2, vussuer2), "vussur2");
7315
7658
+}
7659
--- a/src/gcc/testsuite/gcc.dg/vmx/st-be-order.c
7660
+++ b/src/gcc/testsuite/gcc.dg/vmx/st-be-order.c
7661
@@ -0,0 +1,83 @@
7662
+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
7663
+
7664
+#include "harness.h"
7665
+
7666
+static unsigned char svuc[16] __attribute__ ((aligned (16)));
7667
+static signed char svsc[16] __attribute__ ((aligned (16)));
7668
+static unsigned char svbc[16] __attribute__ ((aligned (16)));
7669
+static unsigned short svus[8] __attribute__ ((aligned (16)));
7670
+static signed short svss[8] __attribute__ ((aligned (16)));
7671
+static unsigned short svbs[8] __attribute__ ((aligned (16)));
7672
+static unsigned short svp[8] __attribute__ ((aligned (16)));
7673
+static unsigned int svui[4] __attribute__ ((aligned (16)));
7674
+static signed int svsi[4] __attribute__ ((aligned (16)));
7675
+static unsigned int svbi[4] __attribute__ ((aligned (16)));
7676
+static float svf[4] __attribute__ ((aligned (16)));
7677
+
7678
+static void check_arrays ()
7679
+{
7680
+ unsigned int i;
7681
+ for (i = 0; i < 16; ++i)
7682
+ {
7683
+ check (svuc[i] == i, "svuc");
7684
+ check (svsc[i] == i - 8, "svsc");
7685
+ check (svbc[i] == ((i % 2) ? 0xff : 0), "svbc");
7686
+ }
7687
+ for (i = 0; i < 8; ++i)
7688
+ {
7689
+ check (svus[i] == i, "svus");
7690
+ check (svss[i] == i - 4, "svss");
7691
+ check (svbs[i] == ((i % 2) ? 0xffff : 0), "svbs");
7692
+ check (svp[i] == i, "svp");
7693
+ }
7694
+ for (i = 0; i < 4; ++i)
7695
+ {
7696
+ check (svui[i] == i, "svui");
7697
+ check (svsi[i] == i - 2, "svsi");
7698
+ check (svbi[i] == ((i % 2) ? 0xffffffff : 0), "svbi");
7699
+ check (svf[i] == i * 1.0f, "svf");
7700
+ }
7701
+}
7702
+
7703
+static void test ()
7704
+{
7705
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
7706
+ vector unsigned char vuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
7707
+ vector signed char vsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};
7708
+ vector bool char vbc = {255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0};
7709
+ vector unsigned short vus = {7,6,5,4,3,2,1,0};
7710
+ vector signed short vss = {3,2,1,0,-1,-2,-3,-4};
7711
+ vector bool short vbs = {65535,0,65535,0,65535,0,65535,0};
7712
+ vector pixel vp = {7,6,5,4,3,2,1,0};
7713
+ vector unsigned int vui = {3,2,1,0};
7714
+ vector signed int vsi = {1,0,-1,-2};
7715
+ vector bool int vbi = {0xffffffff,0,0xffffffff,0};
7716
+ vector float vf = {3.0,2.0,1.0,0.0};
7717
+#else
7718
+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
7719
+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
7720
+ vector bool char vbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};
7721
+ vector unsigned short vus = {0,1,2,3,4,5,6,7};
7722
+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
7723
+ vector bool short vbs = {0,65535,0,65535,0,65535,0,65535};
7724
+ vector pixel vp = {0,1,2,3,4,5,6,7};
7725
+ vector unsigned int vui = {0,1,2,3};
7726
+ vector signed int vsi = {-2,-1,0,1};
7727
+ vector bool int vbi = {0,0xffffffff,0,0xffffffff};
7728
+ vector float vf = {0.0,1.0,2.0,3.0};
7729
+#endif
7730
+
7731
+ vec_st (vuc, 0, (vector unsigned char *)svuc);
7732
+ vec_st (vsc, 0, (vector signed char *)svsc);
7733
+ vec_st (vbc, 0, (vector bool char *)svbc);
7734
+ vec_st (vus, 0, (vector unsigned short *)svus);
7735
+ vec_st (vss, 0, (vector signed short *)svss);
7736
+ vec_st (vbs, 0, (vector bool short *)svbs);
7737
+ vec_st (vp, 0, (vector pixel *)svp);
7738
+ vec_st (vui, 0, (vector unsigned int *)svui);
7739
+ vec_st (vsi, 0, (vector signed int *)svsi);
7740
+ vec_st (vbi, 0, (vector bool int *)svbi);
7741
+ vec_st (vf, 0, (vector float *)svf);
7742
+
7743
+ check_arrays ();
7744
+}
7316
7745
--- a/src/gcc/testsuite/gcc.dg/vmx/gcc-bug-i.c
7317
7746
+++ b/src/gcc/testsuite/gcc.dg/vmx/gcc-bug-i.c
7318
7747
@@ -13,12 +13,27 @@
7358
7787
return result;
7359
7788
}
7360
7789
7790
--- a/src/gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c
7791
+++ b/src/gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c
7792
@@ -0,0 +1,34 @@
7793
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
7794
+/* { dg-require-effective-target powerpc_vsx_ok } */
7795
+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */
7796
+
7797
+#include "harness.h"
7798
+
7799
+static unsigned long svul[2] __attribute__ ((aligned (16)));
7800
+static double svd[2] __attribute__ ((aligned (16)));
7801
+
7802
+static void check_arrays ()
7803
+{
7804
+ unsigned int i;
7805
+ for (i = 0; i < 2; ++i)
7806
+ {
7807
+ check (svul[i] == i, "svul");
7808
+ check (svd[i] == i * 1.0, "svd");
7809
+ }
7810
+}
7811
+
7812
+static void test ()
7813
+{
7814
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
7815
+ vector unsigned long vul = {1,0};
7816
+ vector double vd = {1.0,0.0};
7817
+#else
7818
+ vector unsigned long vul = {0,1};
7819
+ vector double vd = {0.0,1.0};
7820
+#endif
7821
+
7822
+ vec_st (vul, 0, (vector unsigned long *)svul);
7823
+ vec_st (vd, 0, (vector double *)svd);
7824
+
7825
+ check_arrays ();
7826
+}
7827
--- a/src/gcc/testsuite/gcc.dg/vmx/lde.c
7828
+++ b/src/gcc/testsuite/gcc.dg/vmx/lde.c
7829
@@ -0,0 +1,59 @@
7830
+#include "harness.h"
7831
+
7832
+static unsigned char svuc[16] __attribute__ ((aligned (16)));
7833
+static signed char svsc[16] __attribute__ ((aligned (16)));
7834
+static unsigned short svus[8] __attribute__ ((aligned (16)));
7835
+static signed short svss[8] __attribute__ ((aligned (16)));
7836
+static unsigned int svui[4] __attribute__ ((aligned (16)));
7837
+static signed int svsi[4] __attribute__ ((aligned (16)));
7838
+static float svf[4] __attribute__ ((aligned (16)));
7839
+
7840
+static void init ()
7841
+{
7842
+ unsigned int i;
7843
+ for (i = 0; i < 16; ++i)
7844
+ {
7845
+ svuc[i] = i;
7846
+ svsc[i] = i - 8;
7847
+ }
7848
+ for (i = 0; i < 8; ++i)
7849
+ {
7850
+ svus[i] = i;
7851
+ svss[i] = i - 4;
7852
+ }
7853
+ for (i = 0; i < 4; ++i)
7854
+ {
7855
+ svui[i] = i;
7856
+ svsi[i] = i - 2;
7857
+ svf[i] = i * 1.0f;
7858
+ }
7859
+}
7860
+
7861
+static void test ()
7862
+{
7863
+ vector unsigned char vuc;
7864
+ vector signed char vsc;
7865
+ vector unsigned short vus;
7866
+ vector signed short vss;
7867
+ vector unsigned int vui;
7868
+ vector signed int vsi;
7869
+ vector float vf;
7870
+
7871
+ init ();
7872
+
7873
+ vuc = vec_lde (9*1, (unsigned char *)svuc);
7874
+ vsc = vec_lde (14*1, (signed char *)svsc);
7875
+ vus = vec_lde (7*2, (unsigned short *)svus);
7876
+ vss = vec_lde (1*2, (signed short *)svss);
7877
+ vui = vec_lde (3*4, (unsigned int *)svui);
7878
+ vsi = vec_lde (2*4, (signed int *)svsi);
7879
+ vf = vec_lde (0*4, (float *)svf);
7880
+
7881
+ check (vec_extract (vuc, 9) == 9, "vuc");
7882
+ check (vec_extract (vsc, 14) == 6, "vsc");
7883
+ check (vec_extract (vus, 7) == 7, "vus");
7884
+ check (vec_extract (vss, 1) == -3, "vss");
7885
+ check (vec_extract (vui, 3) == 3, "vui");
7886
+ check (vec_extract (vsi, 2) == 0, "vsi");
7887
+ check (vec_extract (vf, 0) == 0.0, "vf");
7888
+}
7889
--- a/src/gcc/testsuite/gcc.dg/vmx/pack.c
7890
+++ b/src/gcc/testsuite/gcc.dg/vmx/pack.c
7891
@@ -0,0 +1,108 @@
7892
+#include "harness.h"
7893
+
7894
+#define BIG 4294967295
7895
+
7896
+static void test()
7897
+{
7898
+ /* Input vectors. */
7899
+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};
7900
+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};
7901
+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};
7902
+ vector signed short vssb = {0,1,2,3,4,5,6,7};
7903
+ vector bool short vbsa = {0,65535,65535,0,0,0,65535,0};
7904
+ vector bool short vbsb = {65535,0,0,65535,65535,65535,0,65535};
7905
+ vector unsigned int vuia = {0,1,2,3};
7906
+ vector unsigned int vuib = {4,5,6,7};
7907
+ vector signed int vsia = {-4,-3,-2,-1};
7908
+ vector signed int vsib = {0,1,2,3};
7909
+ vector bool int vbia = {0,BIG,BIG,BIG};
7910
+ vector bool int vbib = {BIG,0,0,0};
7911
+ vector unsigned int vipa = {(0<<24) + (2<<19) + (3<<11) + (4<<3),
7912
+ (1<<24) + (5<<19) + (6<<11) + (7<<3),
7913
+ (0<<24) + (8<<19) + (9<<11) + (10<<3),
7914
+ (1<<24) + (11<<19) + (12<<11) + (13<<3)};
7915
+ vector unsigned int vipb = {(1<<24) + (14<<19) + (15<<11) + (16<<3),
7916
+ (0<<24) + (17<<19) + (18<<11) + (19<<3),
7917
+ (1<<24) + (20<<19) + (21<<11) + (22<<3),
7918
+ (0<<24) + (23<<19) + (24<<11) + (25<<3)};
7919
+ vector unsigned short vusc = {0,256,1,257,2,258,3,259};
7920
+ vector unsigned short vusd = {4,260,5,261,6,262,7,263};
7921
+ vector signed short vssc = {-1,-128,0,127,-2,-129,1,128};
7922
+ vector signed short vssd = {-3,-130,2,129,-4,-131,3,130};
7923
+ vector unsigned int vuic = {0,65536,1,65537};
7924
+ vector unsigned int vuid = {2,65538,3,65539};
7925
+ vector signed int vsic = {-1,-32768,0,32767};
7926
+ vector signed int vsid = {-2,-32769,1,32768};
7927
+
7928
+ /* Result vectors. */
7929
+ vector unsigned char vucr;
7930
+ vector signed char vscr;
7931
+ vector bool char vbcr;
7932
+ vector unsigned short vusr;
7933
+ vector signed short vssr;
7934
+ vector bool short vbsr;
7935
+ vector pixel vpr;
7936
+ vector unsigned char vucsr;
7937
+ vector signed char vscsr;
7938
+ vector unsigned short vussr;
7939
+ vector signed short vsssr;
7940
+ vector unsigned char vucsur1, vucsur2;
7941
+ vector unsigned short vussur1, vussur2;
7942
+
7943
+ /* Expected result vectors. */
7944
+ vector unsigned char vucer = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
7945
+ vector signed char vscer = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
7946
+ vector bool char vbcer = {0,255,255,0,0,0,255,0,255,0,0,255,255,255,0,255};
7947
+ vector unsigned short vuser = {0,1,2,3,4,5,6,7};
7948
+ vector signed short vsser = {-4,-3,-2,-1,0,1,2,3};
7949
+ vector bool short vbser = {0,65535,65535,65535,65535,0,0,0};
7950
+ vector pixel vper = {(0<<15) + (2<<10) + (3<<5) + 4,
7951
+ (1<<15) + (5<<10) + (6<<5) + 7,
7952
+ (0<<15) + (8<<10) + (9<<5) + 10,
7953
+ (1<<15) + (11<<10) + (12<<5) + 13,
7954
+ (1<<15) + (14<<10) + (15<<5) + 16,
7955
+ (0<<15) + (17<<10) + (18<<5) + 19,
7956
+ (1<<15) + (20<<10) + (21<<5) + 22,
7957
+ (0<<15) + (23<<10) + (24<<5) + 25};
7958
+ vector unsigned char vucser = {0,255,1,255,2,255,3,255,4,255,5,255,6,255,7,255};
7959
+ vector signed char vscser = {-1,-128,0,127,-2,-128,1,127,
7960
+ -3,-128,2,127,-4,-128,3,127};
7961
+ vector unsigned short vusser = {0,65535,1,65535,2,65535,3,65535};
7962
+ vector signed short vssser = {-1,-32768,0,32767,-2,-32768,1,32767};
7963
+ vector unsigned char vucsuer1 = {0,255,1,255,2,255,3,255,4,255,5,255,6,255,7,255};
7964
+ vector unsigned char vucsuer2 = {0,0,0,127,0,0,1,128,0,0,2,129,0,0,3,130};
7965
+ vector unsigned short vussuer1 = {0,65535,1,65535,2,65535,3,65535};
7966
+ vector unsigned short vussuer2 = {0,0,0,32767,0,0,1,32768};
7967
+
7968
+ vucr = vec_pack (vusa, vusb);
7969
+ vscr = vec_pack (vssa, vssb);
7970
+ vbcr = vec_pack (vbsa, vbsb);
7971
+ vusr = vec_pack (vuia, vuib);
7972
+ vssr = vec_pack (vsia, vsib);
7973
+ vbsr = vec_pack (vbia, vbib);
7974
+ vpr = vec_packpx (vipa, vipb);
7975
+ vucsr = vec_packs (vusc, vusd);
7976
+ vscsr = vec_packs (vssc, vssd);
7977
+ vussr = vec_packs (vuic, vuid);
7978
+ vsssr = vec_packs (vsic, vsid);
7979
+ vucsur1 = vec_packsu (vusc, vusd);
7980
+ vucsur2 = vec_packsu (vssc, vssd);
7981
+ vussur1 = vec_packsu (vuic, vuid);
7982
+ vussur2 = vec_packsu (vsic, vsid);
7983
+
7984
+ check (vec_all_eq (vucr, vucer), "vucr");
7985
+ check (vec_all_eq (vscr, vscer), "vscr");
7986
+ check (vec_all_eq (vbcr, vbcer), "vbcr");
7987
+ check (vec_all_eq (vusr, vuser), "vusr");
7988
+ check (vec_all_eq (vssr, vsser), "vssr");
7989
+ check (vec_all_eq (vbsr, vbser), "vbsr");
7990
+ check (vec_all_eq (vpr, vper ), "vpr" );
7991
+ check (vec_all_eq (vucsr, vucser), "vucsr");
7992
+ check (vec_all_eq (vscsr, vscser), "vscsr");
7993
+ check (vec_all_eq (vussr, vusser), "vussr");
7994
+ check (vec_all_eq (vsssr, vssser), "vsssr");
7995
+ check (vec_all_eq (vucsur1, vucsuer1), "vucsur1");
7996
+ check (vec_all_eq (vucsur2, vucsuer2), "vucsur2");
7997
+ check (vec_all_eq (vussur1, vussuer1), "vussur1");
7998
+ check (vec_all_eq (vussur2, vussuer2), "vussur2");
7999
+}
7361
8000
--- a/src/gcc/testsuite/gcc.dg/vmx/unpack-be-order.c
7362
8001
+++ b/src/gcc/testsuite/gcc.dg/vmx/unpack-be-order.c
7363
8002
@@ -0,0 +1,88 @@
7449
8088
+ check (vec_all_eq (vbih, vbihr), "vbih");
7450
8089
+ check (vec_all_eq (vbil, vbilr), "vbil");
7451
8090
+}
7452
--- a/src/gcc/testsuite/gcc.dg/vmx/pack.c
7453
+++ b/src/gcc/testsuite/gcc.dg/vmx/pack.c
7454
@@ -0,0 +1,108 @@
7455
+#include "harness.h"
7456
+
7457
+#define BIG 4294967295
7458
+
7459
+static void test()
7460
+{
7461
+ /* Input vectors. */
7462
+ vector unsigned short vusa = {0,1,2,3,4,5,6,7};
7463
+ vector unsigned short vusb = {8,9,10,11,12,13,14,15};
7464
+ vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};
7465
+ vector signed short vssb = {0,1,2,3,4,5,6,7};
7466
+ vector bool short vbsa = {0,65535,65535,0,0,0,65535,0};
7467
+ vector bool short vbsb = {65535,0,0,65535,65535,65535,0,65535};
7468
+ vector unsigned int vuia = {0,1,2,3};
7469
+ vector unsigned int vuib = {4,5,6,7};
7470
+ vector signed int vsia = {-4,-3,-2,-1};
7471
+ vector signed int vsib = {0,1,2,3};
7472
+ vector bool int vbia = {0,BIG,BIG,BIG};
7473
+ vector bool int vbib = {BIG,0,0,0};
7474
+ vector unsigned int vipa = {(0<<24) + (2<<19) + (3<<11) + (4<<3),
7475
+ (1<<24) + (5<<19) + (6<<11) + (7<<3),
7476
+ (0<<24) + (8<<19) + (9<<11) + (10<<3),
7477
+ (1<<24) + (11<<19) + (12<<11) + (13<<3)};
7478
+ vector unsigned int vipb = {(1<<24) + (14<<19) + (15<<11) + (16<<3),
7479
+ (0<<24) + (17<<19) + (18<<11) + (19<<3),
7480
+ (1<<24) + (20<<19) + (21<<11) + (22<<3),
7481
+ (0<<24) + (23<<19) + (24<<11) + (25<<3)};
7482
+ vector unsigned short vusc = {0,256,1,257,2,258,3,259};
7483
+ vector unsigned short vusd = {4,260,5,261,6,262,7,263};
7484
+ vector signed short vssc = {-1,-128,0,127,-2,-129,1,128};
7485
+ vector signed short vssd = {-3,-130,2,129,-4,-131,3,130};
7486
+ vector unsigned int vuic = {0,65536,1,65537};
7487
+ vector unsigned int vuid = {2,65538,3,65539};
7488
+ vector signed int vsic = {-1,-32768,0,32767};
7489
+ vector signed int vsid = {-2,-32769,1,32768};
7490
+
7491
+ /* Result vectors. */
7492
+ vector unsigned char vucr;
7493
+ vector signed char vscr;
7494
+ vector bool char vbcr;
7495
+ vector unsigned short vusr;
7496
+ vector signed short vssr;
7497
+ vector bool short vbsr;
7498
+ vector pixel vpr;
7499
+ vector unsigned char vucsr;
7500
+ vector signed char vscsr;
7501
+ vector unsigned short vussr;
7502
+ vector signed short vsssr;
7503
+ vector unsigned char vucsur1, vucsur2;
7504
+ vector unsigned short vussur1, vussur2;
7505
+
7506
+ /* Expected result vectors. */
7507
+ vector unsigned char vucer = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
7508
+ vector signed char vscer = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
7509
+ vector bool char vbcer = {0,255,255,0,0,0,255,0,255,0,0,255,255,255,0,255};
7510
+ vector unsigned short vuser = {0,1,2,3,4,5,6,7};
7511
+ vector signed short vsser = {-4,-3,-2,-1,0,1,2,3};
7512
+ vector bool short vbser = {0,65535,65535,65535,65535,0,0,0};
7513
+ vector pixel vper = {(0<<15) + (2<<10) + (3<<5) + 4,
7514
+ (1<<15) + (5<<10) + (6<<5) + 7,
7515
+ (0<<15) + (8<<10) + (9<<5) + 10,
7516
+ (1<<15) + (11<<10) + (12<<5) + 13,
7517
+ (1<<15) + (14<<10) + (15<<5) + 16,
7518
+ (0<<15) + (17<<10) + (18<<5) + 19,
7519
+ (1<<15) + (20<<10) + (21<<5) + 22,
7520
+ (0<<15) + (23<<10) + (24<<5) + 25};
7521
+ vector unsigned char vucser = {0,255,1,255,2,255,3,255,4,255,5,255,6,255,7,255};
7522
+ vector signed char vscser = {-1,-128,0,127,-2,-128,1,127,
7523
+ -3,-128,2,127,-4,-128,3,127};
7524
+ vector unsigned short vusser = {0,65535,1,65535,2,65535,3,65535};
7525
+ vector signed short vssser = {-1,-32768,0,32767,-2,-32768,1,32767};
7526
+ vector unsigned char vucsuer1 = {0,255,1,255,2,255,3,255,4,255,5,255,6,255,7,255};
7527
+ vector unsigned char vucsuer2 = {0,0,0,127,0,0,1,128,0,0,2,129,0,0,3,130};
7528
+ vector unsigned short vussuer1 = {0,65535,1,65535,2,65535,3,65535};
7529
+ vector unsigned short vussuer2 = {0,0,0,32767,0,0,1,32768};
7530
+
7531
+ vucr = vec_pack (vusa, vusb);
7532
+ vscr = vec_pack (vssa, vssb);
7533
+ vbcr = vec_pack (vbsa, vbsb);
7534
+ vusr = vec_pack (vuia, vuib);
7535
+ vssr = vec_pack (vsia, vsib);
7536
+ vbsr = vec_pack (vbia, vbib);
7537
+ vpr = vec_packpx (vipa, vipb);
7538
+ vucsr = vec_packs (vusc, vusd);
7539
+ vscsr = vec_packs (vssc, vssd);
7540
+ vussr = vec_packs (vuic, vuid);
7541
+ vsssr = vec_packs (vsic, vsid);
7542
+ vucsur1 = vec_packsu (vusc, vusd);
7543
+ vucsur2 = vec_packsu (vssc, vssd);
7544
+ vussur1 = vec_packsu (vuic, vuid);
7545
+ vussur2 = vec_packsu (vsic, vsid);
7546
+
7547
+ check (vec_all_eq (vucr, vucer), "vucr");
7548
+ check (vec_all_eq (vscr, vscer), "vscr");
7549
+ check (vec_all_eq (vbcr, vbcer), "vbcr");
7550
+ check (vec_all_eq (vusr, vuser), "vusr");
7551
+ check (vec_all_eq (vssr, vsser), "vssr");
7552
+ check (vec_all_eq (vbsr, vbser), "vbsr");
7553
+ check (vec_all_eq (vpr, vper ), "vpr" );
7554
+ check (vec_all_eq (vucsr, vucser), "vucsr");
7555
+ check (vec_all_eq (vscsr, vscser), "vscsr");
7556
+ check (vec_all_eq (vussr, vusser), "vussr");
7557
+ check (vec_all_eq (vsssr, vssser), "vsssr");
7558
+ check (vec_all_eq (vucsur1, vucsuer1), "vucsur1");
7559
+ check (vec_all_eq (vucsur2, vucsuer2), "vucsur2");
7560
+ check (vec_all_eq (vussur1, vussuer1), "vussur1");
7561
+ check (vec_all_eq (vussur2, vussuer2), "vussur2");
8091
--- a/src/gcc/testsuite/gcc.dg/vmx/st.c
8092
+++ b/src/gcc/testsuite/gcc.dg/vmx/st.c
8093
@@ -0,0 +1,67 @@
8094
+#include "harness.h"
8095
+
8096
+static unsigned char svuc[16] __attribute__ ((aligned (16)));
8097
+static signed char svsc[16] __attribute__ ((aligned (16)));
8098
+static unsigned char svbc[16] __attribute__ ((aligned (16)));
8099
+static unsigned short svus[8] __attribute__ ((aligned (16)));
8100
+static signed short svss[8] __attribute__ ((aligned (16)));
8101
+static unsigned short svbs[8] __attribute__ ((aligned (16)));
8102
+static unsigned short svp[8] __attribute__ ((aligned (16)));
8103
+static unsigned int svui[4] __attribute__ ((aligned (16)));
8104
+static signed int svsi[4] __attribute__ ((aligned (16)));
8105
+static unsigned int svbi[4] __attribute__ ((aligned (16)));
8106
+static float svf[4] __attribute__ ((aligned (16)));
8107
+
8108
+static void check_arrays ()
8109
+{
8110
+ unsigned int i;
8111
+ for (i = 0; i < 16; ++i)
8112
+ {
8113
+ check (svuc[i] == i, "svuc");
8114
+ check (svsc[i] == i - 8, "svsc");
8115
+ check (svbc[i] == ((i % 2) ? 0xff : 0), "svbc");
8116
+ }
8117
+ for (i = 0; i < 8; ++i)
8118
+ {
8119
+ check (svus[i] == i, "svus");
8120
+ check (svss[i] == i - 4, "svss");
8121
+ check (svbs[i] == ((i % 2) ? 0xffff : 0), "svbs");
8122
+ check (svp[i] == i, "svp");
8123
+ }
8124
+ for (i = 0; i < 4; ++i)
8125
+ {
8126
+ check (svui[i] == i, "svui");
8127
+ check (svsi[i] == i - 2, "svsi");
8128
+ check (svbi[i] == ((i % 2) ? 0xffffffff : 0), "svbi");
8129
+ check (svf[i] == i * 1.0f, "svf");
8130
+ }
8131
+}
8132
+
8133
+static void test ()
8134
+{
8135
+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
8136
+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
8137
+ vector bool char vbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};
8138
+ vector unsigned short vus = {0,1,2,3,4,5,6,7};
8139
+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
8140
+ vector bool short vbs = {0,65535,0,65535,0,65535,0,65535};
8141
+ vector pixel vp = {0,1,2,3,4,5,6,7};
8142
+ vector unsigned int vui = {0,1,2,3};
8143
+ vector signed int vsi = {-2,-1,0,1};
8144
+ vector bool int vbi = {0,0xffffffff,0,0xffffffff};
8145
+ vector float vf = {0.0,1.0,2.0,3.0};
8146
+
8147
+ vec_st (vuc, 0, (vector unsigned char *)svuc);
8148
+ vec_st (vsc, 0, (vector signed char *)svsc);
8149
+ vec_st (vbc, 0, (vector bool char *)svbc);
8150
+ vec_st (vus, 0, (vector unsigned short *)svus);
8151
+ vec_st (vss, 0, (vector signed short *)svss);
8152
+ vec_st (vbs, 0, (vector bool short *)svbs);
8153
+ vec_st (vp, 0, (vector pixel *)svp);
8154
+ vec_st (vui, 0, (vector unsigned int *)svui);
8155
+ vec_st (vsi, 0, (vector signed int *)svsi);
8156
+ vec_st (vbi, 0, (vector bool int *)svbi);
8157
+ vec_st (vf, 0, (vector float *)svf);
8158
+
8159
+ check_arrays ();
8160
+}
8161
--- a/src/gcc/testsuite/gcc.dg/vmx/ste-be-order.c
8162
+++ b/src/gcc/testsuite/gcc.dg/vmx/ste-be-order.c
8163
@@ -0,0 +1,53 @@
8164
+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
8165
+
8166
+#include "harness.h"
8167
+
8168
+static unsigned char svuc[16] __attribute__ ((aligned (16)));
8169
+static signed char svsc[16] __attribute__ ((aligned (16)));
8170
+static unsigned short svus[8] __attribute__ ((aligned (16)));
8171
+static signed short svss[8] __attribute__ ((aligned (16)));
8172
+static unsigned int svui[4] __attribute__ ((aligned (16)));
8173
+static signed int svsi[4] __attribute__ ((aligned (16)));
8174
+static float svf[4] __attribute__ ((aligned (16)));
8175
+
8176
+static void check_arrays ()
8177
+{
8178
+ check (svuc[9] == 9, "svuc");
8179
+ check (svsc[14] == 6, "svsc");
8180
+ check (svus[7] == 7, "svus");
8181
+ check (svss[1] == -3, "svss");
8182
+ check (svui[3] == 3, "svui");
8183
+ check (svsi[2] == 0, "svsi");
8184
+ check (svf[0] == 0.0, "svf");
8185
+}
8186
+
8187
+static void test ()
8188
+{
8189
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
8190
+ vector unsigned char vuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
8191
+ vector signed char vsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};
8192
+ vector unsigned short vus = {7,6,5,4,3,2,1,0};
8193
+ vector signed short vss = {3,2,1,0,-1,-2,-3,-4};
8194
+ vector unsigned int vui = {3,2,1,0};
8195
+ vector signed int vsi = {1,0,-1,-2};
8196
+ vector float vf = {3.0,2.0,1.0,0.0};
8197
+#else
8198
+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
8199
+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
8200
+ vector unsigned short vus = {0,1,2,3,4,5,6,7};
8201
+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
8202
+ vector unsigned int vui = {0,1,2,3};
8203
+ vector signed int vsi = {-2,-1,0,1};
8204
+ vector float vf = {0.0,1.0,2.0,3.0};
8205
+#endif
8206
+
8207
+ vec_ste (vuc, 9*1, (unsigned char *)svuc);
8208
+ vec_ste (vsc, 14*1, (signed char *)svsc);
8209
+ vec_ste (vus, 7*2, (unsigned short *)svus);
8210
+ vec_ste (vss, 1*2, (signed short *)svss);
8211
+ vec_ste (vui, 3*4, (unsigned int *)svui);
8212
+ vec_ste (vsi, 2*4, (signed int *)svsi);
8213
+ vec_ste (vf, 0*4, (float *)svf);
8214
+
8215
+ check_arrays ();
7562
8216
+}
7563
8217
--- a/src/gcc/testsuite/gcc.dg/vmx/insert.c
7564
8218
+++ b/src/gcc/testsuite/gcc.dg/vmx/insert.c
7600
8254
+ "vec_insert (vg)");
7601
8255
+}
7602
8256
+
8257
--- a/src/gcc/testsuite/gcc.dg/vmx/ld-vsx.c
8258
+++ b/src/gcc/testsuite/gcc.dg/vmx/ld-vsx.c
8259
@@ -0,0 +1,35 @@
8260
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
8261
+/* { dg-require-effective-target powerpc_vsx_ok } */
8262
+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */
8263
+
8264
+#include "harness.h"
8265
+
8266
+static unsigned long svul[2] __attribute__ ((aligned (16)));
8267
+static double svd[2] __attribute__ ((aligned (16)));
8268
+
8269
+static void init ()
8270
+{
8271
+ unsigned int i;
8272
+ for (i = 0; i < 2; ++i)
8273
+ {
8274
+ svul[i] = i;
8275
+ svd[i] = i * 1.0;
8276
+ }
8277
+}
8278
+
8279
+static void test ()
8280
+{
8281
+ vector unsigned long evul = {0,1};
8282
+ vector double evd = {0.0,1.0};
8283
+
8284
+ vector unsigned long vul;
8285
+ vector double vd;
8286
+
8287
+ init ();
8288
+
8289
+ vul = vec_ld (0, (vector unsigned long *)svul);
8290
+ vd = vec_ld (0, (vector double *)svd);
8291
+
8292
+ check (vec_all_eq (vul, evul), "vul");
8293
+ check (vec_all_eq (vd, evd ), "vd" );
8294
+}
7603
8295
--- a/src/gcc/testsuite/gcc.dg/vmx/extract-vsx.c
7604
8296
+++ b/src/gcc/testsuite/gcc.dg/vmx/extract-vsx.c
7605
8297
@@ -0,0 +1,16 @@
7727
8419
+#endif
7728
8420
+}
7729
8421
+
8422
--- a/src/gcc/testsuite/gcc.dg/vmx/ldl-be-order.c
8423
+++ b/src/gcc/testsuite/gcc.dg/vmx/ldl-be-order.c
8424
@@ -0,0 +1,107 @@
8425
+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
8426
+
8427
+#include "harness.h"
8428
+
8429
+static unsigned char svuc[16] __attribute__ ((aligned (16)));
8430
+static signed char svsc[16] __attribute__ ((aligned (16)));
8431
+static unsigned char svbc[16] __attribute__ ((aligned (16)));
8432
+static unsigned short svus[8] __attribute__ ((aligned (16)));
8433
+static signed short svss[8] __attribute__ ((aligned (16)));
8434
+static unsigned short svbs[8] __attribute__ ((aligned (16)));
8435
+static unsigned short svp[8] __attribute__ ((aligned (16)));
8436
+static unsigned int svui[4] __attribute__ ((aligned (16)));
8437
+static signed int svsi[4] __attribute__ ((aligned (16)));
8438
+static unsigned int svbi[4] __attribute__ ((aligned (16)));
8439
+static float svf[4] __attribute__ ((aligned (16)));
8440
+
8441
+static void init ()
8442
+{
8443
+ unsigned int i;
8444
+ for (i = 0; i < 16; ++i)
8445
+ {
8446
+ svuc[i] = i;
8447
+ svsc[i] = i - 8;
8448
+ svbc[i] = (i % 2) ? 0xff : 0;
8449
+ }
8450
+ for (i = 0; i < 8; ++i)
8451
+ {
8452
+ svus[i] = i;
8453
+ svss[i] = i - 4;
8454
+ svbs[i] = (i % 2) ? 0xffff : 0;
8455
+ svp[i] = i;
8456
+ }
8457
+ for (i = 0; i < 4; ++i)
8458
+ {
8459
+ svui[i] = i;
8460
+ svsi[i] = i - 2;
8461
+ svbi[i] = (i % 2) ? 0xffffffff : 0;
8462
+ svf[i] = i * 1.0f;
8463
+ }
8464
+}
8465
+
8466
+static void test ()
8467
+{
8468
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
8469
+ vector unsigned char evuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
8470
+ vector signed char evsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};
8471
+ vector bool char evbc = {255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0};
8472
+ vector unsigned short evus = {7,6,5,4,3,2,1,0};
8473
+ vector signed short evss = {3,2,1,0,-1,-2,-3,-4};
8474
+ vector bool short evbs = {65535,0,65535,0,65535,0,65535,0};
8475
+ vector pixel evp = {7,6,5,4,3,2,1,0};
8476
+ vector unsigned int evui = {3,2,1,0};
8477
+ vector signed int evsi = {1,0,-1,-2};
8478
+ vector bool int evbi = {0xffffffff,0,0xffffffff,0};
8479
+ vector float evf = {3.0,2.0,1.0,0.0};
8480
+#else
8481
+ vector unsigned char evuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
8482
+ vector signed char evsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
8483
+ vector bool char evbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};
8484
+ vector unsigned short evus = {0,1,2,3,4,5,6,7};
8485
+ vector signed short evss = {-4,-3,-2,-1,0,1,2,3};
8486
+ vector bool short evbs = {0,65535,0,65535,0,65535,0,65535};
8487
+ vector pixel evp = {0,1,2,3,4,5,6,7};
8488
+ vector unsigned int evui = {0,1,2,3};
8489
+ vector signed int evsi = {-2,-1,0,1};
8490
+ vector bool int evbi = {0,0xffffffff,0,0xffffffff};
8491
+ vector float evf = {0.0,1.0,2.0,3.0};
8492
+#endif
8493
+
8494
+ vector unsigned char vuc;
8495
+ vector signed char vsc;
8496
+ vector bool char vbc;
8497
+ vector unsigned short vus;
8498
+ vector signed short vss;
8499
+ vector bool short vbs;
8500
+ vector pixel vp;
8501
+ vector unsigned int vui;
8502
+ vector signed int vsi;
8503
+ vector bool int vbi;
8504
+ vector float vf;
8505
+
8506
+ init ();
8507
+
8508
+ vuc = vec_ldl (0, (vector unsigned char *)svuc);
8509
+ vsc = vec_ldl (0, (vector signed char *)svsc);
8510
+ vbc = vec_ldl (0, (vector bool char *)svbc);
8511
+ vus = vec_ldl (0, (vector unsigned short *)svus);
8512
+ vss = vec_ldl (0, (vector signed short *)svss);
8513
+ vbs = vec_ldl (0, (vector bool short *)svbs);
8514
+ vp = vec_ldl (0, (vector pixel *)svp);
8515
+ vui = vec_ldl (0, (vector unsigned int *)svui);
8516
+ vsi = vec_ldl (0, (vector signed int *)svsi);
8517
+ vbi = vec_ldl (0, (vector bool int *)svbi);
8518
+ vf = vec_ldl (0, (vector float *)svf);
8519
+
8520
+ check (vec_all_eq (vuc, evuc), "vuc");
8521
+ check (vec_all_eq (vsc, evsc), "vsc");
8522
+ check (vec_all_eq (vbc, evbc), "vbc");
8523
+ check (vec_all_eq (vus, evus), "vus");
8524
+ check (vec_all_eq (vss, evss), "vss");
8525
+ check (vec_all_eq (vbs, evbs), "vbs");
8526
+ check (vec_all_eq (vp, evp ), "vp" );
8527
+ check (vec_all_eq (vui, evui), "vui");
8528
+ check (vec_all_eq (vsi, evsi), "vsi");
8529
+ check (vec_all_eq (vbi, evbi), "vbi");
8530
+ check (vec_all_eq (vf, evf ), "vf" );
8531
+}
7730
8532
--- a/src/gcc/testsuite/gcc.dg/vmx/mult-even-odd.c
7731
8533
+++ b/src/gcc/testsuite/gcc.dg/vmx/mult-even-odd.c
7732
8534
@@ -0,0 +1,43 @@
7857
8659
+ check (vec_extract (vd, 1) == 1.0, "vd, 1");
7858
8660
+#endif
7859
8661
+}
8662
--- a/src/gcc/testsuite/gcc.dg/vmx/ld-be-order.c
8663
+++ b/src/gcc/testsuite/gcc.dg/vmx/ld-be-order.c
8664
@@ -0,0 +1,107 @@
8665
+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
8666
+
8667
+#include "harness.h"
8668
+
8669
+static unsigned char svuc[16] __attribute__ ((aligned (16)));
8670
+static signed char svsc[16] __attribute__ ((aligned (16)));
8671
+static unsigned char svbc[16] __attribute__ ((aligned (16)));
8672
+static unsigned short svus[8] __attribute__ ((aligned (16)));
8673
+static signed short svss[8] __attribute__ ((aligned (16)));
8674
+static unsigned short svbs[8] __attribute__ ((aligned (16)));
8675
+static unsigned short svp[8] __attribute__ ((aligned (16)));
8676
+static unsigned int svui[4] __attribute__ ((aligned (16)));
8677
+static signed int svsi[4] __attribute__ ((aligned (16)));
8678
+static unsigned int svbi[4] __attribute__ ((aligned (16)));
8679
+static float svf[4] __attribute__ ((aligned (16)));
8680
+
8681
+static void init ()
8682
+{
8683
+ unsigned int i;
8684
+ for (i = 0; i < 16; ++i)
8685
+ {
8686
+ svuc[i] = i;
8687
+ svsc[i] = i - 8;
8688
+ svbc[i] = (i % 2) ? 0xff : 0;
8689
+ }
8690
+ for (i = 0; i < 8; ++i)
8691
+ {
8692
+ svus[i] = i;
8693
+ svss[i] = i - 4;
8694
+ svbs[i] = (i % 2) ? 0xffff : 0;
8695
+ svp[i] = i;
8696
+ }
8697
+ for (i = 0; i < 4; ++i)
8698
+ {
8699
+ svui[i] = i;
8700
+ svsi[i] = i - 2;
8701
+ svbi[i] = (i % 2) ? 0xffffffff : 0;
8702
+ svf[i] = i * 1.0f;
8703
+ }
8704
+}
8705
+
8706
+static void test ()
8707
+{
8708
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
8709
+ vector unsigned char evuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
8710
+ vector signed char evsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8};
8711
+ vector bool char evbc = {255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0};
8712
+ vector unsigned short evus = {7,6,5,4,3,2,1,0};
8713
+ vector signed short evss = {3,2,1,0,-1,-2,-3,-4};
8714
+ vector bool short evbs = {65535,0,65535,0,65535,0,65535,0};
8715
+ vector pixel evp = {7,6,5,4,3,2,1,0};
8716
+ vector unsigned int evui = {3,2,1,0};
8717
+ vector signed int evsi = {1,0,-1,-2};
8718
+ vector bool int evbi = {0xffffffff,0,0xffffffff,0};
8719
+ vector float evf = {3.0,2.0,1.0,0.0};
8720
+#else
8721
+ vector unsigned char evuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
8722
+ vector signed char evsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
8723
+ vector bool char evbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};
8724
+ vector unsigned short evus = {0,1,2,3,4,5,6,7};
8725
+ vector signed short evss = {-4,-3,-2,-1,0,1,2,3};
8726
+ vector bool short evbs = {0,65535,0,65535,0,65535,0,65535};
8727
+ vector pixel evp = {0,1,2,3,4,5,6,7};
8728
+ vector unsigned int evui = {0,1,2,3};
8729
+ vector signed int evsi = {-2,-1,0,1};
8730
+ vector bool int evbi = {0,0xffffffff,0,0xffffffff};
8731
+ vector float evf = {0.0,1.0,2.0,3.0};
8732
+#endif
8733
+
8734
+ vector unsigned char vuc;
8735
+ vector signed char vsc;
8736
+ vector bool char vbc;
8737
+ vector unsigned short vus;
8738
+ vector signed short vss;
8739
+ vector bool short vbs;
8740
+ vector pixel vp;
8741
+ vector unsigned int vui;
8742
+ vector signed int vsi;
8743
+ vector bool int vbi;
8744
+ vector float vf;
8745
+
8746
+ init ();
8747
+
8748
+ vuc = vec_ld (0, (vector unsigned char *)svuc);
8749
+ vsc = vec_ld (0, (vector signed char *)svsc);
8750
+ vbc = vec_ld (0, (vector bool char *)svbc);
8751
+ vus = vec_ld (0, (vector unsigned short *)svus);
8752
+ vss = vec_ld (0, (vector signed short *)svss);
8753
+ vbs = vec_ld (0, (vector bool short *)svbs);
8754
+ vp = vec_ld (0, (vector pixel *)svp);
8755
+ vui = vec_ld (0, (vector unsigned int *)svui);
8756
+ vsi = vec_ld (0, (vector signed int *)svsi);
8757
+ vbi = vec_ld (0, (vector bool int *)svbi);
8758
+ vf = vec_ld (0, (vector float *)svf);
8759
+
8760
+ check (vec_all_eq (vuc, evuc), "vuc");
8761
+ check (vec_all_eq (vsc, evsc), "vsc");
8762
+ check (vec_all_eq (vbc, evbc), "vbc");
8763
+ check (vec_all_eq (vus, evus), "vus");
8764
+ check (vec_all_eq (vss, evss), "vss");
8765
+ check (vec_all_eq (vbs, evbs), "vbs");
8766
+ check (vec_all_eq (vp, evp ), "vp" );
8767
+ check (vec_all_eq (vui, evui), "vui");
8768
+ check (vec_all_eq (vsi, evsi), "vsi");
8769
+ check (vec_all_eq (vbi, evbi), "vbi");
8770
+ check (vec_all_eq (vf, evf ), "vf" );
8771
+}
8772
--- a/src/gcc/testsuite/gcc.dg/vmx/ld.c
8773
+++ b/src/gcc/testsuite/gcc.dg/vmx/ld.c
8774
@@ -0,0 +1,91 @@
8775
+#include "harness.h"
8776
+
8777
+static unsigned char svuc[16] __attribute__ ((aligned (16)));
8778
+static signed char svsc[16] __attribute__ ((aligned (16)));
8779
+static unsigned char svbc[16] __attribute__ ((aligned (16)));
8780
+static unsigned short svus[8] __attribute__ ((aligned (16)));
8781
+static signed short svss[8] __attribute__ ((aligned (16)));
8782
+static unsigned short svbs[8] __attribute__ ((aligned (16)));
8783
+static unsigned short svp[8] __attribute__ ((aligned (16)));
8784
+static unsigned int svui[4] __attribute__ ((aligned (16)));
8785
+static signed int svsi[4] __attribute__ ((aligned (16)));
8786
+static unsigned int svbi[4] __attribute__ ((aligned (16)));
8787
+static float svf[4] __attribute__ ((aligned (16)));
8788
+
8789
+static void init ()
8790
+{
8791
+ unsigned int i;
8792
+ for (i = 0; i < 16; ++i)
8793
+ {
8794
+ svuc[i] = i;
8795
+ svsc[i] = i - 8;
8796
+ svbc[i] = (i % 2) ? 0xff : 0;
8797
+ }
8798
+ for (i = 0; i < 8; ++i)
8799
+ {
8800
+ svus[i] = i;
8801
+ svss[i] = i - 4;
8802
+ svbs[i] = (i % 2) ? 0xffff : 0;
8803
+ svp[i] = i;
8804
+ }
8805
+ for (i = 0; i < 4; ++i)
8806
+ {
8807
+ svui[i] = i;
8808
+ svsi[i] = i - 2;
8809
+ svbi[i] = (i % 2) ? 0xffffffff : 0;
8810
+ svf[i] = i * 1.0f;
8811
+ }
8812
+}
8813
+
8814
+static void test ()
8815
+{
8816
+ vector unsigned char evuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
8817
+ vector signed char evsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
8818
+ vector bool char evbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};
8819
+ vector unsigned short evus = {0,1,2,3,4,5,6,7};
8820
+ vector signed short evss = {-4,-3,-2,-1,0,1,2,3};
8821
+ vector bool short evbs = {0,65535,0,65535,0,65535,0,65535};
8822
+ vector pixel evp = {0,1,2,3,4,5,6,7};
8823
+ vector unsigned int evui = {0,1,2,3};
8824
+ vector signed int evsi = {-2,-1,0,1};
8825
+ vector bool int evbi = {0,0xffffffff,0,0xffffffff};
8826
+ vector float evf = {0.0,1.0,2.0,3.0};
8827
+
8828
+ vector unsigned char vuc;
8829
+ vector signed char vsc;
8830
+ vector bool char vbc;
8831
+ vector unsigned short vus;
8832
+ vector signed short vss;
8833
+ vector bool short vbs;
8834
+ vector pixel vp;
8835
+ vector unsigned int vui;
8836
+ vector signed int vsi;
8837
+ vector bool int vbi;
8838
+ vector float vf;
8839
+
8840
+ init ();
8841
+
8842
+ vuc = vec_ld (0, (vector unsigned char *)svuc);
8843
+ vsc = vec_ld (0, (vector signed char *)svsc);
8844
+ vbc = vec_ld (0, (vector bool char *)svbc);
8845
+ vus = vec_ld (0, (vector unsigned short *)svus);
8846
+ vss = vec_ld (0, (vector signed short *)svss);
8847
+ vbs = vec_ld (0, (vector bool short *)svbs);
8848
+ vp = vec_ld (0, (vector pixel *)svp);
8849
+ vui = vec_ld (0, (vector unsigned int *)svui);
8850
+ vsi = vec_ld (0, (vector signed int *)svsi);
8851
+ vbi = vec_ld (0, (vector bool int *)svbi);
8852
+ vf = vec_ld (0, (vector float *)svf);
8853
+
8854
+ check (vec_all_eq (vuc, evuc), "vuc");
8855
+ check (vec_all_eq (vsc, evsc), "vsc");
8856
+ check (vec_all_eq (vbc, evbc), "vbc");
8857
+ check (vec_all_eq (vus, evus), "vus");
8858
+ check (vec_all_eq (vss, evss), "vss");
8859
+ check (vec_all_eq (vbs, evbs), "vbs");
8860
+ check (vec_all_eq (vp, evp ), "vp" );
8861
+ check (vec_all_eq (vui, evui), "vui");
8862
+ check (vec_all_eq (vsi, evsi), "vsi");
8863
+ check (vec_all_eq (vbi, evbi), "vbi");
8864
+ check (vec_all_eq (vf, evf ), "vf" );
8865
+}
7860
8866
--- a/src/gcc/testsuite/gcc.dg/vmx/sn7153.c
7861
8867
+++ b/src/gcc/testsuite/gcc.dg/vmx/sn7153.c
7862
8868
@@ -34,7 +34,11 @@
7871
8877
{
7872
8878
union {vector unsigned short v; unsigned short s[8];} u;
7873
8879
u.v = vec_mfvscr();
8880
--- a/src/gcc/testsuite/gcc.dg/vmx/stl.c
8881
+++ b/src/gcc/testsuite/gcc.dg/vmx/stl.c
8882
@@ -0,0 +1,67 @@
8883
+#include "harness.h"
8884
+
8885
+static unsigned char svuc[16] __attribute__ ((aligned (16)));
8886
+static signed char svsc[16] __attribute__ ((aligned (16)));
8887
+static unsigned char svbc[16] __attribute__ ((aligned (16)));
8888
+static unsigned short svus[8] __attribute__ ((aligned (16)));
8889
+static signed short svss[8] __attribute__ ((aligned (16)));
8890
+static unsigned short svbs[8] __attribute__ ((aligned (16)));
8891
+static unsigned short svp[8] __attribute__ ((aligned (16)));
8892
+static unsigned int svui[4] __attribute__ ((aligned (16)));
8893
+static signed int svsi[4] __attribute__ ((aligned (16)));
8894
+static unsigned int svbi[4] __attribute__ ((aligned (16)));
8895
+static float svf[4] __attribute__ ((aligned (16)));
8896
+
8897
+static void check_arrays ()
8898
+{
8899
+ unsigned int i;
8900
+ for (i = 0; i < 16; ++i)
8901
+ {
8902
+ check (svuc[i] == i, "svuc");
8903
+ check (svsc[i] == i - 8, "svsc");
8904
+ check (svbc[i] == ((i % 2) ? 0xff : 0), "svbc");
8905
+ }
8906
+ for (i = 0; i < 8; ++i)
8907
+ {
8908
+ check (svus[i] == i, "svus");
8909
+ check (svss[i] == i - 4, "svss");
8910
+ check (svbs[i] == ((i % 2) ? 0xffff : 0), "svbs");
8911
+ check (svp[i] == i, "svp");
8912
+ }
8913
+ for (i = 0; i < 4; ++i)
8914
+ {
8915
+ check (svui[i] == i, "svui");
8916
+ check (svsi[i] == i - 2, "svsi");
8917
+ check (svbi[i] == ((i % 2) ? 0xffffffff : 0), "svbi");
8918
+ check (svf[i] == i * 1.0f, "svf");
8919
+ }
8920
+}
8921
+
8922
+static void test ()
8923
+{
8924
+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
8925
+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
8926
+ vector bool char vbc = {0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255};
8927
+ vector unsigned short vus = {0,1,2,3,4,5,6,7};
8928
+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
8929
+ vector bool short vbs = {0,65535,0,65535,0,65535,0,65535};
8930
+ vector pixel vp = {0,1,2,3,4,5,6,7};
8931
+ vector unsigned int vui = {0,1,2,3};
8932
+ vector signed int vsi = {-2,-1,0,1};
8933
+ vector bool int vbi = {0,0xffffffff,0,0xffffffff};
8934
+ vector float vf = {0.0,1.0,2.0,3.0};
8935
+
8936
+ vec_stl (vuc, 0, (vector unsigned char *)svuc);
8937
+ vec_stl (vsc, 0, (vector signed char *)svsc);
8938
+ vec_stl (vbc, 0, (vector bool char *)svbc);
8939
+ vec_stl (vus, 0, (vector unsigned short *)svus);
8940
+ vec_stl (vss, 0, (vector signed short *)svss);
8941
+ vec_stl (vbs, 0, (vector bool short *)svbs);
8942
+ vec_stl (vp, 0, (vector pixel *)svp);
8943
+ vec_stl (vui, 0, (vector unsigned int *)svui);
8944
+ vec_stl (vsi, 0, (vector signed int *)svsi);
8945
+ vec_stl (vbi, 0, (vector bool int *)svbi);
8946
+ vec_stl (vf, 0, (vector float *)svf);
8947
+
8948
+ check_arrays ();
8949
+}
8950
--- a/src/gcc/testsuite/gcc.dg/vmx/st-vsx.c
8951
+++ b/src/gcc/testsuite/gcc.dg/vmx/st-vsx.c
8952
@@ -0,0 +1,29 @@
8953
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
8954
+/* { dg-require-effective-target powerpc_vsx_ok } */
8955
+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */
8956
+
8957
+#include "harness.h"
8958
+
8959
+static unsigned long svul[2] __attribute__ ((aligned (16)));
8960
+static double svd[2] __attribute__ ((aligned (16)));
8961
+
8962
+static void check_arrays ()
8963
+{
8964
+ unsigned int i;
8965
+ for (i = 0; i < 2; ++i)
8966
+ {
8967
+ check (svul[i] == i, "svul");
8968
+ check (svd[i] == i * 1.0, "svd");
8969
+ }
8970
+}
8971
+
8972
+static void test ()
8973
+{
8974
+ vector unsigned long vul = {0,1};
8975
+ vector double vd = {0.0,1.0};
8976
+
8977
+ vec_st (vul, 0, (vector unsigned long *)svul);
8978
+ vec_st (vd, 0, (vector double *)svd);
8979
+
8980
+ check_arrays ();
8981
+}
7874
8982
--- a/src/gcc/testsuite/gcc.dg/vmx/sum2s.c
7875
8983
+++ b/src/gcc/testsuite/gcc.dg/vmx/sum2s.c
7876
8984
@@ -0,0 +1,13 @@
8036
9144
+}
8037
9145
--- a/src/gcc/testsuite/gcc.dg/vmx/vsums-be-order.c
8038
9146
+++ b/src/gcc/testsuite/gcc.dg/vmx/vsums-be-order.c
8039
@@ -0,0 +1,19 @@
9147
@@ -0,0 +1,20 @@
8040
9148
+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
8041
9149
+
8042
9150
+#include "harness.h"
8047
9155
+
8048
9156
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
8049
9157
+ vector signed int vb = {128,0,0,0};
9158
+ vector signed int evd = {136,0,0,0};
8050
9159
+#else
8051
9160
+ vector signed int vb = {0,0,0,128};
9161
+ vector signed int evd = {0,0,0,136};
8052
9162
+#endif
8053
9163
+
8054
9164
+ vector signed int vd = vec_sums (va, vb);
8055
+ signed int r = vec_extract (vd, 3);
8056
+
8057
+ check (r == 136, "sums");
9165
+
9166
+ check (vec_all_eq (vd, evd), "sums");
9167
+}
9168
--- a/src/gcc/testsuite/gcc.dg/vmx/ldl-vsx.c
9169
+++ b/src/gcc/testsuite/gcc.dg/vmx/ldl-vsx.c
9170
@@ -0,0 +1,35 @@
9171
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
9172
+/* { dg-require-effective-target powerpc_vsx_ok } */
9173
+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */
9174
+
9175
+#include "harness.h"
9176
+
9177
+static unsigned long svul[2] __attribute__ ((aligned (16)));
9178
+static double svd[2] __attribute__ ((aligned (16)));
9179
+
9180
+static void init ()
9181
+{
9182
+ unsigned int i;
9183
+ for (i = 0; i < 2; ++i)
9184
+ {
9185
+ svul[i] = i;
9186
+ svd[i] = i * 1.0;
9187
+ }
9188
+}
9189
+
9190
+static void test ()
9191
+{
9192
+ vector unsigned long evul = {0,1};
9193
+ vector double evd = {0.0,1.0};
9194
+
9195
+ vector unsigned long vul;
9196
+ vector double vd;
9197
+
9198
+ init ();
9199
+
9200
+ vul = vec_ldl (0, (vector unsigned long *)svul);
9201
+ vd = vec_ldl (0, (vector double *)svd);
9202
+
9203
+ check (vec_all_eq (vul, evul), "vul");
9204
+ check (vec_all_eq (vd, evd ), "vd" );
9205
+}
9206
--- a/src/gcc/testsuite/gcc.dg/vmx/ste.c
9207
+++ b/src/gcc/testsuite/gcc.dg/vmx/ste.c
9208
@@ -0,0 +1,41 @@
9209
+#include "harness.h"
9210
+
9211
+static unsigned char svuc[16] __attribute__ ((aligned (16)));
9212
+static signed char svsc[16] __attribute__ ((aligned (16)));
9213
+static unsigned short svus[8] __attribute__ ((aligned (16)));
9214
+static signed short svss[8] __attribute__ ((aligned (16)));
9215
+static unsigned int svui[4] __attribute__ ((aligned (16)));
9216
+static signed int svsi[4] __attribute__ ((aligned (16)));
9217
+static float svf[4] __attribute__ ((aligned (16)));
9218
+
9219
+static void check_arrays ()
9220
+{
9221
+ check (svuc[9] == 9, "svuc");
9222
+ check (svsc[14] == 6, "svsc");
9223
+ check (svus[7] == 7, "svus");
9224
+ check (svss[1] == -3, "svss");
9225
+ check (svui[3] == 3, "svui");
9226
+ check (svsi[2] == 0, "svsi");
9227
+ check (svf[0] == 0.0, "svf");
9228
+}
9229
+
9230
+static void test ()
9231
+{
9232
+ vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
9233
+ vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
9234
+ vector unsigned short vus = {0,1,2,3,4,5,6,7};
9235
+ vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
9236
+ vector unsigned int vui = {0,1,2,3};
9237
+ vector signed int vsi = {-2,-1,0,1};
9238
+ vector float vf = {0.0,1.0,2.0,3.0};
9239
+
9240
+ vec_ste (vuc, 9*1, (unsigned char *)svuc);
9241
+ vec_ste (vsc, 14*1, (signed char *)svsc);
9242
+ vec_ste (vus, 7*2, (unsigned short *)svus);
9243
+ vec_ste (vss, 1*2, (signed short *)svss);
9244
+ vec_ste (vui, 3*4, (unsigned int *)svui);
9245
+ vec_ste (vsi, 2*4, (signed int *)svsi);
9246
+ vec_ste (vf, 0*4, (float *)svf);
9247
+
9248
+ check_arrays ();
9249
+}
9250
--- a/src/gcc/testsuite/gcc.dg/vmx/lde-be-order.c
9251
+++ b/src/gcc/testsuite/gcc.dg/vmx/lde-be-order.c
9252
@@ -0,0 +1,73 @@
9253
+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
9254
+
9255
+#include "harness.h"
9256
+
9257
+static unsigned char svuc[16] __attribute__ ((aligned (16)));
9258
+static signed char svsc[16] __attribute__ ((aligned (16)));
9259
+static unsigned short svus[8] __attribute__ ((aligned (16)));
9260
+static signed short svss[8] __attribute__ ((aligned (16)));
9261
+static unsigned int svui[4] __attribute__ ((aligned (16)));
9262
+static signed int svsi[4] __attribute__ ((aligned (16)));
9263
+static float svf[4] __attribute__ ((aligned (16)));
9264
+
9265
+static void init ()
9266
+{
9267
+ int i;
9268
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
9269
+ for (i = 15; i >= 0; --i)
9270
+#else
9271
+ for (i = 0; i < 16; ++i)
9272
+#endif
9273
+ {
9274
+ svuc[i] = i;
9275
+ svsc[i] = i - 8;
9276
+ }
9277
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
9278
+ for (i = 7; i >= 0; --i)
9279
+#else
9280
+ for (i = 0; i < 8; ++i)
9281
+#endif
9282
+ {
9283
+ svus[i] = i;
9284
+ svss[i] = i - 4;
9285
+ }
9286
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
9287
+ for (i = 3; i >= 0; --i)
9288
+#else
9289
+ for (i = 0; i < 4; ++i)
9290
+#endif
9291
+ {
9292
+ svui[i] = i;
9293
+ svsi[i] = i - 2;
9294
+ svf[i] = i * 1.0f;
9295
+ }
9296
+}
9297
+
9298
+static void test ()
9299
+{
9300
+ vector unsigned char vuc;
9301
+ vector signed char vsc;
9302
+ vector unsigned short vus;
9303
+ vector signed short vss;
9304
+ vector unsigned int vui;
9305
+ vector signed int vsi;
9306
+ vector float vf;
9307
+
9308
+ init ();
9309
+
9310
+ vuc = vec_lde (9*1, (unsigned char *)svuc);
9311
+ vsc = vec_lde (14*1, (signed char *)svsc);
9312
+ vus = vec_lde (7*2, (unsigned short *)svus);
9313
+ vss = vec_lde (1*2, (signed short *)svss);
9314
+ vui = vec_lde (3*4, (unsigned int *)svui);
9315
+ vsi = vec_lde (2*4, (signed int *)svsi);
9316
+ vf = vec_lde (0*4, (float *)svf);
9317
+
9318
+ check (vec_extract (vuc, 9) == 9, "vuc");
9319
+ check (vec_extract (vsc, 14) == 6, "vsc");
9320
+ check (vec_extract (vus, 7) == 7, "vus");
9321
+ check (vec_extract (vss, 1) == -3, "vss");
9322
+ check (vec_extract (vui, 3) == 3, "vui");
9323
+ check (vec_extract (vsi, 2) == 0, "vsi");
9324
+ check (vec_extract (vf, 0) == 0.0, "vf");
8058
9325
+}
8059
9326
--- a/src/gcc/testsuite/gcc.dg/vmx/splat-vsx.c
8060
9327
+++ b/src/gcc/testsuite/gcc.dg/vmx/splat-vsx.c
8154
9421
+ check (vec_all_eq (vdh, vdrh), "vdh" );
8155
9422
+ check (vec_all_eq (vdl, vdrl), "vdl" );
8156
9423
+}
9424
--- a/src/gcc/testsuite/gcc.dg/vmx/stl-vsx.c
9425
+++ b/src/gcc/testsuite/gcc.dg/vmx/stl-vsx.c
9426
@@ -0,0 +1,29 @@
9427
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
9428
+/* { dg-require-effective-target powerpc_vsx_ok } */
9429
+/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */
9430
+
9431
+#include "harness.h"
9432
+
9433
+static unsigned long svul[2] __attribute__ ((aligned (16)));
9434
+static double svd[2] __attribute__ ((aligned (16)));
9435
+
9436
+static void check_arrays ()
9437
+{
9438
+ unsigned int i;
9439
+ for (i = 0; i < 2; ++i)
9440
+ {
9441
+ check (svul[i] == i, "svul");
9442
+ check (svd[i] == i * 1.0, "svd");
9443
+ }
9444
+}
9445
+
9446
+static void test ()
9447
+{
9448
+ vector unsigned long vul = {0,1};
9449
+ vector double vd = {0.0,1.0};
9450
+
9451
+ vec_stl (vul, 0, (vector unsigned long *)svul);
9452
+ vec_stl (vd, 0, (vector double *)svd);
9453
+
9454
+ check_arrays ();
9455
+}
8157
9456
--- a/src/gcc/testsuite/gcc.dg/stack-usage-1.c
8158
9457
+++ b/src/gcc/testsuite/gcc.dg/stack-usage-1.c
8159
9458
@@ -38,7 +38,11 @@
8477
9776
emit_move_insn (gen_rtx_REG (GET_MODE (decl_rtl),
8478
9777
--- a/src/gcc/ChangeLog.ibm
8479
9778
+++ b/src/gcc/ChangeLog.ibm
8480
@@ -0,0 +1,2897 @@
9779
@@ -0,0 +1,2972 @@
9780
+2014-02-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
9781
+
9782
+ * config/rs6000/rs6000.c (rs6000_emit_le_vsx_move): Relax assert
9783
+ to permit subregs.
9784
+
9785
+2014-02-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
9786
+
9787
+ Backport from mainline 208049
9788
+ 2014-02-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
9789
+
9790
+ * config/rs6000/altivec.md (altivec_lve<VI_char>x): Replace
9791
+ define_insn with define_expand and new define_insn
9792
+ *altivec_lve<VI_char>x_internal.
9793
+ (altivec_stve<VI_char>x): Replace define_insn with define_expand
9794
+ and new define_insn *altivec_stve<VI_char>x_internal.
9795
+ * config/rs6000/rs6000-protos.h (altivec_expand_stvex_be): New
9796
+ prototype.
9797
+ * config/rs6000/rs6000.c (altivec_expand_lvx_be): Document use by
9798
+ lve*x built-ins.
9799
+ (altivec_expand_stvex_be): New function.
9800
+
9801
+2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
9802
+
9803
+ Backport from mainline 208021
9804
+ 2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
9805
+
9806
+ * config/rs6000/altivec.md (altivec_vsumsws): Replace second
9807
+ vspltw with vsldoi.
9808
+ (reduc_uplus_v16qi): Use gen_altivec_vsumsws_direct instead of
9809
+ gen_altivec_vsumsws.
9810
+
9811
+2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
9812
+
9813
+ Backport from mainline 208019
9814
+ 2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
9815
+
9816
+ * config/rs6000/altivec.md (altivec_lvxl): Rename as
9817
+ *altivec_lvxl_<mode>_internal and use VM2 iterator instead of
9818
+ V4SI.
9819
+ (altivec_lvxl_<mode>): New define_expand incorporating
9820
+ -maltivec=be semantics where needed.
9821
+ (altivec_lvx): Rename as *altivec_lvx_<mode>_internal.
9822
+ (altivec_lvx_<mode>): New define_expand incorporating -maltivec=be
9823
+ semantics where needed.
9824
+ (altivec_stvx): Rename as *altivec_stvx_<mode>_internal.
9825
+ (altivec_stvx_<mode>): New define_expand incorporating
9826
+ -maltivec=be semantics where needed.
9827
+ (altivec_stvxl): Rename as *altivec_stvxl_<mode>_internal and use
9828
+ VM2 iterator instead of V4SI.
9829
+ (altivec_stvxl_<mode>): New define_expand incorporating
9830
+ -maltivec=be semantics where needed.
9831
+ * config/rs6000/rs6000-builtin.def: Add new built-in definitions
9832
+ LVXL_V2DF, LVXL_V2DI, LVXL_V4SF, LVXL_V4SI, LVXL_V8HI, LVXL_V16QI,
9833
+ LVX_V2DF, LVX_V2DI, LVX_V4SF, LVX_V4SI, LVX_V8HI, LVX_V16QI,
9834
+ STVX_V2DF, STVX_V2DI, STVX_V4SF, STVX_V4SI, STVX_V8HI, STVX_V16QI,
9835
+ STVXL_V2DF, STVXL_V2DI, STVXL_V4SF, STVXL_V4SI, STVXL_V8HI,
9836
+ STVXL_V16QI.
9837
+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Replace
9838
+ ALTIVEC_BUILTIN_LVX with ALTIVEC_BUILTIN_LVX_<MODE> throughout;
9839
+ similarly for ALTIVEC_BUILTIN_LVXL, ALTIVEC_BUILTIN_STVX, and
9840
+ ALTIVEC_BUILTIN_STVXL.
9841
+ * config/rs6000/rs6000-protos.h (altivec_expand_lvx_be): New
9842
+ prototype.
9843
+ (altivec_expand_stvx_be): Likewise.
9844
+ * config/rs6000/rs6000.c (swap_selector_for_mode): New function.
9845
+ (altivec_expand_lvx_be): Likewise.
9846
+ (altivec_expand_stvx_be): Likewise.
9847
+ (altivec_expand_builtin): Add cases for
9848
+ ALTIVEC_BUILTIN_STVX_<MODE>, ALTIVEC_BUILTIN_STVXL_<MODE>,
9849
+ ALTIVEC_BUILTIN_LVXL_<MODE>, and ALTIVEC_BUILTIN_LVX_<MODE>.
9850
+ (altivec_init_builtins): Add definitions for
9851
+ __builtin_altivec_lvxl_<mode>, __builtin_altivec_lvx_<mode>,
9852
+ __builtin_altivec_stvx_<mode>, and
9853
+ __builtin_altivec_stvxl_<mode>.
9854
+
8481
9855
+2014-02-19 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
8482
9856
+
8483
9857
+ Backport from mainline r207919.
13272
14646
+#endif /* _HTMINTRIN_H */
13273
14647
--- a/src/gcc/config/rs6000/rs6000-protos.h
13274
14648
+++ b/src/gcc/config/rs6000/rs6000-protos.h
13275
@@ -50,11 +50,13 @@
14649
@@ -50,12 +50,17 @@
13276
14650
extern rtx find_addr_reg (rtx);
13277
14651
extern rtx gen_easy_altivec_constant (rtx);
13278
14652
extern const char *output_vec_const_move (rtx *);
13284
14658
extern bool altivec_expand_vec_perm_const (rtx op[4]);
13285
14659
+extern void altivec_expand_vec_perm_le (rtx op[4]);
13286
14660
extern bool rs6000_expand_vec_perm_const (rtx op[4]);
14661
+extern void altivec_expand_lvx_be (rtx, rtx, enum machine_mode, unsigned);
14662
+extern void altivec_expand_stvx_be (rtx, rtx, enum machine_mode, unsigned);
14663
+extern void altivec_expand_stvex_be (rtx, rtx, enum machine_mode, unsigned);
13287
14664
extern void rs6000_expand_extract_even (rtx, rtx, rtx);
13288
14665
extern void rs6000_expand_interleave (rtx, rtx, rtx, bool);
13289
@@ -70,6 +72,11 @@
14666
extern void build_mask64_2_operands (rtx, rtx *);
14667
@@ -70,6 +75,11 @@
13290
14668
extern int registers_ok_for_quad_peep (rtx, rtx);
13291
14669
extern int mems_ok_for_quad_peep (rtx, rtx);
13292
14670
extern bool gpr_or_gpr_p (rtx, rtx);
13298
14676
extern enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx,
13299
14677
enum reg_class);
13300
14678
extern enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
13301
@@ -116,6 +123,7 @@
14679
@@ -116,6 +126,7 @@
13302
14680
extern void rs6000_fatal_bad_address (rtx);
13303
14681
extern rtx create_TOC_reference (rtx, rtx);
13304
14682
extern void rs6000_split_multireg_move (rtx, rtx);
13306
14684
extern void rs6000_emit_move (rtx, rtx, enum machine_mode);
13307
14685
extern rtx rs6000_secondary_memory_needed_rtx (enum machine_mode);
13308
14686
extern rtx (*rs6000_legitimize_reload_address_ptr) (rtx, enum machine_mode,
13309
@@ -135,6 +143,7 @@
14687
@@ -135,6 +146,7 @@
13310
14688
extern rtx rs6000_address_for_altivec (rtx);
13311
14689
extern rtx rs6000_allocate_stack_temp (enum machine_mode, bool, bool);
13312
14690
extern int rs6000_loop_align (rtx);
13314
14692
#endif /* RTX_CODE */
13315
14693
13316
14694
#ifdef TREE_CODE
13317
@@ -146,6 +155,7 @@
14695
@@ -146,6 +158,7 @@
13318
14696
extern rtx rs6000_libcall_value (enum machine_mode);
13319
14697
extern rtx rs6000_va_arg (tree, tree);
13320
14698
extern int function_ok_for_sibcall (tree);
13322
14700
extern void rs6000_elf_declare_function_name (FILE *, const char *, tree);
13323
14701
extern bool rs6000_elf_in_small_data_p (const_tree);
13324
14702
#ifdef ARGS_SIZE_RTX
13325
@@ -170,7 +180,8 @@
14703
@@ -170,7 +183,8 @@
13326
14704
extern void rs6000_emit_epilogue (int);
13327
14705
extern void rs6000_emit_eh_reg_restore (rtx, rtx);
13328
14706
extern const char * output_isel (rtx *);
13744
15122
/* SPE convenience macros. */
13745
15123
#define BU_SPE_1(ENUM, NAME, ATTR, ICODE) \
13746
15124
RS6000_BUILTIN_1 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \
13747
@@ -1012,7 +1169,7 @@
15125
@@ -636,8 +793,26 @@
15126
BU_ALTIVEC_X (LVEHX, "lvehx", MEM)
15127
BU_ALTIVEC_X (LVEWX, "lvewx", MEM)
15128
BU_ALTIVEC_X (LVXL, "lvxl", MEM)
15129
+BU_ALTIVEC_X (LVXL_V2DF, "lvxl_v2df", MEM)
15130
+BU_ALTIVEC_X (LVXL_V2DI, "lvxl_v2di", MEM)
15131
+BU_ALTIVEC_X (LVXL_V4SF, "lvxl_v4sf", MEM)
15132
+BU_ALTIVEC_X (LVXL_V4SI, "lvxl_v4si", MEM)
15133
+BU_ALTIVEC_X (LVXL_V8HI, "lvxl_v8hi", MEM)
15134
+BU_ALTIVEC_X (LVXL_V16QI, "lvxl_v16qi", MEM)
15135
BU_ALTIVEC_X (LVX, "lvx", MEM)
15136
+BU_ALTIVEC_X (LVX_V2DF, "lvx_v2df", MEM)
15137
+BU_ALTIVEC_X (LVX_V2DI, "lvx_v2di", MEM)
15138
+BU_ALTIVEC_X (LVX_V4SF, "lvx_v4sf", MEM)
15139
+BU_ALTIVEC_X (LVX_V4SI, "lvx_v4si", MEM)
15140
+BU_ALTIVEC_X (LVX_V8HI, "lvx_v8hi", MEM)
15141
+BU_ALTIVEC_X (LVX_V16QI, "lvx_v16qi", MEM)
15142
BU_ALTIVEC_X (STVX, "stvx", MEM)
15143
+BU_ALTIVEC_X (STVX_V2DF, "stvx_v2df", MEM)
15144
+BU_ALTIVEC_X (STVX_V2DI, "stvx_v2di", MEM)
15145
+BU_ALTIVEC_X (STVX_V4SF, "stvx_v4sf", MEM)
15146
+BU_ALTIVEC_X (STVX_V4SI, "stvx_v4si", MEM)
15147
+BU_ALTIVEC_X (STVX_V8HI, "stvx_v8hi", MEM)
15148
+BU_ALTIVEC_X (STVX_V16QI, "stvx_v16qi", MEM)
15149
BU_ALTIVEC_C (LVLX, "lvlx", MEM)
15150
BU_ALTIVEC_C (LVLXL, "lvlxl", MEM)
15151
BU_ALTIVEC_C (LVRX, "lvrx", MEM)
15152
@@ -646,6 +821,12 @@
15153
BU_ALTIVEC_X (STVEHX, "stvehx", MEM)
15154
BU_ALTIVEC_X (STVEWX, "stvewx", MEM)
15155
BU_ALTIVEC_X (STVXL, "stvxl", MEM)
15156
+BU_ALTIVEC_X (STVXL_V2DF, "stvxl_v2df", MEM)
15157
+BU_ALTIVEC_X (STVXL_V2DI, "stvxl_v2di", MEM)
15158
+BU_ALTIVEC_X (STVXL_V4SF, "stvxl_v4sf", MEM)
15159
+BU_ALTIVEC_X (STVXL_V4SI, "stvxl_v4si", MEM)
15160
+BU_ALTIVEC_X (STVXL_V8HI, "stvxl_v8hi", MEM)
15161
+BU_ALTIVEC_X (STVXL_V16QI, "stvxl_v16qi", MEM)
15162
BU_ALTIVEC_C (STVLX, "stvlx", MEM)
15163
BU_ALTIVEC_C (STVLXL, "stvlxl", MEM)
15164
BU_ALTIVEC_C (STVRX, "stvrx", MEM)
15165
@@ -1012,7 +1193,7 @@
13748
15166
BU_VSX_1 (XVRESP, "xvresp", CONST, vsx_frev4sf2)
13749
15167
13750
15168
BU_VSX_1 (XSCVDPSP, "xscvdpsp", CONST, vsx_xscvdpsp)
13753
15171
BU_VSX_1 (XVCVDPSP, "xvcvdpsp", CONST, vsx_xvcvdpsp)
13754
15172
BU_VSX_1 (XVCVSPDP, "xvcvspdp", CONST, vsx_xvcvspdp)
13755
15173
BU_VSX_1 (XSTSQRTDP_FE, "xstsqrtdp_fe", CONST, vsx_tsqrtdf2_fe)
13756
@@ -1052,9 +1209,9 @@
15174
@@ -1052,9 +1233,9 @@
13757
15175
13758
15176
BU_VSX_1 (XSRDPI, "xsrdpi", CONST, vsx_xsrdpi)
13759
15177
BU_VSX_1 (XSRDPIC, "xsrdpic", CONST, vsx_xsrdpic)
13766
15184
13767
15185
/* VSX predicate functions. */
13768
15186
BU_VSX_P (XVCMPEQSP_P, "xvcmpeqsp_p", CONST, vector_eq_v4sf_p)
13769
@@ -1132,6 +1289,166 @@
15187
@@ -1132,6 +1313,166 @@
13770
15188
BU_VSX_OVERLOAD_X (LD, "ld")
13771
15189
BU_VSX_OVERLOAD_X (ST, "st")
13772
15190
13933
15351
/* 3 argument paired floating point builtins. */
13934
15352
BU_PAIRED_3 (MSUB, "msub", FP, fmsv2sf4)
13935
15353
BU_PAIRED_3 (MADD, "madd", FP, fmav2sf4)
13936
@@ -1430,10 +1747,10 @@
15354
@@ -1430,10 +1771,10 @@
13937
15355
RS6000_BTC_FP)
13938
15356
13939
15357
BU_SPECIAL_X (RS6000_BUILTIN_GET_TB, "__builtin_ppc_get_timebase",
14093
15511
{ ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP,
14094
15512
RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
14095
15513
{ ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP,
15514
@@ -1045,54 +1106,54 @@
15515
RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
15516
{ VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,
15517
RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
15518
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15519
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
15520
RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
15521
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15522
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
15523
RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
15524
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15525
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
15526
RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
15527
~RS6000_BTI_unsigned_V2DI, 0 },
15528
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15529
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
15530
RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
15531
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15532
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
15533
RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
15534
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15535
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
15536
RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
15537
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15538
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
15539
RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
15540
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15541
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
15542
RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
15543
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15544
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
15545
RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
15546
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15547
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
15548
RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
15549
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15550
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
15551
RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
15552
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15553
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
15554
RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
15555
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15556
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
15557
RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
15558
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15559
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
15560
RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
15561
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15562
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
15563
RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
15564
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15565
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
15566
RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
15567
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15568
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
15569
RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
15570
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15571
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
15572
RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
15573
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15574
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
15575
RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
15576
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15577
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
15578
RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
15579
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15580
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
15581
RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
15582
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15583
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
15584
RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
15585
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15586
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
15587
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
15588
- { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
15589
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
15590
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
15591
{ ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
15592
RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
15593
@@ -1130,55 +1191,55 @@
15594
RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
15595
{ ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
15596
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
15597
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15598
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
15599
RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
15600
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15601
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
15602
RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
15603
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15604
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
15605
RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
15606
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15607
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
15608
RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
15609
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15610
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
15611
RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
15612
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15613
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
15614
RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
15615
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15616
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
15617
RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
15618
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15619
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
15620
RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
15621
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15622
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
15623
RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
15624
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15625
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
15626
RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
15627
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15628
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
15629
RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
15630
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15631
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
15632
RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
15633
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15634
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
15635
RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
15636
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15637
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
15638
RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
15639
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15640
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
15641
RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
15642
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15643
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
15644
RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
15645
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15646
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
15647
RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
15648
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15649
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
15650
RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
15651
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15652
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
15653
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
15654
~RS6000_BTI_unsigned_V16QI, 0 },
15655
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15656
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
15657
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
15658
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15659
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
15660
RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
15661
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15662
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
15663
RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
15664
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15665
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
15666
RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
15667
~RS6000_BTI_unsigned_V2DI, 0 },
15668
- { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
15669
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
15670
RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
15671
{ ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
15672
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
14096
15673
@@ -1418,6 +1479,18 @@
14097
15674
RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
14098
15675
{ ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
14227
15804
{ ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP,
14228
15805
RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
14229
15806
{ ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP,
15807
@@ -2730,63 +2855,63 @@
15808
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE },
15809
{ ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
15810
RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE },
15811
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15812
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
15813
RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
15814
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15815
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
15816
RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
15817
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15818
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
15819
RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
15820
~RS6000_BTI_unsigned_V2DI },
15821
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15822
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
15823
RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
15824
~RS6000_BTI_bool_V2DI },
15825
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15826
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
15827
RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
15828
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15829
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
15830
RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
15831
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15832
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
15833
RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
15834
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15835
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
15836
RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
15837
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15838
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
15839
RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
15840
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15841
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
15842
RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
15843
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15844
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
15845
RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
15846
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15847
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
15848
RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
15849
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15850
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
15851
RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
15852
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15853
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
15854
RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
15855
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15856
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
15857
RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
15858
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15859
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
15860
RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
15861
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15862
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
15863
RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
15864
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15865
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
15866
RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
15867
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15868
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
15869
RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
15870
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15871
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
15872
RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
15873
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15874
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
15875
RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
15876
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15877
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
15878
RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
15879
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15880
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
15881
RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
15882
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15883
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
15884
RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
15885
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15886
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
15887
RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
15888
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15889
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
15890
RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
15891
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15892
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
15893
RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
15894
- { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
15895
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
15896
RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
15897
{ ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
15898
RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
15899
@@ -2858,64 +2983,64 @@
15900
RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
15901
{ ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
15902
RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
15903
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15904
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
15905
RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
15906
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15907
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
15908
RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
15909
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15910
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
15911
RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
15912
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15913
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
15914
RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
15915
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15916
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
15917
RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
15918
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15919
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
15920
RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
15921
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15922
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
15923
RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
15924
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15925
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
15926
RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
15927
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15928
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
15929
RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
15930
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15931
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
15932
RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
15933
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15934
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
15935
RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
15936
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15937
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
15938
RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
15939
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15940
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
15941
RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
15942
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15943
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
15944
RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
15945
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15946
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
15947
RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
15948
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15949
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
15950
RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
15951
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15952
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
15953
RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
15954
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15955
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
15956
RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
15957
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15958
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
15959
RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
15960
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15961
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
15962
RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
15963
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15964
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
15965
RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
15966
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15967
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
15968
RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
15969
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15970
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
15971
RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
15972
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15973
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
15974
RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
15975
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15976
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
15977
RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
15978
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15979
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
15980
RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
15981
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15982
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
15983
RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
15984
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15985
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
15986
RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
15987
~RS6000_BTI_unsigned_V2DI },
15988
- { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
15989
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
15990
RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
15991
~RS6000_BTI_bool_V2DI },
15992
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
14230
15993
@@ -3327,6 +3452,20 @@
14231
15994
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
14232
15995
{ ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
16923
18686
+
16924
18687
+ if (MEM_P (source))
16925
18688
+ {
16926
+ gcc_assert (REG_P (dest));
18689
+ gcc_assert (REG_P (dest) || GET_CODE (dest) == SUBREG);
16927
18690
+ rs6000_emit_le_vsx_load (dest, source, mode);
16928
18691
+ }
16929
18692
+ else
18246
20009
/* Return true if a builtin function is overloaded. */
18247
20010
bool
18248
20011
rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
18249
@@ -10352,7 +11901,198 @@
20012
@@ -10190,7 +11739,101 @@
20013
return target;
20014
}
20015
20016
+/* Return a constant vector for use as a little-endian permute control vector
20017
+ to reverse the order of elements of the given vector mode. */
20018
static rtx
20019
+swap_selector_for_mode (enum machine_mode mode)
20020
+{
20021
+ /* These are little endian vectors, so their elements are reversed
20022
+ from what you would normally expect for a permute control vector. */
20023
+ unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
20024
+ unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
20025
+ unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
20026
+ unsigned int swap16[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
20027
+ unsigned int *swaparray, i;
20028
+ rtx perm[16];
20029
+
20030
+ switch (mode)
20031
+ {
20032
+ case V2DFmode:
20033
+ case V2DImode:
20034
+ swaparray = swap2;
20035
+ break;
20036
+ case V4SFmode:
20037
+ case V4SImode:
20038
+ swaparray = swap4;
20039
+ break;
20040
+ case V8HImode:
20041
+ swaparray = swap8;
20042
+ break;
20043
+ case V16QImode:
20044
+ swaparray = swap16;
20045
+ break;
20046
+ default:
20047
+ gcc_unreachable ();
20048
+ }
20049
+
20050
+ for (i = 0; i < 16; ++i)
20051
+ perm[i] = GEN_INT (swaparray[i]);
20052
+
20053
+ return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)));
20054
+}
20055
+
20056
+/* Generate code for an "lvx", "lvxl", or "lve*x" built-in for a little endian target
20057
+ with -maltivec=be specified. Issue the load followed by an element-reversing
20058
+ permute. */
20059
+void
20060
+altivec_expand_lvx_be (rtx op0, rtx op1, enum machine_mode mode, unsigned unspec)
20061
+{
20062
+ rtx tmp = gen_reg_rtx (mode);
20063
+ rtx load = gen_rtx_SET (VOIDmode, tmp, op1);
20064
+ rtx lvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
20065
+ rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, load, lvx));
20066
+ rtx sel = swap_selector_for_mode (mode);
20067
+ rtx vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, tmp, tmp, sel), UNSPEC_VPERM);
20068
+
20069
+ gcc_assert (REG_P (op0));
20070
+ emit_insn (par);
20071
+ emit_insn (gen_rtx_SET (VOIDmode, op0, vperm));
20072
+}
20073
+
20074
+/* Generate code for a "stvx" or "stvxl" built-in for a little endian target
20075
+ with -maltivec=be specified. Issue the store preceded by an element-reversing
20076
+ permute. */
20077
+void
20078
+altivec_expand_stvx_be (rtx op0, rtx op1, enum machine_mode mode, unsigned unspec)
20079
+{
20080
+ rtx tmp = gen_reg_rtx (mode);
20081
+ rtx store = gen_rtx_SET (VOIDmode, op0, tmp);
20082
+ rtx stvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
20083
+ rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, store, stvx));
20084
+ rtx sel = swap_selector_for_mode (mode);
20085
+ rtx vperm;
20086
+
20087
+ gcc_assert (REG_P (op1));
20088
+ vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
20089
+ emit_insn (gen_rtx_SET (VOIDmode, tmp, vperm));
20090
+ emit_insn (par);
20091
+}
20092
+
20093
+/* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
20094
+ specified. Issue the store preceded by an element-reversing permute. */
20095
+void
20096
+altivec_expand_stvex_be (rtx op0, rtx op1, enum machine_mode mode, unsigned unspec)
20097
+{
20098
+ enum machine_mode inner_mode = GET_MODE_INNER (mode);
20099
+ rtx tmp = gen_reg_rtx (mode);
20100
+ rtx stvx = gen_rtx_UNSPEC (inner_mode, gen_rtvec (1, tmp), unspec);
20101
+ rtx sel = swap_selector_for_mode (mode);
20102
+ rtx vperm;
20103
+
20104
+ gcc_assert (REG_P (op1));
20105
+ vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
20106
+ emit_insn (gen_rtx_SET (VOIDmode, tmp, vperm));
20107
+ emit_insn (gen_rtx_SET (VOIDmode, op0, stvx));
20108
+}
20109
+
20110
+static rtx
20111
altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
20112
{
20113
rtx pat, addr;
20114
@@ -10352,7 +11995,198 @@
18250
20115
return NULL_RTX;
18251
20116
}
18252
20117
18445
20310
rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
18446
20311
{
18447
20312
rtx pat;
18448
@@ -10428,7 +12168,28 @@
20313
@@ -10428,7 +12262,28 @@
18449
20314
return const0_rtx;
18450
20315
}
18451
20316
}
18474
20339
if (target == 0
18475
20340
|| GET_MODE (target) != tmode
18476
20341
|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
18477
@@ -11412,6 +13173,8 @@
20342
@@ -10770,16 +12625,38 @@
20343
20344
switch (fcode)
20345
{
20346
+ case ALTIVEC_BUILTIN_STVX_V2DF:
20347
+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);
20348
+ case ALTIVEC_BUILTIN_STVX_V2DI:
20349
+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);
20350
+ case ALTIVEC_BUILTIN_STVX_V4SF:
20351
+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);
20352
case ALTIVEC_BUILTIN_STVX:
20353
+ case ALTIVEC_BUILTIN_STVX_V4SI:
20354
return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
20355
+ case ALTIVEC_BUILTIN_STVX_V8HI:
20356
+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);
20357
+ case ALTIVEC_BUILTIN_STVX_V16QI:
20358
+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);
20359
case ALTIVEC_BUILTIN_STVEBX:
20360
return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
20361
case ALTIVEC_BUILTIN_STVEHX:
20362
return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
20363
case ALTIVEC_BUILTIN_STVEWX:
20364
return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
20365
+ case ALTIVEC_BUILTIN_STVXL_V2DF:
20366
+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
20367
+ case ALTIVEC_BUILTIN_STVXL_V2DI:
20368
+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
20369
+ case ALTIVEC_BUILTIN_STVXL_V4SF:
20370
+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
20371
case ALTIVEC_BUILTIN_STVXL:
20372
- return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
20373
+ case ALTIVEC_BUILTIN_STVXL_V4SI:
20374
+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
20375
+ case ALTIVEC_BUILTIN_STVXL_V8HI:
20376
+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
20377
+ case ALTIVEC_BUILTIN_STVXL_V16QI:
20378
+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
20379
20380
case ALTIVEC_BUILTIN_STVLX:
20381
return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
20382
@@ -10923,12 +12800,44 @@
20383
case ALTIVEC_BUILTIN_LVEWX:
20384
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
20385
exp, target, false);
20386
+ case ALTIVEC_BUILTIN_LVXL_V2DF:
20387
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
20388
+ exp, target, false);
20389
+ case ALTIVEC_BUILTIN_LVXL_V2DI:
20390
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
20391
+ exp, target, false);
20392
+ case ALTIVEC_BUILTIN_LVXL_V4SF:
20393
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
20394
+ exp, target, false);
20395
case ALTIVEC_BUILTIN_LVXL:
20396
- return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
20397
+ case ALTIVEC_BUILTIN_LVXL_V4SI:
20398
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
20399
exp, target, false);
20400
+ case ALTIVEC_BUILTIN_LVXL_V8HI:
20401
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
20402
+ exp, target, false);
20403
+ case ALTIVEC_BUILTIN_LVXL_V16QI:
20404
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
20405
+ exp, target, false);
20406
+ case ALTIVEC_BUILTIN_LVX_V2DF:
20407
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,
20408
+ exp, target, false);
20409
+ case ALTIVEC_BUILTIN_LVX_V2DI:
20410
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,
20411
+ exp, target, false);
20412
+ case ALTIVEC_BUILTIN_LVX_V4SF:
20413
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,
20414
+ exp, target, false);
20415
case ALTIVEC_BUILTIN_LVX:
20416
+ case ALTIVEC_BUILTIN_LVX_V4SI:
20417
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
20418
exp, target, false);
20419
+ case ALTIVEC_BUILTIN_LVX_V8HI:
20420
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,
20421
+ exp, target, false);
20422
+ case ALTIVEC_BUILTIN_LVX_V16QI:
20423
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,
20424
+ exp, target, false);
20425
case ALTIVEC_BUILTIN_LVLX:
20426
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
20427
exp, target, true);
20428
@@ -11412,6 +13321,8 @@
18478
20429
error ("Builtin function %s is only valid for the cell processor", name);
18479
20430
else if ((fnmask & RS6000_BTM_VSX) != 0)
18480
20431
error ("Builtin function %s requires the -mvsx option", name);
18483
20434
else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
18484
20435
error ("Builtin function %s requires the -maltivec option", name);
18485
20436
else if ((fnmask & RS6000_BTM_PAIRED) != 0)
18486
@@ -11516,7 +13279,8 @@
20437
@@ -11516,7 +13427,8 @@
18487
20438
case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
18488
20439
case ALTIVEC_BUILTIN_MASK_FOR_STORE:
18489
20440
{
18493
20444
enum machine_mode tmode = insn_data[icode].operand[0].mode;
18494
20445
enum machine_mode mode = insn_data[icode].operand[1].mode;
18495
20446
tree arg;
18496
@@ -11591,7 +13355,14 @@
20447
@@ -11591,7 +13503,14 @@
18497
20448
if (success)
18498
20449
return ret;
18499
20450
}
18508
20459
gcc_assert (TARGET_ALTIVEC || TARGET_VSX || TARGET_SPE || TARGET_PAIRED_FLOAT);
18509
20460
18510
20461
/* Handle simple unary operations. */
18511
@@ -11773,6 +13544,9 @@
20462
@@ -11773,6 +13692,9 @@
18512
20463
spe_init_builtins ();
18513
20464
if (TARGET_EXTRA_BUILTINS)
18514
20465
altivec_init_builtins ();
18518
20469
if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT)
18519
20470
rs6000_common_init_builtins ();
18520
20471
18521
@@ -12118,6 +13892,10 @@
20472
@@ -12118,6 +14040,10 @@
18522
20473
= build_function_type_list (integer_type_node,
18523
20474
integer_type_node, V4SI_type_node,
18524
20475
V4SI_type_node, NULL_TREE);
18529
20480
tree void_ftype_v4si
18530
20481
= build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
18531
20482
tree v8hi_ftype_void
18532
@@ -12200,6 +13978,8 @@
20483
@@ -12200,6 +14126,8 @@
18533
20484
= build_function_type_list (integer_type_node,
18534
20485
integer_type_node, V2DF_type_node,
18535
20486
V2DF_type_node, NULL_TREE);
18538
20489
tree v4si_ftype_v4si
18539
20490
= build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
18540
20491
tree v8hi_ftype_v8hi
18541
@@ -12335,6 +14115,9 @@
20492
@@ -12225,10 +14153,58 @@
20493
def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
20494
def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
20495
def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
20496
+ def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
20497
+ ALTIVEC_BUILTIN_LVXL_V2DF);
20498
+ def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
20499
+ ALTIVEC_BUILTIN_LVXL_V2DI);
20500
+ def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
20501
+ ALTIVEC_BUILTIN_LVXL_V4SF);
20502
+ def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
20503
+ ALTIVEC_BUILTIN_LVXL_V4SI);
20504
+ def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
20505
+ ALTIVEC_BUILTIN_LVXL_V8HI);
20506
+ def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
20507
+ ALTIVEC_BUILTIN_LVXL_V16QI);
20508
def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
20509
+ def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
20510
+ ALTIVEC_BUILTIN_LVX_V2DF);
20511
+ def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
20512
+ ALTIVEC_BUILTIN_LVX_V2DI);
20513
+ def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
20514
+ ALTIVEC_BUILTIN_LVX_V4SF);
20515
+ def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
20516
+ ALTIVEC_BUILTIN_LVX_V4SI);
20517
+ def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
20518
+ ALTIVEC_BUILTIN_LVX_V8HI);
20519
+ def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
20520
+ ALTIVEC_BUILTIN_LVX_V16QI);
20521
def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
20522
+ def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
20523
+ ALTIVEC_BUILTIN_STVX_V2DF);
20524
+ def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
20525
+ ALTIVEC_BUILTIN_STVX_V2DI);
20526
+ def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
20527
+ ALTIVEC_BUILTIN_STVX_V4SF);
20528
+ def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
20529
+ ALTIVEC_BUILTIN_STVX_V4SI);
20530
+ def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
20531
+ ALTIVEC_BUILTIN_STVX_V8HI);
20532
+ def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
20533
+ ALTIVEC_BUILTIN_STVX_V16QI);
20534
def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
20535
def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
20536
+ def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
20537
+ ALTIVEC_BUILTIN_STVXL_V2DF);
20538
+ def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
20539
+ ALTIVEC_BUILTIN_STVXL_V2DI);
20540
+ def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
20541
+ ALTIVEC_BUILTIN_STVXL_V4SF);
20542
+ def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
20543
+ ALTIVEC_BUILTIN_STVXL_V4SI);
20544
+ def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
20545
+ ALTIVEC_BUILTIN_STVXL_V8HI);
20546
+ def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
20547
+ ALTIVEC_BUILTIN_STVXL_V16QI);
20548
def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
20549
def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
20550
def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
20551
@@ -12335,6 +14311,9 @@
18542
20552
case VOIDmode:
18543
20553
type = int_ftype_int_opaque_opaque;
18544
20554
break;
18548
20558
case V4SImode:
18549
20559
type = int_ftype_int_v4si_v4si;
18550
20560
break;
18551
@@ -12368,6 +14151,9 @@
20561
@@ -12368,6 +14347,9 @@
18552
20562
18553
20563
switch (mode0)
18554
20564
{
18558
20568
case V4SImode:
18559
20569
type = v4si_ftype_v4si;
18560
20570
break;
18561
@@ -12500,6 +14286,79 @@
20571
@@ -12500,6 +14482,79 @@
18562
20572
def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
18563
20573
}
18564
20574
18638
20648
/* Hash function for builtin functions with up to 3 arguments and a return
18639
20649
type. */
18640
20650
static unsigned
18641
@@ -12573,11 +14432,27 @@
20651
@@ -12573,11 +14628,27 @@
18642
20652
are type correct. */
18643
20653
switch (builtin)
18644
20654
{
18666
20676
h.uns_p[0] = 1;
18667
20677
h.uns_p[1] = 1;
18668
20678
h.uns_p[2] = 1;
18669
@@ -12600,6 +14475,14 @@
20679
@@ -12600,6 +14671,14 @@
18670
20680
case VSX_BUILTIN_XXSEL_8HI_UNS:
18671
20681
case VSX_BUILTIN_XXSEL_4SI_UNS:
18672
20682
case VSX_BUILTIN_XXSEL_2DI_UNS:
18681
20691
h.uns_p[0] = 1;
18682
20692
h.uns_p[1] = 1;
18683
20693
h.uns_p[2] = 1;
18684
@@ -12741,9 +14624,24 @@
20694
@@ -12741,9 +14820,24 @@
18685
20695
else
18686
20696
{
18687
20697
enum insn_code icode = d->icode;
18708
20718
type = builtin_function_type (insn_data[icode].operand[0].mode,
18709
20719
insn_data[icode].operand[1].mode,
18710
20720
insn_data[icode].operand[2].mode,
18711
@@ -12781,9 +14679,24 @@
20721
@@ -12781,9 +14875,24 @@
18712
20722
else
18713
20723
{
18714
20724
enum insn_code icode = d->icode;
18735
20745
mode0 = insn_data[icode].operand[0].mode;
18736
20746
mode1 = insn_data[icode].operand[1].mode;
18737
20747
mode2 = insn_data[icode].operand[2].mode;
18738
@@ -12843,9 +14756,24 @@
20748
@@ -12843,9 +14952,24 @@
18739
20749
else
18740
20750
{
18741
20751
enum insn_code icode = d->icode;
18762
20772
mode0 = insn_data[icode].operand[0].mode;
18763
20773
mode1 = insn_data[icode].operand[1].mode;
18764
20774
18765
@@ -13632,7 +15560,7 @@
20775
@@ -13632,7 +15756,7 @@
18766
20776
static bool eliminated = false;
18767
20777
rtx ret;
18768
20778
18771
20781
ret = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
18772
20782
else
18773
20783
{
18774
@@ -13661,6 +15589,17 @@
20784
@@ -13661,6 +15785,17 @@
18775
20785
return ret;
18776
20786
}
18777
20787
18789
20799
static tree
18790
20800
rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)
18791
20801
{
18792
@@ -13691,31 +15630,228 @@
20802
@@ -13691,31 +15826,228 @@
18793
20803
return NULL_TREE;
18794
20804
}
18795
20805
19035
21045
/* Inform reload about cases where moving X with a mode MODE to a register in
19036
21046
RCLASS requires an extra scratch or immediate register. Return the class
19037
21047
needed for the immediate register.
19038
@@ -13739,12 +15875,36 @@
21048
@@ -13739,12 +16071,36 @@
19039
21049
bool default_p = false;
19040
21050
19041
21051
sri->icode = CODE_FOR_nothing;
19076
21086
ret = NO_REGS;
19077
21087
sri->icode = CODE_FOR_nothing;
19078
21088
sri->extra_cost = 0;
19079
@@ -13755,22 +15915,43 @@
21089
@@ -13755,22 +16111,43 @@
19080
21090
19081
21091
/* Loads to and stores from gprs can do reg+offset, and wouldn't need
19082
21092
an extra register in that case, but it would need an extra
19126
21136
else if (rclass == VSX_REGS || rclass == ALTIVEC_REGS
19127
21137
|| rclass == FLOAT_REGS || rclass == NO_REGS)
19128
21138
{
19129
@@ -13814,12 +15995,12 @@
21139
@@ -13814,12 +16191,12 @@
19130
21140
else
19131
21141
{
19132
21142
enum reg_class xclass = REGNO_REG_CLASS (regno);
19142
21152
default_p = true;
19143
21153
else
19144
21154
ret = NO_REGS;
19145
@@ -13829,7 +16010,7 @@
21155
@@ -13829,7 +16206,7 @@
19146
21156
default_p = true;
19147
21157
}
19148
21158
else if (TARGET_POWERPC64
19151
21161
&& MEM_P (x)
19152
21162
&& GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
19153
21163
{
19154
@@ -13868,7 +16049,7 @@
21164
@@ -13868,7 +16245,7 @@
19155
21165
default_p = true;
19156
21166
}
19157
21167
else if (!TARGET_POWERPC64
19160
21170
&& MEM_P (x)
19161
21171
&& GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
19162
21172
{
19163
@@ -13946,6 +16127,36 @@
21173
@@ -13946,6 +16323,36 @@
19164
21174
return ret;
19165
21175
}
19166
21176
19197
21207
/* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
19198
21208
to SP+reg addressing. */
19199
21209
19200
@@ -13964,19 +16175,14 @@
21210
@@ -13964,19 +16371,14 @@
19201
21211
rtx cc_clobber;
19202
21212
19203
21213
if (TARGET_DEBUG_ADDR)
19224
21234
rclass = REGNO_REG_CLASS (regno);
19225
21235
addr = XEXP (mem, 0);
19226
21236
19227
@@ -13995,19 +16201,24 @@
21237
@@ -13995,19 +16397,24 @@
19228
21238
if (GET_CODE (addr) == PRE_MODIFY)
19229
21239
{
19230
21240
scratch_or_premodify = XEXP (addr, 0);
19253
21263
19254
21264
if (!REG_P (addr_op2)
19255
21265
&& (GET_CODE (addr_op2) != CONST_INT
19256
@@ -14035,7 +16246,7 @@
21266
@@ -14035,7 +16442,7 @@
19257
21267
scratch_or_premodify = scratch;
19258
21268
}
19259
21269
else if (!legitimate_indirect_address_p (addr, false)
19262
21272
false, true))
19263
21273
{
19264
21274
if (TARGET_DEBUG_ADDR)
19265
@@ -14051,9 +16262,21 @@
21275
@@ -14051,9 +16458,21 @@
19266
21276
}
19267
21277
break;
19268
21278
19286
21296
case VSX_REGS:
19287
21297
case ALTIVEC_REGS:
19288
21298
19289
@@ -14073,36 +16296,38 @@
21299
@@ -14073,36 +16492,38 @@
19290
21300
/* If we aren't using a VSX load, save the PRE_MODIFY register and use it
19291
21301
as the address later. */
19292
21302
if (GET_CODE (addr) == PRE_MODIFY
19337
21347
19338
21348
if (TARGET_DEBUG_ADDR)
19339
21349
{
19340
@@ -14121,7 +16346,8 @@
21350
@@ -14121,7 +16542,8 @@
19341
21351
}
19342
21352
19343
21353
else if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == CONST
19347
21357
{
19348
21358
if (TARGET_DEBUG_ADDR)
19349
21359
{
19350
@@ -14137,12 +16363,12 @@
21360
@@ -14137,12 +16559,12 @@
19351
21361
}
19352
21362
19353
21363
else
19362
21372
}
19363
21373
19364
21374
/* If the original address involved a pre-modify that we couldn't use the VSX
19365
@@ -14189,7 +16415,7 @@
21375
@@ -14189,7 +16611,7 @@
19366
21376
/* Adjust the address if it changed. */
19367
21377
if (addr != XEXP (mem, 0))
19368
21378
{
19371
21381
if (TARGET_DEBUG_ADDR)
19372
21382
fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
19373
21383
}
19374
@@ -14254,8 +16480,10 @@
21384
@@ -14254,8 +16676,10 @@
19375
21385
return;
19376
21386
}
19377
21387
19384
21394
19385
21395
static void
19386
21396
rs6000_alloc_sdmode_stack_slot (void)
19387
@@ -14265,7 +16493,14 @@
21397
@@ -14265,7 +16689,14 @@
19388
21398
gimple_stmt_iterator gsi;
19389
21399
19390
21400
gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX);
19399
21409
FOR_EACH_BB (bb)
19400
21410
for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
19401
21411
{
19402
@@ -14326,8 +16561,7 @@
21412
@@ -14326,8 +16757,7 @@
19403
21413
{
19404
21414
enum machine_mode mode = GET_MODE (x);
19405
21415
19409
21419
return rclass;
19410
21420
19411
21421
if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
19412
@@ -14382,60 +16616,45 @@
21422
@@ -14382,60 +16812,45 @@
19413
21423
set and vice versa. */
19414
21424
19415
21425
static bool
19493
21503
19494
21504
return ret;
19495
21505
}
19496
@@ -14499,15 +16718,21 @@
21506
@@ -14499,15 +16914,21 @@
19497
21507
/* Constants, memory, and FP registers can go into FP registers. */
19498
21508
if ((regno == -1 || FP_REGNO_P (regno))
19499
21509
&& (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
19518
21528
/* Memory, and AltiVec registers can go into AltiVec registers. */
19519
21529
if ((regno == -1 || ALTIVEC_REGNO_P (regno))
19520
21530
&& rclass == ALTIVEC_REGS)
19521
@@ -14551,8 +16776,42 @@
21531
@@ -14551,8 +16972,42 @@
19522
21532
if (from_size != to_size)
19523
21533
{
19524
21534
enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
19563
21573
}
19564
21574
19565
21575
if (TARGET_E500_DOUBLE
19566
@@ -14566,10 +16825,19 @@
21576
@@ -14566,10 +17021,19 @@
19567
21577
/* Since the VSX register set includes traditional floating point registers
19568
21578
and altivec registers, just check for the size being different instead of
19569
21579
trying to check whether the modes are vector modes. Otherwise it won't
19585
21595
if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
19586
21596
&& (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
19587
21597
return true;
19588
@@ -14599,6 +16867,161 @@
21598
@@ -14599,6 +17063,161 @@
19589
21599
return ret;
19590
21600
}
19591
21601
19747
21757
/* Given a comparison operation, return the bit number in CCR to test. We
19748
21758
know this is a valid comparison.
19749
21759
19750
@@ -14824,6 +17247,7 @@
21760
@@ -14824,6 +17443,7 @@
19751
21761
ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
19752
21762
break;
19753
21763
19755
21765
case ABI_V4:
19756
21766
case ABI_DARWIN:
19757
21767
break;
19758
@@ -15303,7 +17727,7 @@
21768
@@ -15303,7 +17923,7 @@
19759
21769
return;
19760
21770
19761
21771
case 'Y':
19764
21774
if (REG_P (x))
19765
21775
fputs (reg_names[REGNO (x) + 2], file);
19766
21776
else if (MEM_P (x))
19767
@@ -15353,7 +17777,7 @@
21777
@@ -15353,7 +17973,7 @@
19768
21778
return;
19769
21779
19770
21780
case 'Z':
19773
21783
if (REG_P (x))
19774
21784
fputs (reg_names[REGNO (x) + 3], file);
19775
21785
else if (MEM_P (x))
19776
@@ -15384,7 +17808,8 @@
21786
@@ -15384,7 +18004,8 @@
19777
21787
if ((TARGET_SPE || TARGET_E500_DOUBLE)
19778
21788
&& (GET_MODE_SIZE (GET_MODE (x)) == 8
19779
21789
|| GET_MODE (x) == TFmode
19783
21793
{
19784
21794
/* Handle [reg]. */
19785
21795
if (REG_P (tmp))
19786
@@ -16767,7 +19192,8 @@
21796
@@ -16767,7 +19388,8 @@
19787
21797
}
19788
21798
19789
21799
/* A subroutine of the atomic operation splitters. Emit a load-locked
19793
21803
19794
21804
static void
19795
21805
emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
19796
@@ -16776,12 +19202,26 @@
21806
@@ -16776,12 +19398,26 @@
19797
21807
19798
21808
switch (mode)
19799
21809
{
19821
21831
default:
19822
21832
gcc_unreachable ();
19823
21833
}
19824
@@ -16798,12 +19238,21 @@
21834
@@ -16798,12 +19434,21 @@
19825
21835
19826
21836
switch (mode)
19827
21837
{
19843
21853
default:
19844
21854
gcc_unreachable ();
19845
21855
}
19846
@@ -16950,7 +19399,7 @@
21856
@@ -16950,7 +19595,7 @@
19847
21857
{
19848
21858
rtx boolval, retval, mem, oldval, newval, cond;
19849
21859
rtx label1, label2, x, mask, shift;
19852
21862
enum memmodel mod_s, mod_f;
19853
21863
bool is_weak;
19854
21864
19855
@@ -16962,23 +19411,30 @@
21865
@@ -16962,23 +19607,30 @@
19856
21866
is_weak = (INTVAL (operands[5]) != 0);
19857
21867
mod_s = (enum memmodel) INTVAL (operands[6]);
19858
21868
mod_f = (enum memmodel) INTVAL (operands[7]);
19893
21903
/* Prepare to adjust the return value. */
19894
21904
retval = gen_reg_rtx (SImode);
19895
21905
mode = SImode;
19896
@@ -17006,7 +19462,25 @@
21906
@@ -17006,7 +19658,25 @@
19897
21907
}
19898
21908
19899
21909
cond = gen_reg_rtx (CCmode);
19920
21930
emit_insn (gen_rtx_SET (VOIDmode, cond, x));
19921
21931
19922
21932
x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
19923
@@ -17016,7 +19490,7 @@
21933
@@ -17016,7 +19686,7 @@
19924
21934
if (mask)
19925
21935
x = rs6000_mask_atomic_subword (retval, newval, mask);
19926
21936
19929
21939
19930
21940
if (!is_weak)
19931
21941
{
19932
@@ -17034,6 +19508,8 @@
21942
@@ -17034,6 +19704,8 @@
19933
21943
19934
21944
if (shift)
19935
21945
rs6000_finish_atomic_subword (operands[1], retval, shift);
19938
21948
19939
21949
/* In all cases, CR0 contains EQ on success, and NE on failure. */
19940
21950
x = gen_rtx_EQ (SImode, cond, const0_rtx);
19941
@@ -17057,7 +19533,7 @@
21951
@@ -17057,7 +19729,7 @@
19942
21952
mode = GET_MODE (mem);
19943
21953
19944
21954
mask = shift = NULL_RTX;
19947
21957
{
19948
21958
mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
19949
21959
19950
@@ -17106,53 +19582,70 @@
21960
@@ -17106,53 +19778,70 @@
19951
21961
{
19952
21962
enum memmodel model = (enum memmodel) INTVAL (model_rtx);
19953
21963
enum machine_mode mode = GET_MODE (mem);
20053
22063
}
20054
22064
20055
22065
mem = rs6000_pre_atomic_barrier (mem, model);
20056
@@ -17185,9 +19678,11 @@
22066
@@ -17185,9 +19874,11 @@
20057
22067
NULL_RTX, 1, OPTAB_LIB_WIDEN);
20058
22068
x = rs6000_mask_atomic_subword (before, x, mask);
20059
22069
}
20066
22076
20067
22077
x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
20068
22078
emit_unlikely_jump (x, label);
20069
@@ -17196,11 +19691,22 @@
22079
@@ -17196,11 +19887,22 @@
20070
22080
20071
22081
if (shift)
20072
22082
{
20089
22099
else if (orig_after && after != orig_after)
20090
22100
emit_move_insn (orig_after, after);
20091
22101
}
20092
@@ -17240,6 +19746,39 @@
22102
@@ -17240,6 +19942,39 @@
20093
22103
20094
22104
gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
20095
22105
20129
22139
if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
20130
22140
{
20131
22141
/* Move register range backwards, if we might have destructive
20132
@@ -17694,7 +20233,7 @@
22142
@@ -17694,7 +20429,7 @@
20133
22143
}
20134
22144
else
20135
22145
{
20138
22148
if (info->first_fp_reg_save > 61)
20139
22149
strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
20140
22150
strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
20141
@@ -17705,7 +20244,8 @@
22151
@@ -17705,7 +20440,8 @@
20142
22152
by the static chain. It would require too much fiddling and the
20143
22153
static chain is rarely used anyway. FPRs are saved w.r.t the stack
20144
22154
pointer on Darwin, and AIX uses r1 or r12. */
20148
22158
strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
20149
22159
| SAVE_INLINE_GPRS
20150
22160
| SAVE_INLINE_VRS | REST_INLINE_VRS);
20151
@@ -17838,7 +20378,35 @@
22161
@@ -17838,7 +20574,35 @@
20152
22162
The required alignment for AIX configurations is two words (i.e., 8
20153
22163
or 16 bytes).
20154
22164
20184
22194
V.4 stack frames look like:
20185
22195
20186
22196
SP----> +---------------------------------------+
20187
@@ -17898,6 +20466,7 @@
22197
@@ -17898,6 +20662,7 @@
20188
22198
rs6000_stack_t *info_ptr = &stack_info;
20189
22199
int reg_size = TARGET_32BIT ? 4 : 8;
20190
22200
int ehrd_size;
20192
22202
int save_align;
20193
22203
int first_gp;
20194
22204
HOST_WIDE_INT non_fixed_size;
20195
@@ -17991,6 +20560,18 @@
22205
@@ -17991,6 +20756,18 @@
20196
22206
else
20197
22207
ehrd_size = 0;
20198
22208
20211
22221
/* Determine various sizes. */
20212
22222
info_ptr->reg_size = reg_size;
20213
22223
info_ptr->fixed_size = RS6000_SAVE_AREA;
20214
@@ -18030,6 +20611,7 @@
22224
@@ -18030,6 +20807,7 @@
20215
22225
gcc_unreachable ();
20216
22226
20217
22227
case ABI_AIX:
20219
22229
case ABI_DARWIN:
20220
22230
info_ptr->fp_save_offset = - info_ptr->fp_size;
20221
22231
info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
20222
@@ -18059,6 +20641,8 @@
22232
@@ -18059,6 +20837,8 @@
20223
22233
}
20224
22234
else
20225
22235
info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
20228
22238
info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
20229
22239
info_ptr->lr_save_offset = 2*reg_size;
20230
22240
break;
20231
@@ -18121,6 +20705,7 @@
22241
@@ -18121,6 +20901,7 @@
20232
22242
+ info_ptr->spe_gp_size
20233
22243
+ info_ptr->spe_padding_size
20234
22244
+ ehrd_size
20236
22246
+ info_ptr->cr_size
20237
22247
+ info_ptr->vrsave_size,
20238
22248
save_align);
20239
@@ -18134,7 +20719,7 @@
22249
@@ -18134,7 +20915,7 @@
20240
22250
20241
22251
/* Determine if we need to save the link register. */
20242
22252
if (info_ptr->calls_p
20245
22255
&& crtl->profile
20246
22256
&& !TARGET_PROFILE_KERNEL)
20247
22257
|| (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
20248
@@ -18280,6 +20865,7 @@
22258
@@ -18280,6 +21061,7 @@
20249
22259
default: abi_string = "Unknown"; break;
20250
22260
case ABI_NONE: abi_string = "NONE"; break;
20251
22261
case ABI_AIX: abi_string = "AIX"; break;
20253
22263
case ABI_DARWIN: abi_string = "Darwin"; break;
20254
22264
case ABI_V4: abi_string = "V.4"; break;
20255
22265
}
20256
@@ -18401,7 +20987,8 @@
22266
@@ -18401,7 +21183,8 @@
20257
22267
/* Currently we don't optimize very well between prolog and body
20258
22268
code and for PIC code the code can be actually quite bad, so
20259
22269
don't try to be too clever here. */
20263
22273
{
20264
22274
cfun->machine->ra_needs_full_frame = 1;
20265
22275
20266
@@ -18460,13 +21047,13 @@
22276
@@ -18460,13 +21243,13 @@
20267
22277
return false;
20268
22278
}
20269
22279
20282
22292
&& decl
20283
22293
&& !DECL_EXTERNAL (decl)
20284
22294
&& (*targetm.binds_local_p) (decl))
20285
@@ -18567,7 +21154,7 @@
22295
@@ -18567,7 +21350,7 @@
20286
22296
rtx dest;
20287
22297
dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
20288
22298
20291
22301
{
20292
22302
char buf[30];
20293
22303
rtx lab, tmp1, tmp2, got;
20294
@@ -18595,7 +21182,7 @@
22304
@@ -18595,7 +21378,7 @@
20295
22305
emit_insn (gen_load_toc_v4_pic_si ());
20296
22306
emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
20297
22307
}
20300
22310
{
20301
22311
char buf[30];
20302
22312
rtx temp0 = (fromprolog
20303
@@ -18643,7 +21230,7 @@
22313
@@ -18643,7 +21426,7 @@
20304
22314
}
20305
22315
else
20306
22316
{
20309
22319
20310
22320
if (TARGET_32BIT)
20311
22321
emit_insn (gen_load_toc_aix_si (dest));
20312
@@ -19048,7 +21635,7 @@
22322
@@ -19048,7 +21831,7 @@
20313
22323
20314
22324
static rtx
20315
22325
rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
20318
22328
{
20319
22329
rtx real, temp;
20320
22330
20321
@@ -19139,6 +21726,11 @@
22331
@@ -19139,6 +21922,11 @@
20322
22332
}
20323
22333
}
20324
22334
20330
22340
RTX_FRAME_RELATED_P (insn) = 1;
20331
22341
add_reg_note (insn, REG_FRAME_RELATED_EXPR, real);
20332
22342
20333
@@ -19246,7 +21838,7 @@
22343
@@ -19246,7 +22034,7 @@
20334
22344
reg = gen_rtx_REG (mode, regno);
20335
22345
insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
20336
22346
return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
20339
22349
}
20340
22350
20341
22351
/* Emit an offset memory reference suitable for a frame store, while
20342
@@ -19362,7 +21954,7 @@
22352
@@ -19362,7 +22150,7 @@
20343
22353
if ((sel & SAVRES_LR))
20344
22354
suffix = "_x";
20345
22355
}
20348
22358
{
20349
22359
#if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
20350
22360
/* No out-of-line save/restore routines for GPRs on AIX. */
20351
@@ -19503,7 +22095,7 @@
22361
@@ -19503,7 +22291,7 @@
20352
22362
static inline unsigned
20353
22363
ptr_regno_for_savres (int sel)
20354
22364
{
20357
22367
return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
20358
22368
return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
20359
22369
}
20360
@@ -19588,6 +22180,43 @@
22370
@@ -19588,6 +22376,43 @@
20361
22371
return insn;
20362
22372
}
20363
22373
20401
22411
/* Determine whether the gp REG is really used. */
20402
22412
20403
22413
static bool
20404
@@ -19653,6 +22282,17 @@
22414
@@ -19653,6 +22478,17 @@
20405
22415
#define NOT_INUSE(R) do {} while (0)
20406
22416
#endif
20407
22417
20419
22429
if (flag_stack_usage_info)
20420
22430
current_function_static_stack_size = info->total_size;
20421
22431
20422
@@ -19767,7 +22407,7 @@
22432
@@ -19767,7 +22603,7 @@
20423
22433
20424
22434
insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
20425
22435
rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
20428
22438
sp_off = frame_off = info->total_size;
20429
22439
}
20430
22440
20431
@@ -19852,14 +22492,14 @@
22441
@@ -19852,14 +22688,14 @@
20432
22442
20433
22443
insn = emit_move_insn (mem, reg);
20434
22444
rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
20445
22455
&& !(strategy & (SAVE_INLINE_GPRS
20446
22456
| SAVE_NOINLINE_GPRS_SAVES_LR))
20447
22457
? 11 : 12);
20448
@@ -19868,21 +22508,9 @@
22458
@@ -19868,21 +22704,9 @@
20449
22459
&& REGNO (frame_reg_rtx) != cr_save_regno
20450
22460
&& !(using_static_chain_p && cr_save_regno == 11))
20451
22461
{
20468
22478
}
20469
22479
20470
22480
/* Do any required saving of fpr's. If only one or two to save, do
20471
@@ -19920,7 +22548,7 @@
22481
@@ -19920,7 +22744,7 @@
20472
22482
info->lr_save_offset,
20473
22483
DFmode, sel);
20474
22484
rs6000_frame_related (insn, ptr_reg, sp_off,
20477
22487
if (lr)
20478
22488
END_USE (0);
20479
22489
}
20480
@@ -19999,7 +22627,7 @@
22490
@@ -19999,7 +22823,7 @@
20481
22491
SAVRES_SAVE | SAVRES_GPR);
20482
22492
20483
22493
rs6000_frame_related (insn, spe_save_area_ptr, sp_off - save_off,
20486
22496
}
20487
22497
20488
22498
/* Move the static chain pointer back. */
20489
@@ -20049,7 +22677,7 @@
22499
@@ -20049,7 +22873,7 @@
20490
22500
info->lr_save_offset + ptr_off,
20491
22501
reg_mode, sel);
20492
22502
rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
20495
22505
if (lr)
20496
22506
END_USE (0);
20497
22507
}
20498
@@ -20065,7 +22693,7 @@
22508
@@ -20065,7 +22889,7 @@
20499
22509
info->gp_save_offset + frame_off + reg_size * i);
20500
22510
insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
20501
22511
rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
20504
22514
}
20505
22515
else if (!WORLD_SAVE_P (info))
20506
22516
{
20507
@@ -20134,7 +22762,8 @@
22517
@@ -20134,7 +22958,8 @@
20508
22518
be updated if we arrived at this function via a plt call or
20509
22519
toc adjusting stub. */
20510
22520
emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
20514
22524
hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
20515
22525
emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
20516
22526
compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
20517
@@ -20153,7 +22782,7 @@
22527
@@ -20153,7 +22978,7 @@
20518
22528
LABEL_NUSES (toc_save_done) += 1;
20519
22529
20520
22530
save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
20523
22533
sp_off - frame_off);
20524
22534
20525
22535
emit_label (toc_save_done);
20526
@@ -20193,28 +22822,123 @@
22536
@@ -20193,28 +23018,123 @@
20527
22537
rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20528
22538
GEN_INT (info->cr_save_offset + frame_off));
20529
22539
rtx mem = gen_frame_mem (SImode, addr);
20658
22668
/* Update stack and set back pointer unless this is V.4,
20659
22669
for which it was done previously. */
20660
22670
if (!WORLD_SAVE_P (info) && info->push_p
20661
@@ -20292,7 +23016,7 @@
22671
@@ -20292,7 +23212,7 @@
20662
22672
info->altivec_save_offset + ptr_off,
20663
22673
0, V4SImode, SAVRES_SAVE | SAVRES_VR);
20664
22674
rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
20667
22677
if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
20668
22678
{
20669
22679
/* The oddity mentioned above clobbered our frame reg. */
20670
@@ -20308,7 +23032,7 @@
22680
@@ -20308,7 +23228,7 @@
20671
22681
for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20672
22682
if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
20673
22683
{
20676
22686
int offset;
20677
22687
20678
22688
offset = (info->altivec_save_offset + frame_off
20679
@@ -20326,8 +23050,18 @@
22689
@@ -20326,8 +23246,18 @@
20680
22690
20681
22691
insn = emit_move_insn (mem, savereg);
20682
22692
20696
22706
}
20697
22707
}
20698
22708
20699
@@ -20351,7 +23085,8 @@
22709
@@ -20351,7 +23281,8 @@
20700
22710
be using r12 as frame_reg_rtx and r11 as the static chain
20701
22711
pointer for nested functions. */
20702
22712
save_regno = 12;
20706
22716
save_regno = 11;
20707
22717
else if (REGNO (frame_reg_rtx) == 12)
20708
22718
{
20709
@@ -20390,7 +23125,7 @@
22719
@@ -20390,7 +23321,7 @@
20710
22720
can use register 0. This allows us to use a plain 'blr' to return
20711
22721
from the procedure more often. */
20712
22722
int save_LR_around_toc_setup = (TARGET_ELF
20715
22725
&& flag_pic
20716
22726
&& ! info->lr_save_p
20717
22727
&& EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
20718
@@ -20452,7 +23187,7 @@
22728
@@ -20452,7 +23383,7 @@
20719
22729
if (rs6000_save_toc_in_prologue_p ())
20720
22730
{
20721
22731
rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
20724
22734
}
20725
22735
}
20726
22736
20727
@@ -20493,6 +23228,49 @@
22737
@@ -20493,6 +23424,49 @@
20728
22738
}
20729
22739
}
20730
22740
20774
22784
rs6000_pic_labelno++;
20775
22785
}
20776
22786
20777
@@ -20545,6 +23323,7 @@
22787
@@ -20545,6 +23519,7 @@
20778
22788
20779
22789
if (using_mfcr_multiple && count > 1)
20780
22790
{
20782
22792
rtvec p;
20783
22793
int ndx;
20784
22794
20785
@@ -20562,16 +23341,43 @@
22795
@@ -20562,16 +23537,43 @@
20786
22796
gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
20787
22797
ndx++;
20788
22798
}
20830
22840
{
20831
22841
rtx insn = get_last_insn ();
20832
22842
rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
20833
@@ -20612,10 +23418,22 @@
22843
@@ -20612,10 +23614,22 @@
20834
22844
static rtx
20835
22845
add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
20836
22846
{
20854
22864
if (info->lr_save_p)
20855
22865
cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20856
22866
gen_rtx_REG (Pmode, LR_REGNO),
20857
@@ -21113,6 +23931,35 @@
22867
@@ -21113,6 +24127,35 @@
20858
22868
|| (!restoring_GPRs_inline
20859
22869
&& info->first_fp_reg_save == 64));
20860
22870
20890
22900
/* Get the old lr if we saved it. If we are restoring registers
20891
22901
out-of-line, then the out-of-line routines can do this for us. */
20892
22902
if (restore_lr && restoring_GPRs_inline)
20893
@@ -21156,7 +24003,7 @@
22903
@@ -21156,7 +24199,7 @@
20894
22904
{
20895
22905
rtx reg = gen_rtx_REG (reg_mode, 2);
20896
22906
emit_insn (gen_frame_load (reg, frame_reg_rtx,
20899
22909
}
20900
22910
20901
22911
for (i = 0; ; ++i)
20902
@@ -21442,6 +24289,7 @@
22912
@@ -21442,6 +24485,7 @@
20903
22913
if (! restoring_FPRs_inline)
20904
22914
{
20905
22915
int i;
20907
22917
rtx sym;
20908
22918
20909
22919
if (flag_shrink_wrap)
20910
@@ -21450,10 +24298,9 @@
22920
@@ -21450,10 +24494,9 @@
20911
22921
sym = rs6000_savres_routine_sym (info,
20912
22922
SAVRES_FPR | (lr ? SAVRES_LR : 0));
20913
22923
RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym);
20921
22931
for (i = 0; i < 64 - info->first_fp_reg_save; i++)
20922
22932
{
20923
22933
rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
20924
@@ -21531,7 +24378,8 @@
22934
@@ -21531,7 +24574,8 @@
20925
22935
20926
22936
System V.4 Powerpc's (and the embedded ABI derived from it) use a
20927
22937
different traceback table. */
20931
22941
&& rs6000_traceback != traceback_none && !cfun->is_thunk)
20932
22942
{
20933
22943
const char *fname = NULL;
20934
@@ -21859,6 +24707,12 @@
22944
@@ -21859,6 +24903,12 @@
20935
22945
SIBLING_CALL_P (insn) = 1;
20936
22946
emit_barrier ();
20937
22947
20944
22954
/* Run just enough of rest_of_compilation to get the insns emitted.
20945
22955
There's not really enough bulk here to make other passes such as
20946
22956
instruction scheduling worth while. Note that use_thunk calls
20947
@@ -22555,7 +25409,7 @@
22957
@@ -22555,7 +25605,7 @@
20948
22958
if (TARGET_PROFILE_KERNEL)
20949
22959
return;
20950
22960
20953
22963
{
20954
22964
#ifndef NO_PROFILE_COUNTERS
20955
22965
# define NO_PROFILE_COUNTERS 0
20956
@@ -22699,29 +25553,9 @@
22966
@@ -22699,29 +25749,9 @@
20957
22967
break;
20958
22968
20959
22969
case ABI_AIX:
20985
22995
break;
20986
22996
}
20987
22997
}
20988
@@ -22847,6 +25681,7 @@
22998
@@ -22847,6 +25877,7 @@
20989
22999
|| rs6000_cpu_attr == CPU_POWER4
20990
23000
|| rs6000_cpu_attr == CPU_POWER5
20991
23001
|| rs6000_cpu_attr == CPU_POWER7
20993
23003
|| rs6000_cpu_attr == CPU_CELL)
20994
23004
&& recog_memoized (dep_insn)
20995
23005
&& (INSN_CODE (dep_insn) >= 0))
20996
@@ -23129,7 +25964,8 @@
23006
@@ -23129,7 +26160,8 @@
20997
23007
if (rs6000_cpu_attr == CPU_CELL)
20998
23008
return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
20999
23009
21003
23013
{
21004
23014
enum attr_type type = get_attr_type (insn);
21005
23015
if (type == TYPE_LOAD_EXT_U
21006
@@ -23154,7 +25990,8 @@
23016
@@ -23154,7 +26186,8 @@
21007
23017
|| GET_CODE (PATTERN (insn)) == CLOBBER)
21008
23018
return false;
21009
23019
21013
23023
{
21014
23024
enum attr_type type = get_attr_type (insn);
21015
23025
if (type == TYPE_LOAD_U || type == TYPE_STORE_U
21016
@@ -23433,6 +26270,8 @@
23026
@@ -23433,6 +26466,8 @@
21017
23027
case CPU_POWER6:
21018
23028
case CPU_POWER7:
21019
23029
return 5;
21022
23032
default:
21023
23033
return 1;
21024
23034
}
21025
@@ -24060,6 +26899,39 @@
23035
@@ -24060,6 +27095,39 @@
21026
23036
break;
21027
23037
}
21028
23038
break;
21062
23072
default:
21063
23073
break;
21064
23074
}
21065
@@ -24138,6 +27010,25 @@
23075
@@ -24138,6 +27206,25 @@
21066
23076
break;
21067
23077
}
21068
23078
break;
21088
23098
default:
21089
23099
break;
21090
23100
}
21091
@@ -24227,8 +27118,9 @@
23101
@@ -24227,8 +27314,9 @@
21092
23102
if (can_issue_more && !is_branch_slot_insn (next_insn))
21093
23103
can_issue_more--;
21094
23104
21100
23110
{
21101
23111
nop = gen_group_ending_nop ();
21102
23112
emit_insn_before (nop, next_insn);
21103
@@ -24599,6 +27491,11 @@
23113
@@ -24599,6 +27687,11 @@
21104
23114
ret = (TARGET_32BIT) ? 12 : 24;
21105
23115
break;
21106
23116
21112
23122
case ABI_DARWIN:
21113
23123
case ABI_V4:
21114
23124
ret = (TARGET_32BIT) ? 40 : 48;
21115
@@ -24654,6 +27551,7 @@
23125
@@ -24654,6 +27747,7 @@
21116
23126
break;
21117
23127
21118
23128
/* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
21120
23130
case ABI_DARWIN:
21121
23131
case ABI_V4:
21122
23132
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
21123
@@ -24948,7 +27846,7 @@
23133
@@ -24948,7 +28042,7 @@
21124
23134
static void
21125
23135
rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
21126
23136
{
21129
23139
&& TARGET_MINIMAL_TOC
21130
23140
&& !TARGET_RELOCATABLE)
21131
23141
{
21132
@@ -24969,7 +27867,8 @@
23142
@@ -24969,7 +28063,8 @@
21133
23143
else
21134
23144
fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
21135
23145
}
21139
23149
fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
21140
23150
else
21141
23151
{
21142
@@ -25519,7 +28418,7 @@
23152
@@ -25519,7 +28614,7 @@
21143
23153
{
21144
23154
if (flag_pic)
21145
23155
return 3;
21148
23158
return 2;
21149
23159
else
21150
23160
return 0;
21151
@@ -25595,7 +28494,7 @@
23161
@@ -25595,7 +28690,7 @@
21152
23162
void
21153
23163
rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
21154
23164
{
21157
23167
{
21158
23168
fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
21159
23169
ASM_OUTPUT_LABEL (file, name);
21160
@@ -25661,8 +28560,7 @@
23170
@@ -25661,8 +28756,7 @@
21161
23171
fprintf (file, "%s:\n", desc_name);
21162
23172
fprintf (file, "\t.long %s\n", orig_name);
21163
23173
fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
21167
23177
fprintf (file, "\t.previous\n");
21168
23178
}
21169
23179
ASM_OUTPUT_LABEL (file, name);
21170
@@ -25691,7 +28589,7 @@
23180
@@ -25691,7 +28785,7 @@
21171
23181
}
21172
23182
#endif
21173
23183
#if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
21176
23186
file_end_indicate_exec_stack ();
21177
23187
#endif
21178
23188
}
21179
@@ -26431,7 +29329,8 @@
23189
@@ -26431,7 +29525,8 @@
21180
23190
/* For those processors that have slow LR/CTR moves, make them more
21181
23191
expensive than memory in order to bias spills to memory .*/
21182
23192
else if ((rs6000_cpu == PROCESSOR_POWER6
21186
23196
&& reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
21187
23197
ret = 6 * hard_regno_nregs[0][mode];
21188
23198
21189
@@ -26441,7 +29340,7 @@
23199
@@ -26441,7 +29536,7 @@
21190
23200
}
21191
23201
21192
23202
/* If we have VSX, we can easily move between FPR or Altivec registers. */
21195
23205
&& reg_classes_intersect_p (to, VSX_REGS)
21196
23206
&& reg_classes_intersect_p (from, VSX_REGS))
21197
23207
ret = 2 * hard_regno_nregs[32][mode];
21198
@@ -26482,7 +29381,8 @@
23208
@@ -26482,7 +29577,8 @@
21199
23209
21200
23210
if (reg_classes_intersect_p (rclass, GENERAL_REGS))
21201
23211
ret = 4 * hard_regno_nregs[0][mode];
21205
23215
ret = 4 * hard_regno_nregs[32][mode];
21206
23216
else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
21207
23217
ret = 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
21208
@@ -26644,54 +29544,26 @@
23218
@@ -26644,54 +29740,26 @@
21209
23219
emit_insn (gen_rtx_SET (VOIDmode, dst, r));
21210
23220
}
21211
23221
21275
23285
enum insn_code code = optab_handler (smul_optab, mode);
21276
23286
insn_gen_fn gen_mul = GEN_FCN (code);
21277
23287
21278
@@ -26705,47 +29577,45 @@
23288
@@ -26705,47 +29773,45 @@
21279
23289
gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
21280
23290
UNSPEC_FRES)));
21281
23291
21352
23362
if (note_p)
21353
23363
add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
21354
23364
}
21355
@@ -26759,7 +29629,16 @@
23365
@@ -26759,7 +29825,16 @@
21356
23366
enum machine_mode mode = GET_MODE (src);
21357
23367
rtx x0 = gen_reg_rtx (mode);
21358
23368
rtx y = gen_reg_rtx (mode);
21370
23380
REAL_VALUE_TYPE dconst3_2;
21371
23381
int i;
21372
23382
rtx halfthree;
21373
@@ -26921,6 +29800,137 @@
23383
@@ -26921,6 +29996,137 @@
21374
23384
}
21375
23385
}
21376
23386
21508
23518
/* Expand an Altivec constant permutation. Return true if we match
21509
23519
an efficient implementation; false to fall back to VPERM. */
21510
23520
21511
@@ -26928,26 +29938,43 @@
23521
@@ -26928,26 +30134,43 @@
21512
23522
altivec_expand_vec_perm_const (rtx operands[4])
21513
23523
{
21514
23524
struct altivec_perm_insn {
21561
23571
};
21562
23572
21563
23573
unsigned int i, j, elt, which;
21564
@@ -27004,7 +30031,9 @@
23574
@@ -27004,7 +30227,9 @@
21565
23575
break;
21566
23576
if (i == 16)
21567
23577
{
21572
23582
return true;
21573
23583
}
21574
23584
21575
@@ -27015,9 +30044,10 @@
23585
@@ -27015,9 +30240,10 @@
21576
23586
break;
21577
23587
if (i == 16)
21578
23588
{
21585
23595
emit_move_insn (target, gen_lowpart (V16QImode, x));
21586
23596
return true;
21587
23597
}
21588
@@ -27033,9 +30063,10 @@
23598
@@ -27033,9 +30259,10 @@
21589
23599
break;
21590
23600
if (i == 16)
21591
23601
{
21598
23608
emit_move_insn (target, gen_lowpart (V16QImode, x));
21599
23609
return true;
21600
23610
}
21601
@@ -27047,6 +30078,9 @@
23611
@@ -27047,6 +30274,9 @@
21602
23612
{
21603
23613
bool swapped;
21604
23614
21608
23618
elt = patterns[j].perm[0];
21609
23619
if (perm[0] == elt)
21610
23620
swapped = false;
21611
@@ -27070,7 +30104,30 @@
23621
@@ -27070,7 +30300,30 @@
21612
23622
enum machine_mode omode = insn_data[icode].operand[0].mode;
21613
23623
enum machine_mode imode = insn_data[icode].operand[1].mode;
21614
23624
21640
23650
x = op0, op0 = op1, op1 = x;
21641
23651
if (imode != V16QImode)
21642
23652
{
21643
@@ -27088,6 +30145,12 @@
23653
@@ -27088,6 +30341,12 @@
21644
23654
}
21645
23655
}
21646
23656
21653
23663
return false;
21654
23664
}
21655
23665
21656
@@ -27136,7 +30199,6 @@
23666
@@ -27136,7 +30395,6 @@
21657
23667
vmode = GET_MODE (target);
21658
23668
gcc_assert (GET_MODE_NUNITS (vmode) == 2);
21659
23669
dmode = mode_for_vector (GET_MODE_INNER (vmode), 4);
21661
23671
x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
21662
23672
v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
21663
23673
x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
21664
@@ -27232,7 +30294,7 @@
23674
@@ -27232,7 +30490,7 @@
21665
23675
unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
21666
23676
rtx perm[16];
21667
23677
21670
23680
for (i = 0; i < nelt / 2; i++)
21671
23681
{
21672
23682
perm[i * 2] = GEN_INT (i + high);
21673
@@ -27287,6 +30349,8 @@
23683
@@ -27287,6 +30545,8 @@
21674
23684
{
21675
23685
enum machine_mode mode;
21676
23686
unsigned int regno;
21679
23689
21680
23690
/* Special handling for structs in darwin64. */
21681
23691
if (TARGET_MACHO
21682
@@ -27306,6 +30370,36 @@
23692
@@ -27306,6 +30566,36 @@
21683
23693
/* Otherwise fall through to standard ABI rules. */
21684
23694
}
21685
23695
21716
23726
if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
21717
23727
{
21718
23728
/* Long long return value need be split in -mpowerpc64, 32bit ABI. */
21719
@@ -27418,6 +30512,13 @@
23729
@@ -27418,6 +30708,13 @@
21720
23730
}
21721
23731
21722
23732
21730
23740
/* Given FROM and TO register numbers, say whether this elimination is allowed.
21731
23741
Frame pointer elimination is automatically handled.
21732
23742
21733
@@ -27680,22 +30781,33 @@
23743
@@ -27680,22 +30977,33 @@
21734
23744
{
21735
23745
{ "altivec", OPTION_MASK_ALTIVEC, false, true },
21736
23746
{ "cmpb", OPTION_MASK_CMPB, false, true },
21765
23775
#ifdef OPTION_MASK_64BIT
21766
23776
#if TARGET_AIX_OS
21767
23777
{ "aix64", OPTION_MASK_64BIT, false, false },
21768
@@ -27735,6 +30847,9 @@
23778
@@ -27735,6 +31043,9 @@
21769
23779
{ "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
21770
23780
{ "popcntd", RS6000_BTM_POPCNTD, false, false },
21771
23781
{ "cell", RS6000_BTM_CELL, false, false },
21775
23785
};
21776
23786
21777
23787
/* Option variables that we want to support inside attribute((target)) and
21778
@@ -28251,7 +31366,6 @@
23788
@@ -28251,7 +31562,6 @@
21779
23789
size_t cur_column;
21780
23790
size_t max_column = 76;
21781
23791
const char *comma = "";
21783
23793
21784
23794
if (indent)
21785
23795
start_column += fprintf (file, "%*s", indent, "");
21786
@@ -28282,7 +31396,6 @@
23796
@@ -28282,7 +31592,6 @@
21787
23797
fprintf (stderr, ", \\\n%*s", (int)start_column, "");
21788
23798
cur_column = start_column + len;
21789
23799
comma = "";
21791
23801
}
21792
23802
21793
23803
fprintf (file, "%s%s%s%s", comma, prefix, no_str,
21794
@@ -28292,7 +31405,7 @@
23804
@@ -28292,7 +31601,7 @@
21795
23805
}
21796
23806
}
21797
23807
21800
23810
}
21801
23811
21802
23812
/* Helper function to print the current isa options on a line. */
21803
@@ -28468,118 +31581,149 @@
23813
@@ -28468,118 +31777,149 @@
21804
23814
}
21805
23815
21806
23816
22034
24044
}
22035
24045
22036
24046
/* Return whether we need to always update the saved TOC pointer when we update
22037
@@ -28680,6 +31824,656 @@
24047
@@ -28680,6 +32020,656 @@
22038
24048
add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
22039
24049
}
22040
24050
25999
28009
+ if (VECTOR_ELT_ORDER_BIG)
26000
28010
+ return "vsumsws %0,%1,%2";
26001
28011
+ else
26002
+ return "vspltw %3,%2,0\n\tvsumsws %3,%1,%3\n\tvspltw %0,%3,3";
28012
+ return "vspltw %3,%2,0\n\tvsumsws %3,%1,%3\n\tvsldoi %0,%3,%3,12";
26003
28013
+}
26004
28014
+ [(set_attr "type" "veccomplex")
26005
28015
+ (set (attr "length")
26435
28445
"vcmpgtu<VI_char>. %0,%1,%2"
26436
28446
[(set_attr "type" "veccmp")])
26437
28447
26438
@@ -1779,20 +2394,28 @@
28448
@@ -1710,12 +2325,26 @@
28449
;; Parallel some of the LVE* and STV*'s with unspecs because some have
28450
;; identical rtl but different instructions-- and gcc gets confused.
28451
28452
-(define_insn "altivec_lve<VI_char>x"
28453
+(define_expand "altivec_lve<VI_char>x"
28454
[(parallel
28455
[(set (match_operand:VI 0 "register_operand" "=v")
28456
(match_operand:VI 1 "memory_operand" "Z"))
28457
(unspec [(const_int 0)] UNSPEC_LVE)])]
28458
"TARGET_ALTIVEC"
28459
+{
28460
+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
28461
+ {
28462
+ altivec_expand_lvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_LVE);
28463
+ DONE;
28464
+ }
28465
+})
28466
+
28467
+(define_insn "*altivec_lve<VI_char>x_internal"
28468
+ [(parallel
28469
+ [(set (match_operand:VI 0 "register_operand" "=v")
28470
+ (match_operand:VI 1 "memory_operand" "Z"))
28471
+ (unspec [(const_int 0)] UNSPEC_LVE)])]
28472
+ "TARGET_ALTIVEC"
28473
"lve<VI_char>x %0,%y1"
28474
[(set_attr "type" "vecload")])
28475
28476
@@ -1728,46 +2357,114 @@
28477
"lvewx %0,%y1"
28478
[(set_attr "type" "vecload")])
28479
28480
-(define_insn "altivec_lvxl"
28481
+(define_expand "altivec_lvxl_<mode>"
28482
[(parallel
28483
- [(set (match_operand:V4SI 0 "register_operand" "=v")
28484
- (match_operand:V4SI 1 "memory_operand" "Z"))
28485
+ [(set (match_operand:VM2 0 "register_operand" "=v")
28486
+ (match_operand:VM2 1 "memory_operand" "Z"))
28487
(unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
28488
"TARGET_ALTIVEC"
28489
- "lvxl %0,%y1"
28490
+{
28491
+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
28492
+ {
28493
+ altivec_expand_lvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_SET_VSCR);
28494
+ DONE;
28495
+ }
28496
+})
28497
+
28498
+(define_insn "*altivec_lvxl_<mode>_internal"
28499
+ [(parallel
28500
+ [(set (match_operand:VM2 0 "register_operand" "=v")
28501
+ (match_operand:VM2 1 "memory_operand" "Z"))
28502
+ (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
28503
+ "TARGET_ALTIVEC"
28504
+ "lvx %0,%y1"
28505
[(set_attr "type" "vecload")])
28506
28507
-(define_insn "altivec_lvx_<mode>"
28508
+(define_expand "altivec_lvx_<mode>"
28509
[(parallel
28510
[(set (match_operand:VM2 0 "register_operand" "=v")
28511
(match_operand:VM2 1 "memory_operand" "Z"))
28512
(unspec [(const_int 0)] UNSPEC_LVX)])]
28513
"TARGET_ALTIVEC"
28514
+{
28515
+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
28516
+ {
28517
+ altivec_expand_lvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_LVX);
28518
+ DONE;
28519
+ }
28520
+})
28521
+
28522
+(define_insn "*altivec_lvx_<mode>_internal"
28523
+ [(parallel
28524
+ [(set (match_operand:VM2 0 "register_operand" "=v")
28525
+ (match_operand:VM2 1 "memory_operand" "Z"))
28526
+ (unspec [(const_int 0)] UNSPEC_LVX)])]
28527
+ "TARGET_ALTIVEC"
28528
"lvx %0,%y1"
28529
[(set_attr "type" "vecload")])
28530
28531
-(define_insn "altivec_stvx_<mode>"
28532
+(define_expand "altivec_stvx_<mode>"
28533
[(parallel
28534
[(set (match_operand:VM2 0 "memory_operand" "=Z")
28535
(match_operand:VM2 1 "register_operand" "v"))
28536
(unspec [(const_int 0)] UNSPEC_STVX)])]
28537
"TARGET_ALTIVEC"
28538
+{
28539
+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
28540
+ {
28541
+ altivec_expand_stvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_STVX);
28542
+ DONE;
28543
+ }
28544
+})
28545
+
28546
+(define_insn "*altivec_stvx_<mode>_internal"
28547
+ [(parallel
28548
+ [(set (match_operand:VM2 0 "memory_operand" "=Z")
28549
+ (match_operand:VM2 1 "register_operand" "v"))
28550
+ (unspec [(const_int 0)] UNSPEC_STVX)])]
28551
+ "TARGET_ALTIVEC"
28552
"stvx %1,%y0"
28553
[(set_attr "type" "vecstore")])
28554
28555
-(define_insn "altivec_stvxl"
28556
+(define_expand "altivec_stvxl_<mode>"
28557
[(parallel
28558
- [(set (match_operand:V4SI 0 "memory_operand" "=Z")
28559
- (match_operand:V4SI 1 "register_operand" "v"))
28560
+ [(set (match_operand:VM2 0 "memory_operand" "=Z")
28561
+ (match_operand:VM2 1 "register_operand" "v"))
28562
(unspec [(const_int 0)] UNSPEC_STVXL)])]
28563
"TARGET_ALTIVEC"
28564
+{
28565
+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
28566
+ {
28567
+ altivec_expand_stvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_STVXL);
28568
+ DONE;
28569
+ }
28570
+})
28571
+
28572
+(define_insn "*altivec_stvxl_<mode>_internal"
28573
+ [(parallel
28574
+ [(set (match_operand:VM2 0 "memory_operand" "=Z")
28575
+ (match_operand:VM2 1 "register_operand" "v"))
28576
+ (unspec [(const_int 0)] UNSPEC_STVXL)])]
28577
+ "TARGET_ALTIVEC"
28578
"stvxl %1,%y0"
28579
[(set_attr "type" "vecstore")])
28580
28581
-(define_insn "altivec_stve<VI_char>x"
28582
+(define_expand "altivec_stve<VI_char>x"
28583
[(set (match_operand:<VI_scalar> 0 "memory_operand" "=Z")
28584
(unspec:<VI_scalar> [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))]
28585
"TARGET_ALTIVEC"
28586
+{
28587
+ if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
28588
+ {
28589
+ altivec_expand_stvex_be (operands[0], operands[1], <MODE>mode, UNSPEC_STVE);
28590
+ DONE;
28591
+ }
28592
+})
28593
+
28594
+(define_insn "*altivec_stve<VI_char>x_internal"
28595
+ [(set (match_operand:<VI_scalar> 0 "memory_operand" "=Z")
28596
+ (unspec:<VI_scalar> [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))]
28597
+ "TARGET_ALTIVEC"
28598
"stve<VI_char>x %1,%y0"
28599
[(set_attr "type" "vecstore")])
28600
28601
@@ -1779,20 +2476,28 @@
26439
28602
[(set_attr "type" "vecstore")])
26440
28603
26441
28604
;; Generate
26474
28637
})
26475
28638
26476
28639
;; Generate
26477
@@ -1844,7 +2467,7 @@
28640
@@ -1844,7 +2549,7 @@
26478
28641
26479
28642
emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
26480
28643
emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
26483
28646
DONE;
26484
28647
})
26485
28648
26486
@@ -1950,50 +2573,20 @@
28649
@@ -1860,7 +2565,7 @@
28650
28651
emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
28652
emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
28653
- emit_insn (gen_altivec_vsumsws (dest, vtmp1, vzero));
28654
+ emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero));
28655
DONE;
28656
})
28657
28658
@@ -1950,50 +2655,20 @@
26487
28659
DONE;
26488
28660
}")
26489
28661
26546
28718
(define_insn "vperm_v8hiv4si"
26547
28719
[(set (match_operand:V4SI 0 "register_operand" "=v")
26548
28720
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
26549
@@ -2025,25 +2618,26 @@
28721
@@ -2025,25 +2700,26 @@
26550
28722
rtx vzero = gen_reg_rtx (V8HImode);
26551
28723
rtx mask = gen_reg_rtx (V16QImode);
26552
28724
rtvec v = rtvec_alloc (16);
26589
28761
26590
28762
emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
26591
28763
emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
26592
@@ -2060,25 +2654,26 @@
28764
@@ -2060,25 +2736,26 @@
26593
28765
rtx vzero = gen_reg_rtx (V4SImode);
26594
28766
rtx mask = gen_reg_rtx (V16QImode);
26595
28767
rtvec v = rtvec_alloc (16);
26632
28804
26633
28805
emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
26634
28806
emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
26635
@@ -2095,25 +2690,26 @@
28807
@@ -2095,25 +2772,26 @@
26636
28808
rtx vzero = gen_reg_rtx (V8HImode);
26637
28809
rtx mask = gen_reg_rtx (V16QImode);
26638
28810
rtvec v = rtvec_alloc (16);
26675
28847
26676
28848
emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
26677
28849
emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
26678
@@ -2130,25 +2726,26 @@
28850
@@ -2130,25 +2808,26 @@
26679
28851
rtx vzero = gen_reg_rtx (V4SImode);
26680
28852
rtx mask = gen_reg_rtx (V16QImode);
26681
28853
rtvec v = rtvec_alloc (16);
26718
28890
26719
28891
emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
26720
28892
emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
26721
@@ -2166,9 +2763,18 @@
26722
rtx ve = gen_reg_rtx (V8HImode);
26723
rtx vo = gen_reg_rtx (V8HImode);
26724
26725
- emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2]));
26726
- emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2]));
26727
- emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
26728
+ if (BYTES_BIG_ENDIAN)
26729
+ {
26730
+ emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
26731
+ emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
26732
+ emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo));
26733
+ }
26734
+ else
26735
+ {
26736
+ emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2]));
26737
+ emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2]));
26738
+ emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
26739
+ }
26740
DONE;
26741
}")
26742
26743
@@ -2183,9 +2789,18 @@
26744
rtx ve = gen_reg_rtx (V8HImode);
26745
rtx vo = gen_reg_rtx (V8HImode);
26746
26747
- emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2]));
26748
- emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2]));
26749
- emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
26750
+ if (BYTES_BIG_ENDIAN)
26751
+ {
26752
+ emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
26753
+ emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
26754
+ emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo));
26755
+ }
26756
+ else
26757
+ {
26758
+ emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2]));
26759
+ emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2]));
26760
+ emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
26761
+ }
26762
DONE;
26763
}")
26764
26765
@@ -2200,9 +2815,18 @@
26766
rtx ve = gen_reg_rtx (V8HImode);
26767
rtx vo = gen_reg_rtx (V8HImode);
26768
26769
- emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2]));
26770
- emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2]));
26771
- emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
26772
+ if (BYTES_BIG_ENDIAN)
26773
+ {
26774
+ emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
26775
+ emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
26776
+ emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo));
26777
+ }
26778
+ else
26779
+ {
26780
+ emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2]));
26781
+ emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2]));
26782
+ emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
26783
+ }
26784
DONE;
26785
}")
26786
26787
@@ -2217,9 +2841,18 @@
26788
rtx ve = gen_reg_rtx (V8HImode);
26789
rtx vo = gen_reg_rtx (V8HImode);
26790
26791
- emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2]));
26792
- emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2]));
26793
- emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
26794
+ if (BYTES_BIG_ENDIAN)
26795
+ {
26796
+ emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
26797
+ emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
26798
+ emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo));
26799
+ }
26800
+ else
26801
+ {
26802
+ emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2]));
26803
+ emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2]));
26804
+ emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
26805
+ }
26806
DONE;
26807
}")
26808
26809
@@ -2234,9 +2867,18 @@
28893
@@ -2166,9 +2845,18 @@
28894
rtx ve = gen_reg_rtx (V8HImode);
28895
rtx vo = gen_reg_rtx (V8HImode);
28896
28897
- emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2]));
28898
- emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2]));
28899
- emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
28900
+ if (BYTES_BIG_ENDIAN)
28901
+ {
28902
+ emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
28903
+ emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
28904
+ emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo));
28905
+ }
28906
+ else
28907
+ {
28908
+ emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2]));
28909
+ emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2]));
28910
+ emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
28911
+ }
28912
DONE;
28913
}")
28914
28915
@@ -2183,9 +2871,18 @@
28916
rtx ve = gen_reg_rtx (V8HImode);
28917
rtx vo = gen_reg_rtx (V8HImode);
28918
28919
- emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2]));
28920
- emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2]));
28921
- emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
28922
+ if (BYTES_BIG_ENDIAN)
28923
+ {
28924
+ emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
28925
+ emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
28926
+ emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo));
28927
+ }
28928
+ else
28929
+ {
28930
+ emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2]));
28931
+ emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2]));
28932
+ emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
28933
+ }
28934
DONE;
28935
}")
28936
28937
@@ -2200,9 +2897,18 @@
28938
rtx ve = gen_reg_rtx (V8HImode);
28939
rtx vo = gen_reg_rtx (V8HImode);
28940
28941
- emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2]));
28942
- emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2]));
28943
- emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
28944
+ if (BYTES_BIG_ENDIAN)
28945
+ {
28946
+ emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
28947
+ emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
28948
+ emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo));
28949
+ }
28950
+ else
28951
+ {
28952
+ emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2]));
28953
+ emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2]));
28954
+ emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
28955
+ }
28956
DONE;
28957
}")
28958
28959
@@ -2217,9 +2923,18 @@
28960
rtx ve = gen_reg_rtx (V8HImode);
28961
rtx vo = gen_reg_rtx (V8HImode);
28962
28963
- emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2]));
28964
- emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2]));
28965
- emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
28966
+ if (BYTES_BIG_ENDIAN)
28967
+ {
28968
+ emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
28969
+ emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
28970
+ emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo));
28971
+ }
28972
+ else
28973
+ {
28974
+ emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2]));
28975
+ emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2]));
28976
+ emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
28977
+ }
28978
DONE;
28979
}")
28980
28981
@@ -2234,9 +2949,18 @@
26810
28982
rtx ve = gen_reg_rtx (V4SImode);
26811
28983
rtx vo = gen_reg_rtx (V4SImode);
26812
28984
26828
29000
DONE;
26829
29001
}")
26830
29002
26831
@@ -2251,9 +2893,18 @@
29003
@@ -2251,9 +2975,18 @@
26832
29004
rtx ve = gen_reg_rtx (V4SImode);
26833
29005
rtx vo = gen_reg_rtx (V4SImode);
26834
29006
26850
29022
DONE;
26851
29023
}")
26852
29024
26853
@@ -2268,9 +2919,18 @@
29025
@@ -2268,9 +3001,18 @@
26854
29026
rtx ve = gen_reg_rtx (V4SImode);
26855
29027
rtx vo = gen_reg_rtx (V4SImode);
26856
29028
26872
29044
DONE;
26873
29045
}")
26874
29046
26875
@@ -2285,35 +2945,28 @@
29047
@@ -2285,35 +3027,28 @@
26876
29048
rtx ve = gen_reg_rtx (V4SImode);
26877
29049
rtx vo = gen_reg_rtx (V4SImode);
26878
29050
26927
29099
26928
29100
(define_expand "altivec_negv4sf2"
26929
29101
[(use (match_operand:V4SF 0 "register_operand" ""))
26930
@@ -2460,3 +3113,34 @@
29102
@@ -2460,3 +3195,34 @@
26931
29103
emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
26932
29104
DONE;
26933
29105
}")
Loggerhead is a web-based interface for Breezy
Version: 2.0.1