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// Copyright 2011 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
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#define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
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#include "assembler.h"
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#include "mips/assembler-mips.h"
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#include "v8globals.h"
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// Forward declaration.
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// Reserved Register Usage Summary.
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// Registers t8, t9, and at are reserved for use by the MacroAssembler.
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// The programmer should know that the MacroAssembler may clobber these three,
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// but won't touch other registers except in special cases.
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// Per the MIPS ABI, register t9 must be used for indirect function call
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// via 'jalr t9' or 'jr t9' instructions. This is relied upon by gcc when
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// trying to update gp register for position-independent-code. Whenever
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// MIPS generated code calls C code, it must be via t9 register.
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// cp is assumed to be a callee saved register.
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const Register roots = s6; // Roots array pointer.
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const Register cp = s7; // JavaScript context pointer.
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const Register fp = s8_fp; // Alias for fp.
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// Registers used for condition evaluation.
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const Register condReg1 = s4;
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const Register condReg2 = s5;
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// Flags used for the AllocateInNewSpace functions.
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enum AllocationFlags {
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NO_ALLOCATION_FLAGS = 0,
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// Return the pointer to the allocated already tagged as a heap object.
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// The content of the result register already contains the allocation top in
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RESULT_CONTAINS_TOP = 1 << 1,
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// Specify that the requested size of the space to allocate is specified in
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// words instead of bytes.
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SIZE_IN_WORDS = 1 << 2
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// Flags used for the ObjectToDoubleFPURegister function.
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enum ObjectToDoubleFlags {
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NO_OBJECT_TO_DOUBLE_FLAGS = 0,
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// Object is known to be a non smi.
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OBJECT_NOT_SMI = 1 << 0,
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// Don't load NaNs or infinities, branch to the non number case instead.
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AVOID_NANS_AND_INFINITIES = 1 << 1
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// Allow programmer to use Branch Delay Slot of Branches, Jumps, Calls.
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enum BranchDelaySlot {
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// MacroAssembler implements a collection of frequently used macros.
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class MacroAssembler: public Assembler {
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// The isolate parameter can be NULL if the macro assembler should
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// not use isolate-dependent functionality. In this case, it's the
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// responsibility of the caller to never invoke such function on the
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MacroAssembler(Isolate* isolate, void* buffer, int size);
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#define COND_TYPED_ARGS Condition cond, Register r1, const Operand& r2
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#define COND_ARGS cond, r1, r2
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// Cases when relocation is not needed.
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#define DECLARE_NORELOC_PROTOTYPE(Name, target_type) \
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void Name(target_type target, BranchDelaySlot bd = PROTECT); \
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inline void Name(BranchDelaySlot bd, target_type target) { \
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void Name(target_type target, \
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BranchDelaySlot bd = PROTECT); \
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inline void Name(BranchDelaySlot bd, \
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target_type target, \
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Name(target, COND_ARGS, bd); \
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#define DECLARE_BRANCH_PROTOTYPES(Name) \
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DECLARE_NORELOC_PROTOTYPE(Name, Label*) \
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DECLARE_NORELOC_PROTOTYPE(Name, int16_t)
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DECLARE_BRANCH_PROTOTYPES(Branch)
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DECLARE_BRANCH_PROTOTYPES(BranchAndLink)
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#undef DECLARE_BRANCH_PROTOTYPES
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#undef COND_TYPED_ARGS
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// Jump, Call, and Ret pseudo instructions implementing inter-working.
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#define COND_ARGS Condition cond = al, Register rs = zero_reg, \
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const Operand& rt = Operand(zero_reg), BranchDelaySlot bd = PROTECT
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void Jump(Register target, COND_ARGS);
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void Jump(intptr_t target, RelocInfo::Mode rmode, COND_ARGS);
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void Jump(Address target, RelocInfo::Mode rmode, COND_ARGS);
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void Jump(Handle<Code> code, RelocInfo::Mode rmode, COND_ARGS);
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int CallSize(Register target, COND_ARGS);
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void Call(Register target, COND_ARGS);
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int CallSize(Address target, RelocInfo::Mode rmode, COND_ARGS);
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void Call(Address target, RelocInfo::Mode rmode, COND_ARGS);
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int CallSize(Handle<Code> code,
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RelocInfo::Mode rmode = RelocInfo::CODE_TARGET,
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unsigned ast_id = kNoASTId,
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void Call(Handle<Code> code,
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RelocInfo::Mode rmode = RelocInfo::CODE_TARGET,
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unsigned ast_id = kNoASTId,
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inline void Ret(BranchDelaySlot bd) {
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Ret(al, zero_reg, Operand(zero_reg), bd);
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// Emit code to discard a non-negative number of pointer-sized elements
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// from the stack, clobbering only the sp register.
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Condition cond = cc_always,
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Register reg = no_reg,
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const Operand& op = Operand(no_reg));
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void DropAndRet(int drop = 0,
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Condition cond = cc_always,
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Register reg = no_reg,
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const Operand& op = Operand(no_reg));
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// Swap two registers. If the scratch register is omitted then a slightly
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// less efficient form using xor instead of mov is emitted.
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void Swap(Register reg1, Register reg2, Register scratch = no_reg);
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void Call(Label* target);
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inline void Move(Register dst, Register src) {
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inline void Move(FPURegister dst, FPURegister src) {
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inline void Move(Register dst_low, Register dst_high, FPURegister src) {
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mfc1(dst_high, FPURegister::from_code(src.code() + 1));
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inline void Move(FPURegister dst, Register src_low, Register src_high) {
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mtc1(src_high, FPURegister::from_code(dst.code() + 1));
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// Jump unconditionally to given label.
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// We NEED a nop in the branch delay slot, as it used by v8, for example in
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// CodeGenerator::ProcessDeferred().
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// Currently the branch delay slot is filled by the MacroAssembler.
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// Use rather b(Label) for code generation.
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// Load an object from the root table.
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void LoadRoot(Register destination,
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Heap::RootListIndex index);
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void LoadRoot(Register destination,
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Heap::RootListIndex index,
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Condition cond, Register src1, const Operand& src2);
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// Store an object to the root table.
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void StoreRoot(Register source,
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Heap::RootListIndex index);
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void StoreRoot(Register source,
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Heap::RootListIndex index,
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Condition cond, Register src1, const Operand& src2);
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// Check if object is in new space.
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// scratch can be object itself, but it will be clobbered.
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void InNewSpace(Register object,
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Condition cc, // eq for new space, ne otherwise.
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// For the page containing |object| mark the region covering [address]
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// dirty. The object address must be in the first 8K of an allocated page.
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void RecordWriteHelper(Register object,
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// For the page containing |object| mark the region covering
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// [object+offset] dirty. The object address must be in the first 8K
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// of an allocated page. The 'scratch' registers are used in the
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// implementation and all 3 registers are clobbered by the
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// operation, as well as the 'at' register. RecordWrite updates the
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// write barrier even when storing smis.
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void RecordWrite(Register object,
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// For the page containing |object| mark the region covering
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// [address] dirty. The object address must be in the first 8K of an
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// allocated page. All 3 registers are clobbered by the operation,
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// as well as the ip register. RecordWrite updates the write barrier
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// even when storing smis.
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void RecordWrite(Register object,
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// ---------------------------------------------------------------------------
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// Inline caching support.
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// Generate code for checking access rights - used for security checks
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// on access to global objects across environments. The holder register
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// is left untouched, whereas both scratch registers are clobbered.
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void CheckAccessGlobalProxy(Register holder_reg,
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void LoadFromNumberDictionary(Label* miss,
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inline void MarkCode(NopMarkerTypes type) {
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// Check if the given instruction is a 'type' marker.
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// ie. check if it is a sll zero_reg, zero_reg, <type> (referenced as
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// nop(type)). These instructions are generated to mark special location in
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// the code, like some special IC code.
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static inline bool IsMarkedCode(Instr instr, int type) {
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ASSERT((FIRST_IC_MARKER <= type) && (type < LAST_CODE_MARKER));
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return IsNop(instr, type);
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static inline int GetCodeMarker(Instr instr) {
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uint32_t opcode = ((instr & kOpcodeMask));
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uint32_t rt = ((instr & kRtFieldMask) >> kRtShift);
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uint32_t rs = ((instr & kRsFieldMask) >> kRsShift);
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uint32_t sa = ((instr & kSaFieldMask) >> kSaShift);
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// Return <n> if we have a sll zero_reg, zero_reg, n
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bool sllzz = (opcode == SLL &&
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rt == static_cast<uint32_t>(ToNumber(zero_reg)) &&
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rs == static_cast<uint32_t>(ToNumber(zero_reg)));
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(sllzz && FIRST_IC_MARKER <= sa && sa < LAST_CODE_MARKER) ? sa : -1;
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ASSERT((type == -1) ||
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((FIRST_IC_MARKER <= type) && (type < LAST_CODE_MARKER)));
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// ---------------------------------------------------------------------------
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// Allocation support.
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// Allocate an object in new space. The object_size is specified
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// either in bytes or in words if the allocation flag SIZE_IN_WORDS
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// is passed. If the new space is exhausted control continues at the
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// gc_required label. The allocated object is returned in result. If
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// the flag tag_allocated_object is true the result is tagged as as
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// a heap object. All registers are clobbered also when control
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// continues at the gc_required label.
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void AllocateInNewSpace(int object_size,
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AllocationFlags flags);
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void AllocateInNewSpace(Register object_size,
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AllocationFlags flags);
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// Undo allocation in new space. The object passed and objects allocated after
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// it will no longer be allocated. The caller must make sure that no pointers
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// are left to the object(s) no longer allocated as they would be invalid when
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// allocation is undone.
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void UndoAllocationInNewSpace(Register object, Register scratch);
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void AllocateTwoByteString(Register result,
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void AllocateAsciiString(Register result,
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void AllocateTwoByteConsString(Register result,
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void AllocateAsciiConsString(Register result,
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void AllocateTwoByteSlicedString(Register result,
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void AllocateAsciiSlicedString(Register result,
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// Allocates a heap number or jumps to the gc_required label if the young
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// space is full and a scavenge is needed. All registers are clobbered also
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// when control continues at the gc_required label.
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void AllocateHeapNumber(Register result,
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Register heap_number_map,
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void AllocateHeapNumberWithValue(Register result,
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// ---------------------------------------------------------------------------
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// Instruction macros.
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#define DEFINE_INSTRUCTION(instr) \
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void instr(Register rd, Register rs, const Operand& rt); \
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void instr(Register rd, Register rs, Register rt) { \
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instr(rd, rs, Operand(rt)); \
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void instr(Register rs, Register rt, int32_t j) { \
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instr(rs, rt, Operand(j)); \
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#define DEFINE_INSTRUCTION2(instr) \
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void instr(Register rs, const Operand& rt); \
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void instr(Register rs, Register rt) { \
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instr(rs, Operand(rt)); \
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void instr(Register rs, int32_t j) { \
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instr(rs, Operand(j)); \
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DEFINE_INSTRUCTION(Addu);
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DEFINE_INSTRUCTION(Subu);
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DEFINE_INSTRUCTION(Mul);
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DEFINE_INSTRUCTION2(Mult);
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DEFINE_INSTRUCTION2(Multu);
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DEFINE_INSTRUCTION2(Div);
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DEFINE_INSTRUCTION2(Divu);
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DEFINE_INSTRUCTION(And);
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DEFINE_INSTRUCTION(Or);
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DEFINE_INSTRUCTION(Xor);
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DEFINE_INSTRUCTION(Nor);
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DEFINE_INSTRUCTION2(Neg);
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DEFINE_INSTRUCTION(Slt);
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DEFINE_INSTRUCTION(Sltu);
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// MIPS32 R2 instruction macro.
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DEFINE_INSTRUCTION(Ror);
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#undef DEFINE_INSTRUCTION
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#undef DEFINE_INSTRUCTION2
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// ---------------------------------------------------------------------------
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// Pseudo-instructions.
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void mov(Register rd, Register rt) { or_(rd, rt, zero_reg); }
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// Load int32 in the rd register.
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void li(Register rd, Operand j, bool gen2instr = false);
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inline void li(Register rd, int32_t j, bool gen2instr = false) {
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li(rd, Operand(j), gen2instr);
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inline void li(Register dst, Handle<Object> value, bool gen2instr = false) {
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li(dst, Operand(value), gen2instr);
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// Push multiple registers on the stack.
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// Registers are saved in numerical order, with higher numbered registers
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// saved in higher memory addresses.
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void MultiPush(RegList regs);
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void MultiPushReversed(RegList regs);
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void MultiPushFPU(RegList regs);
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void MultiPushReversedFPU(RegList regs);
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// Lower case push() for compatibility with arch-independent code.
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void push(Register src) {
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Addu(sp, sp, Operand(-kPointerSize));
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sw(src, MemOperand(sp, 0));
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void Push(Handle<Object> handle);
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// Push two registers. Pushes leftmost register first (to highest address).
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void Push(Register src1, Register src2) {
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Subu(sp, sp, Operand(2 * kPointerSize));
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sw(src1, MemOperand(sp, 1 * kPointerSize));
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sw(src2, MemOperand(sp, 0 * kPointerSize));
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// Push three registers. Pushes leftmost register first (to highest address).
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void Push(Register src1, Register src2, Register src3) {
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Subu(sp, sp, Operand(3 * kPointerSize));
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sw(src1, MemOperand(sp, 2 * kPointerSize));
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sw(src2, MemOperand(sp, 1 * kPointerSize));
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sw(src3, MemOperand(sp, 0 * kPointerSize));
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// Push four registers. Pushes leftmost register first (to highest address).
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void Push(Register src1, Register src2, Register src3, Register src4) {
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Subu(sp, sp, Operand(4 * kPointerSize));
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sw(src1, MemOperand(sp, 3 * kPointerSize));
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sw(src2, MemOperand(sp, 2 * kPointerSize));
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sw(src3, MemOperand(sp, 1 * kPointerSize));
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sw(src4, MemOperand(sp, 0 * kPointerSize));
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void Push(Register src, Condition cond, Register tst1, Register tst2) {
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// Since we don't have conditional execution we use a Branch.
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Branch(3, cond, tst1, Operand(tst2));
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Subu(sp, sp, Operand(kPointerSize));
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sw(src, MemOperand(sp, 0));
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// Pops multiple values from the stack and load them in the
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// registers specified in regs. Pop order is the opposite as in MultiPush.
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void MultiPop(RegList regs);
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void MultiPopReversed(RegList regs);
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void MultiPopFPU(RegList regs);
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void MultiPopReversedFPU(RegList regs);
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// Lower case pop() for compatibility with arch-independent code.
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void pop(Register dst) {
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lw(dst, MemOperand(sp, 0));
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Addu(sp, sp, Operand(kPointerSize));
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// Pop two registers. Pops rightmost register first (from lower address).
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void Pop(Register src1, Register src2) {
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ASSERT(!src1.is(src2));
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lw(src2, MemOperand(sp, 0 * kPointerSize));
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lw(src1, MemOperand(sp, 1 * kPointerSize));
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Addu(sp, sp, 2 * kPointerSize);
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void Pop(uint32_t count = 1) {
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Addu(sp, sp, Operand(count * kPointerSize));
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// Push and pop the registers that can hold pointers, as defined by the
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// RegList constant kSafepointSavedRegisters.
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void PushSafepointRegisters();
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void PopSafepointRegisters();
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void PushSafepointRegistersAndDoubles();
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void PopSafepointRegistersAndDoubles();
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// Store value in register src in the safepoint stack slot for
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void StoreToSafepointRegisterSlot(Register src, Register dst);
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void StoreToSafepointRegistersAndDoublesSlot(Register src, Register dst);
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// Load the value of the src register from its safepoint stack slot
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// into register dst.
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void LoadFromSafepointRegisterSlot(Register dst, Register src);
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// MIPS32 R2 instruction macro.
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void Ins(Register rt, Register rs, uint16_t pos, uint16_t size);
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void Ext(Register rt, Register rs, uint16_t pos, uint16_t size);
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// Convert unsigned word to double.
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void Cvt_d_uw(FPURegister fd, FPURegister fs, FPURegister scratch);
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void Cvt_d_uw(FPURegister fd, Register rs, FPURegister scratch);
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// Convert double to unsigned word.
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void Trunc_uw_d(FPURegister fd, FPURegister fs, FPURegister scratch);
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void Trunc_uw_d(FPURegister fd, Register rs, FPURegister scratch);
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// Convert the HeapNumber pointed to by source to a 32bits signed integer
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// dest. If the HeapNumber does not fit into a 32bits signed integer branch
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// to not_int32 label. If FPU is available double_scratch is used but not
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void ConvertToInt32(Register source,
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FPURegister double_scratch,
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// Helper for EmitECMATruncate.
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// This will truncate a floating-point value outside of the singed 32bit
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// integer range to a 32bit signed integer.
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// Expects the double value loaded in input_high and input_low.
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// Exits with the answer in 'result'.
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// Note that this code does not work for values in the 32bit range!
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void EmitOutOfInt32RangeTruncate(Register result,
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// Performs a truncating conversion of a floating point number as used by
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// the JS bitwise operations. See ECMA-262 9.5: ToInt32.
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// Exits with 'result' holding the answer and all other registers clobbered.
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void EmitECMATruncate(Register result,
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FPURegister double_input,
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FPURegister single_scratch,
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// -------------------------------------------------------------------------
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// Activation frames.
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void EnterInternalFrame() { EnterFrame(StackFrame::INTERNAL); }
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void LeaveInternalFrame() { LeaveFrame(StackFrame::INTERNAL); }
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void EnterConstructFrame() { EnterFrame(StackFrame::CONSTRUCT); }
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void LeaveConstructFrame() { LeaveFrame(StackFrame::CONSTRUCT); }
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// argc - argument count to be dropped by LeaveExitFrame.
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// save_doubles - saves FPU registers on stack, currently disabled.
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// stack_space - extra stack space.
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void EnterExitFrame(bool save_doubles,
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int stack_space = 0);
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// Leave the current exit frame.
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void LeaveExitFrame(bool save_doubles, Register arg_count);
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// Get the actual activation frame alignment for target environment.
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static int ActivationFrameAlignment();
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// Make sure the stack is aligned. Only emits code in debug mode.
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void AssertStackIsAligned();
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void LoadContext(Register dst, int context_chain_length);
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void LoadGlobalFunction(int index, Register function);
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// Load the initial map from the global function. The registers
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// function and map can be the same, function is then overwritten.
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void LoadGlobalFunctionInitialMap(Register function,
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// -------------------------------------------------------------------------
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// JavaScript invokes.
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// Setup call kind marking in t1. The method takes t1 as an
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// explicit first parameter to make the code more readable at the
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void SetCallKind(Register dst, CallKind kind);
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// Invoke the JavaScript function code by either calling or jumping.
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void InvokeCode(Register code,
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const ParameterCount& expected,
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const ParameterCount& actual,
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const CallWrapper& call_wrapper,
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void InvokeCode(Handle<Code> code,
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const ParameterCount& expected,
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const ParameterCount& actual,
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RelocInfo::Mode rmode,
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// Invoke the JavaScript function in the given register. Changes the
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// current context to the context in the function before invoking.
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void InvokeFunction(Register function,
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const ParameterCount& actual,
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const CallWrapper& call_wrapper,
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void InvokeFunction(JSFunction* function,
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const ParameterCount& actual,
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void IsObjectJSObjectType(Register heap_object,
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void IsInstanceJSObjectType(Register map,
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void IsObjectJSStringType(Register object,
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#ifdef ENABLE_DEBUGGER_SUPPORT
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// Exception handling.
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// Push a new try handler and link into try handler chain.
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// The return address must be passed in register ra.
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// Clobber t0, t1, t2.
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void PushTryHandler(CodeLocation try_location, HandlerType type);
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// Unlink the stack handler on top of the stack from the try handler chain.
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// Must preserve the result register.
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void PopTryHandler();
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// Passes thrown value (in v0) to the handler of top of the try handler chain.
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void Throw(Register value);
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// Propagates an uncatchable exception to the top of the current JS stack's
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void ThrowUncatchable(UncatchableExceptionType type, Register value);
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// Copies a fixed number of fields of heap objects from src to dst.
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void CopyFields(Register dst, Register src, RegList temps, int field_count);
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// Copies a number of bytes from src to dst. All registers are clobbered. On
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// exit src and dst will point to the place just after where the last byte was
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// read or written and length will be zero.
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void CopyBytes(Register src,
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// -------------------------------------------------------------------------
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// Support functions.
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// Try to get function prototype of a function and puts the value in
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// the result register. Checks that the function really is a
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// function and jumps to the miss label if the fast checks fail. The
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// function register will be untouched; the other registers may be
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void TryGetFunctionPrototype(Register function,
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void GetObjectType(Register function,
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// Check if a map for a JSObject indicates that the object has fast elements.
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// Jump to the specified label if it does not.
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void CheckFastElements(Register map,
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// Check if the map of an object is equal to a specified map (either
729
// given directly or as an index into the root list) and branch to
730
// label if not. Skip the smi check if not required (object is known
731
// to be a heap object).
732
void CheckMap(Register obj,
736
SmiCheckType smi_check_type);
738
void CheckMap(Register obj,
740
Heap::RootListIndex index,
742
SmiCheckType smi_check_type);
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// Check if the map of an object is equal to a specified map and branch to a
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// specified target if equal. Skip the smi check if not required (object is
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// known to be a heap object)
747
void DispatchMap(Register obj,
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Handle<Code> success,
751
SmiCheckType smi_check_type);
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// Generates code for reporting that an illegal operation has
755
void IllegalOperation(int num_arguments);
757
// Picks out an array index from the hash field.
759
// hash - holds the index's hash. Clobbered.
760
// index - holds the overwritten index on exit.
761
void IndexFromHash(Register hash, Register index);
763
// Get the number of least significant bits from a register.
764
void GetLeastBitsFromSmi(Register dst, Register src, int num_least_bits);
765
void GetLeastBitsFromInt32(Register dst, Register src, int mun_least_bits);
767
// Load the value of a number object into a FPU double register. If the
768
// object is not a number a jump to the label not_number is performed
769
// and the FPU double register is unchanged.
770
void ObjectToDoubleFPURegister(
775
Register heap_number_map,
777
ObjectToDoubleFlags flags = NO_OBJECT_TO_DOUBLE_FLAGS);
779
// Load the value of a smi object into a FPU double register. The register
780
// scratch1 can be the same register as smi in which case smi will hold the
781
// untagged value afterwards.
782
void SmiToDoubleFPURegister(Register smi,
786
// -------------------------------------------------------------------------
787
// Overflow handling functions.
788
// Usage: first call the appropriate arithmetic function, then call one of the
789
// jump functions with the overflow_dst register as the second parameter.
791
void AdduAndCheckForOverflow(Register dst,
794
Register overflow_dst,
795
Register scratch = at);
797
void SubuAndCheckForOverflow(Register dst,
800
Register overflow_dst,
801
Register scratch = at);
803
void BranchOnOverflow(Label* label,
804
Register overflow_check,
805
BranchDelaySlot bd = PROTECT) {
806
Branch(label, lt, overflow_check, Operand(zero_reg), bd);
809
void BranchOnNoOverflow(Label* label,
810
Register overflow_check,
811
BranchDelaySlot bd = PROTECT) {
812
Branch(label, ge, overflow_check, Operand(zero_reg), bd);
815
void RetOnOverflow(Register overflow_check, BranchDelaySlot bd = PROTECT) {
816
Ret(lt, overflow_check, Operand(zero_reg), bd);
819
void RetOnNoOverflow(Register overflow_check, BranchDelaySlot bd = PROTECT) {
820
Ret(ge, overflow_check, Operand(zero_reg), bd);
823
// -------------------------------------------------------------------------
827
void CallStub(CodeStub* stub, Condition cond = cc_always,
828
Register r1 = zero_reg, const Operand& r2 = Operand(zero_reg));
830
// Call a code stub and return the code object called. Try to generate
831
// the code if necessary. Do not perform a GC but instead return a retry
833
MUST_USE_RESULT MaybeObject* TryCallStub(CodeStub* stub,
834
Condition cond = cc_always,
835
Register r1 = zero_reg,
839
// Tail call a code stub (jump).
840
void TailCallStub(CodeStub* stub);
842
// Tail call a code stub (jump) and return the code object called. Try to
843
// generate the code if necessary. Do not perform a GC but instead return
844
// a retry after GC failure.
845
MUST_USE_RESULT MaybeObject* TryTailCallStub(CodeStub* stub,
846
Condition cond = cc_always,
847
Register r1 = zero_reg,
851
void CallJSExitStub(CodeStub* stub);
853
// Call a runtime routine.
854
void CallRuntime(const Runtime::Function* f, int num_arguments);
855
void CallRuntimeSaveDoubles(Runtime::FunctionId id);
857
// Convenience function: Same as above, but takes the fid instead.
858
void CallRuntime(Runtime::FunctionId fid, int num_arguments);
860
// Convenience function: call an external reference.
861
void CallExternalReference(const ExternalReference& ext,
864
// Tail call of a runtime routine (jump).
865
// Like JumpToExternalReference, but also takes care of passing the number
867
void TailCallExternalReference(const ExternalReference& ext,
871
// Tail call of a runtime routine (jump). Try to generate the code if
872
// necessary. Do not perform a GC but instead return a retry after GC
874
MUST_USE_RESULT MaybeObject* TryTailCallExternalReference(
875
const ExternalReference& ext, int num_arguments, int result_size);
877
// Convenience function: tail call a runtime routine (jump).
878
void TailCallRuntime(Runtime::FunctionId fid,
882
// Before calling a C-function from generated code, align arguments on stack
883
// and add space for the four mips argument slots.
884
// After aligning the frame, non-register arguments must be stored on the
885
// stack, after the argument-slots using helper: CFunctionArgumentOperand().
886
// The argument count assumes all arguments are word sized.
887
// Some compilers/platforms require the stack to be aligned when calling
889
// Needs a scratch register to do some arithmetic. This register will be
891
void PrepareCallCFunction(int num_arguments, Register scratch);
893
// Arguments 1-4 are placed in registers a0 thru a3 respectively.
894
// Arguments 5..n are stored to stack using following:
895
// sw(t0, CFunctionArgumentOperand(5));
897
// Calls a C function and cleans up the space for arguments allocated
898
// by PrepareCallCFunction. The called function is not allowed to trigger a
899
// garbage collection, since that might move the code and invalidate the
900
// return address (unless this is somehow accounted for by the called
902
void CallCFunction(ExternalReference function, int num_arguments);
903
void CallCFunction(Register function, Register scratch, int num_arguments);
904
void GetCFunctionDoubleResult(const DoubleRegister dst);
906
// There are two ways of passing double arguments on MIPS, depending on
907
// whether soft or hard floating point ABI is used. These functions
908
// abstract parameter passing for the three different ways we call
909
// C functions from generated code.
910
void SetCallCDoubleArguments(DoubleRegister dreg);
911
void SetCallCDoubleArguments(DoubleRegister dreg1, DoubleRegister dreg2);
912
void SetCallCDoubleArguments(DoubleRegister dreg, Register reg);
914
// Calls an API function. Allocates HandleScope, extracts returned value
915
// from handle and propagates exceptions. Restores context.
916
MaybeObject* TryCallApiFunctionAndReturn(ExternalReference function,
919
// Jump to the builtin routine.
920
void JumpToExternalReference(const ExternalReference& builtin);
922
MaybeObject* TryJumpToExternalReference(const ExternalReference& ext);
924
// Invoke specified builtin JavaScript function. Adds an entry to
925
// the unresolved list if the name does not resolve.
926
void InvokeBuiltin(Builtins::JavaScript id,
928
const CallWrapper& call_wrapper = NullCallWrapper());
930
// Store the code object for the given builtin in the target register and
931
// setup the function in a1.
932
void GetBuiltinEntry(Register target, Builtins::JavaScript id);
934
// Store the function for the given builtin in the target register.
935
void GetBuiltinFunction(Register target, Builtins::JavaScript id);
939
uint32_t flags; // See Bootstrapper::FixupFlags decoders/encoders.
943
Handle<Object> CodeObject() {
944
ASSERT(!code_object_.is_null());
948
// -------------------------------------------------------------------------
949
// StatsCounter support.
951
void SetCounter(StatsCounter* counter, int value,
952
Register scratch1, Register scratch2);
953
void IncrementCounter(StatsCounter* counter, int value,
954
Register scratch1, Register scratch2);
955
void DecrementCounter(StatsCounter* counter, int value,
956
Register scratch1, Register scratch2);
959
// -------------------------------------------------------------------------
962
// Calls Abort(msg) if the condition cc is not satisfied.
963
// Use --debug_code to enable.
964
void Assert(Condition cc, const char* msg, Register rs, Operand rt);
965
void AssertRegisterIsRoot(Register reg, Heap::RootListIndex index);
966
void AssertFastElements(Register elements);
968
// Like Assert(), but always enabled.
969
void Check(Condition cc, const char* msg, Register rs, Operand rt);
971
// Print a message to stdout and abort execution.
972
void Abort(const char* msg);
974
// Verify restrictions about code generated in stubs.
975
void set_generating_stub(bool value) { generating_stub_ = value; }
976
bool generating_stub() { return generating_stub_; }
977
void set_allow_stub_calls(bool value) { allow_stub_calls_ = value; }
978
bool allow_stub_calls() { return allow_stub_calls_; }
980
// ---------------------------------------------------------------------------
983
// Check whether the value of reg is a power of two and not zero. If not
984
// control continues at the label not_power_of_two. If reg is a power of two
985
// the register scratch contains the value of (reg - 1) when control falls
987
void JumpIfNotPowerOfTwoOrZero(Register reg,
989
Label* not_power_of_two_or_zero);
991
// -------------------------------------------------------------------------
994
// Try to convert int32 to smi. If the value is to large, preserve
995
// the original value and jump to not_a_smi. Destroys scratch and
997
// This is only used by crankshaft atm so it is unimplemented on MIPS.
998
void TrySmiTag(Register reg, Label* not_a_smi, Register scratch) {
999
UNIMPLEMENTED_MIPS();
1002
void SmiTag(Register reg) {
1003
Addu(reg, reg, reg);
1006
void SmiTag(Register dst, Register src) {
1007
Addu(dst, src, src);
1010
void SmiUntag(Register reg) {
1011
sra(reg, reg, kSmiTagSize);
1014
void SmiUntag(Register dst, Register src) {
1015
sra(dst, src, kSmiTagSize);
1018
// Jump the register contains a smi.
1019
inline void JumpIfSmi(Register value, Label* smi_label,
1020
Register scratch = at) {
1021
ASSERT_EQ(0, kSmiTag);
1022
andi(scratch, value, kSmiTagMask);
1023
Branch(smi_label, eq, scratch, Operand(zero_reg));
1026
// Jump if the register contains a non-smi.
1027
inline void JumpIfNotSmi(Register value, Label* not_smi_label,
1028
Register scratch = at) {
1029
ASSERT_EQ(0, kSmiTag);
1030
andi(scratch, value, kSmiTagMask);
1031
Branch(not_smi_label, ne, scratch, Operand(zero_reg));
1034
// Jump if either of the registers contain a non-smi.
1035
void JumpIfNotBothSmi(Register reg1, Register reg2, Label* on_not_both_smi);
1036
// Jump if either of the registers contain a smi.
1037
void JumpIfEitherSmi(Register reg1, Register reg2, Label* on_either_smi);
1039
// Abort execution if argument is a smi. Used in debug code.
1040
void AbortIfSmi(Register object);
1041
void AbortIfNotSmi(Register object);
1043
// Abort execution if argument is a string. Used in debug code.
1044
void AbortIfNotString(Register object);
1046
// Abort execution if argument is not the root value with the given index.
1047
void AbortIfNotRootValue(Register src,
1048
Heap::RootListIndex root_value_index,
1049
const char* message);
1051
// ---------------------------------------------------------------------------
1052
// HeapNumber utilities.
1054
void JumpIfNotHeapNumber(Register object,
1055
Register heap_number_map,
1057
Label* on_not_heap_number);
1059
// -------------------------------------------------------------------------
1060
// String utilities.
1062
// Checks if both instance types are sequential ASCII strings and jumps to
1063
// label if either is not.
1064
void JumpIfBothInstanceTypesAreNotSequentialAscii(
1065
Register first_object_instance_type,
1066
Register second_object_instance_type,
1071
// Check if instance type is sequential ASCII string and jump to label if
1073
void JumpIfInstanceTypeIsNotSequentialAscii(Register type,
1077
// Test that both first and second are sequential ASCII strings.
1078
// Assume that they are non-smis.
1079
void JumpIfNonSmisNotBothSequentialAsciiStrings(Register first,
1085
// Test that both first and second are sequential ASCII strings.
1086
// Check that they are non-smis.
1087
void JumpIfNotBothSequentialAsciiStrings(Register first,
1093
void LoadInstanceDescriptors(Register map, Register descriptors);
1096
void CallCFunctionHelper(Register function,
1097
ExternalReference function_reference,
1101
void BranchShort(int16_t offset, BranchDelaySlot bdslot = PROTECT);
1102
void BranchShort(int16_t offset, Condition cond, Register rs,
1104
BranchDelaySlot bdslot = PROTECT);
1105
void BranchShort(Label* L, BranchDelaySlot bdslot = PROTECT);
1106
void BranchShort(Label* L, Condition cond, Register rs,
1108
BranchDelaySlot bdslot = PROTECT);
1109
void BranchAndLinkShort(int16_t offset, BranchDelaySlot bdslot = PROTECT);
1110
void BranchAndLinkShort(int16_t offset, Condition cond, Register rs,
1112
BranchDelaySlot bdslot = PROTECT);
1113
void BranchAndLinkShort(Label* L, BranchDelaySlot bdslot = PROTECT);
1114
void BranchAndLinkShort(Label* L, Condition cond, Register rs,
1116
BranchDelaySlot bdslot = PROTECT);
1117
void J(Label* L, BranchDelaySlot bdslot);
1118
void Jr(Label* L, BranchDelaySlot bdslot);
1119
void Jalr(Label* L, BranchDelaySlot bdslot);
1121
// Helper functions for generating invokes.
1122
void InvokePrologue(const ParameterCount& expected,
1123
const ParameterCount& actual,
1124
Handle<Code> code_constant,
1128
const CallWrapper& call_wrapper,
1129
CallKind call_kind);
1131
// Get the code for the given builtin. Returns if able to resolve
1132
// the function in the 'resolved' flag.
1133
Handle<Code> ResolveBuiltin(Builtins::JavaScript id, bool* resolved);
1135
// Activation support.
1136
void EnterFrame(StackFrame::Type type);
1137
void LeaveFrame(StackFrame::Type type);
1139
void InitializeNewString(Register string,
1141
Heap::RootListIndex map_index,
1145
// Compute memory operands for safepoint stack slots.
1146
static int SafepointRegisterStackIndex(int reg_code);
1147
MemOperand SafepointRegisterSlot(Register reg);
1148
MemOperand SafepointRegistersAndDoublesSlot(Register reg);
1150
bool UseAbsoluteCodePointers();
1152
bool generating_stub_;
1153
bool allow_stub_calls_;
1154
// This handle will be patched with the code object on installation.
1155
Handle<Object> code_object_;
1157
// Needs access to SafepointRegisterStackIndex for optimized frame
1159
friend class OptimizedFrame;
1163
// The code patcher is used to patch (typically) small parts of code e.g. for
1164
// debugging and other types of instrumentation. When using the code patcher
1165
// the exact number of bytes specified must be emitted. It is not legal to emit
1166
// relocation information. If any of these constraints are violated it causes
1167
// an assertion to fail.
1170
CodePatcher(byte* address, int instructions);
1171
virtual ~CodePatcher();
1173
// Macro assembler to emit code.
1174
MacroAssembler* masm() { return &masm_; }
1176
// Emit an instruction directly.
1177
void Emit(Instr instr);
1179
// Emit an address directly.
1180
void Emit(Address addr);
1182
// Change the condition part of an instruction leaving the rest of the current
1183
// instruction unchanged.
1184
void ChangeBranchCondition(Condition cond);
1187
byte* address_; // The address of the code being patched.
1188
int instructions_; // Number of instructions of the expected patch size.
1189
int size_; // Number of bytes of the expected patch size.
1190
MacroAssembler masm_; // Macro assembler used to generate the code.
1194
// -----------------------------------------------------------------------------
1195
// Static helper functions.
1197
static MemOperand ContextOperand(Register context, int index) {
1198
return MemOperand(context, Context::SlotOffset(index));
1202
static inline MemOperand GlobalObjectOperand() {
1203
return ContextOperand(cp, Context::GLOBAL_INDEX);
1207
// Generate a MemOperand for loading a field from an object.
1208
static inline MemOperand FieldMemOperand(Register object, int offset) {
1209
return MemOperand(object, offset - kHeapObjectTag);
1213
// Generate a MemOperand for storing arguments 5..N on the stack
1214
// when calling CallCFunction().
1215
static inline MemOperand CFunctionArgumentOperand(int index) {
1216
ASSERT(index > kCArgSlotCount);
1217
// Argument 5 takes the slot just past the four Arg-slots.
1218
int offset = (index - 5) * kPointerSize + kCArgsSlotsSize;
1219
return MemOperand(sp, offset);
1223
#ifdef GENERATED_CODE_COVERAGE
1224
#define CODE_COVERAGE_STRINGIFY(x) #x
1225
#define CODE_COVERAGE_TOSTRING(x) CODE_COVERAGE_STRINGIFY(x)
1226
#define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__)
1227
#define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm->
1229
#define ACCESS_MASM(masm) masm->
1232
} } // namespace v8::internal
1234
#endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
added
removed
.pc/0015_hash-collision-fix-v8-3.6.patch/src/mips/macro-assembler-mips.h
