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Viewing changes to arch/avr32/mach-at32ap/at32ap700x.c

  • Committer: Bazaar Package Importer
  • Author(s): John Rigby, Upstream Fixes, Andy Green, John Rigby
  • Date: 2011-04-14 12:16:06 UTC
  • Revision ID: james.westby@ubuntu.com-20110414121606-b77podkyqgr2oix7
Tags: 2.6.38-1002.3
[ Upstream Fixes ]

* MUSB: shutdown: Make sure block is awake before doing shutdown
  - LP: #745737
* Fixed gpio polarity of gpio USB-phy reset.
  - LP: #747639

[ Andy Green ]

* LINARO: SAUCE: disable CONFIG_OMAP_RESET_CLOCKS
  - LP: #752900

[ John Rigby ]

* Rebase to new upstreams:
  Linux v2.6.38.1
  linaro-linux-2.6.38-upstream-29Mar2011
  Ubuntu-2.6.38-7.35
* SAUCE: OMAP4: clock: wait for module to become accessible on
  a clk enable
  - LP: #745737
* Rebase to new upstreams:
  Linux v2.6.38.2
  linaro-linux-2.6.38-upstream-5Apr2011
  Ubuntu-2.6.38-8.41
  - LP: #732842
* Update configs for device tree, dvfs and lttng
* LINARO: add building of dtb's
* LINARO: SAUCE: Disable lowest operating freqs on omap34xx
  - LP: #732912

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                rx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
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                rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3);
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                rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
 
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                rx_dws->src_master = 0;
 
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                rx_dws->dst_master = 1;
 
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                rx_dws->src_msize = DW_DMA_MSIZE_1;
 
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                rx_dws->dst_msize = DW_DMA_MSIZE_1;
 
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                rx_dws->fc = DW_DMA_FC_D_P2M;
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        }
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        /* Check if DMA slave interface for playback should be configured. */
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                tx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
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                tx_dws->cfg_hi = DWC_CFGH_DST_PER(4);
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                tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
 
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                tx_dws->src_master = 0;
 
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                tx_dws->dst_master = 1;
 
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                tx_dws->src_msize = DW_DMA_MSIZE_1;
 
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                tx_dws->dst_msize = DW_DMA_MSIZE_1;
 
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                tx_dws->fc = DW_DMA_FC_D_M2P;
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        }
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        if (platform_device_add_data(pdev, data,
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        dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
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        dws->cfg_hi = DWC_CFGH_DST_PER(2);
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        dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
 
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        dws->src_master = 0;
 
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        dws->dst_master = 1;
 
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        dws->src_msize = DW_DMA_MSIZE_1;
 
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        dws->dst_msize = DW_DMA_MSIZE_1;
 
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        dws->fc = DW_DMA_FC_D_M2P;
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        if (platform_device_add_data(pdev, data,
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                                sizeof(struct atmel_abdac_pdata)))