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Viewing changes to ubuntu/rtl8192se/rtl_dm.h

  • Committer: Bazaar Package Importer
  • Author(s): Stefan Bader, Amit Kucheria
  • Date: 2010-03-23 18:05:12 UTC
  • Revision ID: james.westby@ubuntu.com-20100323180512-iavj906ocnphdubp
Tags: 2.6.33-500.3
[ Amit Kucheria ]

* [Config] Fix the debug package name to end in -dbgsym
* SAUCE: Add the ubuntu/ drivers to omap
* SAUCE: Re-export the symbols for aufs
* [Config] Enable AUFS and COMPCACHE

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ubuntu/rtl8192se/rtl_dm.h
 
1
/******************************************************************************
 
2
 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
 
3
 *
 
4
 * This program is distributed in the hope that it will be useful, but WITHOUT
 
5
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 
6
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 
7
 * more details.
 
8
 *
 
9
 * You should have received a copy of the GNU General Public License along with
 
10
 * this program; if not, write to the Free Software Foundation, Inc.,
 
11
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 
12
 *
 
13
 * The full GNU General Public License is included in this distribution in the
 
14
 * file called LICENSE.
 
15
 *
 
16
 * Contact Information:
 
17
 * wlanfae <wlanfae@realtek.com>
 
18
******************************************************************************/
 
19
#ifndef __R8192UDM_H__
 
20
#define __R8192UDM_H__
 
21
 
 
22
 
 
23
/*--------------------------Define Parameters-------------------------------*/
 
24
#define                 OFDM_Table_Length       19
 
25
#define         CCK_Table_length        12
 
26
 
 
27
#define         DM_DIG_THRESH_HIGH                                      40
 
28
#define         DM_DIG_THRESH_LOW                                       35
 
29
 
 
30
#define         DM_FALSEALARM_THRESH_LOW        40
 
31
#define         DM_FALSEALARM_THRESH_HIGH       1000
 
32
 
 
33
#define         DM_DIG_HIGH_PWR_THRESH_HIGH             75
 
34
#define         DM_DIG_HIGH_PWR_THRESH_LOW              70
 
35
 
 
36
#define         BW_AUTO_SWITCH_HIGH_LOW                 25
 
37
#define         BW_AUTO_SWITCH_LOW_HIGH                 30
 
38
 
 
39
#define         DM_check_fsync_time_interval                            500
 
40
 
 
41
 
 
42
#define         DM_DIG_BACKOFF                          12
 
43
#ifdef RTL8192SE
 
44
#define         DM_DIG_MAX                                      0x3e
 
45
#elif defined RTL8190P || defined RTL8192E
 
46
#define         DM_DIG_MAX                                      0x36
 
47
#endif
 
48
#define         DM_DIG_MIN                                      0x1c
 
49
#define         DM_DIG_MIN_Netcore                      0x12
 
50
 
 
51
#define         DM_DIG_BACKOFF_MAX                      12
 
52
#define         DM_DIG_BACKOFF_MIN                      -4
 
53
 
 
54
#define         RxPathSelection_SS_TH_low               30
 
55
#define         RxPathSelection_diff_TH                 18
 
56
 
 
57
#define         RateAdaptiveTH_High                     50
 
58
#define         RateAdaptiveTH_Low_20M          30
 
59
#define         RateAdaptiveTH_Low_40M          10
 
60
#define         VeryLowRSSI                                     15
 
61
 
 
62
#ifdef RTL8192SE
 
63
#define         CTSToSelfTHVal                          30
 
64
#elif defined RTL8190P || defined RTL8192E
 
65
#define         CTSToSelfTHVal                                  35
 
66
#endif
 
67
 
 
68
#define         WAIotTHVal                                              25
 
69
 
 
70
#define         E_FOR_TX_POWER_TRACK               300
 
71
#define         TX_POWER_NEAR_FIELD_THRESH_HIGH         68
 
72
#define         TX_POWER_NEAR_FIELD_THRESH_LOW          62
 
73
#define         TX_POWER_ATHEROAP_THRESH_HIGH           78
 
74
#define         TX_POWER_ATHEROAP_THRESH_LOW            72
 
75
 
 
76
#define                 Current_Tx_Rate_Reg         0x1e0
 
77
#define                 Initial_Tx_Rate_Reg         0x1e1 
 
78
#define                 Tx_Retry_Count_Reg         0x1ac
 
79
#define         RegC38_TH                                20
 
80
 
 
81
#define         TX_POWER_NEAR_FIELD_THRESH_LVL2 74
 
82
#define         TX_POWER_NEAR_FIELD_THRESH_LVL1 67
 
83
 
 
84
#define         TxHighPwrLevel_Normal           0       
 
85
#define         TxHighPwrLevel_Level1           1
 
86
#define         TxHighPwrLevel_Level2           2
 
87
 
 
88
#define         DM_Type_ByFW                    0
 
89
#define         DM_Type_ByDriver                1
 
90
 
 
91
/*--------------------------Define Parameters-------------------------------*/
 
92
 
 
93
 
 
94
/*------------------------------Define structure----------------------------*/ 
 
95
typedef struct _dynamic_initial_gain_threshold_
 
96
{
 
97
        u8              dig_enable_flag;
 
98
        u8              dig_algorithm;
 
99
        u8              Dig_TwoPort_Algorithm;
 
100
        u8              Dig_Ext_Port_Stage;
 
101
        u8              dbg_mode;
 
102
        u8              dig_algorithm_switch;
 
103
        
 
104
        long            rssi_low_thresh;
 
105
        long            rssi_high_thresh;
 
106
 
 
107
        u32             FALowThresh;
 
108
        u32             FAHighThresh;
 
109
        
 
110
        long            rssi_high_power_lowthresh;
 
111
        long            rssi_high_power_highthresh;
 
112
 
 
113
        u8              dig_state;
 
114
        u8              dig_highpwr_state;
 
115
        u8              CurSTAConnectState;
 
116
        u8              PreSTAConnectState;
 
117
        u8              CurAPConnectState;
 
118
        u8              PreAPConnectState;
 
119
 
 
120
        u8              curpd_thstate;
 
121
        u8              prepd_thstate;
 
122
        u8              curcs_ratio_state;
 
123
        u8              precs_ratio_state;
 
124
 
 
125
        u32             pre_ig_value;
 
126
        u32             cur_ig_value;
 
127
 
 
128
        u8              Backoff_Enable_Flag;
 
129
        u8              backoff_val;
 
130
        char            BackoffVal_range_max;
 
131
        char            BackoffVal_range_min;
 
132
        u8              rx_gain_range_max;
 
133
        u8              rx_gain_range_min;
 
134
        bool            initialgain_lowerbound_state;
 
135
 
 
136
        long            rssi_val;
 
137
}dig_t;
 
138
 
 
139
typedef enum tag_dynamic_init_gain_state_definition
 
140
{
 
141
        DM_STA_DIG_OFF = 0,     
 
142
        DM_STA_DIG_ON,          
 
143
        DM_STA_DIG_MAX
 
144
}dm_dig_sta_e;
 
145
 
 
146
 
 
147
typedef enum tag_dynamic_ratr_state_definition
 
148
{
 
149
        DM_RATR_STA_HIGH = 0,
 
150
        DM_RATR_STA_MIDDLE = 1,
 
151
        DM_RATR_STA_LOW = 2,
 
152
        DM_RATR_STA_MAX
 
153
}dm_ratr_sta_e;
 
154
 
 
155
typedef enum tag_dynamic_init_gain_operation_type_definition
 
156
{
 
157
        DIG_TYPE_THRESH_HIGH    = 0,
 
158
        DIG_TYPE_THRESH_LOW     = 1,
 
159
        DIG_TYPE_THRESH_HIGHPWR_HIGH    = 2,
 
160
        DIG_TYPE_THRESH_HIGHPWR_LOW     = 3,
 
161
        DIG_TYPE_DBG_MODE                               = 4,
 
162
        DIG_TYPE_RSSI                                           = 5,
 
163
        DIG_TYPE_ALGORITHM                              = 6,
 
164
        DIG_TYPE_BACKOFF                                        = 7,
 
165
        DIG_TYPE_PWDB_FACTOR                    = 8,
 
166
        DIG_TYPE_RX_GAIN_MIN                            = 9,
 
167
        DIG_TYPE_RX_GAIN_MAX                            = 10,
 
168
        DIG_TYPE_ENABLE                 = 20,
 
169
        DIG_TYPE_DISABLE                = 30,
 
170
        DIG_OP_TYPE_MAX
 
171
}dm_dig_op_e;
 
172
 
 
173
typedef enum tag_dig_algorithm_definition
 
174
{
 
175
        DIG_ALGO_BY_FALSE_ALARM = 0,    
 
176
        DIG_ALGO_BY_RSSI        = 1,
 
177
        DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM = 2,
 
178
        DIG_ALGO_BY_TOW_PORT = 3,
 
179
        DIG_ALGO_MAX
 
180
}dm_dig_alg_e;
 
181
 
 
182
typedef enum tag_DIG_TWO_PORT_ALGO_Definition
 
183
{
 
184
        DIG_TWO_PORT_ALGO_RSSI = 0,
 
185
        DIG_TWO_PORT_ALGO_FALSE_ALARM = 1,
 
186
}DM_DIG_TWO_PORT_ALG_E;
 
187
 
 
188
 
 
189
typedef enum tag_DIG_EXT_PORT_ALGO_Definition
 
190
{
 
191
        DIG_EXT_PORT_STAGE_0 = 0,
 
192
        DIG_EXT_PORT_STAGE_1 = 1,
 
193
        DIG_EXT_PORT_STAGE_2 = 2,
 
194
        DIG_EXT_PORT_STAGE_3 = 3,
 
195
        DIG_EXT_PORT_STAGE_MAX = 4,
 
196
}DM_DIG_EXT_PORT_ALG_E;
 
197
 
 
198
typedef enum tag_dig_dbgmode_definition
 
199
{
 
200
        DIG_DBG_OFF = 0,        
 
201
        DIG_DBG_ON = 1,
 
202
        DIG_DBG_MAX
 
203
}dm_dig_dbg_e;
 
204
 
 
205
typedef enum tag_dig_connect_definition
 
206
{
 
207
        DIG_STA_DISCONNECT = 0, 
 
208
        DIG_STA_CONNECT = 1,
 
209
        DIG_STA_BEFORE_CONNECT = 2,
 
210
        DIG_AP_DISCONNECT = 3,
 
211
        DIG_AP_CONNECT = 4, 
 
212
        DIG_AP_ADD_STATION = 5,
 
213
        DIG_CONNECT_MAX
 
214
}dm_dig_connect_e;
 
215
 
 
216
typedef enum tag_dig_packetdetection_threshold_definition
 
217
{
 
218
        DIG_PD_AT_LOW_POWER = 0,        
 
219
        DIG_PD_AT_NORMAL_POWER = 1,
 
220
        DIG_PD_AT_HIGH_POWER = 2,
 
221
        DIG_PD_MAX
 
222
}dm_dig_pd_th_e;
 
223
 
 
224
typedef enum tag_dig_cck_cs_ratio_state_definition
 
225
{
 
226
        DIG_CS_RATIO_LOWER = 0, 
 
227
        DIG_CS_RATIO_HIGHER = 1,
 
228
        DIG_CS_MAX
 
229
}dm_dig_cs_ratio_e;
 
230
typedef struct _Dynamic_Rx_Path_Selection_
 
231
{
 
232
        u8              Enable;
 
233
        u8              DbgMode;
 
234
        u8              cck_method;
 
235
        u8              cck_Rx_path;
 
236
 
 
237
        u8              SS_TH_low;
 
238
        u8              diff_TH;
 
239
        u8              disabledRF;
 
240
        u8              reserved;
 
241
        
 
242
        u8              rf_rssi[4];
 
243
        u8              rf_enable_rssi_th[4];
 
244
        long            cck_pwdb_sta[4];
 
245
}DRxPathSel;
 
246
 
 
247
typedef enum tag_CCK_Rx_Path_Method_Definition
 
248
{
 
249
        CCK_Rx_Version_1 = 0,   
 
250
        CCK_Rx_Version_2= 1,
 
251
        CCK_Rx_Version_MAX
 
252
}DM_CCK_Rx_Path_Method;
 
253
 
 
254
 
 
255
typedef enum tag_DM_DbgMode_Definition
 
256
{
 
257
        DM_DBG_OFF = 0, 
 
258
        DM_DBG_ON = 1,
 
259
        DM_DBG_MAX
 
260
}DM_DBG_E;
 
261
 
 
262
typedef struct tag_Tx_Config_Cmd_Format
 
263
{
 
264
        u32     Op;                                     
 
265
        u32     Length;                                 
 
266
        u32     Value;
 
267
}DCMD_TXCMD_T, *PDCMD_TXCMD_T;
 
268
/*------------------------------Define structure----------------------------*/ 
 
269
 
 
270
 
 
271
/*------------------------Export global variable----------------------------*/
 
272
extern  dig_t   dm_digtable;
 
273
extern  u8              dm_shadow[16][256];
 
274
extern DRxPathSel      DM_RxPathSelTable;
 
275
 
 
276
extern  u8                      test_flag;
 
277
/*------------------------Export global variable----------------------------*/
 
278
 
 
279
 
 
280
/*------------------------Export Marco Definition---------------------------*/
 
281
#define DM_APInitGainChangeNotify(Event) {dm_digtable.CurAPConnectState = Event;}
 
282
/*------------------------Export Marco Definition---------------------------*/
 
283
 
 
284
 
 
285
/*--------------------------Exported Function prototype---------------------*/
 
286
/*--------------------------Exported Function prototype---------------------*/
 
287
extern  void    init_hal_dm(struct net_device *dev);
 
288
extern  void deinit_hal_dm(struct net_device *dev);
 
289
 
 
290
extern void hal_dm_watchdog(struct net_device *dev);
 
291
 
 
292
 
 
293
extern  void    init_rate_adaptive(struct net_device *dev);
 
294
extern  void    dm_txpower_trackingcallback(void *data);
 
295
 
 
296
#ifndef RTL8192SE
 
297
extern  void    dm_cck_txpower_adjust(struct net_device *dev,bool  binch14);
 
298
#endif
 
299
 
 
300
extern  void    dm_restore_dynamic_mechanism_state(struct net_device *dev);
 
301
extern  void    dm_backup_dynamic_mechanism_state(struct net_device *dev);
 
302
extern  void    dm_change_dynamic_initgain_thresh(struct net_device *dev,
 
303
                                                                u32             dm_type,
 
304
                                                                u32             dm_value);
 
305
extern  void    DM_ChangeFsyncSetting(struct net_device *dev,
 
306
                                                                                                s32             DM_Type,
 
307
                                                                                                s32             DM_Value);
 
308
extern  void dm_force_tx_fw_info(struct net_device *dev,
 
309
                                                                                u32             force_type,
 
310
                                                                                u32             force_value);
 
311
extern  void    dm_init_edca_turbo(struct net_device *dev);
 
312
extern  void    dm_rf_operation_test_callback(unsigned long data);
 
313
extern  void    dm_rf_pathcheck_workitemcallback(void *data);
 
314
extern  void dm_fsync_timer_callback(unsigned long data);
 
315
#if 0
 
316
extern  bool    dm_check_lbus_status(struct net_device *dev);
 
317
#endif
 
318
extern  void dm_check_fsync(struct net_device *dev);
 
319
extern  void    dm_shadow_init(struct net_device *dev);
 
320
extern  void dm_initialize_txpower_tracking(struct net_device *dev);
 
321
 
 
322
#if (defined RTL8192E || defined RTL8192SE)
 
323
extern  void    dm_CheckRfCtrlGPIO(void *data);
 
324
#endif
 
325
 
 
326
 
 
327
#endif  /*__R8192UDM_H__ */
 
328
 
 
329
 
 
330
/* End of r8192U_dm.h */