1
/******************************************************************************
2
* Copyright (c) 2013 IBM Corporation
4
* This program and the accompanying materials
5
* are made available under the terms of the BSD License
6
* which accompanies this distribution, and is available at
7
* http://www.opensource.org/licenses/bsd-license.php
10
* IBM Corporation - initial implementation
11
*****************************************************************************/
13
* Definitions for XHCI Controller - Revision 1.0 (5/21/10)
23
#define BIT(x) (1 << x)
25
/* 5.3 Host Controller Capability Registers
28
struct xhci_cap_regs {
36
#define XHCI_HCCPARAMS_CSZ BIT(2)
39
} __attribute__ ((packed));
41
/* Table 27: Host Controller USB Port Register Set */
42
struct xhci_port_regs {
44
#define PORTSC_CCS BIT(0)
45
#define PORTSC_PED BIT(1)
46
#define PORTSC_OCA BIT(3)
47
#define PORTSC_PR BIT(4)
48
#define PORTSC_PLS_MASK (0xF << 5)
49
#define PORTSC_PLS_U0 0
50
#define PORTSC_PLS_U1 1
51
#define PORTSC_PLS_U2 2
52
#define PORTSC_PLS_U3 3
53
#define PORTSC_PLS_DISABLED 4
54
#define PORTSC_PLS_RXDETECT 5
55
#define PORTSC_PLS_INACTIVE 6
56
#define PORTSC_PLS_POLLING 7
57
#define PORTSC_PLS_RECOVERY 8
58
#define PORTSC_PLS_HOTRESET 9
59
#define PORTSC_PLS_COMP_MODE 10
60
#define PORTSC_PLS_TEST_MODE 11
61
#define PORTSC_PLS_RESUME 15
62
#define PORTSC_PP BIT(9)
63
#define PORTSC_PS_MASK (0xF << 10)
64
#define PORTSC_PIC_MASK (0x3 << 14)
65
#define PORTSC_LWS BIT(16)
66
#define PORTSC_CSC BIT(17)
67
#define PORTSC_PEC BIT(18)
68
#define PORTSC_WRC BIT(19)
69
#define PORTSC_OCC BIT(20)
70
#define PORTSC_PRC BIT(21)
71
#define PORTSC_PLC BIT(22)
72
#define PORTSC_CEC BIT(23)
73
#define PORTSC_CAS BIT(24)
74
#define PORTSC_WCE BIT(25)
75
#define PORTSC_WDE BIT(26)
76
#define PORTSC_WOE BIT(27)
77
#define PORTSC_DR BIT(30)
78
#define PORTSC_WPR BIT(31)
83
} __attribute__ ((packed));
95
struct port_state ps_array_usb2[] = {
96
{1, 0, 0, 0, PORTSC_PLS_U0, "ERROR"}
99
struct port_state ps_array_usb3[] = {
100
{0, 0, 0, 0, PORTSC_PLS_DISABLED, "Powered-OFF"},
101
{1, 0, 0, 0, PORTSC_PLS_POLLING, "Polling"},
102
{1, 0, 0, 0, PORTSC_PLS_U0, "Polling"},
103
{1, 0, 0, 0, PORTSC_PLS_RXDETECT, "*** Disconnected ***"},
104
{1, 0, 0, 0, PORTSC_PLS_DISABLED, "Disabled"},
105
{1, 0, 0, 0, PORTSC_PLS_INACTIVE, "Error"},
106
{1, 0, 0, 0, PORTSC_PLS_TEST_MODE,"Loopback"},
107
{1, 0, 0, 0, PORTSC_PLS_COMP_MODE,"Compliancek"},
108
{1, 1, 0, 1, PORTSC_PLS_U0, "****** Reset ******"},
109
{1, 1, 1, 0, PORTSC_PLS_U0, "****** Enabled ******"},
112
/* 5.4 Host Controller Operational Registers
115
struct xhci_op_regs {
117
#define XHCI_USBCMD_RS BIT(0)
118
#define XHCI_USBCMD_HCRST BIT(1)
121
#define XHCI_USBSTS_HCH BIT(0)
122
#define XHCI_USBSTS_CNR BIT(11)
125
uint8_t reserved[8]; /* 0C - 13 */
126
uint32_t dnctrl; /* Device notification control */
127
uint64_t crcr; /* Command ring control */
128
#define XHCI_CRCR_CRP_MASK 0xFFFFFFFFFFFFFFC0
129
#define XHCI_CRCR_CRR BIT(3)
130
#define XHCI_CRCR_CRP_SIZE 4096
132
uint8_t reserved1[16]; /* 20 - 2F */
133
uint64_t dcbaap; /* Device Context Base Address Array Pointer */
134
#define XHCI_DCBAAP_MAX_SIZE 2048
136
uint32_t config; /* Configure */
137
#define XHCI_CONFIG_MAX_SLOT 4
139
uint8_t reserved2[964]; /* 3C - 3FF */
140
/* USB Port register set */
141
#define XHCI_PORT_MAX 256
142
struct xhci_port_regs prs[XHCI_PORT_MAX];
143
} __attribute__ ((packed));
146
* 5.5.2 Interrupter Register Set
147
* Table 42: Interrupter Registers
149
struct xhci_int_regs {
153
#define XHCI_ERST_SIZE_MASK 0xFFFF
156
#define XHCI_ERST_ADDR_MASK (~(0x3FUL))
158
#define XHCI_ERDP_MASK (~(0xFUL))
159
} __attribute__ ((packed));
161
/* 5.5 Host Controller Runtime Registers */
162
struct xhci_run_regs {
163
uint32_t mfindex; /* microframe index */
164
uint8_t reserved[28];
165
#define XHCI_IRS_MAX 1024
166
struct xhci_int_regs irs[XHCI_IRS_MAX];
167
} __attribute__ ((packed));
169
/* 5.6 Doorbell Registers*/
170
struct xhci_db_regs {
172
} __attribute__ ((packed));
174
#define COMP_SUCCESS 1
176
#define TRB_SLOT_ID(x) (((x) & (0xFF << 24)) >> 24)
177
#define TRB_CMD_SLOT_ID(x) ((x & 0xFF) << 24)
178
#define TRB_TYPE(x) (((x) & (0x3F << 10)) >> 10)
179
#define TRB_CMD_TYPE(x) ((x & 0x3F) << 10)
180
#define TRB_STATUS(x) (((x) & (0xFF << 24)) >> 24)
181
#define TRB_ADDR_LOW(x) ((uint32_t)((uint64_t)(x)))
182
#define TRB_ADDR_HIGH(x) ((uint32_t)((uint64_t)(x) >> 32))
183
#define TRB_TRT(x) (((x) & 0x3) << 16 )
184
#define TRB_DIR_IN BIT(16)
185
#define TRB_IOC BIT(5)
186
#define TRB_IDT BIT(6)
188
#define TRB_CYCLE_STATE BIT(0)
190
struct xhci_transfer_trb {
194
} __attribute__ ((packed));
196
struct xhci_link_trb {
200
} __attribute__ ((packed));
203
struct xhci_event_trb {
207
} __attribute__ ((packed));
210
#define TRB_SETUP_STAGE 2
211
#define TRB_DATA_STAGE 3
212
#define TRB_STATUS_STAGE 4
215
#define TRB_EVENT_DATA 7
217
#define TRB_ENABLE_SLOT 9
218
#define TRB_DISABLE_SLOT 10
219
#define TRB_ADDRESS_DEV 11
220
#define TRB_CONFIG_EP 12
221
#define TRB_EVAL_CNTX 13
222
#define TRB_TRANSFER_EVENT 32
223
#define TRB_CMD_COMPLETION 33
224
#define TRB_PORT_STATUS 34
226
struct xhci_command_trb {
228
}__attribute__ ((packed));
231
struct xhci_event_trb event;
232
struct xhci_transfer_trb xfer;
233
struct xhci_command_trb cmd;
234
struct xhci_link_trb link;
245
union xhci_trb *trbs;
246
struct xhci_seg *next;
251
uint32_t cycle_state;
252
enum xhci_seg_type type;
255
#define XHCI_TRB_SIZE 16
256
#define XHCI_EVENT_TRBS_SIZE 4096
257
#define XHCI_CONTROL_TRBS_SIZE 4096
258
#define XHCI_DATA_TRBS_SIZE 4096
259
#define XHCI_ERST_NUM_SEGS 1
261
#define XHCI_MAX_BULK_SIZE 0xF000
263
struct xhci_erst_entry {
267
} __attribute__ ((packed));
270
struct xhci_erst_entry *entries;
272
uint32_t num_segs; /* number of segments */
275
struct xhci_control_ctx {
278
uint32_t reserved[6];
279
} __attribute__ ((packed));
281
struct xhci_slot_ctx {
283
#define SLOT_SPEED_FS BIT(20)
284
#define SLOT_SPEED_LS BIT(21)
285
#define SLOT_SPEED_HS BIT(22)
286
#define SLOT_SPEED_SS BIT(23)
287
#define LAST_CONTEXT(x) (x << 27)
290
#define ROOT_HUB_PORT(x) ((x & 0xff) << 16)
294
#define USB_DEV_ADDRESS(x) (x & 0xFFU)
295
#define SLOT_STATE(x) ((x >> 27) & 0x1FU)
296
#define SLOT_STATE_DIS_ENA 0
297
#define SLOT_STATE_DEFAULT 1
298
#define SLOT_STATE_ADDRESSED 2
299
#define SLOT_STATE_CONFIGURED 3
302
uint32_t reserved[4];
303
} __attribute__ ((packed));
308
#define MAX_PACKET_SIZE(x) (((x) & 0xFFFF) << 16)
309
#define MAX_BURST(x) (((x) & 0xFF) << 8)
310
#define EP_TYPE(x) (((x) & 0x07) << 3)
311
#define EP_ISOC_OUT 1
312
#define EP_BULK_OUT 2
319
#define ERROR_COUNT(x) (((x) & 0x03) << 1)
323
uint32_t reserved[3];
324
} __attribute__ ((packed));
328
#define XHCI_CTX_TYPE_DEVICE 0x1
329
#define XHCI_CTX_TYPE_INPUT 0x2
332
#define XHCI_CTX_BUF_SIZE 4096
339
struct xhci_ctx in_ctx;
340
struct xhci_ctx out_ctx;
341
struct xhci_seg control;
342
struct xhci_seg bulk_in;
343
struct xhci_seg bulk_out;
348
struct xhci_cap_regs *cap_regs;
349
struct xhci_op_regs *op_regs;
350
struct xhci_run_regs *run_regs;
351
struct xhci_db_regs *db_regs;
352
struct usb_hcd_dev *hcidev;
353
struct xhci_dev xdevs[XHCI_CONFIG_MAX_SLOT + 1];
354
struct usb_pipe *freelist;
355
struct usb_pipe *end;
358
struct xhci_seg ering;
359
struct xhci_seg crseg;
360
struct xhci_erst erst;
366
#define XHCI_PIPE_POOL_SIZE 4096
372
struct usb_pipe pipe;
373
struct xhci_seg *seg;
376
#endif /* USB_XHCI_H */
added
removed
lib/libusb/usb-xhci.h
