1
/******************************************************************************
2
* Copyright (c) 2007, 2011, 2013 IBM Corporation
4
* This program and the accompanying materials
5
* are made available under the terms of the BSD License
6
* which accompanies this distribution, and is available at
7
* http://www.opensource.org/licenses/bsd-license.php
10
* IBM Corporation - initial implementation
11
*****************************************************************************/
13
* Definitions for the e1000 Gigabit Ethernet Driver for SLOF
22
//#define E1K_DEBUG // main debug switch, w/o it the other ones don't work
23
//#define E1K_SHOW_RCV
24
//#define E1K_SHOW_RCV_DATA
25
//#define E1K_SHOW_XMIT
26
//#define E1K_SHOW_XMIT_DATA
29
* pci register offsets
31
// PCI command register
32
#define PCI_COM_R ((uint16_t) 0x0004)
33
// PCI Cache Line Size register
34
#define PCI_CACHELS_R ((uint16_t) 0x000c)
36
#define PCI_BAR1_R ((uint16_t) 0x0010)
38
#define PCI_BAR2_R ((uint16_t) 0x0014)
40
#define PCI_SUBID_R ((uint16_t) 0x002e)
43
* e1000 register offsets
45
// Device Control register
46
#define CTRL ((uint16_t) 0x0000)
47
// Device Status register
48
#define STATUS ((uint16_t) 0x0008)
49
// Eeprom Read register
50
#define EERD ((uint16_t) 0x0014)
51
// Interrupt Mask Clear register
52
#define IMC ((uint16_t) 0x00d8)
53
// Receive Control register
54
#define RCTL ((uint16_t) 0x0100)
55
// Receive Descriptor Base Address Low register
56
#define RDBAL ((uint16_t) 0x2800)
57
// Receive Descriptor Base Address High register
58
#define RDBAH ((uint16_t) 0x2804)
59
// Receive Descriptor Length register
60
#define RDLEN ((uint16_t) 0x2808)
61
// Receive Descriptor Head register
62
#define RDH ((uint16_t) 0x2810)
63
// Receive Descriptor Tail register
64
#define RDT ((uint16_t) 0x2818)
65
// Receive Delay Timer register
66
#define RDTR ((uint16_t) 0x2820)
67
// Transmit Control register
68
#define TCTL ((uint16_t) 0x0400)
69
// Transmit Descriptor Base Address Low register
70
#define TDBAL ((uint16_t) 0x3800)
71
// Transmit Descriptor Base Address High register
72
#define TDBAH ((uint16_t) 0x3804)
73
// Transmit Descriptor Length register
74
#define TDLEN ((uint16_t) 0x3808)
75
// Transmit Descriptor Head register
76
#define TDH ((uint16_t) 0x3810)
77
// Transmit Descriptor Tail register
78
#define TDT ((uint16_t) 0x3818)
79
// Receive Address Low register
80
#define RAL0 ((uint16_t) 0x5400)
81
// Receive Address High register
82
#define RAH0 ((uint16_t) 0x5404)
88
#define rd08(a) ci_read_8((uint32_t *)(a))
89
#define rd16(a) ci_read_16((uint32_t *)(a))
90
#define rd32(a) ci_read_32((uint32_t *)(a))
91
#define wr08(a,v) ci_write_8((uint32_t *)(a), (v))
92
#define wr16(a,v) ci_write_16((uint32_t *)(a), (v))
93
#define wr32(a,v) ci_write_32((uint32_t *)(a), (v))
94
//#define printk snk_kernel_interface->print
95
//#define ms_delay snk_kernel_interface->ms_delay
97
#define BIT08(bit) ((uint8_t) 0x1 << (bit))
98
#define BIT16(bit) ((uint16_t) 0x1 << (bit))
99
#define BIT32(bit) ((uint32_t) 0x1 << (bit))
101
//#define mb() asm volatile("sync" ::: "memory");
103
extern net_driver_t *e1k_open(void);
104
extern void e1k_close(net_driver_t *driver);
105
extern int e1k_read(char *buf, int len);
106
extern int e1k_write(char *buf, int len);
107
extern int e1k_mac_setup(uint16_t vendor_id, uint16_t device_id,
108
uint64_t baseaddr, char *mac_addr);