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* Purpose: Definitions for the cs461x driver
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* This file is part of Open Sound System.
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* Copyright (C) 4Front Technologies 1996-2008.
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* This this source file is released under GPL v2 license (no other versions).
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* See the COPYING file included in the main directory of this source
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* distribution for the license terms and conditions.
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* The following define the offsets of the registers accessed via base address
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* register zero on the CS461x part.
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#define BA0_HISR 0x00000000
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#define BA0_HSR0 0x00000004
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#define BA0_HICR 0x00000008
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#define BA0_DMSR 0x00000100
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#define BA0_HSAR 0x00000110
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#define BA0_HDAR 0x00000114
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#define BA0_HDMR 0x00000118
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#define BA0_HDCR 0x0000011C
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#define BA0_PFMC 0x00000200
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#define BA0_PFCV1 0x00000204
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#define BA0_PFCV2 0x00000208
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#define BA0_PCICFG00 0x00000300
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#define BA0_PCICFG04 0x00000304
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#define BA0_PCICFG08 0x00000308
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#define BA0_PCICFG0C 0x0000030C
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#define BA0_PCICFG10 0x00000310
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#define BA0_PCICFG14 0x00000314
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#define BA0_PCICFG18 0x00000318
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#define BA0_PCICFG1C 0x0000031C
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#define BA0_PCICFG20 0x00000320
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#define BA0_PCICFG24 0x00000324
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#define BA0_PCICFG28 0x00000328
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#define BA0_PCICFG2C 0x0000032C
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#define BA0_PCICFG30 0x00000330
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#define BA0_PCICFG34 0x00000334
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#define BA0_PCICFG38 0x00000338
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#define BA0_PCICFG3C 0x0000033C
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#define BA0_CLKCR1 0x00000400
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#define BA0_CLKCR2 0x00000404
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#define BA0_PLLM 0x00000408
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#define BA0_PLLCC 0x0000040C
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#define BA0_FRR 0x00000410
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#define BA0_CFL1 0x00000414
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#define BA0_CFL2 0x00000418
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#define BA0_SERMC1 0x00000420
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#define BA0_SERMC2 0x00000424
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#define BA0_SERC1 0x00000428
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#define BA0_SERC2 0x0000042C
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#define BA0_SERC3 0x00000430
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#define BA0_SERC4 0x00000434
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#define BA0_SERC5 0x00000438
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#define BA0_SERBSP 0x0000043C
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#define BA0_SERBST 0x00000440
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#define BA0_SERBCM 0x00000444
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#define BA0_SERBAD 0x00000448
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#define BA0_SERBCF 0x0000044C
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#define BA0_SERBWP 0x00000450
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#define BA0_SERBRP 0x00000454
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#define BA0_ASER_FADDR 0x00000458
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#define BA0_ACCTL 0x00000460
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#define BA0_ACSTS 0x00000464
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#define BA0_ACOSV 0x00000468
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#define BA0_ACCAD 0x0000046C
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#define BA0_ACCDA 0x00000470
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#define BA0_ACISV 0x00000474
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#define BA0_ACSAD 0x00000478
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#define BA0_ACSDA 0x0000047C
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#define BA0_JSPT 0x00000480
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#define BA0_JSCTL 0x00000484
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#define BA0_JSC1 0x00000488
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#define BA0_JSC2 0x0000048C
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#define BA0_MIDCR 0x00000490
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#define BA0_MIDSR 0x00000494
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#define BA0_MIDWP 0x00000498
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#define BA0_MIDRP 0x0000049C
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#define BA0_JSIO 0x000004A0
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#define BA0_ASER_MASTER 0x000004A4
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#define BA0_CFGI 0x000004B0
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#define BA0_SSVID 0x000004B4
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#define BA0_GPIOR 0x000004B8
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#define BA0_EGPIODR 0x000004BC
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#define BA0_EGPIOPTR 0x000004C0
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#define BA0_EGPIOTR 0x000004C4
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#define BA0_EGPIOWR 0x000004C8
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#define BA0_EGPIOSR 0x000004CC
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#define BA0_SERC6 0x000004D0
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#define BA0_SERC7 0x000004D4
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#define BA0_SERACC 0x000004D8
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#define BA0_ACCTL2 0x000004E0
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#define BA0_ACSTS2 0x000004E4
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#define BA0_ACOSV2 0x000004E8
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#define BA0_ACCAD2 0x000004EC
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#define BA0_ACCDA2 0x000004F0
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#define BA0_ACISV2 0x000004F4
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#define BA0_ACSAD2 0x000004F8
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#define BA0_ACSDA2 0x000004FC
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#define BA0_IOTAC0 0x00000500
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#define BA0_IOTAC1 0x00000504
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#define BA0_IOTAC2 0x00000508
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#define BA0_IOTAC3 0x0000050C
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#define BA0_IOTAC4 0x00000510
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#define BA0_IOTAC5 0x00000514
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#define BA0_IOTAC6 0x00000518
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#define BA0_IOTAC7 0x0000051C
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#define BA0_IOTAC8 0x00000520
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#define BA0_IOTAC9 0x00000524
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#define BA0_IOTAC10 0x00000528
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#define BA0_IOTAC11 0x0000052C
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#define BA0_IOTFR0 0x00000540
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#define BA0_IOTFR1 0x00000544
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#define BA0_IOTFR2 0x00000548
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#define BA0_IOTFR3 0x0000054C
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#define BA0_IOTFR4 0x00000550
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#define BA0_IOTFR5 0x00000554
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#define BA0_IOTFR6 0x00000558
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#define BA0_IOTFR7 0x0000055C
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#define BA0_IOTFIFO 0x00000580
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#define BA0_IOTRRD 0x00000584
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#define BA0_IOTFP 0x00000588
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#define BA0_IOTCR 0x0000058C
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#define BA0_DPCID 0x00000590
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#define BA0_DPCIA 0x00000594
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#define BA0_DPCIC 0x00000598
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#define BA0_PCPCIR 0x00000600
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#define BA0_PCPCIG 0x00000604
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#define BA0_PCPCIEN 0x00000608
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#define BA0_EPCIPMC 0x00000610
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* The following define the offsets of the registers and memories accessed via
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* base address register one on the CS461x part.
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#define BA1_SP_DMEM0 0x00000000
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#define BA1_SP_DMEM1 0x00010000
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#define BA1_SP_PMEM 0x00020000
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#define BA1_SP_REG 0x00030000
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#define BA1_SPCR 0x00030000
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#define BA1_DREG 0x00030004
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#define BA1_DSRWP 0x00030008
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#define BA1_TWPR 0x0003000C
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#define BA1_SPWR 0x00030010
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#define BA1_SPIR 0x00030014
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#define BA1_FGR1 0x00030020
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#define BA1_SPCS 0x00030028
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#define BA1_SDSR 0x0003002C
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#define BA1_FRMT 0x00030030
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#define BA1_FRCC 0x00030034
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#define BA1_FRSC 0x00030038
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#define BA1_OMNI_MEM 0x000E0000
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* The following defines are for the flags in the host interrupt status
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#define HISR_VC_MASK 0x0000FFFF
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#define HISR_VC0 0x00000001
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#define HISR_VC1 0x00000002
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#define HISR_VC2 0x00000004
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#define HISR_VC3 0x00000008
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#define HISR_VC4 0x00000010
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#define HISR_VC5 0x00000020
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#define HISR_VC6 0x00000040
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#define HISR_VC7 0x00000080
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#define HISR_VC8 0x00000100
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#define HISR_VC9 0x00000200
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#define HISR_VC10 0x00000400
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#define HISR_VC11 0x00000800
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#define HISR_VC12 0x00001000
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#define HISR_VC13 0x00002000
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#define HISR_VC14 0x00004000
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#define HISR_VC15 0x00008000
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#define HISR_INT0 0x00010000
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#define HISR_INT1 0x00020000
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#define HISR_DMAI 0x00040000
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#define HISR_FROVR 0x00080000
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#define HISR_MIDI 0x00100000
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#define HISR_RESERVED 0x0FE00000
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#define HISR_SBINT 0x00200000
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#define HISR_RESERVED 0x0FC00000
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#define HISR_H0P 0x40000000
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#define HISR_INTENA 0x80000000
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* The following defines are for the flags in the host signal register 0.
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#define HSR0_VC_MASK 0xFFFFFFFF
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#define HSR0_VC16 0x00000001
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#define HSR0_VC17 0x00000002
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#define HSR0_VC18 0x00000004
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#define HSR0_VC19 0x00000008
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#define HSR0_VC20 0x00000010
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#define HSR0_VC21 0x00000020
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#define HSR0_VC22 0x00000040
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#define HSR0_VC23 0x00000080
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#define HSR0_VC24 0x00000100
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#define HSR0_VC25 0x00000200
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#define HSR0_VC26 0x00000400
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#define HSR0_VC27 0x00000800
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#define HSR0_VC28 0x00001000
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#define HSR0_VC29 0x00002000
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#define HSR0_VC30 0x00004000
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#define HSR0_VC31 0x00008000
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#define HSR0_VC32 0x00010000
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#define HSR0_VC33 0x00020000
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#define HSR0_VC34 0x00040000
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#define HSR0_VC35 0x00080000
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#define HSR0_VC36 0x00100000
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#define HSR0_VC37 0x00200000
232
#define HSR0_VC38 0x00400000
233
#define HSR0_VC39 0x00800000
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#define HSR0_VC40 0x01000000
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#define HSR0_VC41 0x02000000
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#define HSR0_VC42 0x04000000
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#define HSR0_VC43 0x08000000
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#define HSR0_VC44 0x10000000
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#define HSR0_VC45 0x20000000
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#define HSR0_VC46 0x40000000
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#define HSR0_VC47 0x80000000
244
* The following defines are for the flags in the host interrupt control
247
#define HICR_IEV 0x00000001
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#define HICR_CHGM 0x00000002
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* The following defines are for the flags in the DMA status register.
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#define DMSR_HP 0x00000001
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#define DMSR_HR 0x00000002
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#define DMSR_SP 0x00000004
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#define DMSR_SR 0x00000008
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* The following defines are for the flags in the host DMA source address
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#define HSAR_HOST_ADDR_MASK 0xFFFFFFFF
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#define HSAR_DSP_ADDR_MASK 0x0000FFFF
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#define HSAR_MEMID_MASK 0x000F0000
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#define HSAR_MEMID_SP_DMEM0 0x00000000
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#define HSAR_MEMID_SP_DMEM1 0x00010000
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#define HSAR_MEMID_SP_PMEM 0x00020000
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#define HSAR_MEMID_SP_DEBUG 0x00030000
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#define HSAR_MEMID_OMNI_MEM 0x000E0000
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#define HSAR_END 0x40000000
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#define HSAR_ERR 0x80000000
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* The following defines are for the flags in the host DMA destination address
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#define HDAR_HOST_ADDR_MASK 0xFFFFFFFF
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#define HDAR_DSP_ADDR_MASK 0x0000FFFF
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#define HDAR_MEMID_MASK 0x000F0000
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#define HDAR_MEMID_SP_DMEM0 0x00000000
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#define HDAR_MEMID_SP_DMEM1 0x00010000
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#define HDAR_MEMID_SP_PMEM 0x00020000
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#define HDAR_MEMID_SP_DEBUG 0x00030000
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#define HDAR_MEMID_OMNI_MEM 0x000E0000
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#define HDAR_END 0x40000000
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#define HDAR_ERR 0x80000000
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* The following defines are for the flags in the host DMA control register.
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#define HDMR_AC_MASK 0x0000F000
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#define HDMR_AC_8_16 0x00001000
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#define HDMR_AC_M_S 0x00002000
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#define HDMR_AC_B_L 0x00004000
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#define HDMR_AC_S_U 0x00008000
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* The following defines are for the flags in the host DMA control register.
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#define HDCR_COUNT_MASK 0x000003FF
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#define HDCR_DONE 0x00004000
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#define HDCR_OPT 0x00008000
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#define HDCR_WBD 0x00400000
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#define HDCR_WBS 0x00800000
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#define HDCR_DMS_MASK 0x07000000
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#define HDCR_DMS_LINEAR 0x00000000
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#define HDCR_DMS_16_DWORDS 0x01000000
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#define HDCR_DMS_32_DWORDS 0x02000000
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#define HDCR_DMS_64_DWORDS 0x03000000
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#define HDCR_DMS_128_DWORDS 0x04000000
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#define HDCR_DMS_256_DWORDS 0x05000000
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#define HDCR_DMS_512_DWORDS 0x06000000
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#define HDCR_DMS_1024_DWORDS 0x07000000
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#define HDCR_DH 0x08000000
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#define HDCR_SMS_MASK 0x70000000
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#define HDCR_SMS_LINEAR 0x00000000
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#define HDCR_SMS_16_DWORDS 0x10000000
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#define HDCR_SMS_32_DWORDS 0x20000000
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#define HDCR_SMS_64_DWORDS 0x30000000
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#define HDCR_SMS_128_DWORDS 0x40000000
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#define HDCR_SMS_256_DWORDS 0x50000000
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#define HDCR_SMS_512_DWORDS 0x60000000
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#define HDCR_SMS_1024_DWORDS 0x70000000
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#define HDCR_SH 0x80000000
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#define HDCR_COUNT_SHIFT 0
328
* The following defines are for the flags in the performance monitor control
331
#define PFMC_C1SS_MASK 0x0000001F
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#define PFMC_C1EV 0x00000020
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#define PFMC_C1RS 0x00008000
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#define PFMC_C2SS_MASK 0x001F0000
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#define PFMC_C2EV 0x00200000
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#define PFMC_C2RS 0x80000000
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#define PFMC_C1SS_SHIFT 0
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#define PFMC_C2SS_SHIFT 16
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#define PFMC_BUS_GRANT 0
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#define PFMC_GRANT_AFTER_REQ 1
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#define PFMC_TRANSACTION 2
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#define PFMC_DWORD_TRANSFER 3
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#define PFMC_SLAVE_READ 4
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#define PFMC_SLAVE_WRITE 5
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#define PFMC_PREEMPTION 6
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#define PFMC_DISCONNECT_RETRY 7
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#define PFMC_INTERRUPT 8
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#define PFMC_BUS_OWNERSHIP 9
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#define PFMC_TRANSACTION_LAG 10
350
#define PFMC_PCI_CLOCK 11
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#define PFMC_SERIAL_CLOCK 12
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#define PFMC_SP_CLOCK 13
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* The following defines are for the flags in the performance counter value 1
358
#define PFCV1_PC1V_MASK 0xFFFFFFFF
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#define PFCV1_PC1V_SHIFT 0
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* The following defines are for the flags in the performance counter value 2
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#define PFCV2_PC2V_MASK 0xFFFFFFFF
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#define PFCV2_PC2V_SHIFT 0
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* The following defines are for the flags in the clock control register 1.
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#define CLKCR1_OSCS 0x00000001
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#define CLKCR1_OSCP 0x00000002
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#define CLKCR1_PLLSS_MASK 0x0000000C
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#define CLKCR1_PLLSS_SERIAL 0x00000000
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#define CLKCR1_PLLSS_CRYSTAL 0x00000004
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#define CLKCR1_PLLSS_PCI 0x00000008
377
#define CLKCR1_PLLSS_RESERVED 0x0000000C
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#define CLKCR1_PLLP 0x00000010
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#define CLKCR1_SWCE 0x00000020
380
#define CLKCR1_PLLOS 0x00000040
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* The following defines are for the flags in the clock control register 2.
385
#define CLKCR2_PDIVS_MASK 0x0000000F
386
#define CLKCR2_PDIVS_1 0x00000001
387
#define CLKCR2_PDIVS_2 0x00000002
388
#define CLKCR2_PDIVS_4 0x00000004
389
#define CLKCR2_PDIVS_7 0x00000007
390
#define CLKCR2_PDIVS_8 0x00000008
391
#define CLKCR2_PDIVS_16 0x00000000
394
* The following defines are for the flags in the PLL multiplier register.
396
#define PLLM_MASK 0x000000FF
400
* The following defines are for the flags in the PLL capacitor coefficient
403
#define PLLCC_CDR_MASK 0x00000007
405
#define PLLCC_CDR_240_350_MHZ 0x00000000
406
#define PLLCC_CDR_184_265_MHZ 0x00000001
407
#define PLLCC_CDR_144_205_MHZ 0x00000002
408
#define PLLCC_CDR_111_160_MHZ 0x00000003
409
#define PLLCC_CDR_87_123_MHZ 0x00000004
410
#define PLLCC_CDR_67_96_MHZ 0x00000005
411
#define PLLCC_CDR_52_74_MHZ 0x00000006
412
#define PLLCC_CDR_45_58_MHZ 0x00000007
415
#define PLLCC_CDR_271_398_MHZ 0x00000000
416
#define PLLCC_CDR_227_330_MHZ 0x00000001
417
#define PLLCC_CDR_167_239_MHZ 0x00000002
418
#define PLLCC_CDR_150_215_MHZ 0x00000003
419
#define PLLCC_CDR_107_154_MHZ 0x00000004
420
#define PLLCC_CDR_98_140_MHZ 0x00000005
421
#define PLLCC_CDR_73_104_MHZ 0x00000006
422
#define PLLCC_CDR_63_90_MHZ 0x00000007
424
#define PLLCC_LPF_MASK 0x000000F8
426
#define PLLCC_LPF_23850_60000_KHZ 0x00000000
427
#define PLLCC_LPF_7960_26290_KHZ 0x00000008
428
#define PLLCC_LPF_4160_10980_KHZ 0x00000018
429
#define PLLCC_LPF_1740_4580_KHZ 0x00000038
430
#define PLLCC_LPF_724_1910_KHZ 0x00000078
431
#define PLLCC_LPF_317_798_KHZ 0x000000F8
434
#define PLLCC_LPF_25580_64530_KHZ 0x00000000
435
#define PLLCC_LPF_14360_37270_KHZ 0x00000008
436
#define PLLCC_LPF_6100_16020_KHZ 0x00000018
437
#define PLLCC_LPF_2540_6690_KHZ 0x00000038
438
#define PLLCC_LPF_1050_2780_KHZ 0x00000078
439
#define PLLCC_LPF_450_1160_KHZ 0x000000F8
443
* The following defines are for the flags in the feature reporting register.
445
#define FRR_FAB_MASK 0x00000003
446
#define FRR_MASK_MASK 0x0000001C
448
#define FRR_CFOP_MASK 0x000000E0
450
#define FRR_CFOP_MASK 0x00000FE0
452
#define FRR_CFOP_NOT_DVD 0x00000020
453
#define FRR_CFOP_A3D 0x00000040
454
#define FRR_CFOP_128_PIN 0x00000080
456
#define FRR_CFOP_CS4280 0x00000800
458
#define FRR_FAB_SHIFT 0
459
#define FRR_MASK_SHIFT 2
460
#define FRR_CFOP_SHIFT 5
463
* The following defines are for the flags in the configuration load 1
466
#define CFL1_CLOCK_SOURCE_MASK 0x00000003
467
#define CFL1_CLOCK_SOURCE_CS423X 0x00000000
468
#define CFL1_CLOCK_SOURCE_AC97 0x00000001
469
#define CFL1_CLOCK_SOURCE_CRYSTAL 0x00000002
470
#define CFL1_CLOCK_SOURCE_DUAL_AC97 0x00000003
471
#define CFL1_VALID_DATA_MASK 0x000000FF
474
* The following defines are for the flags in the configuration load 2
477
#define CFL2_VALID_DATA_MASK 0x000000FF
480
* The following defines are for the flags in the serial port master control
483
#define SERMC1_MSPE 0x00000001
484
#define SERMC1_PTC_MASK 0x0000000E
485
#define SERMC1_PTC_CS423X 0x00000000
486
#define SERMC1_PTC_AC97 0x00000002
487
#define SERMC1_PTC_DAC 0x00000004
488
#define SERMC1_PLB 0x00000010
489
#define SERMC1_XLB 0x00000020
492
* The following defines are for the flags in the serial port master control
495
#define SERMC2_LROE 0x00000001
496
#define SERMC2_MCOE 0x00000002
497
#define SERMC2_MCDIV 0x00000004
500
* The following defines are for the flags in the serial port 1 configuration
503
#define SERC1_SO1EN 0x00000001
504
#define SERC1_SO1F_MASK 0x0000000E
505
#define SERC1_SO1F_CS423X 0x00000000
506
#define SERC1_SO1F_AC97 0x00000002
507
#define SERC1_SO1F_DAC 0x00000004
508
#define SERC1_SO1F_SPDIF 0x00000006
511
* The following defines are for the flags in the serial port 2 configuration
514
#define SERC2_SI1EN 0x00000001
515
#define SERC2_SI1F_MASK 0x0000000E
516
#define SERC2_SI1F_CS423X 0x00000000
517
#define SERC2_SI1F_AC97 0x00000002
518
#define SERC2_SI1F_ADC 0x00000004
519
#define SERC2_SI1F_SPDIF 0x00000006
522
* The following defines are for the flags in the serial port 3 configuration
525
#define SERC3_SO2EN 0x00000001
526
#define SERC3_SO2F_MASK 0x00000006
527
#define SERC3_SO2F_DAC 0x00000000
528
#define SERC3_SO2F_SPDIF 0x00000002
531
* The following defines are for the flags in the serial port 4 configuration
534
#define SERC4_SO3EN 0x00000001
535
#define SERC4_SO3F_MASK 0x00000006
536
#define SERC4_SO3F_DAC 0x00000000
537
#define SERC4_SO3F_SPDIF 0x00000002
540
* The following defines are for the flags in the serial port 5 configuration
543
#define SERC5_SI2EN 0x00000001
544
#define SERC5_SI2F_MASK 0x00000006
545
#define SERC5_SI2F_ADC 0x00000000
546
#define SERC5_SI2F_SPDIF 0x00000002
549
* The following defines are for the flags in the serial port backdoor sample
552
#define SERBSP_FSP_MASK 0x0000000F
553
#define SERBSP_FSP_SHIFT 0
556
* The following defines are for the flags in the serial port backdoor status
559
#define SERBST_RRDY 0x00000001
560
#define SERBST_WBSY 0x00000002
563
* The following defines are for the flags in the serial port backdoor command
566
#define SERBCM_RDC 0x00000001
567
#define SERBCM_WRC 0x00000002
570
* The following defines are for the flags in the serial port backdoor address
574
#define SERBAD_FAD_MASK 0x000000FF
576
#define SERBAD_FAD_MASK 0x000001FF
578
#define SERBAD_FAD_SHIFT 0
581
* The following defines are for the flags in the serial port backdoor
582
* configuration register.
584
#define SERBCF_HBP 0x00000001
587
* The following defines are for the flags in the serial port backdoor write
590
#define SERBWP_FWD_MASK 0x000FFFFF
591
#define SERBWP_FWD_SHIFT 0
594
* The following defines are for the flags in the serial port backdoor read
597
#define SERBRP_FRD_MASK 0x000FFFFF
598
#define SERBRP_FRD_SHIFT 0
601
* The following defines are for the flags in the async FIFO address register.
604
#define ASER_FADDR_A1_MASK 0x000001FF
605
#define ASER_FADDR_EN1 0x00008000
606
#define ASER_FADDR_A2_MASK 0x01FF0000
607
#define ASER_FADDR_EN2 0x80000000
608
#define ASER_FADDR_A1_SHIFT 0
609
#define ASER_FADDR_A2_SHIFT 16
613
* The following defines are for the flags in the AC97 control register.
615
#define ACCTL_RSTN 0x00000001
616
#define ACCTL_ESYN 0x00000002
617
#define ACCTL_VFRM 0x00000004
618
#define ACCTL_DCV 0x00000008
619
#define ACCTL_CRW 0x00000010
620
#define ACCTL_ASYN 0x00000020
622
#define ACCTL_TC 0x00000040
626
* The following defines are for the flags in the AC97 status register.
628
#define ACSTS_CRDY 0x00000001
629
#define ACSTS_VSTS 0x00000002
631
#define ACSTS_WKUP 0x00000004
635
* The following defines are for the flags in the AC97 output slot valid
638
#define ACOSV_SLV3 0x00000001
639
#define ACOSV_SLV4 0x00000002
640
#define ACOSV_SLV5 0x00000004
641
#define ACOSV_SLV6 0x00000008
642
#define ACOSV_SLV7 0x00000010
643
#define ACOSV_SLV8 0x00000020
644
#define ACOSV_SLV9 0x00000040
645
#define ACOSV_SLV10 0x00000080
646
#define ACOSV_SLV11 0x00000100
647
#define ACOSV_SLV12 0x00000200
650
* The following defines are for the flags in the AC97 command address
653
#define ACCAD_CI_MASK 0x0000007F
654
#define ACCAD_CI_SHIFT 0
657
* The following defines are for the flags in the AC97 command data register.
659
#define ACCDA_CD_MASK 0x0000FFFF
660
#define ACCDA_CD_SHIFT 0
663
* The following defines are for the flags in the AC97 input slot valid
666
#define ACISV_ISV3 0x00000001
667
#define ACISV_ISV4 0x00000002
668
#define ACISV_ISV5 0x00000004
669
#define ACISV_ISV6 0x00000008
670
#define ACISV_ISV7 0x00000010
671
#define ACISV_ISV8 0x00000020
672
#define ACISV_ISV9 0x00000040
673
#define ACISV_ISV10 0x00000080
674
#define ACISV_ISV11 0x00000100
675
#define ACISV_ISV12 0x00000200
678
* The following defines are for the flags in the AC97 status address
681
#define ACSAD_SI_MASK 0x0000007F
682
#define ACSAD_SI_SHIFT 0
685
* The following defines are for the flags in the AC97 status data register.
687
#define ACSDA_SD_MASK 0x0000FFFF
688
#define ACSDA_SD_SHIFT 0
691
* The following defines are for the flags in the joystick poll/trigger
694
#define JSPT_CAX 0x00000001
695
#define JSPT_CAY 0x00000002
696
#define JSPT_CBX 0x00000004
697
#define JSPT_CBY 0x00000008
698
#define JSPT_BA1 0x00000010
699
#define JSPT_BA2 0x00000020
700
#define JSPT_BB1 0x00000040
701
#define JSPT_BB2 0x00000080
704
* The following defines are for the flags in the joystick control register.
706
#define JSCTL_SP_MASK 0x00000003
707
#define JSCTL_SP_SLOW 0x00000000
708
#define JSCTL_SP_MEDIUM_SLOW 0x00000001
709
#define JSCTL_SP_MEDIUM_FAST 0x00000002
710
#define JSCTL_SP_FAST 0x00000003
711
#define JSCTL_ARE 0x00000004
714
* The following defines are for the flags in the joystick coordinate pair 1
717
#define JSC1_Y1V_MASK 0x0000FFFF
718
#define JSC1_X1V_MASK 0xFFFF0000
719
#define JSC1_Y1V_SHIFT 0
720
#define JSC1_X1V_SHIFT 16
723
* The following defines are for the flags in the joystick coordinate pair 2
726
#define JSC2_Y2V_MASK 0x0000FFFF
727
#define JSC2_X2V_MASK 0xFFFF0000
728
#define JSC2_Y2V_SHIFT 0
729
#define JSC2_X2V_SHIFT 16
732
* The following defines are for the flags in the MIDI control register.
734
#define MIDCR_TXE 0x00000001 /* Enable transmitting. */
735
#define MIDCR_RXE 0x00000002 /* Enable receiving. */
736
#define MIDCR_RIE 0x00000004 /* Interrupt upon tx ready. */
737
#define MIDCR_TIE 0x00000008 /* Interrupt upon rx ready. */
738
#define MIDCR_MLB 0x00000010 /* Enable midi loopback. */
739
#define MIDCR_MRST 0x00000020 /* Reset interface. */
742
* The following defines are for the flags in the MIDI status register.
744
#define MIDSR_TBF 0x00000001 /* Tx FIFO is full. */
745
#define MIDSR_RBE 0x00000002 /* Rx FIFO is empty. */
748
* The following defines are for the flags in the MIDI write port register.
750
#define MIDWP_MWD_MASK 0x000000FF
751
#define MIDWP_MWD_SHIFT 0
754
* The following defines are for the flags in the MIDI read port register.
756
#define MIDRP_MRD_MASK 0x000000FF
757
#define MIDRP_MRD_SHIFT 0
760
* The following defines are for the flags in the joystick GPIO register.
762
#define JSIO_DAX 0x00000001
763
#define JSIO_DAY 0x00000002
764
#define JSIO_DBX 0x00000004
765
#define JSIO_DBY 0x00000008
766
#define JSIO_AXOE 0x00000010
767
#define JSIO_AYOE 0x00000020
768
#define JSIO_BXOE 0x00000040
769
#define JSIO_BYOE 0x00000080
772
* The following defines are for the flags in the master async/sync serial
773
* port enable register.
776
#define ASER_MASTER_ME 0x00000001
780
* The following defines are for the flags in the configuration interface
783
#define CFGI_CLK 0x00000001
784
#define CFGI_DOUT 0x00000002
785
#define CFGI_DIN_EEN 0x00000004
786
#define CFGI_EELD 0x00000008
789
* The following defines are for the flags in the subsystem ID and vendor ID
792
#define SSVID_VID_MASK 0x0000FFFF
793
#define SSVID_SID_MASK 0xFFFF0000
794
#define SSVID_VID_SHIFT 0
795
#define SSVID_SID_SHIFT 16
798
* The following defines are for the flags in the GPIO pin interface register.
800
#define GPIOR_VOLDN 0x00000001
801
#define GPIOR_VOLUP 0x00000002
802
#define GPIOR_SI2D 0x00000004
803
#define GPIOR_SI2OE 0x00000008
806
* The following defines are for the flags in the extended GPIO pin direction
810
#define EGPIODR_GPOE0 0x00000001
811
#define EGPIODR_GPOE1 0x00000002
812
#define EGPIODR_GPOE2 0x00000004
813
#define EGPIODR_GPOE3 0x00000008
814
#define EGPIODR_GPOE4 0x00000010
815
#define EGPIODR_GPOE5 0x00000020
816
#define EGPIODR_GPOE6 0x00000040
817
#define EGPIODR_GPOE7 0x00000080
818
#define EGPIODR_GPOE8 0x00000100
822
* The following defines are for the flags in the extended GPIO pin polarity/
826
#define EGPIOPTR_GPPT0 0x00000001
827
#define EGPIOPTR_GPPT1 0x00000002
828
#define EGPIOPTR_GPPT2 0x00000004
829
#define EGPIOPTR_GPPT3 0x00000008
830
#define EGPIOPTR_GPPT4 0x00000010
831
#define EGPIOPTR_GPPT5 0x00000020
832
#define EGPIOPTR_GPPT6 0x00000040
833
#define EGPIOPTR_GPPT7 0x00000080
834
#define EGPIOPTR_GPPT8 0x00000100
838
* The following defines are for the flags in the extended GPIO pin sticky
842
#define EGPIOTR_GPS0 0x00000001
843
#define EGPIOTR_GPS1 0x00000002
844
#define EGPIOTR_GPS2 0x00000004
845
#define EGPIOTR_GPS3 0x00000008
846
#define EGPIOTR_GPS4 0x00000010
847
#define EGPIOTR_GPS5 0x00000020
848
#define EGPIOTR_GPS6 0x00000040
849
#define EGPIOTR_GPS7 0x00000080
850
#define EGPIOTR_GPS8 0x00000100
854
* The following defines are for the flags in the extended GPIO ping wakeup
858
#define EGPIOWR_GPW0 0x00000001
859
#define EGPIOWR_GPW1 0x00000002
860
#define EGPIOWR_GPW2 0x00000004
861
#define EGPIOWR_GPW3 0x00000008
862
#define EGPIOWR_GPW4 0x00000010
863
#define EGPIOWR_GPW5 0x00000020
864
#define EGPIOWR_GPW6 0x00000040
865
#define EGPIOWR_GPW7 0x00000080
866
#define EGPIOWR_GPW8 0x00000100
870
* The following defines are for the flags in the extended GPIO pin status
874
#define EGPIOSR_GPS0 0x00000001
875
#define EGPIOSR_GPS1 0x00000002
876
#define EGPIOSR_GPS2 0x00000004
877
#define EGPIOSR_GPS3 0x00000008
878
#define EGPIOSR_GPS4 0x00000010
879
#define EGPIOSR_GPS5 0x00000020
880
#define EGPIOSR_GPS6 0x00000040
881
#define EGPIOSR_GPS7 0x00000080
882
#define EGPIOSR_GPS8 0x00000100
886
* The following defines are for the flags in the serial port 6 configuration
890
#define SERC6_ASDO2EN 0x00000001
894
* The following defines are for the flags in the serial port 7 configuration
898
#define SERC7_ASDI2EN 0x00000001
899
#define SERC7_POSILB 0x00000002
900
#define SERC7_SIPOLB 0x00000004
901
#define SERC7_SOSILB 0x00000008
902
#define SERC7_SISOLB 0x00000010
906
* The following defines are for the flags in the serial port AC link
907
* configuration register.
910
#define SERACC_CODEC_TYPE_MASK 0x00000001
911
#define SERACC_CODEC_TYPE_1_03 0x00000000
912
#define SERACC_CODEC_TYPE_2_0 0x00000001
913
#define SERACC_TWO_CODECS 0x00000002
914
#define SERACC_MDM 0x00000004
915
#define SERACC_HSP 0x00000008
919
* The following defines are for the flags in the AC97 control register 2.
922
#define ACCTL2_RSTN 0x00000001
923
#define ACCTL2_ESYN 0x00000002
924
#define ACCTL2_VFRM 0x00000004
925
#define ACCTL2_DCV 0x00000008
926
#define ACCTL2_CRW 0x00000010
927
#define ACCTL2_ASYN 0x00000020
931
* The following defines are for the flags in the AC97 status register 2.
934
#define ACSTS2_CRDY 0x00000001
935
#define ACSTS2_VSTS 0x00000002
939
* The following defines are for the flags in the AC97 output slot valid
943
#define ACOSV2_SLV3 0x00000001
944
#define ACOSV2_SLV4 0x00000002
945
#define ACOSV2_SLV5 0x00000004
946
#define ACOSV2_SLV6 0x00000008
947
#define ACOSV2_SLV7 0x00000010
948
#define ACOSV2_SLV8 0x00000020
949
#define ACOSV2_SLV9 0x00000040
950
#define ACOSV2_SLV10 0x00000080
951
#define ACOSV2_SLV11 0x00000100
952
#define ACOSV2_SLV12 0x00000200
956
* The following defines are for the flags in the AC97 command address
960
#define ACCAD2_CI_MASK 0x0000007F
961
#define ACCAD2_CI_SHIFT 0
965
* The following defines are for the flags in the AC97 command data register
969
#define ACCDA2_CD_MASK 0x0000FFFF
970
#define ACCDA2_CD_SHIFT 0
974
* The following defines are for the flags in the AC97 input slot valid
978
#define ACISV2_ISV3 0x00000001
979
#define ACISV2_ISV4 0x00000002
980
#define ACISV2_ISV5 0x00000004
981
#define ACISV2_ISV6 0x00000008
982
#define ACISV2_ISV7 0x00000010
983
#define ACISV2_ISV8 0x00000020
984
#define ACISV2_ISV9 0x00000040
985
#define ACISV2_ISV10 0x00000080
986
#define ACISV2_ISV11 0x00000100
987
#define ACISV2_ISV12 0x00000200
991
* The following defines are for the flags in the AC97 status address
995
#define ACSAD2_SI_MASK 0x0000007F
996
#define ACSAD2_SI_SHIFT 0
1000
* The following defines are for the flags in the AC97 status data register 2.
1003
#define ACSDA2_SD_MASK 0x0000FFFF
1004
#define ACSDA2_SD_SHIFT 0
1008
* The following defines are for the flags in the I/O trap address and control
1009
* registers (all 12).
1012
#define IOTAC_SA_MASK 0x0000FFFF
1013
#define IOTAC_MSK_MASK 0x000F0000
1014
#define IOTAC_IODC_MASK 0x06000000
1015
#define IOTAC_IODC_16_BIT 0x00000000
1016
#define IOTAC_IODC_10_BIT 0x02000000
1017
#define IOTAC_IODC_12_BIT 0x04000000
1018
#define IOTAC_WSPI 0x08000000
1019
#define IOTAC_RSPI 0x10000000
1020
#define IOTAC_WSE 0x20000000
1021
#define IOTAC_WE 0x40000000
1022
#define IOTAC_RE 0x80000000
1023
#define IOTAC_SA_SHIFT 0
1024
#define IOTAC_MSK_SHIFT 16
1028
* The following defines are for the flags in the I/O trap fast read registers
1032
#define IOTFR_D_MASK 0x0000FFFF
1033
#define IOTFR_A_MASK 0x000F0000
1034
#define IOTFR_R_MASK 0x0F000000
1035
#define IOTFR_ALL 0x40000000
1036
#define IOTFR_VL 0x80000000
1037
#define IOTFR_D_SHIFT 0
1038
#define IOTFR_A_SHIFT 16
1039
#define IOTFR_R_SHIFT 24
1043
* The following defines are for the flags in the I/O trap FIFO register.
1046
#define IOTFIFO_BA_MASK 0x00003FFF
1047
#define IOTFIFO_S_MASK 0x00FF0000
1048
#define IOTFIFO_OF 0x40000000
1049
#define IOTFIFO_SPIOF 0x80000000
1050
#define IOTFIFO_BA_SHIFT 0
1051
#define IOTFIFO_S_SHIFT 16
1055
* The following defines are for the flags in the I/O trap retry read data
1059
#define IOTRRD_D_MASK 0x0000FFFF
1060
#define IOTRRD_RDV 0x80000000
1061
#define IOTRRD_D_SHIFT 0
1065
* The following defines are for the flags in the I/O trap FIFO pointer
1069
#define IOTFP_CA_MASK 0x00003FFF
1070
#define IOTFP_PA_MASK 0x3FFF0000
1071
#define IOTFP_CA_SHIFT 0
1072
#define IOTFP_PA_SHIFT 16
1076
* The following defines are for the flags in the I/O trap control register.
1079
#define IOTCR_ITD 0x00000001
1080
#define IOTCR_HRV 0x00000002
1081
#define IOTCR_SRV 0x00000004
1082
#define IOTCR_DTI 0x00000008
1083
#define IOTCR_DFI 0x00000010
1084
#define IOTCR_DDP 0x00000020
1085
#define IOTCR_JTE 0x00000040
1086
#define IOTCR_PPE 0x00000080
1090
* The following defines are for the flags in the direct PCI data register.
1093
#define DPCID_D_MASK 0xFFFFFFFF
1094
#define DPCID_D_SHIFT 0
1098
* The following defines are for the flags in the direct PCI address register.
1101
#define DPCIA_A_MASK 0xFFFFFFFF
1102
#define DPCIA_A_SHIFT 0
1106
* The following defines are for the flags in the direct PCI command register.
1109
#define DPCIC_C_MASK 0x0000000F
1110
#define DPCIC_C_IOREAD 0x00000002
1111
#define DPCIC_C_IOWRITE 0x00000003
1112
#define DPCIC_BE_MASK 0x000000F0
1116
* The following defines are for the flags in the PC/PCI request register.
1119
#define PCPCIR_RDC_MASK 0x00000007
1120
#define PCPCIR_C_MASK 0x00007000
1121
#define PCPCIR_REQ 0x00008000
1122
#define PCPCIR_RDC_SHIFT 0
1123
#define PCPCIR_C_SHIFT 12
1127
* The following defines are for the flags in the PC/PCI grant register.
1130
#define PCPCIG_GDC_MASK 0x00000007
1131
#define PCPCIG_VL 0x00008000
1132
#define PCPCIG_GDC_SHIFT 0
1136
* The following defines are for the flags in the PC/PCI master enable
1140
#define PCPCIEN_EN 0x00000001
1144
* The following defines are for the flags in the extended PCI power
1145
* management control register.
1148
#define EPCIPMC_GWU 0x00000001
1149
#define EPCIPMC_FSPC 0x00000002
1153
* The following defines are for the flags in the SP control register.
1155
#define SPCR_RUN 0x00000001
1156
#define SPCR_STPFR 0x00000002
1157
#define SPCR_RUNFR 0x00000004
1158
#define SPCR_TICK 0x00000008
1159
#define SPCR_DRQEN 0x00000020
1160
#define SPCR_RSTSP 0x00000040
1161
#define SPCR_OREN 0x00000080
1163
#define SPCR_PCIINT 0x00000100
1164
#define SPCR_OINTD 0x00000200
1165
#define SPCR_CRE 0x00008000
1169
* The following defines are for the flags in the debug index register.
1171
#define DREG_REGID_MASK 0x0000007F
1172
#define DREG_DEBUG 0x00000080
1173
#define DREG_RGBK_MASK 0x00000700
1174
#define DREG_TRAP 0x00000800
1175
#if !defined(NO_CS4612)
1176
#if !defined(NO_CS4615)
1177
#define DREG_TRAPX 0x00001000
1180
#define DREG_REGID_SHIFT 0
1181
#define DREG_RGBK_SHIFT 8
1182
#define DREG_RGBK_REGID_MASK 0x0000077F
1183
#define DREG_REGID_R0 0x00000010
1184
#define DREG_REGID_R1 0x00000011
1185
#define DREG_REGID_R2 0x00000012
1186
#define DREG_REGID_R3 0x00000013
1187
#define DREG_REGID_R4 0x00000014
1188
#define DREG_REGID_R5 0x00000015
1189
#define DREG_REGID_R6 0x00000016
1190
#define DREG_REGID_R7 0x00000017
1191
#define DREG_REGID_R8 0x00000018
1192
#define DREG_REGID_R9 0x00000019
1193
#define DREG_REGID_RA 0x0000001A
1194
#define DREG_REGID_RB 0x0000001B
1195
#define DREG_REGID_RC 0x0000001C
1196
#define DREG_REGID_RD 0x0000001D
1197
#define DREG_REGID_RE 0x0000001E
1198
#define DREG_REGID_RF 0x0000001F
1199
#define DREG_REGID_RA_BUS_LOW 0x00000020
1200
#define DREG_REGID_RA_BUS_HIGH 0x00000038
1201
#define DREG_REGID_YBUS_LOW 0x00000050
1202
#define DREG_REGID_YBUS_HIGH 0x00000058
1203
#define DREG_REGID_TRAP_0 0x00000100
1204
#define DREG_REGID_TRAP_1 0x00000101
1205
#define DREG_REGID_TRAP_2 0x00000102
1206
#define DREG_REGID_TRAP_3 0x00000103
1207
#define DREG_REGID_TRAP_4 0x00000104
1208
#define DREG_REGID_TRAP_5 0x00000105
1209
#define DREG_REGID_TRAP_6 0x00000106
1210
#define DREG_REGID_TRAP_7 0x00000107
1211
#define DREG_REGID_INDIRECT_ADDRESS 0x0000010E
1212
#define DREG_REGID_TOP_OF_STACK 0x0000010F
1213
#if !defined(NO_CS4612)
1214
#if !defined(NO_CS4615)
1215
#define DREG_REGID_TRAP_8 0x00000110
1216
#define DREG_REGID_TRAP_9 0x00000111
1217
#define DREG_REGID_TRAP_10 0x00000112
1218
#define DREG_REGID_TRAP_11 0x00000113
1219
#define DREG_REGID_TRAP_12 0x00000114
1220
#define DREG_REGID_TRAP_13 0x00000115
1221
#define DREG_REGID_TRAP_14 0x00000116
1222
#define DREG_REGID_TRAP_15 0x00000117
1223
#define DREG_REGID_TRAP_16 0x00000118
1224
#define DREG_REGID_TRAP_17 0x00000119
1225
#define DREG_REGID_TRAP_18 0x0000011A
1226
#define DREG_REGID_TRAP_19 0x0000011B
1227
#define DREG_REGID_TRAP_20 0x0000011C
1228
#define DREG_REGID_TRAP_21 0x0000011D
1229
#define DREG_REGID_TRAP_22 0x0000011E
1230
#define DREG_REGID_TRAP_23 0x0000011F
1233
#define DREG_REGID_RSA0_LOW 0x00000200
1234
#define DREG_REGID_RSA0_HIGH 0x00000201
1235
#define DREG_REGID_RSA1_LOW 0x00000202
1236
#define DREG_REGID_RSA1_HIGH 0x00000203
1237
#define DREG_REGID_RSA2 0x00000204
1238
#define DREG_REGID_RSA3 0x00000205
1239
#define DREG_REGID_RSI0_LOW 0x00000206
1240
#define DREG_REGID_RSI0_HIGH 0x00000207
1241
#define DREG_REGID_RSI1 0x00000208
1242
#define DREG_REGID_RSI2 0x00000209
1243
#define DREG_REGID_SAGUSTATUS 0x0000020A
1244
#define DREG_REGID_RSCONFIG01_LOW 0x0000020B
1245
#define DREG_REGID_RSCONFIG01_HIGH 0x0000020C
1246
#define DREG_REGID_RSCONFIG23_LOW 0x0000020D
1247
#define DREG_REGID_RSCONFIG23_HIGH 0x0000020E
1248
#define DREG_REGID_RSDMA01E 0x0000020F
1249
#define DREG_REGID_RSDMA23E 0x00000210
1250
#define DREG_REGID_RSD0_LOW 0x00000211
1251
#define DREG_REGID_RSD0_HIGH 0x00000212
1252
#define DREG_REGID_RSD1_LOW 0x00000213
1253
#define DREG_REGID_RSD1_HIGH 0x00000214
1254
#define DREG_REGID_RSD2_LOW 0x00000215
1255
#define DREG_REGID_RSD2_HIGH 0x00000216
1256
#define DREG_REGID_RSD3_LOW 0x00000217
1257
#define DREG_REGID_RSD3_HIGH 0x00000218
1258
#define DREG_REGID_SRAR_HIGH 0x0000021A
1259
#define DREG_REGID_SRAR_LOW 0x0000021B
1260
#define DREG_REGID_DMA_STATE 0x0000021C
1261
#define DREG_REGID_CURRENT_DMA_STREAM 0x0000021D
1262
#define DREG_REGID_NEXT_DMA_STREAM 0x0000021E
1263
#define DREG_REGID_CPU_STATUS 0x00000300
1264
#define DREG_REGID_MAC_MODE 0x00000301
1265
#define DREG_REGID_STACK_AND_REPEAT 0x00000302
1266
#define DREG_REGID_INDEX0 0x00000304
1267
#define DREG_REGID_INDEX1 0x00000305
1268
#define DREG_REGID_DMA_STATE_0_3 0x00000400
1269
#define DREG_REGID_DMA_STATE_4_7 0x00000404
1270
#define DREG_REGID_DMA_STATE_8_11 0x00000408
1271
#define DREG_REGID_DMA_STATE_12_15 0x0000040C
1272
#define DREG_REGID_DMA_STATE_16_19 0x00000410
1273
#define DREG_REGID_DMA_STATE_20_23 0x00000414
1274
#define DREG_REGID_DMA_STATE_24_27 0x00000418
1275
#define DREG_REGID_DMA_STATE_28_31 0x0000041C
1276
#define DREG_REGID_DMA_STATE_32_35 0x00000420
1277
#define DREG_REGID_DMA_STATE_36_39 0x00000424
1278
#define DREG_REGID_DMA_STATE_40_43 0x00000428
1279
#define DREG_REGID_DMA_STATE_44_47 0x0000042C
1280
#define DREG_REGID_DMA_STATE_48_51 0x00000430
1281
#define DREG_REGID_DMA_STATE_52_55 0x00000434
1282
#define DREG_REGID_DMA_STATE_56_59 0x00000438
1283
#define DREG_REGID_DMA_STATE_60_63 0x0000043C
1284
#define DREG_REGID_DMA_STATE_64_67 0x00000440
1285
#define DREG_REGID_DMA_STATE_68_71 0x00000444
1286
#define DREG_REGID_DMA_STATE_72_75 0x00000448
1287
#define DREG_REGID_DMA_STATE_76_79 0x0000044C
1288
#define DREG_REGID_DMA_STATE_80_83 0x00000450
1289
#define DREG_REGID_DMA_STATE_84_87 0x00000454
1290
#define DREG_REGID_DMA_STATE_88_91 0x00000458
1291
#define DREG_REGID_DMA_STATE_92_95 0x0000045C
1292
#define DREG_REGID_TRAP_SELECT 0x00000500
1293
#define DREG_REGID_TRAP_WRITE_0 0x00000500
1294
#define DREG_REGID_TRAP_WRITE_1 0x00000501
1295
#define DREG_REGID_TRAP_WRITE_2 0x00000502
1296
#define DREG_REGID_TRAP_WRITE_3 0x00000503
1297
#define DREG_REGID_TRAP_WRITE_4 0x00000504
1298
#define DREG_REGID_TRAP_WRITE_5 0x00000505
1299
#define DREG_REGID_TRAP_WRITE_6 0x00000506
1300
#define DREG_REGID_TRAP_WRITE_7 0x00000507
1301
#if !defined(NO_CS4612)
1302
#if !defined(NO_CS4615)
1303
#define DREG_REGID_TRAP_WRITE_8 0x00000510
1304
#define DREG_REGID_TRAP_WRITE_9 0x00000511
1305
#define DREG_REGID_TRAP_WRITE_10 0x00000512
1306
#define DREG_REGID_TRAP_WRITE_11 0x00000513
1307
#define DREG_REGID_TRAP_WRITE_12 0x00000514
1308
#define DREG_REGID_TRAP_WRITE_13 0x00000515
1309
#define DREG_REGID_TRAP_WRITE_14 0x00000516
1310
#define DREG_REGID_TRAP_WRITE_15 0x00000517
1311
#define DREG_REGID_TRAP_WRITE_16 0x00000518
1312
#define DREG_REGID_TRAP_WRITE_17 0x00000519
1313
#define DREG_REGID_TRAP_WRITE_18 0x0000051A
1314
#define DREG_REGID_TRAP_WRITE_19 0x0000051B
1315
#define DREG_REGID_TRAP_WRITE_20 0x0000051C
1316
#define DREG_REGID_TRAP_WRITE_21 0x0000051D
1317
#define DREG_REGID_TRAP_WRITE_22 0x0000051E
1318
#define DREG_REGID_TRAP_WRITE_23 0x0000051F
1321
#define DREG_REGID_MAC0_ACC0_LOW 0x00000600
1322
#define DREG_REGID_MAC0_ACC1_LOW 0x00000601
1323
#define DREG_REGID_MAC0_ACC2_LOW 0x00000602
1324
#define DREG_REGID_MAC0_ACC3_LOW 0x00000603
1325
#define DREG_REGID_MAC1_ACC0_LOW 0x00000604
1326
#define DREG_REGID_MAC1_ACC1_LOW 0x00000605
1327
#define DREG_REGID_MAC1_ACC2_LOW 0x00000606
1328
#define DREG_REGID_MAC1_ACC3_LOW 0x00000607
1329
#define DREG_REGID_MAC0_ACC0_MID 0x00000608
1330
#define DREG_REGID_MAC0_ACC1_MID 0x00000609
1331
#define DREG_REGID_MAC0_ACC2_MID 0x0000060A
1332
#define DREG_REGID_MAC0_ACC3_MID 0x0000060B
1333
#define DREG_REGID_MAC1_ACC0_MID 0x0000060C
1334
#define DREG_REGID_MAC1_ACC1_MID 0x0000060D
1335
#define DREG_REGID_MAC1_ACC2_MID 0x0000060E
1336
#define DREG_REGID_MAC1_ACC3_MID 0x0000060F
1337
#define DREG_REGID_MAC0_ACC0_HIGH 0x00000610
1338
#define DREG_REGID_MAC0_ACC1_HIGH 0x00000611
1339
#define DREG_REGID_MAC0_ACC2_HIGH 0x00000612
1340
#define DREG_REGID_MAC0_ACC3_HIGH 0x00000613
1341
#define DREG_REGID_MAC1_ACC0_HIGH 0x00000614
1342
#define DREG_REGID_MAC1_ACC1_HIGH 0x00000615
1343
#define DREG_REGID_MAC1_ACC2_HIGH 0x00000616
1344
#define DREG_REGID_MAC1_ACC3_HIGH 0x00000617
1345
#define DREG_REGID_RSHOUT_LOW 0x00000620
1346
#define DREG_REGID_RSHOUT_MID 0x00000628
1347
#define DREG_REGID_RSHOUT_HIGH 0x00000630
1350
* The following defines are for the flags in the DMA stream requestor write
1352
#define DSRWP_DSR_MASK 0x0000000F
1353
#define DSRWP_DSR_BG_RQ 0x00000001
1354
#define DSRWP_DSR_PRIORITY_MASK 0x00000006
1355
#define DSRWP_DSR_PRIORITY_0 0x00000000
1356
#define DSRWP_DSR_PRIORITY_1 0x00000002
1357
#define DSRWP_DSR_PRIORITY_2 0x00000004
1358
#define DSRWP_DSR_PRIORITY_3 0x00000006
1359
#define DSRWP_DSR_RQ_PENDING 0x00000008
1362
* The following defines are for the flags in the trap write port register.
1364
#define TWPR_TW_MASK 0x0000FFFF
1365
#define TWPR_TW_SHIFT 0
1368
* The following defines are for the flags in the stack pointer write
1371
#define SPWR_STKP_MASK 0x0000000F
1372
#define SPWR_STKP_SHIFT 0
1375
* The following defines are for the flags in the SP interrupt register.
1377
#define SPIR_FRI 0x00000001
1378
#define SPIR_DOI 0x00000002
1379
#define SPIR_GPI2 0x00000004
1380
#define SPIR_GPI3 0x00000008
1381
#define SPIR_IP0 0x00000010
1382
#define SPIR_IP1 0x00000020
1383
#define SPIR_IP2 0x00000040
1384
#define SPIR_IP3 0x00000080
1387
* The following defines are for the flags in the functional group 1 register.
1389
#define FGR1_F1S_MASK 0x0000FFFF
1390
#define FGR1_F1S_SHIFT 0
1393
* The following defines are for the flags in the SP clock status register.
1395
#define SPCS_FRI 0x00000001
1396
#define SPCS_DOI 0x00000002
1397
#define SPCS_GPI2 0x00000004
1398
#define SPCS_GPI3 0x00000008
1399
#define SPCS_IP0 0x00000010
1400
#define SPCS_IP1 0x00000020
1401
#define SPCS_IP2 0x00000040
1402
#define SPCS_IP3 0x00000080
1403
#define SPCS_SPRUN 0x00000100
1404
#define SPCS_SLEEP 0x00000200
1405
#define SPCS_FG 0x00000400
1406
#define SPCS_ORUN 0x00000800
1407
#define SPCS_IRQ 0x00001000
1408
#define SPCS_FGN_MASK 0x0000E000
1409
#define SPCS_FGN_SHIFT 13
1412
* The following defines are for the flags in the SP DMA requestor status
1415
#define SDSR_DCS_MASK 0x000000FF
1416
#define SDSR_DCS_SHIFT 0
1417
#define SDSR_DCS_NONE 0x00000007
1420
* The following defines are for the flags in the frame timer register.
1422
#define FRMT_FTV_MASK 0x0000FFFF
1423
#define FRMT_FTV_SHIFT 0
1426
* The following defines are for the flags in the frame timer current count
1429
#define FRCC_FCC_MASK 0x0000FFFF
1430
#define FRCC_FCC_SHIFT 0
1433
* The following defines are for the flags in the frame timer save count
1436
#define FRSC_FCS_MASK 0x0000FFFF
1437
#define FRSC_FCS_SHIFT 0
1440
* The following define the various flags stored in the scatter/gather
1443
#define DMA_SG_NEXT_ENTRY_MASK 0x00000FF8
1444
#define DMA_SG_SAMPLE_END_MASK 0x0FFF0000
1445
#define DMA_SG_SAMPLE_END_FLAG 0x10000000
1446
#define DMA_SG_LOOP_END_FLAG 0x20000000
1447
#define DMA_SG_SIGNAL_END_FLAG 0x40000000
1448
#define DMA_SG_SIGNAL_PAGE_FLAG 0x80000000
1449
#define DMA_SG_NEXT_ENTRY_SHIFT 3
1450
#define DMA_SG_SAMPLE_END_SHIFT 16
1453
* The following define the offsets of the fields within the on-chip generic
1456
#define DMA_RQ_CONTROL1 0x00000000
1457
#define DMA_RQ_CONTROL2 0x00000004
1458
#define DMA_RQ_SOURCE_ADDR 0x00000008
1459
#define DMA_RQ_DESTINATION_ADDR 0x0000000C
1460
#define DMA_RQ_NEXT_PAGE_ADDR 0x00000010
1461
#define DMA_RQ_NEXT_PAGE_SGDESC 0x00000014
1462
#define DMA_RQ_LOOP_START_ADDR 0x00000018
1463
#define DMA_RQ_POST_LOOP_ADDR 0x0000001C
1464
#define DMA_RQ_PAGE_MAP_ADDR 0x00000020
1467
* The following defines are for the flags in the first control word of the
1468
* on-chip generic DMA requestor.
1470
#define DMA_RQ_C1_COUNT_MASK 0x000003FF
1471
#define DMA_RQ_C1_DESTINATION_SCATTER 0x00001000
1472
#define DMA_RQ_C1_SOURCE_GATHER 0x00002000
1473
#define DMA_RQ_C1_DONE_FLAG 0x00004000
1474
#define DMA_RQ_C1_OPTIMIZE_STATE 0x00008000
1475
#define DMA_RQ_C1_SAMPLE_END_STATE_MASK 0x00030000
1476
#define DMA_RQ_C1_FULL_PAGE 0x00000000
1477
#define DMA_RQ_C1_BEFORE_SAMPLE_END 0x00010000
1478
#define DMA_RQ_C1_PAGE_MAP_ERROR 0x00020000
1479
#define DMA_RQ_C1_AT_SAMPLE_END 0x00030000
1480
#define DMA_RQ_C1_LOOP_END_STATE_MASK 0x000C0000
1481
#define DMA_RQ_C1_NOT_LOOP_END 0x00000000
1482
#define DMA_RQ_C1_BEFORE_LOOP_END 0x00040000
1483
#define DMA_RQ_C1_2PAGE_LOOP_BEGIN 0x00080000
1484
#define DMA_RQ_C1_LOOP_BEGIN 0x000C0000
1485
#define DMA_RQ_C1_PAGE_MAP_MASK 0x00300000
1486
#define DMA_RQ_C1_PM_NONE_PENDING 0x00000000
1487
#define DMA_RQ_C1_PM_NEXT_PENDING 0x00100000
1488
#define DMA_RQ_C1_PM_RESERVED 0x00200000
1489
#define DMA_RQ_C1_PM_LOOP_NEXT_PENDING 0x00300000
1490
#define DMA_RQ_C1_WRITEBACK_DEST_FLAG 0x00400000
1491
#define DMA_RQ_C1_WRITEBACK_SRC_FLAG 0x00800000
1492
#define DMA_RQ_C1_DEST_SIZE_MASK 0x07000000
1493
#define DMA_RQ_C1_DEST_LINEAR 0x00000000
1494
#define DMA_RQ_C1_DEST_MOD16 0x01000000
1495
#define DMA_RQ_C1_DEST_MOD32 0x02000000
1496
#define DMA_RQ_C1_DEST_MOD64 0x03000000
1497
#define DMA_RQ_C1_DEST_MOD128 0x04000000
1498
#define DMA_RQ_C1_DEST_MOD256 0x05000000
1499
#define DMA_RQ_C1_DEST_MOD512 0x06000000
1500
#define DMA_RQ_C1_DEST_MOD1024 0x07000000
1501
#define DMA_RQ_C1_DEST_ON_HOST 0x08000000
1502
#define DMA_RQ_C1_SOURCE_SIZE_MASK 0x70000000
1503
#define DMA_RQ_C1_SOURCE_LINEAR 0x00000000
1504
#define DMA_RQ_C1_SOURCE_MOD16 0x10000000
1505
#define DMA_RQ_C1_SOURCE_MOD32 0x20000000
1506
#define DMA_RQ_C1_SOURCE_MOD64 0x30000000
1507
#define DMA_RQ_C1_SOURCE_MOD128 0x40000000
1508
#define DMA_RQ_C1_SOURCE_MOD256 0x50000000
1509
#define DMA_RQ_C1_SOURCE_MOD512 0x60000000
1510
#define DMA_RQ_C1_SOURCE_MOD1024 0x70000000
1511
#define DMA_RQ_C1_SOURCE_ON_HOST 0x80000000
1512
#define DMA_RQ_C1_COUNT_SHIFT 0
1515
* The following defines are for the flags in the second control word of the
1516
* on-chip generic DMA requestor.
1518
#define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK 0x0000003F
1519
#define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK 0x00000300
1520
#define DMA_RQ_C2_NO_VIRTUAL_SIGNAL 0x00000000
1521
#define DMA_RQ_C2_SIGNAL_EVERY_DMA 0x00000100
1522
#define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG 0x00000200
1523
#define DMA_RQ_C2_SIGNAL_DEST_PINGPONG 0x00000300
1524
#define DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000
1525
#define DMA_RQ_C2_AC_NONE 0x00000000
1526
#define DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000
1527
#define DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000
1528
#define DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000
1529
#define DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000
1530
#define DMA_RQ_C2_LOOP_END_MASK 0x0FFF0000
1531
#define DMA_RQ_C2_LOOP_MASK 0x30000000
1532
#define DMA_RQ_C2_NO_LOOP 0x00000000
1533
#define DMA_RQ_C2_ONE_PAGE_LOOP 0x10000000
1534
#define DMA_RQ_C2_TWO_PAGE_LOOP 0x20000000
1535
#define DMA_RQ_C2_MULTI_PAGE_LOOP 0x30000000
1536
#define DMA_RQ_C2_SIGNAL_LOOP_BACK 0x40000000
1537
#define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE 0x80000000
1538
#define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT 0
1539
#define DMA_RQ_C2_LOOP_END_SHIFT 16
1542
* The following defines are for the flags in the source and destination words
1543
* of the on-chip generic DMA requestor.
1545
#define DMA_RQ_SD_ADDRESS_MASK 0x0000FFFF
1546
#define DMA_RQ_SD_MEMORY_ID_MASK 0x000F0000
1547
#define DMA_RQ_SD_SP_PARAM_ADDR 0x00000000
1548
#define DMA_RQ_SD_SP_SAMPLE_ADDR 0x00010000
1549
#define DMA_RQ_SD_SP_PROGRAM_ADDR 0x00020000
1550
#define DMA_RQ_SD_SP_DEBUG_ADDR 0x00030000
1551
#define DMA_RQ_SD_OMNIMEM_ADDR 0x000E0000
1552
#define DMA_RQ_SD_END_FLAG 0x40000000
1553
#define DMA_RQ_SD_ERROR_FLAG 0x80000000
1554
#define DMA_RQ_SD_ADDRESS_SHIFT 0
1557
* The following defines are for the flags in the page map address word of the
1558
* on-chip generic DMA requestor.
1560
#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK 0x00000FF8
1561
#define DMA_RQ_PMA_PAGE_TABLE_MASK 0xFFFFF000
1562
#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT 3
1563
#define DMA_RQ_PMA_PAGE_TABLE_SHIFT 12
1565
#define BA1_VARIDEC_BUF_1 0x000
1567
#define BA1_PDTC 0x0c0 /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */
1568
#define BA1_PFIE 0x0c4 /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */
1569
#define BA1_PBA 0x0c8 /* BA1_PLAY_BUFFER_ADDRESS */
1570
#define BA1_PVOL 0x0f8 /* BA1_PLAY_VOLUME_REG */
1571
#define BA1_PSRC 0x288 /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */
1572
#define BA1_PCTL 0x2a4 /* BA1_PLAY_CONTROL_REG */
1573
#define BA1_PPI 0x2b4 /* BA1_PLAY_PHASE_INCREMENT_REG */
1575
#define BA1_CCTL 0x064 /* BA1_CAPTURE_CONTROL_REG */
1576
#define BA1_CIE 0x104 /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */
1577
#define BA1_CBA 0x10c /* BA1_CAPTURE_BUFFER_ADDRESS */
1578
#define BA1_CSRC 0x2c8 /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */
1579
#define BA1_CCI 0x2d8 /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */
1580
#define BA1_CD 0x2e0 /* BA1_CAPTURE_DELAY_REG */
1581
#define BA1_CPI 0x2f4 /* BA1_CAPTURE_PHASE_INCREMENT_REG */
1582
#define BA1_CVOL 0x2f8 /* BA1_CAPTURE_VOLUME_REG */
1584
#define BA1_CFG1 0x134 /* BA1_CAPTURE_FRAME_GROUP_1_REG */
1585
#define BA1_CFG2 0x138 /* BA1_CAPTURE_FRAME_GROUP_2_REG */
1586
#define BA1_CCST 0x13c /* BA1_CAPTURE_CONSTANT_REG */
1587
#define BA1_CSPB 0x340 /* BA1_CAPTURE_SPB_ADDRESS */
1593
#define CS461X_MODE_OUTPUT (1<<0) /* MIDI UART - output */
1594
#define CS461X_MODE_INPUT (1<<1) /* MIDI UART - input */
1596
/****************************************************************************
1598
* The following define the offsets of the AC97 shadow registers, which appear
1599
* as a virtual extension to the base address register zero memory range.
1601
****************************************************************************/
1602
#define AC97_REG_OFFSET_MASK 0x0000007EL
1603
#define AC97_CODEC_NUMBER_MASK 0x00003000L
1605
#define BA0_AC97_RESET 0x00001000L
1606
#define BA0_AC97_MASTER_VOLUME 0x00001002L
1607
#define BA0_AC97_HEADPHONE_VOLUME 0x00001004L
1608
#define BA0_AC97_MASTER_VOLUME_MONO 0x00001006L
1609
#define BA0_AC97_MASTER_TONE 0x00001008L
1610
#define BA0_AC97_PC_BEEP_VOLUME 0x0000100AL
1611
#define BA0_AC97_PHONE_VOLUME 0x0000100CL
1612
#define BA0_AC97_MIC_VOLUME 0x0000100EL
1613
#define BA0_AC97_LINE_IN_VOLUME 0x00001010L
1614
#define BA0_AC97_CD_VOLUME 0x00001012L
1615
#define BA0_AC97_VIDEO_VOLUME 0x00001014L
1616
#define BA0_AC97_AUX_VOLUME 0x00001016L
1617
#define BA0_AC97_PCM_OUT_VOLUME 0x00001018L
1618
#define BA0_AC97_RECORD_SELECT 0x0000101AL
1619
#define BA0_AC97_RECORD_GAIN 0x0000101CL
1620
#define BA0_AC97_RECORD_GAIN_MIC 0x0000101EL
1621
#define BA0_AC97_GENERAL_PURPOSE 0x00001020L
1622
#define BA0_AC97_3D_CONTROL 0x00001022L
1623
#define BA0_AC97_MODEM_RATE 0x00001024L
1624
#define BA0_AC97_POWERDOWN 0x00001026L
1625
#define BA0_AC97_EXT_AUDIO_ID 0x00001028L
1626
#define BA0_AC97_EXT_AUDIO_POWER 0x0000102AL
1627
#define BA0_AC97_PCM_FRONT_DAC_RATE 0x0000102CL
1628
#define BA0_AC97_PCM_SURR_DAC_RATE 0x0000102EL
1629
#define BA0_AC97_PCM_LFE_DAC_RATE 0x00001030L
1630
#define BA0_AC97_PCM_LR_ADC_RATE 0x00001032L
1631
#define BA0_AC97_MIC_ADC_RATE 0x00001034L
1632
#define BA0_AC97_6CH_VOL_C_LFE 0x00001036L
1633
#define BA0_AC97_6CH_VOL_SURROUND 0x00001038L
1634
#define BA0_AC97_RESERVED_3A 0x0000103AL
1635
#define BA0_AC97_EXT_MODEM_ID 0x0000103CL
1636
#define BA0_AC97_EXT_MODEM_POWER 0x0000103EL
1637
#define BA0_AC97_LINE1_CODEC_RATE 0x00001040L
1638
#define BA0_AC97_LINE2_CODEC_RATE 0x00001042L
1639
#define BA0_AC97_HANDSET_CODEC_RATE 0x00001044L
1640
#define BA0_AC97_LINE1_CODEC_LEVEL 0x00001046L
1641
#define BA0_AC97_LINE2_CODEC_LEVEL 0x00001048L
1642
#define BA0_AC97_HANDSET_CODEC_LEVEL 0x0000104AL
1643
#define BA0_AC97_GPIO_PIN_CONFIG 0x0000104CL
1644
#define BA0_AC97_GPIO_PIN_TYPE 0x0000104EL
1645
#define BA0_AC97_GPIO_PIN_STICKY 0x00001050L
1646
#define BA0_AC97_GPIO_PIN_WAKEUP 0x00001052L
1647
#define BA0_AC97_GPIO_PIN_STATUS 0x00001054L
1648
#define BA0_AC97_MISC_MODEM_AFE_STAT 0x00001056L
1649
#define BA0_AC97_RESERVED_58 0x00001058L
1650
#define BA0_AC97_CRYSTAL_REV_N_FAB_ID 0x0000105AL
1651
#define BA0_AC97_TEST_AND_MISC_CTRL 0x0000105CL
1652
#define BA0_AC97_AC_MODE 0x0000105EL
1653
#define BA0_AC97_MISC_CRYSTAL_CONTROL 0x00001060L
1654
#define BA0_AC97_LINE1_HYPRID_CTRL 0x00001062L
1655
#define BA0_AC97_VENDOR_RESERVED_64 0x00001064L
1656
#define BA0_AC97_VENDOR_RESERVED_66 0x00001066L
1657
#define BA0_AC97_SPDIF_CONTROL 0x00001068L
1658
#define BA0_AC97_VENDOR_RESERVED_6A 0x0000106AL
1659
#define BA0_AC97_VENDOR_RESERVED_6C 0x0000106CL
1660
#define BA0_AC97_VENDOR_RESERVED_6E 0x0000106EL
1661
#define BA0_AC97_VENDOR_RESERVED_70 0x00001070L
1662
#define BA0_AC97_VENDOR_RESERVED_72 0x00001072L
1663
#define BA0_AC97_VENDOR_RESERVED_74 0x00001074L
1664
#define BA0_AC97_CAL_ADDRESS 0x00001076L
1665
#define BA0_AC97_CAL_DATA 0x00001078L
1666
#define BA0_AC97_VENDOR_RESERVED_7A 0x0000107AL
1667
#define BA0_AC97_VENDOR_ID1 0x0000107CL
1668
#define BA0_AC97_VENDOR_ID2 0x0000107EL
added
removed
kernel/drv/oss_cs461x/cs461x.h
