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/* Copyright (c) 2009 Dmitry Xmelkov
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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* Neither the name of the copyright holders nor the names of
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE. */
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/* $Id: eewr_byte.S 2024 2009-09-10 01:39:42Z dmix $ */
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#if E2END && __AVR_ARCH__ > 1
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#include <avr/eeprom.h>
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ENTRY eeprom_write_byte
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ENTRY eeprom_write_r18
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#if __AVR_XMEGA__ /* -------------------------------------------- */
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# define CCP_IOREG_gc 0xD8 /* IO Register Protection */
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# ifndef NVM_CMD_READ_EEPROM_gc
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# define NVM_CMD_READ_EEPROM_gc 0x06
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# ifndef NVM_CMD_LOAD_EEPROM_BUFFER_gc
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# define NVM_CMD_LOAD_EEPROM_BUFFER_gc 0x33
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# ifndef NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc
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# define NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc 0x35
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# ifndef NVM_CMD_ERASE_EEPROM_BUFFER_gc
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# define NVM_CMD_ERASE_EEPROM_BUFFER_gc 0x36
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; Prepare base address of NVM.
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; Wait until NVM is not busy.
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1: ldd r19, Z + NVM_STATUS - NVM_BASE
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sbrc r19, NVM_NVMBUSY_bp
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; Disable EEPROM mapping into data space.
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ldd r19, Z + NVM_CTRLB - NVM_BASE
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andi r19, ~NVM_EEMAPEN_bm
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std Z + NVM_CTRLB - NVM_BASE, r19
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; Check the clearance of EEPROM page buffer.
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ldd r19, Z + NVM_STATUS - NVM_BASE
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sbrs r19, NVM_EELOAD_bp
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rjmp 3f ; erase is not required
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; Note that we have only four clock cycles to write to the CCP
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; protected register NVM_CTRLA, after writing to CCP. The 'ldi'
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; instruction always takes one clock to execute and 'std' instruction takes
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; two clock cycles. We fall within the four cycles that the CCP leaves
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; us to write the command execution start bit to the NVM_CTRLA
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; register. Note that r18 must be preserved until written to NVM_DATA0
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; Issue EEPROM Buffer Erase:
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ldi r19, NVM_CMD_ERASE_EEPROM_BUFFER_gc
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std Z + NVM_CMD - NVM_BASE, r19
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std Z + NVM_CTRLA - NVM_BASE, r19
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; Wait until NVM is not busy.
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2: ldd r19, Z + NVM_STATUS - NVM_BASE
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sbrc r19, NVM_NVMBUSY_bp
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; Issue EEPROM Buffer Load command.
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3: ldi r19, NVM_CMD_LOAD_EEPROM_BUFFER_gc
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std Z + NVM_CMD - NVM_BASE, r19
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std Z + NVM_ADDR0 - NVM_BASE, addr_lo
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std Z + NVM_ADDR1 - NVM_BASE, addr_hi
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std Z + NVM_ADDR2 - NVM_BASE, __zero_reg__
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std Z + NVM_DATA0 - NVM_BASE, r18
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; Issue EEPROM Erase & Write command.
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ldi r18, NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc
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std Z + NVM_CMD - NVM_BASE, r18
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ldi r18, CCP_IOREG_gc
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ldi r19, NVM_CMDEX_bm
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std Z + NVM_CTRLA - NVM_BASE, r19
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#else /* ---------------------------------------------------- */
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1: sbic _SFR_IO_ADDR (EECR), EEWE
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# if defined (EEPM0) && defined (EEPM1)
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; Set programming mode: erase and write.
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out _SFR_IO_ADDR (EECR), __zero_reg__
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# elif defined (EEPM0) || defined (EEPM1)
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# error /* Unknown EECR register. */
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out _SFR_IO_ADDR (EEARH), addr_hi
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; This is for chips like ATmega48: the EEAR8 bit must be cleaned.
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out _SFR_IO_ADDR (EEARH), __zero_reg__
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out _SFR_IO_ADDR (EEARL), addr_lo
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out _SFR_IO_ADDR (EEDR), r18
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in __tmp_reg__, _SFR_IO_ADDR (SREG)
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sbi _SFR_IO_ADDR (EECR), EEMWE
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sbi _SFR_IO_ADDR (EECR), EEWE
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out _SFR_IO_ADDR (SREG), __tmp_reg__
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#endif /* ---------------------------------------------------- */
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#endif /* E2END && __AVR_ARCH__ > 1 */
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#endif /* !__DOXYGEN__ */