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This directory contains code optimized for AMD K6 CPUs, meaning K6, K6-2 and
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The mmx and k62mmx subdirectories have routines using MMX instructions. All
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K6s have MMX, the separate directories are just so that ./configure can omit
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them if the assembler doesn't support MMX.
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Times for the loops, with all code and data in L1 cache, are as follows.
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mpn_add_n/sub_n 3.25 normal, 2.75 in-place
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mpn_add/submul_1 7.65-8.4 (varying with data values)
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mpn_mul_basecase 9.25 cycles/crossproduct (approx)
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mpn_sqr_basecase 4.7 cycles/crossproduct (approx)
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or 9.2 cycles/triangleproduct (approx)
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mpn_and/andn/ior/xor_n 1.5-1.75 | varying with
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mpn_iorn/xnor_n 2.0-2.25 | data alignment
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mpn_nand/nior_n 2.0-2.25 /
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K6-2 and K6-3 have dual-issue MMX and get the following improvements.
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mpn_copyi/copyd 0.56 or 1.0 \
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mpn_com_n 1.0-1.2 | varying with
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mpn_and/andn/ior/xor_n 1.2-1.5 | data alignment
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mpn_iorn/xnor_n 1.5-2.0 |
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mpn_nand/nior_n 1.75-2.0 /
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Prefetching of sources hasn't yet given any joy. With the 3DNow "prefetch"
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instruction, code seems to run slower, and with just "mov" loads it doesn't
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seem faster. Results so far are inconsistent. The K6 does a hardware
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prefetch of the second cache line in a sector, so the penalty for not
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prefetching in software is reduced.
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All K6 family chips have MMX, but only K6-2 and K6-3 have 3DNow.
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Plain K6 executes MMX instructions only in the X pipe, but K6-2 and K6-3 can
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execute them in both X and Y (and together).
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Branch misprediction penalty is 1 to 4 cycles (Optimization Manual
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Write-allocate L1 data cache means prefetching of destinations is unnecessary.
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Store queue is 7 entries of 64 bits each.
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Floating point multiplications can be done in parallel with integer
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multiplications, but there doesn't seem to be any way to make use of this.
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Unrolled loops are used to reduce looping overhead. The unrolling is
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configurable up to 32 limbs/loop for most routines, up to 64 for some.
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Sometimes computed jumps into the unrolling are used to handle sizes not a
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multiple of the unrolling. An attractive feature of this is that times
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smoothly increase with operand size, but an indirect jump is about 6 cycles
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and the setups about another 6, so it depends on how much the unrolled code
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is faster than a simple loop as to whether a computed jump ought to be used.
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Position independent code is implemented using a call to get eip for
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computed jumps and a ret is always done, rather than an addl $4,%esp or a
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popl, so the CPU return address branch prediction stack stays synchronised
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with the actual stack in memory. Such a call however still costs 4 to 7
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Branch prediction, in absence of any history, will guess forward jumps are
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not taken and backward jumps are taken. Where possible it's arranged that
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the less likely or less important case is under a taken forward jump.
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Putting emms or femms as late as possible in a routine seems to be fastest.
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Perhaps an emms or femms stalls until all outstanding MMX instructions have
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completed, so putting it later gives them a chance to complete on their own,
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in parallel with other operations (like register popping).
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The Optimization Manual chapter 5 recommends using a femms on K6-2 and K6-3
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at the start of a routine, in case it's been preceded by x87 floating point
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operations. This isn't done because in gmp programs it's expected that x87
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floating point won't be much used and that chances are an mpn routine won't
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have been preceded by any x87 code.
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Instructions in general code are shown paired if they can decode and execute
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together, meaning two short decode instructions with the second not
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depending on the first, only the first using the shifter, no more than one
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load, and no more than one store.
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K6 does some out of order execution so the pairings aren't essential, they
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just show what slots might be available. When decoding is the limiting
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factor things can be scheduled that might not execute until later.
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- if an opcode/modrm or 0Fh/opcode/modrm crosses a cache line boundary,
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short decode is inhibited. The cross.pl script detects this.
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- loops and branch targets should be aligned to 16 bytes, or ensure at least
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2 instructions before a 32 byte boundary. This makes use of the 16 byte
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- (%esi) degrades decoding from short to vector. 0(%esi) doesn't have this
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problem, and can be used as an equivalent, or easier is just to use a
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different register, like %ebx.
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- K6 and pre-CXT core K6-2 have the following problem. (K6-2 CXT and K6-3
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have it fixed, these being cpuid function 1 signatures 0x588 to 0x58F).
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If more than 3 bytes are needed to determine instruction length then
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decoding degrades from direct to long, or from long to vector. This
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happens with forms like "0F opcode mod/rm" with mod/rm=00-xxx-100 since
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with mod=00 the sib determines whether there's a displacement.
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This affects all MMX and 3DNow instructions, and others with an 0F prefix
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like movzbl. The modes affected are anything with an index and no
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displacement, or an index but no base, and this includes (%esp) which is
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The cross.pl script detects problem cases. The workaround is to always
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use a displacement, and to do this with Zdisp if it's zero so the
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assembler doesn't discard it.
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See Optimization Manual rev D page 67 and 3DNow Porting Guide rev B pages
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- indirect jumps and calls are not branch predicted, they measure about 6
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- adcl 2 cycles of decode, maybe 2 cycles executing in the X pipe
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- jecxz 2 cycles taken, 13 not taken (optimization manual says 7 not taken)
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- divl 20 cycles back-to-back
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- imull 2 decode, 2 execute
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- mull 2 decode, 3 execute (optimization manual decoding sample)
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- rcll/rcrl implicit by one bit: 2 cycles
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immediate or %cl count: 11 + 2 per bit for dword
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13 + 4 per bit for byte
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- xchgl %eax,reg 1.5 cycles, back-to-back (strange)
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reg,reg 2 cycles, back-to-back
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"AMD-K6 Processor Code Optimization Application Note", AMD publication
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number 21924, revision D amendment 0, January 2000. This describes K6-2 and
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K6-3. Available on-line,
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http://www.amd.com/K6/k6docs/pdf/21924.pdf
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"AMD-K6 MMX Enhanced Processor x86 Code Optimization Application Note", AMD
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publication number 21828, revision A amendment 0, August 1997. This is an
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older edition of the above document, describing plain K6. Available
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http://www.amd.com/K6/k6docs/pdf/21828.pdf
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"3DNow Technology Manual", AMD publication number 21928F/0-August 1999.
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This describes the femms and prefetch instructions, but nothing else from
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3DNow has been used. Available on-line,
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http://www.amd.com/K6/k6docs/pdf/21928.pdf
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"3DNow Instruction Porting Guide", AMD publication number 22621, revision B,
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August 1999. This has some notes on general K6 optimizations as well as
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3DNow. Available on-line,
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http://www.amd.com/products/cpg/athlon/techdocs/pdf/22621.pdf
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gmp/mpn/x86/k6/README
