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- Committer: Bazaar Package Importer
- Author(s): Stefan Bader, Amit Kucheria
- Date: 2010-03-23 18:05:12 UTC
- Revision ID: james.westby@ubuntu.com-20100323180512-iavj906ocnphdubp
Tags: 2.6.33-500.3
[ Amit Kucheria ]
* [Config] Fix the debug package name to end in -dbgsym
* SAUCE: Add the ubuntu/ drivers to omap
* SAUCE: Re-export the symbols for aufs
* [Config] Enable AUFS and COMPCACHE
* [Config] Fix the debug package name to end in -dbgsym
* SAUCE: Add the ubuntu/ drivers to omap
* SAUCE: Re-export the symbols for aufs
* [Config] Enable AUFS and COMPCACHE
- files added:
- debian.ti-omap/abi/2.6.33-500.2
- debian.ti-omap/abi/2.6.33-500.2/armel
- ubuntu
- ubuntu/aufs
- ubuntu/compcache
- ubuntu/dm-raid4-5
- ubuntu/fsam7400
- ubuntu/include
- ubuntu/include/linux
- ubuntu/iscsitarget
- ubuntu/iscsitarget/include
- ubuntu/lirc
- ubuntu/lirc/lirc_atiusb
- ubuntu/lirc/lirc_bt829
- ubuntu/lirc/lirc_dev
- ubuntu/lirc/lirc_ene0100
- ubuntu/lirc/lirc_gpio
- ubuntu/lirc/lirc_i2c
- ubuntu/lirc/lirc_igorplugusb
- ubuntu/lirc/lirc_imon
- ubuntu/lirc/lirc_it87
- ubuntu/lirc/lirc_ite8709
- ubuntu/lirc/lirc_mceusb
- ubuntu/lirc/lirc_parallel
- ubuntu/lirc/lirc_sasem
- ubuntu/lirc/lirc_serial
- ubuntu/lirc/lirc_sir
- ubuntu/lirc/lirc_streamzap
- ubuntu/lirc/lirc_ttusbir
- ubuntu/lirc/lirc_wpc8769l
- ubuntu/ndiswrapper
- ubuntu/omnibook
- ubuntu/omnibook/debian
- ubuntu/omnibook/doc
- ubuntu/omnibook/misc
- ubuntu/omnibook/misc/hotkeys
- ubuntu/rfkill
- ubuntu/rtl8192se
- ubuntu/rtl8192se/rtl8192s
- ubuntu/rtl8192se/rtllib
- files removed:
- debian.ti-omap/abi/2.6.33-500.1
- debian.ti-omap/abi/2.6.33-500.1/armel
- files modified:
- Makefile
added
removed
ubuntu/rtl8192se/rtl8192s/r8192S_phy.c
1
/******************************************************************************
2
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3
*
4
* This program is distributed in the hope that it will be useful, but WITHOUT
5
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
7
* more details.
8
*
9
* You should have received a copy of the GNU General Public License along with
10
* this program; if not, write to the Free Software Foundation, Inc.,
11
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
12
*
13
* The full GNU General Public License is included in this distribution in the
14
* file called LICENSE.
15
*
16
* Contact Information:
17
* wlanfae <wlanfae@realtek.com>
18
******************************************************************************/
19
#ifdef RTL8192SE
20
21
#include "../rtl_core.h"
22
#include "../rtl_dm.h"
23
#include "r8192S_phy.h"
24
#include "r8192S_phyreg.h"
25
#include "r8192S_rtl6052.h"
26
#include "r8192S_hwimg.h"
27
28
#ifdef ENABLE_DOT11D
29
#include "../rtllib/dot11d.h"
30
#endif
31
32
/*---------------------------Define Local Constant---------------------------*/
33
#define MAX_PRECMD_CNT 16
34
#define MAX_RFDEPENDCMD_CNT 16
35
#define MAX_POSTCMD_CNT 16
36
37
#define MAX_DOZE_WAITING_TIMES_9x 64
38
39
#define PHY_STOP_SWITCH_CLKREQ 0
40
/*---------------------------Define Local Constant---------------------------*/
41
42
/*------------------------Define global variable-----------------------------*/
43
44
#define Rtl819XMAC_Array Rtl8192SEMAC_2T_Array
45
#define Rtl819XAGCTAB_Array Rtl8192SEAGCTAB_Array
46
#define Rtl819XPHY_REG_Array Rtl8192SEPHY_REG_2T2RArray
47
#define Rtl819XPHY_REG_to1T1R_Array Rtl8192SEPHY_ChangeTo_1T1RArray
48
#define Rtl819XPHY_REG_to1T2R_Array Rtl8192SEPHY_ChangeTo_1T2RArray
49
#define Rtl819XPHY_REG_to2T2R_Array Rtl8192SEPHY_ChangeTo_2T2RArray
50
#define Rtl819XPHY_REG_Array_PG Rtl8192SEPHY_REG_Array_PG
51
#define Rtl819XRadioA_Array Rtl8192SERadioA_1T_Array
52
#define Rtl819XRadioB_Array Rtl8192SERadioB_Array
53
#define Rtl819XRadioB_GM_Array Rtl8192SERadioB_GM_Array
54
#define Rtl819XRadioA_to1T_Array Rtl8192SERadioA_to1T_Array
55
#define Rtl819XRadioA_to2T_Array Rtl8192SERadioA_to2T_Array
56
57
/*------------------------Define local variable------------------------------*/
58
#if 0
59
static u32 RF_CHANNEL_TABLE_ZEBRA[]={
60
0,
61
0x085c,
62
0x08dc,
63
0x095c,
64
0x09dc,
65
0x0a5c,
66
0x0adc,
67
0x0b5c,
68
0x0bdc,
69
0x0c5c,
70
0x0cdc,
71
0x0d5c,
72
0x0ddc,
73
0x0e5c,
74
0x0f72,
75
};
76
#endif
77
78
/*------------------------Define local variable------------------------------*/
79
80
81
/*--------------------Define export function prototype-----------------------*/
82
/*--------------------Define export function prototype-----------------------*/
83
84
85
/*---------------------Define local function prototype-----------------------*/
86
87
static u32 phy_FwRFSerialRead( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset);
88
static void phy_FwRFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
89
90
static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset);
91
static void phy_RFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
92
static u32 phy_CalculateBitShift(u32 BitMask);
93
static bool phy_BB8190_Config_HardCode(struct net_device* dev);
94
static bool phy_BB8192S_Config_ParaFile(struct net_device* dev);
95
96
static bool phy_ConfigMACWithHeaderFile(struct net_device* dev);
97
98
static bool phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType);
99
100
static bool phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType);
101
102
static bool phy_SetBBtoDiffRFWithHeaderFile(struct net_device* dev,u8 ConfigType);
103
104
static void phy_InitBBRFRegisterDefinition(struct net_device* dev);
105
static bool phy_SetSwChnlCmdArray( SwChnlCmd* CmdTable,
106
u32 CmdTableIdx,
107
u32 CmdTableSz,
108
SwChnlCmdID CmdID,
109
u32 Para1,
110
u32 Para2,
111
u32 msDelay );
112
113
static bool phy_SwChnlStepByStep(
114
struct net_device* dev,
115
u8 channel,
116
u8 *stage,
117
u8 *step,
118
u32 *delay
119
);
120
121
static void phy_FinishSwChnlNow(struct net_device* dev,u8 channel);
122
123
static u8 phy_DbmToTxPwrIdx( struct net_device* dev, WIRELESS_MODE WirelessMode, long PowerInDbm);
124
static bool phy_SetRFPowerState8192SE(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState);
125
static void phy_CheckEphySwitchReady( struct net_device* dev);
126
127
static long phy_TxPwrIdxToDbm( struct net_device* dev, WIRELESS_MODE WirelessMode, u8 TxPwrIdx);
128
void rtl8192_SetFwCmdIOCallback(struct net_device* dev);
129
130
131
/*---------------------Define local function prototype-----------------------*/
132
133
134
/*----------------------------Function Body----------------------------------*/
135
u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask)
136
{
137
138
u32 ReturnValue = 0, OriginalValue, BitShift;
139
140
#if (DISABLE_BB_RF == 1)
141
return 0;
142
#endif
143
144
RT_TRACE(COMP_RF, "--->PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x)\n", RegAddr, BitMask);
145
146
OriginalValue = read_nic_dword(dev, RegAddr);
147
148
BitShift = phy_CalculateBitShift(BitMask);
149
ReturnValue = (OriginalValue & BitMask) >> BitShift;
150
151
RT_TRACE(COMP_RF, "<---PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x), OriginalValue(%#x)\n", RegAddr, BitMask, OriginalValue);
152
return (ReturnValue);
153
}
154
155
void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data)
156
{
157
u32 OriginalValue, BitShift, NewValue;
158
159
#if (DISABLE_BB_RF == 1)
160
return;
161
#endif
162
163
164
{
165
if(BitMask!= bMaskDWord)
166
{
167
OriginalValue = read_nic_dword(dev, RegAddr);
168
BitShift = phy_CalculateBitShift(BitMask);
169
NewValue = (((OriginalValue) & (~BitMask)) | (Data << BitShift));
170
write_nic_dword(dev, RegAddr, NewValue);
171
}else
172
write_nic_dword(dev, RegAddr, Data);
173
}
174
175
return;
176
}
177
178
179
u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
180
{
181
u32 Original_Value, Readback_Value, BitShift;
182
struct r8192_priv *priv = rtllib_priv(dev);
183
unsigned long flags;
184
185
#if (DISABLE_BB_RF == 1)
186
return 0;
187
#endif
188
189
RT_TRACE(COMP_RF, "--->PHY_QueryRFReg(): RegAddr(%#x), eRFPath(%#x), BitMask(%#x)\n", RegAddr, eRFPath,BitMask);
190
191
if (!((priv->rf_pathmap >> eRFPath) & 0x1))
192
return 0;
193
194
if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
195
return 0;
196
197
spin_lock_irqsave(&priv->rf_lock, flags);
198
if (priv->Rf_Mode == RF_OP_By_FW)
199
{
200
Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
201
}
202
else
203
{
204
Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr);
205
}
206
207
BitShift = phy_CalculateBitShift(BitMask);
208
Readback_Value = (Original_Value & BitMask) >> BitShift;
209
spin_unlock_irqrestore(&priv->rf_lock, flags);
210
211
212
return (Readback_Value);
213
}
214
215
216
void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
217
{
218
219
struct r8192_priv *priv = rtllib_priv(dev);
220
u32 Original_Value, BitShift, New_Value;
221
unsigned long flags;
222
#if (DISABLE_BB_RF == 1)
223
return;
224
#endif
225
226
RT_TRACE(COMP_RF, "--->PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
227
RegAddr, BitMask, Data, eRFPath);
228
229
if (!((priv->rf_pathmap >> eRFPath) & 0x1))
230
return ;
231
if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
232
{
233
return;
234
}
235
236
spin_lock_irqsave(&priv->rf_lock, flags);
237
if (priv->Rf_Mode == RF_OP_By_FW)
238
{
239
if (BitMask != bRFRegOffsetMask)
240
{
241
Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
242
BitShift = phy_CalculateBitShift(BitMask);
243
New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
244
245
phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
246
}
247
else
248
phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
249
}
250
else
251
{
252
if (BitMask != bRFRegOffsetMask)
253
{
254
Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr);
255
BitShift = phy_CalculateBitShift(BitMask);
256
New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
257
258
phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
259
}
260
else
261
phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
262
263
}
264
spin_unlock_irqrestore(&priv->rf_lock, flags);
265
RT_TRACE(COMP_RF, "<---PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
266
RegAddr, BitMask, Data, eRFPath);
267
268
}
269
270
static u32
271
phy_FwRFSerialRead(
272
struct net_device* dev,
273
RF90_RADIO_PATH_E eRFPath,
274
u32 Offset )
275
{
276
u32 retValue = 0;
277
#if 0
278
u32 Data = 0;
279
u8 time = 0;
280
Data |= ((Offset&0xFF)<<12);
281
Data |= ((eRFPath&0x3)<<20);
282
Data |= 0x80000000;
283
while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
284
{
285
if (time++ < 100)
286
{
287
delay_us(10);
288
}
289
else
290
break;
291
}
292
PlatformIOWrite4Byte(dev, QPNR, Data);
293
while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
294
{
295
if (time++ < 100)
296
{
297
delay_us(10);
298
}
299
else
300
return (0);
301
}
302
retValue = PlatformIORead4Byte(dev, RF_DATA);
303
#endif
304
return (retValue);
305
306
} /* phy_FwRFSerialRead */
307
308
static void
309
phy_FwRFSerialWrite(
310
struct net_device* dev,
311
RF90_RADIO_PATH_E eRFPath,
312
u32 Offset,
313
u32 Data )
314
{
315
#if 0
316
u8 time = 0;
317
DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
318
319
Data |= ((Offset&0xFF)<<12);
320
Data |= ((eRFPath&0x3)<<20);
321
Data |= 0x400000;
322
Data |= 0x80000000;
323
324
while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
325
{
326
if (time++ < 100)
327
{
328
delay_us(10);
329
}
330
else
331
break;
332
}
333
PlatformIOWrite4Byte(dev, QPNR, Data);
334
#endif
335
} /* phy_FwRFSerialWrite */
336
337
#if (RTL92SE_FPGA_VERIFY == 1)
338
static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset)
339
{
340
341
u32 retValue = 0;
342
struct r8192_priv *priv = rtllib_priv(dev);
343
BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
344
u32 NewOffset;
345
346
Offset &= 0x3f;
347
348
if( priv->rf_chip == RF_8256 ||
349
priv->rf_chip == RF_8225 ||
350
priv->rf_chip == RF_6052)
351
{
352
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
353
354
if(Offset>=31)
355
{
356
priv->RFReadPageCnt[2]++;
357
priv->RfReg0Value[eRFPath] |= 0x140;
358
359
rtl8192_setBBreg(dev,
360
pPhyReg->rf3wireOffset,
361
bMaskDWord,
362
(priv->RfReg0Value[eRFPath] << 16) );
363
364
NewOffset = Offset - 30;
365
366
}else if(Offset>=16)
367
{
368
priv->RFReadPageCnt[1]++;
369
priv->RfReg0Value[eRFPath] |= 0x100;
370
priv->RfReg0Value[eRFPath] &= (~0x40);
371
372
rtl8192_setBBreg(dev,
373
pPhyReg->rf3wireOffset,
374
bMaskDWord,
375
(priv->RfReg0Value[eRFPath] << 16) );
376
377
NewOffset = Offset - 15;
378
}
379
else
380
{
381
priv->RFReadPageCnt[0]++;
382
NewOffset = Offset;
383
}
384
}
385
else
386
NewOffset = Offset;
387
388
#if (RTL92SE_FPGA_VERIFY == 1)
389
{
390
u32 temp1, temp2;
391
392
temp1 = rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0xffffffff);
393
temp2 = rtl8192_QueryBBReg(dev, pPhyReg->rfHSSIPara2, 0xffffffff);
394
temp2 = temp2 & (~bLSSIReadAddress) | (NewOffset<<24) | bLSSIReadEdge;
395
396
rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, 0xffffffff, temp1&(~bLSSIReadEdge));
397
msleep(1);
398
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, 0xffffffff, temp2);
399
msleep(1);
400
rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, 0xffffffff, temp1|bLSSIReadEdge);
401
msleep(1);
402
403
}
404
#else
405
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
406
407
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
408
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
409
#endif
410
411
mdelay(1);
412
413
retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
414
415
if( priv->rf_chip == RF_8256 ||
416
priv->rf_chip == RF_8225 ||
417
priv->rf_chip == RF_6052)
418
{
419
if (Offset >= 0x10)
420
{
421
priv->RfReg0Value[eRFPath] &= 0xebf;
422
423
rtl8192_setBBreg(
424
dev,
425
pPhyReg->rf3wireOffset,
426
bMaskDWord,
427
(priv->RfReg0Value[eRFPath] << 16) );
428
}
429
430
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);
431
}
432
433
return retValue;
434
}
435
436
437
static void
438
phy_RFSerialWrite(
439
struct net_device* dev,
440
RF90_RADIO_PATH_E eRFPath,
441
u32 Offset,
442
u32 Data
443
)
444
{
445
u32 DataAndAddr = 0;
446
struct r8192_priv *priv = rtllib_priv(dev);
447
BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
448
u32 NewOffset;
449
450
Offset &= 0x3f;
451
452
PHY_RFShadowWrite(dev, eRFPath, Offset, Data);
453
454
if( priv->rf_chip == RF_8256 ||
455
priv->rf_chip == RF_8225 ||
456
priv->rf_chip == RF_6052)
457
{
458
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
459
460
if(Offset>=31)
461
{
462
priv->RFWritePageCnt[2]++;
463
priv->RfReg0Value[eRFPath] |= 0x140;
464
465
rtl8192_setBBreg(dev,
466
pPhyReg->rf3wireOffset,
467
bMaskDWord,
468
(priv->RfReg0Value[eRFPath] << 16) );
469
470
NewOffset = Offset - 30;
471
472
}else if(Offset>=16)
473
{
474
priv->RFWritePageCnt[1]++;
475
priv->RfReg0Value[eRFPath] |= 0x100;
476
priv->RfReg0Value[eRFPath] &= (~0x40);
477
478
479
rtl8192_setBBreg(dev,
480
pPhyReg->rf3wireOffset,
481
bMaskDWord,
482
(priv->RfReg0Value[eRFPath] << 16) );
483
484
NewOffset = Offset - 15;
485
}
486
else
487
{
488
priv->RFWritePageCnt[0]++;
489
NewOffset = Offset;
490
}
491
}
492
else
493
NewOffset = Offset;
494
495
DataAndAddr = (Data<<16) | (NewOffset&0x3f);
496
497
rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
498
499
500
if(Offset==0x0)
501
priv->RfReg0Value[eRFPath] = Data;
502
503
if( priv->rf_chip == RF_8256 ||
504
priv->rf_chip == RF_8225 ||
505
priv->rf_chip == RF_6052)
506
{
507
if (Offset >= 0x10)
508
{
509
if(Offset != 0)
510
{
511
priv->RfReg0Value[eRFPath] &= 0xebf;
512
rtl8192_setBBreg(
513
dev,
514
pPhyReg->rf3wireOffset,
515
bMaskDWord,
516
(priv->RfReg0Value[eRFPath] << 16) );
517
}
518
}
519
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);
520
}
521
522
}
523
#else
524
static u32
525
phy_RFSerialRead(
526
struct net_device* dev,
527
RF90_RADIO_PATH_E eRFPath,
528
u32 Offset
529
)
530
{
531
532
u32 retValue = 0;
533
struct r8192_priv *priv = rtllib_priv(dev);
534
BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
535
u32 NewOffset;
536
u32 tmplong,tmplong2;
537
u8 RfPiEnable=0;
538
#if 0
539
if(priv->rf_chip == RF_8225 && Offset > 0x24)
540
return retValue;
541
if(priv->rf_chip == RF_8256 && Offset > 0x2D)
542
return retValue;
543
#endif
544
Offset &= 0x3f;
545
546
NewOffset = Offset;
547
548
tmplong = rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord);
549
if(eRFPath == RF90_PATH_A)
550
tmplong2 = tmplong;
551
else
552
tmplong2 = rtl8192_QueryBBReg(dev, pPhyReg->rfHSSIPara2, bMaskDWord);
553
tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;
554
555
rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));
556
udelay(1000);
557
558
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
559
udelay(1000);
560
561
rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge);
562
563
if(eRFPath == RF90_PATH_A)
564
RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
565
else if(eRFPath == RF90_PATH_B)
566
RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XB_HSSIParameter1, BIT8);
567
568
if(RfPiEnable)
569
{
570
retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
571
}
572
else
573
{
574
retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
575
}
576
577
retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
578
579
return retValue;
580
581
}
582
583
static void
584
phy_RFSerialWrite(
585
struct net_device* dev,
586
RF90_RADIO_PATH_E eRFPath,
587
u32 Offset,
588
u32 Data
589
)
590
{
591
u32 DataAndAddr = 0;
592
struct r8192_priv *priv = rtllib_priv(dev);
593
BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
594
u32 NewOffset;
595
596
#if 0
597
if(priv->rf_chip == RF_8225 && Offset > 0x24)
598
return;
599
if(priv->rf_chip == RF_8256 && Offset > 0x2D)
600
return;
601
#endif
602
603
Offset &= 0x3f;
604
605
PHY_RFShadowWrite(dev, eRFPath, Offset, Data);
606
607
NewOffset = Offset;
608
609
DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff;
610
611
rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
612
613
}
614
615
#endif
616
617
static u32 phy_CalculateBitShift(u32 BitMask)
618
{
619
u32 i;
620
621
for(i=0; i<=31; i++)
622
{
623
if ( ((BitMask>>i) & 0x1 ) == 1)
624
break;
625
}
626
627
return (i);
628
}
629
630
631
extern bool PHY_MACConfig8192S(struct net_device* dev)
632
{
633
bool rtStatus = true;
634
635
#if RTL8190_Download_Firmware_From_Header
636
rtStatus = phy_ConfigMACWithHeaderFile(dev);
637
#else
638
639
RT_TRACE(COMP_INIT, "Read MACREG.txt\n");
640
#endif
641
return (rtStatus == true) ? 1:0;
642
643
}
644
645
extern bool
646
PHY_BBConfig8192S(struct net_device* dev)
647
{
648
bool rtStatus = true;
649
u8 PathMap = 0, index = 0, rf_num = 0;
650
struct r8192_priv *priv = rtllib_priv(dev);
651
u8 bRegHwParaFile = 1;
652
653
phy_InitBBRFRegisterDefinition(dev);
654
655
switch(bRegHwParaFile)
656
{
657
case 0:
658
phy_BB8190_Config_HardCode(dev);
659
break;
660
661
case 1:
662
rtStatus = phy_BB8192S_Config_ParaFile(dev);
663
break;
664
665
case 2:
666
phy_BB8190_Config_HardCode(dev);
667
phy_BB8192S_Config_ParaFile(dev);
668
break;
669
670
default:
671
phy_BB8190_Config_HardCode(dev);
672
break;
673
}
674
675
PathMap = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_TxInfo, 0xf) |
676
rtl8192_QueryBBReg(dev, rOFDM0_TRxPathEnable, 0xf));
677
priv->rf_pathmap = PathMap;
678
for(index = 0; index<4; index++)
679
{
680
if((PathMap>>index)&0x1)
681
rf_num++;
682
}
683
684
if((priv->rf_type==RF_1T1R && rf_num!=1) ||
685
(priv->rf_type==RF_1T2R && rf_num!=2) ||
686
(priv->rf_type==RF_2T2R && rf_num!=2) ||
687
(priv->rf_type==RF_2T2R_GREEN && rf_num!=2) ||
688
(priv->rf_type==RF_2T4R && rf_num!=4))
689
{
690
RT_TRACE( COMP_INIT, "PHY_BBConfig8192S: RF_Type(%x) does not match RF_Num(%x)!!\n", priv->rf_type, rf_num);
691
}
692
return rtStatus;
693
}
694
695
extern bool
696
PHY_RFConfig8192S(struct net_device* dev)
697
{
698
struct r8192_priv *priv = rtllib_priv(dev);
699
bool rtStatus = true;
700
701
702
if (IS_HARDWARE_TYPE_8192SE(dev))
703
priv->rf_chip = RF_6052;
704
705
switch(priv->rf_chip)
706
{
707
case RF_8225:
708
case RF_6052:
709
rtStatus = PHY_RF6052_Config(dev);
710
break;
711
712
case RF_8256:
713
break;
714
715
case RF_8258:
716
break;
717
718
case RF_PSEUDO_11N:
719
break;
720
default:
721
break;
722
}
723
724
return rtStatus;
725
}
726
727
728
static bool
729
phy_BB8190_Config_HardCode(struct net_device* dev)
730
{
731
return true;
732
}
733
734
735
static bool
736
phy_BB8192S_Config_ParaFile(struct net_device* dev)
737
{
738
struct r8192_priv *priv = rtllib_priv(dev);
739
bool rtStatus = true;
740
741
RT_TRACE(COMP_INIT, "==>phy_BB8192S_Config_ParaFile\n");
742
743
#if RTL8190_Download_Firmware_From_Header
744
if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R ||
745
priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN)
746
{
747
rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_PHY_REG);
748
if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN)
749
{
750
rtStatus = phy_SetBBtoDiffRFWithHeaderFile(dev,BaseBand_Config_PHY_REG);
751
}
752
}else
753
rtStatus = false;
754
#else
755
RT_TRACE(COMP_INIT, "RF_Type == %d\n", priv->rf_type);
756
if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R ||
757
priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN)
758
{
759
rtStatus = phy_ConfigBBWithParaFile(dev, (char* )&szBBRegFile);
760
if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN)
761
{
762
if(priv->rf_type == RF_1T1R)
763
rtStatus = phy_SetBBtoDiffRFWithParaFile(dev, (char* )&szBBRegto1T1RFile);
764
else if(priv->rf_type == RF_1T2R)
765
rtStatus = phy_SetBBtoDiffRFWithParaFile(dev, (char* )&szBBRegto1T2RFile);
766
}
767
768
}else
769
rtStatus = false;
770
#endif
771
772
if(rtStatus != true){
773
RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!");
774
goto phy_BB8190_Config_ParaFile_Fail;
775
}
776
777
if (priv->AutoloadFailFlag == false)
778
{
779
priv->pwrGroupCnt = 0;
780
781
#if RTL8190_Download_Firmware_From_Header
782
rtStatus = phy_ConfigBBWithPgHeaderFile(dev,BaseBand_Config_PHY_REG);
783
#else
784
rtStatus = phy_ConfigBBWithPgParaFile(dev, (char* )&szBBRegPgFile);
785
#endif
786
}
787
if(rtStatus != true){
788
RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!");
789
goto phy_BB8190_Config_ParaFile_Fail;
790
}
791
792
#if RTL8190_Download_Firmware_From_Header
793
rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_AGC_TAB);
794
#else
795
RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile AGC_TAB.txt\n");
796
rtStatus = phy_ConfigBBWithParaFile(dev, (char* )&szAGCTableFile);
797
#endif
798
799
if(rtStatus != true){
800
printk( "phy_BB8192S_Config_ParaFile():AGC Table Fail\n");
801
goto phy_BB8190_Config_ParaFile_Fail;
802
}
803
804
805
#if 0
806
if(pHalData->VersionID > VERSION_8190_BD)
807
{
808
u4RegValue = ( pHalData->AntennaTxPwDiff[2]<<8 |
809
pHalData->AntennaTxPwDiff[1]<<4 |
810
pHalData->AntennaTxPwDiff[0]);
811
812
PHY_SetBBReg(dev, rFPGA0_TxGainStage,
813
(bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
814
815
u4RegValue = pHalData->CrystalCap;
816
PHY_SetBBReg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, u4RegValue);
817
818
}
819
#endif
820
821
priv->bCckHighPower = (bool)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
822
823
824
phy_BB8190_Config_ParaFile_Fail:
825
return rtStatus;
826
}
827
828
static bool
829
phy_ConfigMACWithHeaderFile(struct net_device* dev)
830
{
831
u32 i = 0;
832
u32 ArrayLength = 0;
833
u32* ptrArray;
834
835
/*if(dev->bInHctTest)
836
{
837
RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_ArrayDTM\n"));
838
ArrayLength = MACPHY_ArrayLengthDTM;
839
ptrArray = Rtl819XMACPHY_ArrayDTM;
840
}
841
else if(pHalData->bTXPowerDataReadFromEEPORM)
842
{
843
844
}else*/
845
{
846
RT_TRACE(COMP_INIT, "Read Rtl819XMACPHY_Array\n");
847
ArrayLength = MAC_2T_ArrayLength;
848
ptrArray = Rtl819XMAC_Array;
849
}
850
851
/*for(i = 0 ;i < ArrayLength;i=i+3){
852
RT_TRACE(COMP_SEND, DBG_LOUD, ("The Rtl819XMACPHY_Array[0] is %lx Rtl819XMACPHY_Array[1] is %lx Rtl819XMACPHY_Array[2] is %lx\n",ptrArray[i], ptrArray[i+1], ptrArray[i+2]));
853
if(ptrArray[i] == 0x318)
854
{
855
ptrArray[i+2] = 0x00000800;
856
}
857
PHY_SetBBReg(dev, ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
858
}*/
859
for(i = 0 ;i < ArrayLength;i=i+2){
860
write_nic_byte(dev, ptrArray[i], (u8)ptrArray[i+1]);
861
}
862
return true;
863
}
864
865
866
static bool
867
phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType)
868
{
869
int i;
870
u32* Rtl819XPHY_REGArray_Table;
871
u32* Rtl819XAGCTAB_Array_Table;
872
u16 PHY_REGArrayLen, AGCTAB_ArrayLen;
873
/*if(dev->bInHctTest)
874
{
875
876
AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
877
Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
878
879
if(pHalData->RF_Type == RF_2T4R)
880
{
881
PHY_REGArrayLen = PHY_REGArrayLengthDTM;
882
Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
883
}
884
else if (pHalData->RF_Type == RF_1T2R)
885
{
886
PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
887
Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
888
}
889
890
}
891
else
892
*/
893
AGCTAB_ArrayLen = AGCTAB_ArrayLength;
894
Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
895
PHY_REGArrayLen = PHY_REG_2T2RArrayLength;
896
Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_Array;
897
898
if(ConfigType == BaseBand_Config_PHY_REG)
899
{
900
for(i=0;i<PHY_REGArrayLen;i=i+2)
901
{
902
if (Rtl819XPHY_REGArray_Table[i] == 0xfe)
903
mdelay(50);
904
else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
905
mdelay(5);
906
else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
907
mdelay(1);
908
else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
909
udelay(50);
910
else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
911
udelay(5);
912
else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
913
udelay(1);
914
#ifdef ECS_T20_INIT_DELAY
915
udelay(1);
916
#endif
917
rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
918
919
}
920
}
921
else if(ConfigType == BaseBand_Config_AGC_TAB){
922
for(i=0;i<AGCTAB_ArrayLen;i=i+2)
923
{
924
rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
925
#ifdef ECS_T20_INIT_DELAY
926
udelay(1);
927
#endif
928
}
929
}
930
return true;
931
}
932
933
934
static bool
935
phy_SetBBtoDiffRFWithHeaderFile(struct net_device* dev, u8 ConfigType)
936
{
937
int i;
938
struct r8192_priv *priv = rtllib_priv(dev);
939
u32* Rtl819XPHY_REGArraytoXTXR_Table;
940
u16 PHY_REGArraytoXTXRLen;
941
942
if(priv->rf_type == RF_1T1R)
943
{
944
Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T1R_Array;
945
PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T1RArrayLength;
946
}
947
else if(priv->rf_type == RF_1T2R)
948
{
949
Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T2R_Array;
950
PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T2RArrayLength;
951
}
952
else
953
{
954
return false;
955
}
956
957
if(ConfigType == BaseBand_Config_PHY_REG)
958
{
959
for(i=0;i<PHY_REGArraytoXTXRLen;i=i+3)
960
{
961
if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfe)
962
mdelay(50);
963
else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfd)
964
mdelay(5);
965
else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfc)
966
mdelay(1);
967
else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfb)
968
udelay(50);
969
else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfa)
970
udelay(5);
971
else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xf9)
972
udelay(1);
973
rtl8192_setBBreg(dev, Rtl819XPHY_REGArraytoXTXR_Table[i], Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
974
}
975
}
976
else {
977
RT_TRACE(COMP_SEND, "phy_SetBBtoDiffRFWithHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
978
}
979
return true;
980
}
981
982
void
983
storePwrIndexDiffRateOffset(
984
struct net_device* dev,
985
u32 RegAddr,
986
u32 BitMask,
987
u32 Data
988
)
989
{
990
struct r8192_priv *priv = rtllib_priv(dev);
991
992
if(RegAddr == rTxAGC_Rate18_06)
993
{
994
priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][0] = Data;
995
}
996
if(RegAddr == rTxAGC_Rate54_24)
997
{
998
priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][1] = Data;
999
}
1000
if(RegAddr == rTxAGC_CCK_Mcs32)
1001
{
1002
priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][6] = Data;
1003
}
1004
if(RegAddr == rTxAGC_Mcs03_Mcs00)
1005
{
1006
priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][2] = Data;
1007
}
1008
if(RegAddr == rTxAGC_Mcs07_Mcs04)
1009
{
1010
priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][3] = Data;
1011
}
1012
if(RegAddr == rTxAGC_Mcs11_Mcs08)
1013
{
1014
priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][4] = Data;
1015
}
1016
if(RegAddr == rTxAGC_Mcs15_Mcs12)
1017
{
1018
priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][5] = Data;
1019
priv->pwrGroupCnt++;
1020
}
1021
}
1022
1023
static bool
1024
phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType)
1025
{
1026
int i;
1027
u32* Rtl819XPHY_REGArray_Table_PG;
1028
u16 PHY_REGArrayPGLen;
1029
1030
PHY_REGArrayPGLen = PHY_REG_Array_PGLength;
1031
Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG;
1032
1033
if(ConfigType == BaseBand_Config_PHY_REG)
1034
{
1035
for(i=0;i<PHY_REGArrayPGLen;i=i+3)
1036
{
1037
if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe)
1038
mdelay(50);
1039
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
1040
mdelay(5);
1041
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
1042
mdelay(1);
1043
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
1044
udelay(50);
1045
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
1046
udelay(5);
1047
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
1048
udelay(1);
1049
storePwrIndexDiffRateOffset(dev, Rtl819XPHY_REGArray_Table_PG[i],
1050
Rtl819XPHY_REGArray_Table_PG[i+1],
1051
Rtl819XPHY_REGArray_Table_PG[i+2]);
1052
rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
1053
}
1054
}
1055
else{
1056
RT_TRACE(COMP_SEND, "phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
1057
}
1058
return true;
1059
1060
} /* phy_ConfigBBWithPgHeaderFile */
1061
1062
RT_STATUS rtl8192_phy_configRFPABiascurrent(struct net_device *dev, RF90_RADIO_PATH_E eRFPath)
1063
{
1064
struct r8192_priv *priv = rtllib_priv(dev);
1065
RT_STATUS rtStatus = RT_STATUS_SUCCESS;
1066
u32 tmpval=0;
1067
1068
if(priv->IC_Class != IC_INFERIORITY_A)
1069
{
1070
tmpval = rtl8192_phy_QueryRFReg(dev, eRFPath, RF_IPA, 0xf);
1071
rtl8192_phy_SetRFReg(dev, eRFPath, RF_IPA, 0xf, tmpval+1);
1072
}
1073
1074
return rtStatus;
1075
}
1076
1077
u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
1078
{
1079
struct r8192_priv *priv = rtllib_priv(dev);
1080
int i;
1081
bool rtStatus = true;
1082
u32 *Rtl819XRadioA_Array_Table;
1083
u32 *Rtl819XRadioB_Array_Table;
1084
u16 RadioA_ArrayLen,RadioB_ArrayLen;
1085
1086
RadioA_ArrayLen = RadioA_1T_ArrayLength;
1087
Rtl819XRadioA_Array_Table=Rtl819XRadioA_Array;
1088
1089
if(priv->rf_type == RF_2T2R_GREEN)
1090
{
1091
Rtl819XRadioB_Array_Table = Rtl819XRadioB_GM_Array;
1092
RadioB_ArrayLen = RadioB_GM_ArrayLength;
1093
}
1094
else
1095
{
1096
Rtl819XRadioB_Array_Table=Rtl819XRadioB_Array;
1097
RadioB_ArrayLen = RadioB_ArrayLength;
1098
}
1099
1100
1101
RT_TRACE(COMP_INIT, "PHY_ConfigRFWithHeaderFile: Radio No %x\n", eRFPath);
1102
rtStatus = true;
1103
1104
switch(eRFPath){
1105
case RF90_PATH_A:
1106
for(i = 0;i<RadioA_ArrayLen; i=i+2)
1107
{
1108
if(Rtl819XRadioA_Array_Table[i] == 0xfe)
1109
{
1110
mdelay(50);
1111
}
1112
else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
1113
mdelay(5);
1114
else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
1115
mdelay(1);
1116
else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
1117
udelay(50);
1118
else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
1119
udelay(5);
1120
else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
1121
udelay(1);
1122
else {
1123
rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array_Table[i],
1124
bMask20Bits, Rtl819XRadioA_Array_Table[i+1]);
1125
}
1126
}
1127
rtl8192_phy_configRFPABiascurrent(dev, eRFPath);
1128
break;
1129
case RF90_PATH_B:
1130
for(i = 0;i<RadioB_ArrayLen; i=i+2){
1131
if(Rtl819XRadioB_Array_Table[i] == 0xfe)
1132
{
1133
mdelay(50);
1134
}
1135
else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
1136
mdelay(5);
1137
else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
1138
mdelay(1);
1139
else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
1140
udelay(50);
1141
else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
1142
udelay(5);
1143
else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
1144
udelay(1);
1145
else
1146
{
1147
rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array_Table[i], bMask20Bits, Rtl819XRadioB_Array_Table[i+1]);
1148
}
1149
#ifdef ECS_T20_INIT_DELAY
1150
udelay(1);
1151
#endif
1152
}
1153
break;
1154
case RF90_PATH_C:
1155
break;
1156
case RF90_PATH_D:
1157
break;
1158
default:
1159
break;
1160
}
1161
return rtStatus;
1162
1163
}
1164
1165
bool rtl8192_phy_checkBBAndRF(
1166
struct net_device* dev,
1167
HW90_BLOCK_E CheckBlock,
1168
RF90_RADIO_PATH_E eRFPath
1169
)
1170
{
1171
bool rtStatus = true;
1172
u32 i, CheckTimes = 4,ulRegRead = 0;
1173
u32 WriteAddr[4];
1174
u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
1175
1176
WriteAddr[HW90_BLOCK_MAC] = 0x100;
1177
WriteAddr[HW90_BLOCK_PHY0] = 0x900;
1178
WriteAddr[HW90_BLOCK_PHY1] = 0x800;
1179
WriteAddr[HW90_BLOCK_RF] = 0x3;
1180
1181
for(i=0 ; i < CheckTimes ; i++)
1182
{
1183
1184
switch(CheckBlock)
1185
{
1186
case HW90_BLOCK_MAC:
1187
RT_TRACE(COMP_INIT, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
1188
break;
1189
1190
case HW90_BLOCK_PHY0:
1191
case HW90_BLOCK_PHY1:
1192
write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
1193
ulRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
1194
break;
1195
1196
case HW90_BLOCK_RF:
1197
WriteData[i] &= 0xfff;
1198
rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask20Bits, WriteData[i]);
1199
mdelay(10);
1200
ulRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
1201
mdelay(10);
1202
break;
1203
1204
default:
1205
rtStatus = false;
1206
break;
1207
}
1208
1209
1210
if(ulRegRead != WriteData[i])
1211
{
1212
RT_TRACE(COMP_ERR, "read back error(read:%x, write:%x)\n", ulRegRead, WriteData[i]);
1213
rtStatus = false;
1214
break;
1215
}
1216
}
1217
1218
return rtStatus;
1219
}
1220
1221
#ifdef TO_DO_LIST
1222
void
1223
PHY_SetRFPowerState8192SUsb(
1224
struct net_device* dev,
1225
RF_POWER_STATE RFPowerState
1226
)
1227
{
1228
struct r8192_priv *priv = rtllib_priv(dev);
1229
bool WaitShutDown = false;
1230
u32 DWordContent;
1231
u8 eRFPath;
1232
BB_REGISTER_DEFINITION_T *pPhyReg;
1233
1234
if(priv->SetRFPowerStateInProgress == true)
1235
return;
1236
1237
priv->SetRFPowerStateInProgress = true;
1238
1239
1240
if(RFPowerState==RF_SHUT_DOWN)
1241
{
1242
RFPowerState=RF_OFF;
1243
WaitShutDown=true;
1244
}
1245
1246
1247
priv->RFPowerState = RFPowerState;
1248
switch( priv->rf_chip )
1249
{
1250
case RF_8225:
1251
case RF_6052:
1252
switch( RFPowerState )
1253
{
1254
case RF_ON:
1255
break;
1256
1257
case RF_SLEEP:
1258
break;
1259
1260
case RF_OFF:
1261
break;
1262
}
1263
break;
1264
1265
case RF_8256:
1266
switch( RFPowerState )
1267
{
1268
case RF_ON:
1269
break;
1270
1271
case RF_SLEEP:
1272
break;
1273
1274
case RF_OFF:
1275
for(eRFPath=(RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < RF90_PATH_MAX; eRFPath++)
1276
{
1277
if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1278
continue;
1279
1280
pPhyReg = &priv->PHYRegDef[eRFPath];
1281
rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, bRFSI_RFENV);
1282
rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0);
1283
}
1284
break;
1285
}
1286
break;
1287
1288
case RF_8258:
1289
break;
1290
}
1291
1292
priv->SetRFPowerStateInProgress = false;
1293
}
1294
#endif
1295
1296
void PHY_GetHWRegOriginalValue(struct net_device* dev)
1297
{
1298
struct r8192_priv *priv = rtllib_priv(dev);
1299
#if 0
1300
priv->MCSTxPowerLevelOriginalOffset[0] =
1301
rtl8192_QueryBBReg(dev, rTxAGC_Rate18_06, bMaskDWord);
1302
priv->MCSTxPowerLevelOriginalOffset[1] =
1303
rtl8192_QueryBBReg(dev, rTxAGC_Rate54_24, bMaskDWord);
1304
priv->MCSTxPowerLevelOriginalOffset[2] =
1305
rtl8192_QueryBBReg(dev, rTxAGC_Mcs03_Mcs00, bMaskDWord);
1306
priv->MCSTxPowerLevelOriginalOffset[3] =
1307
rtl8192_QueryBBReg(dev, rTxAGC_Mcs07_Mcs04, bMaskDWord);
1308
priv->MCSTxPowerLevelOriginalOffset[4] =
1309
rtl8192_QueryBBReg(dev, rTxAGC_Mcs11_Mcs08, bMaskDWord);
1310
priv->MCSTxPowerLevelOriginalOffset[5] =
1311
rtl8192_QueryBBReg(dev, rTxAGC_Mcs15_Mcs12, bMaskDWord);
1312
1313
priv->CCKTxPowerLevelOriginalOffset=
1314
rtl8192_QueryBBReg(dev, rTxAGC_CCK_Mcs32, bMaskDWord);
1315
RT_TRACE(COMP_INIT, "Legacy OFDM =%08x/%08x HT_OFDM=%08x/%08x/%08x/%08x\n",
1316
priv->MCSTxPowerLevelOriginalOffset[0], priv->MCSTxPowerLevelOriginalOffset[1] ,
1317
priv->MCSTxPowerLevelOriginalOffset[2], priv->MCSTxPowerLevelOriginalOffset[3] ,
1318
priv->MCSTxPowerLevelOriginalOffset[4], priv->MCSTxPowerLevelOriginalOffset[5] );
1319
#endif
1320
1321
priv->DefaultInitialGain[0] = rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bMaskByte0);
1322
priv->DefaultInitialGain[1] = rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bMaskByte0);
1323
priv->DefaultInitialGain[2] = rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bMaskByte0);
1324
priv->DefaultInitialGain[3] = rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bMaskByte0);
1325
RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
1326
priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
1327
priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
1328
1329
priv->framesync = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector3, bMaskByte0);
1330
priv->framesyncC34 = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector2, bMaskDWord);
1331
RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
1332
rOFDM0_RxDetector3, priv->framesync);
1333
1334
}
1335
1336
1337
1338
static void phy_InitBBRFRegisterDefinition( struct net_device* dev)
1339
{
1340
struct r8192_priv *priv = rtllib_priv(dev);
1341
1342
priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
1343
priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
1344
priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
1345
priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
1346
1347
priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
1348
priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
1349
priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
1350
priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
1351
1352
priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
1353
priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
1354
priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
1355
priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
1356
1357
priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
1358
priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
1359
priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
1360
priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
1361
1362
priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
1363
priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
1364
priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
1365
priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
1366
1367
priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
1368
priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
1369
priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1370
priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1371
1372
priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
1373
priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
1374
priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
1375
priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
1376
1377
priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
1378
priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
1379
priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
1380
priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
1381
1382
priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
1383
priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
1384
priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
1385
priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
1386
1387
priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
1388
priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
1389
priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1390
priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1391
1392
priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
1393
priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
1394
priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
1395
priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
1396
1397
priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
1398
priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
1399
priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
1400
priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
1401
1402
priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
1403
priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
1404
priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
1405
priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
1406
1407
priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
1408
priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
1409
priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
1410
priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
1411
1412
priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
1413
priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
1414
priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
1415
priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
1416
1417
priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
1418
priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
1419
priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
1420
priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
1421
1422
priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
1423
priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
1424
priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
1425
priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
1426
1427
priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
1428
priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
1429
1430
}
1431
1432
1433
bool PHY_SetRFPowerState(struct net_device* dev, RT_RF_POWER_STATE eRFPowerState)
1434
{
1435
struct r8192_priv *priv = rtllib_priv(dev);
1436
bool bResult = false;
1437
1438
RT_TRACE((COMP_PS | COMP_RF), "---------> PHY_SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
1439
1440
if(eRFPowerState == priv->rtllib->eRFPowerState)
1441
{
1442
;
1443
return bResult;
1444
}
1445
1446
bResult = phy_SetRFPowerState8192SE(dev, eRFPowerState);
1447
1448
RT_TRACE((COMP_PS | COMP_RF), "<--------- PHY_SetRFPowerState(): bResult(%d)\n", bResult);
1449
1450
return bResult;
1451
}
1452
1453
static bool phy_SetRFPowerState8192SE(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState)
1454
{
1455
struct r8192_priv *priv = rtllib_priv(dev);
1456
PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->rtllib->PowerSaveControl));
1457
bool bResult = true;
1458
u8 i, QueueID;
1459
struct rtl8192_tx_ring *ring = NULL;
1460
priv->SetRFPowerStateInProgress = true;
1461
1462
switch(priv->rf_chip )
1463
{
1464
default:
1465
switch( eRFPowerState )
1466
{
1467
case eRfOn:
1468
RT_TRACE(COMP_PS,"========>%s():eRfOn\n", __func__);
1469
{
1470
if((priv->rtllib->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
1471
{
1472
bool rtstatus = true;
1473
u32 InitializeCount = 0;
1474
do
1475
{
1476
InitializeCount++;
1477
rtstatus = NicIFEnableNIC(dev);
1478
}while( (rtstatus != true) &&(InitializeCount < 10) );
1479
if(rtstatus != true)
1480
{
1481
RT_TRACE(COMP_ERR,"%s():Initialize Adapter fail,return\n",__FUNCTION__);
1482
priv->SetRFPowerStateInProgress = false;
1483
return false;
1484
}
1485
RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
1486
}
1487
else
1488
{
1489
write_nic_word(dev, CMDR, 0x37FC);
1490
write_nic_byte(dev, TXPAUSE, 0x00);
1491
write_nic_byte(dev, PHY_CCA, 0x3);
1492
}
1493
1494
#if 1
1495
if(priv->rtllib->state == RTLLIB_LINKED)
1496
{
1497
LedControl8192SE(dev, LED_CTL_LINK);
1498
}
1499
else
1500
{
1501
LedControl8192SE(dev, LED_CTL_NO_LINK);
1502
}
1503
#endif
1504
}
1505
break;
1506
case eRfOff:
1507
RT_TRACE(COMP_PS,"========>%s():eRfOff\n", __func__);
1508
{
1509
for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
1510
{
1511
ring = &priv->tx_ring[QueueID];
1512
if(skb_queue_len(&ring->queue) == 0)
1513
{
1514
QueueID++;
1515
continue;
1516
}
1517
#ifdef TO_DO_LIST
1518
#if( DEV_BUS_TYPE==PCI_INTERFACE)
1519
else if(IsLowPowerState(Adapter))
1520
{
1521
RT_TRACE(COMP_PS, DBG_LOUD,
1522
("eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", (i+1), QueueID));
1523
break;
1524
}
1525
#endif
1526
#endif
1527
else
1528
{
1529
RT_TRACE(COMP_PS, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
1530
udelay(10);
1531
i++;
1532
}
1533
1534
if(i >= MAX_DOZE_WAITING_TIMES_9x)
1535
{
1536
RT_TRACE(COMP_PS, "\n\n\n %s(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", __FUNCTION__,MAX_DOZE_WAITING_TIMES_9x, QueueID);
1537
break;
1538
}
1539
}
1540
1541
if(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
1542
{
1543
NicIFDisableNIC(dev);
1544
RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
1545
if(priv->pwrdown && priv->rtllib->RfOffReason>= RF_CHANGE_BY_HW)
1546
write_nic_byte(dev,0x03,0x31);
1547
}
1548
else if(!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC))
1549
{
1550
SET_RTL8192SE_RF_SLEEP(dev);
1551
1552
#if 1
1553
if(priv->rtllib->RfOffReason == RF_CHANGE_BY_IPS )
1554
{
1555
LedControl8192SE(dev,LED_CTL_NO_LINK);
1556
}
1557
else
1558
{
1559
LedControl8192SE(dev, LED_CTL_POWER_OFF);
1560
}
1561
#endif
1562
}
1563
}
1564
break;
1565
1566
case eRfSleep:
1567
RT_TRACE(COMP_PS,"========>%s():eRfSleep\n", __func__);
1568
{
1569
if(priv->rtllib->eRFPowerState == eRfOff)
1570
break;
1571
1572
for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
1573
{
1574
ring = &priv->tx_ring[QueueID];
1575
if(skb_queue_len(&ring->queue) == 0)
1576
{
1577
QueueID++;
1578
continue;
1579
}
1580
#ifdef TO_DO_LIST
1581
#if( DEV_BUS_TYPE==PCI_INTERFACE)
1582
else if(IsLowPowerState(Adapter))
1583
{
1584
RT_TRACE(COMP_PS, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", (i+1), QueueID);
1585
break;
1586
}
1587
#endif
1588
#endif
1589
else
1590
{
1591
RT_TRACE(COMP_PS, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
1592
udelay(10);
1593
i++;
1594
}
1595
1596
if(i >= MAX_DOZE_WAITING_TIMES_9x)
1597
{
1598
RT_TRACE(COMP_PS, "\n\n\n %s(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", __FUNCTION__,MAX_DOZE_WAITING_TIMES_9x, QueueID);
1599
break;
1600
}
1601
}
1602
1603
SET_RTL8192SE_RF_SLEEP(dev);
1604
}
1605
break;
1606
1607
default:
1608
bResult = false;
1609
RT_TRACE(COMP_ERR, "phy_SetRFPowerState8192S(): unknow state to set: 0x%X!!!\n", eRFPowerState);
1610
break;
1611
}
1612
break;
1613
}
1614
1615
if(bResult)
1616
{
1617
priv->rtllib->eRFPowerState = eRFPowerState;
1618
}
1619
1620
priv->SetRFPowerStateInProgress = false;
1621
1622
return bResult;
1623
}
1624
1625
1626
void
1627
PHY_SwitchEphyParameter(struct net_device* dev)
1628
{
1629
struct r8192_priv *priv = rtllib_priv(dev);
1630
1631
write_nic_dword(dev, 0x540, 0x73c11);
1632
write_nic_dword(dev, 0x548, 0x2407c);
1633
1634
write_nic_word(dev, 0x550, 0x1000);
1635
write_nic_byte(dev, 0x554, 0x20);
1636
phy_CheckEphySwitchReady(dev);
1637
1638
write_nic_word(dev, 0x550, 0xa0eb);
1639
write_nic_byte(dev, 0x554, 0x3e);
1640
phy_CheckEphySwitchReady(dev);
1641
1642
write_nic_word(dev, 0x550, 0xff80);
1643
write_nic_byte(dev, 0x554, 0x39);
1644
phy_CheckEphySwitchReady(dev);
1645
1646
if (priv->pci_bridge_vendor & (PCI_BRIDGE_VENDOR_INTEL | PCI_BRIDGE_VENDOR_SIS))
1647
write_nic_byte(dev, 0x560, 0x40);
1648
else
1649
write_nic_byte(dev, 0x560, 0x00);
1650
1651
}
1652
1653
1654
void
1655
PHY_GetTxPowerLevel8192S(
1656
struct net_device* dev,
1657
long* powerlevel
1658
)
1659
{
1660
struct r8192_priv *priv = rtllib_priv(dev);
1661
u8 TxPwrLevel = 0;
1662
long TxPwrDbm;
1663
1664
TxPwrLevel = priv->CurrentCckTxPwrIdx;
1665
TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_B, TxPwrLevel);
1666
1667
TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx + priv->LegacyHTTxPowerDiff;
1668
1669
if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
1670
TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel);
1671
TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx;
1672
1673
if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
1674
TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel);
1675
*powerlevel = TxPwrDbm;
1676
}
1677
1678
#if 1
1679
void getTxPowerIndex(
1680
struct net_device* dev,
1681
u8 channel,
1682
u8* cckPowerLevel,
1683
u8* ofdmPowerLevel
1684
)
1685
{
1686
struct r8192_priv *priv = rtllib_priv(dev);
1687
u8 index = (channel -1);
1688
cckPowerLevel[0] = priv->RfTxPwrLevelCck[0][index];
1689
cckPowerLevel[1] = priv->RfTxPwrLevelCck[1][index];
1690
1691
if (priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R)
1692
{
1693
ofdmPowerLevel[0] = priv->RfTxPwrLevelOfdm1T[0][index];
1694
ofdmPowerLevel[1] = priv->RfTxPwrLevelOfdm1T[1][index];
1695
}
1696
else if (priv->rf_type == RF_2T2R)
1697
{
1698
ofdmPowerLevel[0] = priv->RfTxPwrLevelOfdm2T[0][index];
1699
ofdmPowerLevel[1] = priv->RfTxPwrLevelOfdm2T[1][index];
1700
}
1701
RT_TRACE(COMP_POWER,"Channel-%d, set tx power index !!\n", channel);
1702
}
1703
1704
void ccxPowerIndexCheck(
1705
struct net_device* dev,
1706
u8 channel,
1707
u8* cckPowerLevel,
1708
u8* ofdmPowerLevel
1709
)
1710
{
1711
struct r8192_priv *priv = rtllib_priv(dev);
1712
1713
#ifdef TODO
1714
if( priv->rtllib->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr &&
1715
channel == priv->rtllib->current_network.channel)
1716
{
1717
u8 CckCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, priv->CcxCellPwr);
1718
u8 LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_G, priv->CcxCellPwr);
1719
u8 OfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, priv->CcxCellPwr);
1720
1721
RT_TRACE(COMP_TXAGC,
1722
"CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
1723
priv->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx);
1724
RT_TRACE(COMP_TXAGC,
1725
"EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
1726
channel, cckPowerLevel[0], ofdmPowerLevel[0] + priv->LegacyHTTxPowerDiff, ofdmPowerLevel[0]);
1727
1728
if(cckPowerLevel[0] > CckCellPwrIdx)
1729
cckPowerLevel[0] = CckCellPwrIdx;
1730
if(ofdmPowerLevel[0] + priv->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
1731
{
1732
if((OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff) > 0)
1733
{
1734
ofdmPowerLevel[0] = OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff;
1735
}
1736
else
1737
{
1738
ofdmPowerLevel[0] = 0;
1739
}
1740
}
1741
1742
RT_TRACE(COMP_TXAGC,
1743
"Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
1744
cckPowerLevel[0], ofdmPowerLevel[0] + priv->LegacyHTTxPowerDiff, ofdmPowerLevel[0]);
1745
}
1746
1747
#endif
1748
priv->CurrentCckTxPwrIdx = cckPowerLevel[0];
1749
priv->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0];
1750
1751
RT_TRACE(COMP_TXAGC,
1752
"PHY_SetTxPowerLevel8192S(): CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
1753
cckPowerLevel[0], ofdmPowerLevel[0] + priv->LegacyHTTxPowerDiff, ofdmPowerLevel[0]);
1754
1755
}
1756
/*-----------------------------------------------------------------------------
1757
* Function: SetTxPowerLevel8190()
1758
*
1759
* Overview: This function is export to "HalCommon" moudule
1760
* We must consider RF path later!!!!!!!
1761
*
1762
* Input: PADAPTER Adapter
1763
* u1Byte channel
1764
*
1765
* Output: NONE
1766
*
1767
* Return: NONE
1768
* 2008/11/04 MHC We remove EEPROM_93C56.
1769
* We need to move CCX relative code to independet file.
1770
* 2009/01/21 MHC Support new EEPROM format from SD3 requirement.
1771
*
1772
*---------------------------------------------------------------------------*/
1773
void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
1774
{
1775
struct r8192_priv *priv = rtllib_priv(dev);
1776
u8 cckPowerLevel[2], ofdmPowerLevel[2];
1777
1778
if(priv->bTXPowerDataReadFromEEPORM == false)
1779
return;
1780
getTxPowerIndex(dev, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]);
1781
RT_TRACE(COMP_POWER, "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
1782
channel, cckPowerLevel[0], cckPowerLevel[1], ofdmPowerLevel[0], ofdmPowerLevel[1]);
1783
1784
ccxPowerIndexCheck(dev, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]);
1785
1786
switch(priv->rf_chip)
1787
{
1788
case RF_8225:
1789
break;
1790
1791
case RF_8256:
1792
;
1793
break;
1794
1795
case RF_6052:
1796
PHY_RF6052SetCckTxPower(dev, cckPowerLevel[0]);
1797
PHY_RF6052SetOFDMTxPower(dev, &ofdmPowerLevel[0], channel);
1798
break;
1799
1800
case RF_8258:
1801
break;
1802
default:
1803
break;
1804
}
1805
}
1806
#else
1807
void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
1808
{
1809
struct r8192_priv *priv = rtllib_priv(dev);
1810
u8 powerlevel = (u8)EEPROM_Default_TxPower, powerlevelOFDM24G = 0x10;
1811
s8 ant_pwr_diff = 0;
1812
u32 u4RegValue;
1813
u8 index = (channel -1);
1814
u8 pwrdiff[2] = {0};
1815
u8 ht20pwr[2] = {0}, ht40pwr[2] = {0};
1816
u8 rfpath = 0, rfpathnum = 2;
1817
1818
if(priv->bTXPowerDataReadFromEEPORM == false)
1819
return;
1820
1821
1822
powerlevel = priv->RfTxPwrLevelCck[0][index];
1823
1824
if (priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R)
1825
{
1826
powerlevelOFDM24G = priv->RfTxPwrLevelOfdm1T[0][index];
1827
1828
1829
rfpathnum = 1;
1830
ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm1T[0][index];
1831
}
1832
else if (priv->rf_type == RF_2T2R)
1833
{
1834
powerlevelOFDM24G = priv->RfTxPwrLevelOfdm2T[0][index];
1835
ant_pwr_diff = priv->RfTxPwrLevelOfdm2T[1][index] -
1836
priv->RfTxPwrLevelOfdm2T[0][index];
1837
1838
RT_TRACE(COMP_POWER, "CH-%d HT40 A/B Pwr index = %x/%x(%d/%d)\n",
1839
channel, priv->RfTxPwrLevelOfdm2T[0][index],
1840
priv->RfTxPwrLevelOfdm2T[1][index],
1841
priv->RfTxPwrLevelOfdm2T[0][index],
1842
priv->RfTxPwrLevelOfdm2T[1][index]);
1843
1844
ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm2T[0][index];
1845
ht20pwr[1] = ht40pwr[1] = priv->RfTxPwrLevelOfdm2T[1][index];
1846
}
1847
RT_TRACE(COMP_POWER, "Channel-%d, set tx power index\n", channel);
1848
1849
if (priv->eeprom_version >= 2)
1850
{
1851
if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
1852
{
1853
for (rfpath = 0; rfpath < rfpathnum; rfpath++)
1854
{
1855
pwrdiff[rfpath] = priv->TxPwrHt20Diff[rfpath][index];
1856
1857
if (pwrdiff[rfpath] < 8)
1858
{
1859
ht20pwr[rfpath] += pwrdiff[rfpath];
1860
}
1861
else
1862
{
1863
ht20pwr[rfpath] -= (16-pwrdiff[rfpath]);
1864
}
1865
}
1866
1867
if (priv->rf_type == RF_2T2R)
1868
ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
1869
1870
RT_TRACE(COMP_POWER, "HT20 to HT40 pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
1871
pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]);
1872
}
1873
}
1874
1875
if(ant_pwr_diff > 7)
1876
ant_pwr_diff = 7;
1877
if(ant_pwr_diff < -8)
1878
ant_pwr_diff = -8;
1879
1880
RT_TRACE(COMP_POWER, "CCK/HT Power index = %x/%x(%d/%d), ant_pwr_diff=%d\n",
1881
powerlevel, powerlevelOFDM24G, powerlevel, powerlevelOFDM24G, ant_pwr_diff);
1882
1883
ant_pwr_diff &= 0xf;
1884
1885
priv->AntennaTxPwDiff[2] = 0;
1886
priv->AntennaTxPwDiff[1] = 0;
1887
priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff);
1888
RT_TRACE(COMP_POWER, "pHalData->AntennaTxPwDiff[0]/[1]/[2] = 0x%x/0x%x/0x%x\n",
1889
priv->AntennaTxPwDiff[0], priv->AntennaTxPwDiff[1], priv->AntennaTxPwDiff[2]);
1890
u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 |
1891
priv->AntennaTxPwDiff[1]<<4 |
1892
priv->AntennaTxPwDiff[0] );
1893
RT_TRACE(COMP_POWER, "BCD-Diff=0x%x\n", u4RegValue);
1894
1895
rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
1896
1897
#ifdef TODO
1898
if( priv->rtllib->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr &&
1899
channel == priv->rtllib->current_network.channel)
1900
{
1901
u8 CckCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, priv->CcxCellPwr);
1902
u8 LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_G, priv->CcxCellPwr);
1903
u8 OfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, priv->CcxCellPwr);
1904
1905
RT_TRACE(COMP_TXAGC,
1906
("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
1907
priv->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
1908
RT_TRACE(COMP_TXAGC,
1909
("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
1910
channel, powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
1911
1912
if(powerlevel > CckCellPwrIdx)
1913
powerlevel = CckCellPwrIdx;
1914
if(powerlevelOFDM24G + priv->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
1915
{
1916
if((OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff) > 0)
1917
{
1918
powerlevelOFDM24G = OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff;
1919
}
1920
else
1921
{
1922
powerlevelOFDM24G = 0;
1923
}
1924
}
1925
1926
RT_TRACE(COMP_TXAGC,
1927
("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
1928
powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
1929
}
1930
#endif
1931
priv->CurrentCckTxPwrIdx = powerlevel;
1932
priv->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
1933
1934
RT_TRACE(COMP_POWER, "PHY_SetTxPowerLevel8192S(): CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
1935
powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G);
1936
1937
switch(priv->rf_chip)
1938
{
1939
case RF_8225:
1940
break;
1941
1942
case RF_8256:
1943
break;
1944
1945
case RF_6052:
1946
PHY_RF6052SetCckTxPower(dev, powerlevel);
1947
PHY_RF6052SetOFDMTxPower(dev, powerlevelOFDM24G, channel);
1948
break;
1949
1950
case RF_8258:
1951
break;
1952
default:
1953
break;
1954
}
1955
1956
}
1957
#endif
1958
1959
bool PHY_UpdateTxPowerDbm8192S(struct net_device* dev, long powerInDbm)
1960
{
1961
struct r8192_priv *priv = rtllib_priv(dev);
1962
u8 idx;
1963
u8 rf_path;
1964
1965
u8 CckTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, powerInDbm);
1966
u8 OfdmTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, powerInDbm);
1967
1968
if(OfdmTxPwrIdx - priv->LegacyHTTxPowerDiff > 0)
1969
OfdmTxPwrIdx -= priv->LegacyHTTxPowerDiff;
1970
else
1971
OfdmTxPwrIdx = 0;
1972
1973
RT_TRACE(COMP_POWER, "PHY_UpdateTxPowerDbm8192S(): %ld dBm , CckTxPwrIdx = %d, OfdmTxPwrIdx = %d\n", powerInDbm, CckTxPwrIdx, OfdmTxPwrIdx);
1974
1975
for(idx = 0; idx < 14; idx++)
1976
{
1977
priv->TxPowerLevelCCK[idx] = CckTxPwrIdx;
1978
priv->TxPowerLevelCCK_A[idx] = CckTxPwrIdx;
1979
priv->TxPowerLevelCCK_C[idx] = CckTxPwrIdx;
1980
priv->TxPowerLevelOFDM24G[idx] = OfdmTxPwrIdx;
1981
priv->TxPowerLevelOFDM24G_A[idx] = OfdmTxPwrIdx;
1982
priv->TxPowerLevelOFDM24G_C[idx] = OfdmTxPwrIdx;
1983
for (rf_path = 0; rf_path < 2; rf_path++)
1984
{
1985
priv->RfTxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
1986
priv->RfTxPwrLevelOfdm1T[rf_path][idx] =
1987
priv->RfTxPwrLevelOfdm2T[rf_path][idx] = OfdmTxPwrIdx;
1988
}
1989
}
1990
1991
rtl8192_phy_setTxPower(dev, priv->chan);
1992
1993
return true;
1994
}
1995
1996
extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval)
1997
{
1998
struct r8192_priv *priv = rtllib_priv(dev);
1999
u32 NewBeaconNum;
2000
2001
if(priv->pFirmware->FirmwareVersion >= 0x33)
2002
{
2003
write_nic_dword(dev,WFM5,0xF1000000|(BeaconInterval<<8));
2004
}
2005
else
2006
{
2007
NewBeaconNum = BeaconInterval *32 - 64;
2008
write_nic_dword(dev, WFM3+4, NewBeaconNum);
2009
write_nic_dword(dev, WFM3, 0xB026007C);
2010
}
2011
}
2012
2013
static u8 phy_DbmToTxPwrIdx(
2014
struct net_device* dev,
2015
WIRELESS_MODE WirelessMode,
2016
long PowerInDbm
2017
)
2018
{
2019
u8 TxPwrIdx = 0;
2020
long Offset = 0;
2021
2022
2023
switch(WirelessMode)
2024
{
2025
case WIRELESS_MODE_B:
2026
Offset = -7;
2027
break;
2028
2029
case WIRELESS_MODE_G:
2030
Offset = -8;
2031
break;
2032
2033
case WIRELESS_MODE_N_24G:
2034
default:
2035
Offset = -8;
2036
break;
2037
}
2038
2039
if((PowerInDbm - Offset) > 0)
2040
{
2041
TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);
2042
}
2043
else
2044
{
2045
TxPwrIdx = 0;
2046
}
2047
2048
if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
2049
TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;
2050
2051
return TxPwrIdx;
2052
}
2053
2054
static long phy_TxPwrIdxToDbm(
2055
struct net_device* dev,
2056
WIRELESS_MODE WirelessMode,
2057
u8 TxPwrIdx
2058
)
2059
{
2060
long Offset = 0;
2061
long PwrOutDbm = 0;
2062
2063
switch(WirelessMode)
2064
{
2065
case WIRELESS_MODE_B:
2066
Offset = -7;
2067
break;
2068
2069
case WIRELESS_MODE_G:
2070
case WIRELESS_MODE_N_24G:
2071
Offset = -8;
2072
break;
2073
default:
2074
Offset = -8;
2075
break;
2076
}
2077
2078
PwrOutDbm = TxPwrIdx / 2 + Offset;
2079
2080
return PwrOutDbm;
2081
}
2082
2083
#ifdef TO_DO_LIST
2084
extern void
2085
PHY_ScanOperationBackup8192S(
2086
struct net_device* dev,
2087
u8 Operation
2088
)
2089
{
2090
#if(RTL8192S_DISABLE_FW_DM == 0)
2091
2092
if(!Adapter->bDriverStopped)
2093
{
2094
switch(Operation)
2095
{
2096
case SCAN_OPT_BACKUP:
2097
Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_PAUSE_DM_BY_SCAN);
2098
break;
2099
2100
case SCAN_OPT_RESTORE:
2101
Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_RESUME_DM_BY_SCAN);
2102
break;
2103
2104
default:
2105
RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
2106
break;
2107
}
2108
}
2109
#endif
2110
}
2111
#endif
2112
void PHY_SetBWModeCallback8192S(struct net_device *dev)
2113
{
2114
struct r8192_priv *priv = rtllib_priv(dev);
2115
u8 regBwOpMode, regRRSR_RSC;
2116
2117
2118
2119
RT_TRACE(COMP_SWBW, "==>SetBWModeCallback8192s() Switch to %s bandwidth\n", \
2120
priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
2121
2122
if(priv->rf_chip == RF_PSEUDO_11N)
2123
{
2124
priv->SetBWModeInProgress= false;
2125
return;
2126
}
2127
#ifdef _RTL8192_EXT_PATCH_
2128
if((!priv->up) && (!priv->mesh_up))
2129
#else
2130
if(!priv->up)
2131
#endif
2132
{
2133
priv->SwChnlInProgress = priv->SetBWModeInProgress = false;
2134
return;
2135
}
2136
2137
regBwOpMode = read_nic_byte(dev, BW_OPMODE);
2138
regRRSR_RSC = read_nic_byte(dev, RRSR+2);
2139
2140
switch(priv->CurrentChannelBW)
2141
{
2142
case HT_CHANNEL_WIDTH_20:
2143
regBwOpMode |= BW_OPMODE_20MHZ;
2144
write_nic_byte(dev, BW_OPMODE, regBwOpMode);
2145
break;
2146
2147
case HT_CHANNEL_WIDTH_20_40:
2148
regBwOpMode &= ~BW_OPMODE_20MHZ;
2149
write_nic_byte(dev, BW_OPMODE, regBwOpMode);
2150
2151
break;
2152
2153
default:
2154
RT_TRACE(COMP_DBG, "SetBWModeCallback8192s():\
2155
unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
2156
break;
2157
}
2158
2159
switch(priv->CurrentChannelBW)
2160
{
2161
case HT_CHANNEL_WIDTH_20:
2162
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
2163
rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
2164
2165
if(priv->card_8192_version >= VERSION_8192S_BCUT)
2166
write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
2167
break;
2168
2169
case HT_CHANNEL_WIDTH_20_40:
2170
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
2171
rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
2172
2173
2174
rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
2175
rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
2176
2177
if(priv->card_8192_version >= VERSION_8192S_BCUT)
2178
write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
2179
break;
2180
2181
default:
2182
RT_TRACE(COMP_DBG, "SetBWModeCallback8192s(): unknown Bandwidth: %#X\n"\
2183
,priv->CurrentChannelBW);
2184
break;
2185
2186
}
2187
2188
2189
switch( priv->rf_chip )
2190
{
2191
case RF_8225:
2192
break;
2193
2194
case RF_8256:
2195
break;
2196
2197
case RF_8258:
2198
break;
2199
2200
case RF_PSEUDO_11N:
2201
break;
2202
2203
case RF_6052:
2204
PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
2205
break;
2206
default:
2207
printk("Unknown rf_chip: %d\n", priv->rf_chip);
2208
break;
2209
}
2210
2211
priv->SetBWModeInProgress= false;
2212
2213
RT_TRACE(COMP_SWBW, "<==SetBWModeCallback8192s() \n" );
2214
}
2215
2216
2217
void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
2218
{
2219
struct r8192_priv *priv = rtllib_priv(dev);
2220
2221
2222
2223
2224
2225
if(priv->SetBWModeInProgress)
2226
return;
2227
2228
priv->SetBWModeInProgress= true;
2229
2230
priv->CurrentChannelBW = Bandwidth;
2231
2232
if(Offset==HT_EXTCHNL_OFFSET_LOWER)
2233
priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
2234
else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
2235
priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
2236
else
2237
priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
2238
2239
#if 0
2240
if(!priv->bDriverStopped)
2241
{
2242
#ifdef USE_WORKITEM
2243
PlatformScheduleWorkItem(&(priv->SetBWModeWorkItem));
2244
#else
2245
PlatformSetTimer(dev, &(priv->SetBWModeTimer), 0);
2246
#endif
2247
}
2248
#endif
2249
#ifdef _RTL8192_EXT_PATCH_
2250
if(priv->up || priv->mesh_up)
2251
#else
2252
if (priv->up)
2253
#endif
2254
{
2255
PHY_SetBWModeCallback8192S(dev);
2256
} else {
2257
priv->SetBWModeInProgress= false;
2258
}
2259
}
2260
2261
void PHY_SwChnlCallback8192S(struct net_device *dev)
2262
{
2263
2264
struct r8192_priv *priv = rtllib_priv(dev);
2265
u32 delay;
2266
2267
RT_TRACE(COMP_CH, "==>SwChnlCallback8190Pci(), switch to channel %d\n", priv->chan);
2268
2269
#ifdef _RTL8192_EXT_PATCH_
2270
if((!priv->up) && (!priv->mesh_up))
2271
#else
2272
if(!priv->up)
2273
#endif
2274
{
2275
printk("%s: driver is not up\n", __FUNCTION__);
2276
priv->SwChnlInProgress = priv->SetBWModeInProgress = false;
2277
return;
2278
}
2279
if(priv->rf_chip == RF_PSEUDO_11N)
2280
{
2281
printk("%s: rt chip is RF_PSEUDO_11N\n", __FUNCTION__);
2282
priv->SwChnlInProgress=false;
2283
return;
2284
}
2285
2286
do{
2287
if(!priv->SwChnlInProgress)
2288
break;
2289
2290
if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
2291
{
2292
if(delay>0)
2293
{
2294
mdelay(delay);
2295
}
2296
else
2297
continue;
2298
}
2299
else
2300
{
2301
priv->SwChnlInProgress=false;
2302
break;
2303
}
2304
}while(true);
2305
}
2306
2307
u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
2308
{
2309
struct r8192_priv *priv = rtllib_priv(dev);
2310
2311
#ifdef _RTL8192_EXT_PATCH_
2312
if((!priv->up) && (!priv->mesh_up))
2313
#else
2314
if(!priv->up)
2315
#endif
2316
{
2317
printk("%s: driver is not up.\n",__FUNCTION__);
2318
priv->SwChnlInProgress = priv->SetBWModeInProgress = false;
2319
return false;
2320
}
2321
if(priv->SwChnlInProgress){
2322
printk("%s: SwChnl is in progress\n",__FUNCTION__);
2323
return false;
2324
}
2325
2326
if(priv->SetBWModeInProgress){
2327
printk("%s: Set BWMode is in progress\n",__FUNCTION__);
2328
return false;
2329
}
2330
if (0)
2331
{
2332
u8 path;
2333
for(path=0; path<2; path++){
2334
printk("============>to set channel:%x\n", rtl8192_phy_QueryRFReg(dev, path, 0x18, 0x3ff));
2335
udelay(10);
2336
}
2337
}
2338
switch(priv->rtllib->mode)
2339
{
2340
case WIRELESS_MODE_A:
2341
case WIRELESS_MODE_N_5G:
2342
if (channel<=14){
2343
RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
2344
return false;
2345
}
2346
break;
2347
2348
case WIRELESS_MODE_B:
2349
if (channel>14){
2350
RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
2351
return false;
2352
}
2353
break;
2354
2355
case WIRELESS_MODE_G:
2356
case WIRELESS_MODE_N_24G:
2357
if (channel>14){
2358
RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
2359
return false;
2360
}
2361
break;
2362
2363
default:
2364
break;
2365
}
2366
2367
priv->SwChnlInProgress = true;
2368
if( channel == 0)
2369
channel = 1;
2370
2371
priv->chan=channel;
2372
2373
priv->SwChnlStage=0;
2374
priv->SwChnlStep=0;
2375
2376
#if 0
2377
if(!dev->bDriverStopped)
2378
{
2379
#ifdef USE_WORKITEM
2380
PlatformScheduleWorkItem(&(priv->SwChnlWorkItem));
2381
#else
2382
PlatformSetTimer(dev, &(priv->SwChnlTimer), 0);
2383
#endif
2384
}
2385
#endif
2386
2387
#ifdef _RTL8192_EXT_PATCH_
2388
if(priv->up || priv->mesh_up)
2389
#else
2390
if(priv->up)
2391
#endif
2392
{
2393
PHY_SwChnlCallback8192S(dev);
2394
} else {
2395
priv->SwChnlInProgress = false;
2396
}
2397
return true;
2398
}
2399
2400
2401
void PHY_SwChnlPhy8192S(
2402
struct net_device* dev,
2403
u8 channel
2404
)
2405
{
2406
struct r8192_priv *priv = rtllib_priv(dev);
2407
2408
RT_TRACE(COMP_SCAN, "==>PHY_SwChnlPhy8192S(), switch to channel %d.\n", priv->chan);
2409
2410
#ifdef TO_DO_LIST
2411
if(RT_CANNOT_IO(dev))
2412
return;
2413
#endif
2414
2415
if(priv->SwChnlInProgress)
2416
return;
2417
2418
if(priv->rf_chip == RF_PSEUDO_11N)
2419
{
2420
priv->SwChnlInProgress=false;
2421
return;
2422
}
2423
2424
priv->SwChnlInProgress = true;
2425
if( channel == 0)
2426
channel = 1;
2427
2428
priv->chan=channel;
2429
2430
priv->SwChnlStage = 0;
2431
priv->SwChnlStep = 0;
2432
2433
phy_FinishSwChnlNow(dev,channel);
2434
2435
priv->SwChnlInProgress = false;
2436
}
2437
2438
static bool
2439
phy_SwChnlStepByStep(
2440
struct net_device* dev,
2441
u8 channel,
2442
u8 *stage,
2443
u8 *step,
2444
u32 *delay
2445
)
2446
{
2447
struct r8192_priv *priv = rtllib_priv(dev);
2448
SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
2449
u32 PreCommonCmdCnt;
2450
SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
2451
u32 PostCommonCmdCnt;
2452
SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
2453
u32 RfDependCmdCnt;
2454
SwChnlCmd *CurrentCmd = NULL;
2455
u8 eRFPath;
2456
u16 u2Channel = 0;
2457
2458
RT_TRACE(COMP_CH, "===========>%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
2459
if (!IsLegalChannel(priv->rtllib, channel))
2460
{
2461
RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
2462
return true;
2463
}
2464
2465
2466
PreCommonCmdCnt = 0;
2467
phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2468
CmdID_SetTxPowerLevel, 0, 0, 0);
2469
phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2470
CmdID_End, 0, 0, 0);
2471
2472
PostCommonCmdCnt = 0;
2473
2474
phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
2475
CmdID_End, 0, 0, 0);
2476
2477
RfDependCmdCnt = 0;
2478
switch( priv->rf_chip )
2479
{
2480
case RF_8225:
2481
if (channel < 1 || channel > 14)
2482
RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
2483
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2484
CmdID_RF_WriteReg, rRfChannel, channel, 10);
2485
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2486
CmdID_End, 0, 0, 0);
2487
break;
2488
2489
case RF_8256:
2490
if (channel < 1 || channel > 14)
2491
RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
2492
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2493
CmdID_RF_WriteReg, rRfChannel, channel, 10);
2494
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2495
CmdID_End, 0, 0, 0);
2496
break;
2497
2498
case RF_6052:
2499
if (channel < 1 || channel > 14)
2500
RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
2501
2502
u2Channel = channel;
2503
2504
switch(priv->CurrentChannelBW)
2505
{
2506
case HT_CHANNEL_WIDTH_20:
2507
u2Channel |= BIT10;
2508
break;
2509
2510
case HT_CHANNEL_WIDTH_20_40:
2511
u2Channel &= ~BIT10;
2512
break;
2513
default:
2514
u2Channel |= BIT10;
2515
break;
2516
}
2517
u2Channel |= BIT12|BIT13|BIT14;
2518
2519
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2520
CmdID_RF_WriteReg, RF_CHNLBW, u2Channel, 10);
2521
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2522
CmdID_End, 0, 0, 0);
2523
break;
2524
2525
case RF_8258:
2526
break;
2527
2528
default:
2529
return false;
2530
break;
2531
}
2532
2533
2534
do{
2535
switch(*stage)
2536
{
2537
case 0:
2538
CurrentCmd=&PreCommonCmd[*step];
2539
break;
2540
case 1:
2541
CurrentCmd=&RfDependCmd[*step];
2542
break;
2543
case 2:
2544
CurrentCmd=&PostCommonCmd[*step];
2545
break;
2546
}
2547
2548
if(CurrentCmd->CmdID==CmdID_End)
2549
{
2550
if((*stage)==2)
2551
{
2552
return true;
2553
}
2554
else
2555
{
2556
(*stage)++;
2557
(*step)=0;
2558
continue;
2559
}
2560
}
2561
2562
switch(CurrentCmd->CmdID)
2563
{
2564
case CmdID_SetTxPowerLevel:
2565
#ifndef CONFIG_MP
2566
rtl8192_phy_setTxPower(dev,channel);
2567
#endif
2568
break;
2569
case CmdID_WritePortUlong:
2570
write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
2571
break;
2572
case CmdID_WritePortUshort:
2573
write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
2574
break;
2575
case CmdID_WritePortUchar:
2576
write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
2577
break;
2578
case CmdID_RF_WriteReg:
2579
for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
2580
{
2581
if (IS_HARDWARE_TYPE_8192SE(dev)) {
2582
#ifdef CONFIG_FW_SETCHAN
2583
u32 rf_bw = ((priv->RfRegChnlVal[eRFPath] & 0xfffffc00) | (CurrentCmd->Para2 & 0xFF00));
2584
#endif
2585
priv->RfRegChnlVal[eRFPath] = ((priv->RfRegChnlVal[eRFPath] & 0xfffffc00) | CurrentCmd->Para2);
2586
2587
#ifdef CONFIG_FW_SETCHAN
2588
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, rf_bw);
2589
#else
2590
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, priv->RfRegChnlVal[eRFPath]);
2591
#endif
2592
} else {
2593
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, (CurrentCmd->Para2));
2594
}
2595
}
2596
break;
2597
default:
2598
break;
2599
}
2600
2601
break;
2602
}while(true);
2603
2604
(*delay)=CurrentCmd->msDelay;
2605
(*step)++;
2606
RT_TRACE(COMP_CH, "<===========%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
2607
return false;
2608
}
2609
2610
static bool
2611
phy_SetSwChnlCmdArray(
2612
SwChnlCmd* CmdTable,
2613
u32 CmdTableIdx,
2614
u32 CmdTableSz,
2615
SwChnlCmdID CmdID,
2616
u32 Para1,
2617
u32 Para2,
2618
u32 msDelay
2619
)
2620
{
2621
SwChnlCmd* pCmd;
2622
2623
if(CmdTable == NULL)
2624
{
2625
return false;
2626
}
2627
if(CmdTableIdx >= CmdTableSz)
2628
{
2629
return false;
2630
}
2631
2632
pCmd = CmdTable + CmdTableIdx;
2633
pCmd->CmdID = CmdID;
2634
pCmd->Para1 = Para1;
2635
pCmd->Para2 = Para2;
2636
pCmd->msDelay = msDelay;
2637
2638
return true;
2639
}
2640
2641
static void
2642
phy_FinishSwChnlNow(
2643
struct net_device* dev,
2644
u8 channel
2645
)
2646
{
2647
struct r8192_priv *priv = rtllib_priv(dev);
2648
u32 delay;
2649
2650
while(!phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
2651
{
2652
if(delay>0)
2653
mdelay(delay);
2654
#ifdef _RTL8192_EXT_PATCH_
2655
if((!priv->up) && (!priv->mesh_up))
2656
#else
2657
if(!priv->up)
2658
#endif
2659
break;
2660
}
2661
}
2662
2663
#ifdef TO_DO_LIST
2664
extern VOID
2665
PHY_SetMonitorMode8192S(
2666
IN PADAPTER pAdapter,
2667
IN BOOLEAN bEnableMonitorMode
2668
)
2669
{
2670
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2671
BOOLEAN bFilterOutNonAssociatedBSSID = false;
2672
2673
if(bEnableMonitorMode)
2674
{
2675
bFilterOutNonAssociatedBSSID = false;
2676
RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): enable monitor mode\n"));
2677
2678
pHalData->bInMonitorMode = true;
2679
pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, true, true);
2680
pAdapter->HalFunc.SetHwRegHandler(pAdapter, HW_VAR_CECHK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
2681
}
2682
else
2683
{
2684
bFilterOutNonAssociatedBSSID = true;
2685
RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): disable monitor mode\n"));
2686
2687
pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, false, true);
2688
pHalData->bInMonitorMode = false;
2689
pAdapter->HalFunc.SetHwRegHandler(pAdapter, HW_VAR_CECHK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
2690
}
2691
}
2692
#endif
2693
2694
2695
u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
2696
{
2697
bool rtValue = true;
2698
2699
#if 0
2700
if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
2701
{
2702
rtValue = false;
2703
}
2704
if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
2705
{
2706
2707
}
2708
#endif
2709
return rtValue;
2710
2711
} /* PHY_CheckIsLegalRfPath8192S */
2712
2713
2714
2715
void
2716
PHY_IQCalibrate( struct net_device* dev)
2717
{
2718
u32 i, reg;
2719
u32 old_value;
2720
long X, Y, TX0[4];
2721
u32 TXA[4];
2722
2723
2724
for (i = 0; i < 10; i++)
2725
{
2726
rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
2727
udelay(5);
2728
rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
2729
udelay(5);
2730
rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
2731
udelay(5);
2732
rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140148);
2733
udelay(5);
2734
rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604a2);
2735
udelay(5);
2736
rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
2737
udelay(5);
2738
rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x0214014d);
2739
udelay(5);
2740
rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x281608ba);
2741
udelay(5);
2742
rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x000028d1);
2743
udelay(5);
2744
rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000001);
2745
udelay(5);
2746
rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000001);
2747
udelay(2000);
2748
rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
2749
udelay(5);
2750
rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
2751
udelay(5);
2752
rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
2753
2754
2755
reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
2756
2757
if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
2758
{
2759
old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
2760
2761
X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
2762
TXA[RF90_PATH_A] = (X * old_value)/0x100;
2763
reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
2764
reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
2765
rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
2766
udelay(5);
2767
2768
Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
2769
TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
2770
reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
2771
reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
2772
rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
2773
reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
2774
reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
2775
rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
2776
udelay(5);
2777
2778
reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
2779
X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
2780
reg = (reg & 0xFFFFFC00) |X;
2781
rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
2782
Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
2783
reg = (reg & 0xFFFF03FF) |Y<<10;
2784
rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
2785
udelay(5);
2786
old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
2787
2788
X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
2789
reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
2790
TXA[RF90_PATH_A] = (X * old_value) / 0x100;
2791
reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
2792
rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
2793
udelay(5);
2794
2795
Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
2796
TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
2797
reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
2798
reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
2799
rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
2800
reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
2801
reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
2802
rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
2803
udelay(5);
2804
2805
reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
2806
X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
2807
reg = (reg & 0xFFFFFC00) |X;
2808
rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
2809
2810
Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
2811
reg = (reg & 0xFFFF03FF) |Y<<10;
2812
rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
2813
udelay(5);
2814
2815
RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
2816
break;
2817
}
2818
2819
}
2820
2821
2822
2823
2824
}
2825
2826
extern void PHY_IQCalibrateBcut(struct net_device* dev)
2827
{
2828
u32 i, reg;
2829
u32 old_value;
2830
long X, Y, TX0[4];
2831
u32 TXA[4];
2832
u32 calibrate_set[13] = {0};
2833
u32 load_value[13];
2834
u8 RfPiEnable=0;
2835
2836
/*
2837
0xee0[31:0]=0x3fed92fb;
2838
0xedc[31:0] =0x3fed92fb;
2839
0xe70[31:0] =0x3fed92fb;
2840
0xe74[31:0] =0x3fed92fb;
2841
0xe78[31:0] =0x3fed92fb;
2842
0xe7c[31:0]= 0x3fed92fb;
2843
0xe80[31:0]= 0x3fed92fb;
2844
0xe84[31:0]= 0x3fed92fb;
2845
0xe88[31:0]= 0x3fed92fb;
2846
0xe8c[31:0]= 0x3fed92fb;
2847
0xed0[31:0]= 0x3fed92fb;
2848
0xed4[31:0]= 0x3fed92fb;
2849
0xed8[31:0]= 0x3fed92fb;
2850
*/
2851
calibrate_set [0] = 0xee0;
2852
calibrate_set [1] = 0xedc;
2853
calibrate_set [2] = 0xe70;
2854
calibrate_set [3] = 0xe74;
2855
calibrate_set [4] = 0xe78;
2856
calibrate_set [5] = 0xe7c;
2857
calibrate_set [6] = 0xe80;
2858
calibrate_set [7] = 0xe84;
2859
calibrate_set [8] = 0xe88;
2860
calibrate_set [9] = 0xe8c;
2861
calibrate_set [10] = 0xed0;
2862
calibrate_set [11] = 0xed4;
2863
calibrate_set [12] = 0xed8;
2864
for (i = 0; i < 13; i++)
2865
{
2866
load_value[i] = rtl8192_QueryBBReg(dev, calibrate_set[i], bMaskDWord);
2867
rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, 0x3fed92fb);
2868
2869
}
2870
2871
RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
2872
for (i = 0; i < 10; i++)
2873
{
2874
RT_TRACE(COMP_INIT, "IQK -%d\n", i);
2875
if (!RfPiEnable)
2876
{
2877
rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000100);
2878
rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000100);
2879
}
2880
2881
rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
2882
udelay(5);
2883
rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
2884
udelay(5);
2885
rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
2886
udelay(5);
2887
rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140102);
2888
udelay(5);
2889
rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604c2);
2890
udelay(5);
2891
rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
2892
udelay(5);
2893
rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x02140102);
2894
udelay(5);
2895
rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x28160d05);
2896
udelay(5);
2897
rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
2898
udelay(5);
2899
rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
2900
udelay(5);
2901
2902
udelay(2000);
2903
2904
rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x020028d1);
2905
udelay(5);
2906
rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
2907
udelay(5);
2908
rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
2909
2910
udelay(2000);
2911
2912
rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
2913
udelay(5);
2914
rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
2915
udelay(5);
2916
rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
2917
2918
if (!RfPiEnable)
2919
{
2920
rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000000);
2921
rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000000);
2922
}
2923
2924
2925
reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
2926
2927
if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
2928
{
2929
old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
2930
2931
X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
2932
TXA[RF90_PATH_A] = (X * old_value)/0x100;
2933
reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
2934
reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
2935
rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
2936
udelay(5);
2937
2938
Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
2939
TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
2940
reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
2941
reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
2942
rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
2943
reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
2944
reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
2945
rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
2946
udelay(5);
2947
2948
reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
2949
X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
2950
reg = (reg & 0xFFFFFC00) |X;
2951
rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
2952
Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
2953
reg = (reg & 0xFFFF03FF) |Y<<10;
2954
rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
2955
udelay(5);
2956
old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
2957
2958
X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
2959
reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
2960
TXA[RF90_PATH_A] = (X * old_value) / 0x100;
2961
reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
2962
rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
2963
udelay(5);
2964
2965
Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
2966
TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
2967
reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
2968
reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
2969
rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
2970
reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
2971
reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
2972
rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
2973
udelay(5);
2974
2975
reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
2976
X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
2977
reg = (reg & 0xFFFFFC00) |X;
2978
rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
2979
2980
Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
2981
reg = (reg & 0xFFFF03FF) |Y<<10;
2982
rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
2983
udelay(5);
2984
2985
RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
2986
break;
2987
}
2988
2989
}
2990
2991
for (i = 0; i < 13; i++)
2992
rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, load_value[i]);
2993
2994
2995
2996
2997
2998
}
2999
3000
#define HalGetFirmwareVerison(priv) (priv->pFirmware->FirmwareVersion )
3001
bool rtl8192se_set_fw_cmd(struct net_device* dev, FW_CMD_IO_TYPE FwCmdIO)
3002
{
3003
struct r8192_priv *priv = rtllib_priv(dev);
3004
u32 FwParam = FW_CMD_IO_PARA_QUERY(priv);
3005
u16 FwCmdMap = FW_CMD_IO_QUERY(priv);
3006
bool bPostProcessing = false;
3007
3008
RT_TRACE(COMP_CMD, "-->HalSetFwCmd8192S(): Set FW Cmd(%#x), SetFwCmdInProgress(%d)\n", FwCmdIO, priv->SetFwCmdInProgress);
3009
3010
3011
3012
3013
3014
RT_TRACE(COMP_CMD, "-->HalSetFwCmd8192S(): Set FW Cmd(%#x), SetFwCmdInProgress(%d)\n",
3015
FwCmdIO, priv->SetFwCmdInProgress);
3016
3017
do{
3018
3019
if(HalGetFirmwareVerison(priv) >= 0x35)
3020
{
3021
switch(FwCmdIO)
3022
{
3023
case FW_CMD_RA_REFRESH_N:
3024
FwCmdIO = FW_CMD_RA_REFRESH_N_COMB;
3025
break;
3026
case FW_CMD_RA_REFRESH_BG:
3027
FwCmdIO = FW_CMD_RA_REFRESH_BG_COMB;
3028
break;
3029
default:
3030
break;
3031
}
3032
}
3033
else
3034
{
3035
if((FwCmdIO == FW_CMD_IQK_ENABLE) ||
3036
(FwCmdIO == FW_CMD_RA_REFRESH_N) ||
3037
(FwCmdIO == FW_CMD_RA_REFRESH_BG))
3038
{
3039
bPostProcessing = true;
3040
break;
3041
}
3042
}
3043
3044
if(HalGetFirmwareVerison(priv) >= 0x3E)
3045
{
3046
if(FwCmdIO == FW_CMD_CTRL_DM_BY_DRIVER)
3047
FwCmdIO = FW_CMD_CTRL_DM_BY_DRIVER_NEW;
3048
}
3049
3050
3051
switch(FwCmdIO)
3052
{
3053
3054
case FW_CMD_RA_INIT:
3055
RT_TRACE(COMP_CMD, "[FW CMD] [New Version] RA init!!\n");
3056
FwCmdMap |= FW_RA_INIT_CTL;
3057
FW_CMD_IO_SET(priv, FwCmdMap);
3058
FW_CMD_IO_CLR(priv, FW_RA_INIT_CTL);
3059
break;
3060
3061
case FW_CMD_DIG_DISABLE:
3062
RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set DIG disable!!\n");
3063
FwCmdMap &= ~FW_DIG_ENABLE_CTL;
3064
FW_CMD_IO_SET(priv, FwCmdMap);
3065
break;
3066
3067
case FW_CMD_DIG_ENABLE:
3068
case FW_CMD_DIG_RESUME:
3069
if(!(priv->DMFlag & HAL_DM_DIG_DISABLE))
3070
{
3071
RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set DIG enable or resume!!\n");
3072
FwCmdMap |= (FW_DIG_ENABLE_CTL|FW_SS_CTL);
3073
FW_CMD_IO_SET(priv, FwCmdMap);
3074
}
3075
break;
3076
3077
case FW_CMD_DIG_HALT:
3078
RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set DIG halt!!\n");
3079
FwCmdMap &= ~(FW_DIG_ENABLE_CTL|FW_SS_CTL);
3080
FW_CMD_IO_SET(priv, FwCmdMap);
3081
break;
3082
3083
case FW_CMD_TXPWR_TRACK_THERMAL:
3084
{
3085
u8 ThermalVal = 0;
3086
FwCmdMap |= FW_PWR_TRK_CTL;
3087
FwParam &= FW_PWR_TRK_PARAM_CLR;
3088
ThermalVal = priv->ThermalValue;
3089
FwParam |= ((ThermalVal<<24) |(priv->ThermalMeter[0]<<16));
3090
RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n", FwCmdMap, FwParam);
3091
FW_CMD_PARA_SET(priv, FwParam);
3092
FW_CMD_IO_SET(priv, FwCmdMap);
3093
FW_CMD_IO_CLR(priv, FW_PWR_TRK_CTL);
3094
}
3095
break;
3096
3097
case FW_CMD_RA_REFRESH_N_COMB:
3098
FwCmdMap |= FW_RA_N_CTL;
3099
FwCmdMap &= ~(FW_RA_BG_CTL |FW_RA_INIT_CTL);
3100
FwParam &= FW_RA_PARAM_CLR;
3101
if(!(priv->rtllib->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL))
3102
FwParam |= ((priv->rtllib->pHTInfo->IOTRaFunc)&0xf);
3103
FwParam |= ((priv->rtllib->pHTInfo->IOTPeer & 0xf) <<4);
3104
RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n", FwCmdMap, FwParam);
3105
FW_CMD_PARA_SET(priv, FwParam);
3106
FW_CMD_IO_SET(priv, FwCmdMap);
3107
FW_CMD_IO_CLR(priv, FW_RA_N_CTL);
3108
break;
3109
3110
case FW_CMD_RA_REFRESH_BG_COMB:
3111
FwCmdMap |= FW_RA_BG_CTL;
3112
FwCmdMap &= ~(FW_RA_N_CTL|FW_RA_INIT_CTL);
3113
FwParam &= FW_RA_PARAM_CLR;
3114
if(!(priv->rtllib->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL))
3115
FwParam |= ((priv->rtllib->pHTInfo->IOTRaFunc)&0xf);
3116
FwParam |= ((priv->rtllib->pHTInfo->IOTPeer & 0xf) <<4);
3117
RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set RA/IOT Comb in BG mode!! FwCmdMap(%#x), FwParam(%#x)\n", FwCmdMap, FwParam);
3118
FW_CMD_PARA_SET(priv, FwParam);
3119
FW_CMD_IO_SET(priv, FwCmdMap);
3120
FW_CMD_IO_CLR(priv, FW_RA_BG_CTL);
3121
break;
3122
3123
case FW_CMD_IQK_ENABLE:
3124
RT_TRACE(COMP_CMD, "[FW CMD] [New Version] IQK enable.\n");
3125
FwCmdMap |= FW_IQK_CTL;
3126
FW_CMD_IO_SET(priv, FwCmdMap);
3127
FW_CMD_IO_CLR(priv, FW_IQK_CTL);
3128
break;
3129
3130
case FW_CMD_CTRL_DM_BY_DRIVER_NEW:
3131
RT_TRACE(COMP_CMD, "[FW CMD][New Version] Inform FW driver control some DM!! FwCmdMap(%#x), FwParam(%#x)\n", FwCmdMap, FwParam);
3132
FwCmdMap |= FW_DRIVER_CTRL_DM_CTL;
3133
FW_CMD_IO_SET(priv, FwCmdMap);
3134
break;
3135
3136
case FW_CMD_RESUME_DM_BY_SCAN:
3137
RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Resume DM after scan.\n");
3138
FwCmdMap |= (FW_DIG_ENABLE_CTL|FW_HIGH_PWR_ENABLE_CTL|FW_SS_CTL);
3139
3140
if(priv->DMFlag & HAL_DM_DIG_DISABLE || !dm_digtable.dig_enable_flag)
3141
FwCmdMap &= ~FW_DIG_ENABLE_CTL;
3142
3143
if((priv->DMFlag & HAL_DM_HIPWR_DISABLE) ||
3144
(priv->rtllib->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) ||
3145
(priv->rtllib->bdynamic_txpower_enable == true))
3146
FwCmdMap &= ~FW_HIGH_PWR_ENABLE_CTL;
3147
3148
if( (dm_digtable.Dig_Ext_Port_Stage == DIG_EXT_PORT_STAGE_0) ||
3149
(dm_digtable.Dig_Ext_Port_Stage == DIG_EXT_PORT_STAGE_1))
3150
FwCmdMap &= ~FW_DIG_ENABLE_CTL;
3151
3152
FW_CMD_IO_SET(priv, FwCmdMap);
3153
bPostProcessing = true;
3154
break;
3155
3156
case FW_CMD_PAUSE_DM_BY_SCAN:
3157
RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Pause DM before scan.\n");
3158
FwCmdMap &= ~(FW_DIG_ENABLE_CTL|FW_HIGH_PWR_ENABLE_CTL|FW_SS_CTL);
3159
FW_CMD_IO_SET(priv, FwCmdMap);
3160
bPostProcessing = true;
3161
break;
3162
3163
case FW_CMD_HIGH_PWR_DISABLE:
3164
RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set HighPwr disable!!\n");
3165
FwCmdMap &= ~FW_HIGH_PWR_ENABLE_CTL;
3166
FW_CMD_IO_SET(priv, FwCmdMap);
3167
bPostProcessing = true;
3168
break;
3169
3170
case FW_CMD_HIGH_PWR_ENABLE:
3171
if(((priv->rtllib->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0) &&
3172
!(priv->DMFlag & HAL_DM_HIPWR_DISABLE) &&
3173
(priv->rtllib->bdynamic_txpower_enable != true))
3174
{
3175
RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set HighPwr enable!!\n");
3176
FwCmdMap |= (FW_HIGH_PWR_ENABLE_CTL|FW_SS_CTL);
3177
FW_CMD_IO_SET(priv, FwCmdMap);
3178
bPostProcessing = true;
3179
}
3180
break;
3181
3182
case FW_CMD_DIG_MODE_FA:
3183
RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set DIG Mode to FA.\n");
3184
FwCmdMap |= FW_FA_CTL;
3185
FW_CMD_IO_SET(priv, FwCmdMap);
3186
break;
3187
3188
case FW_CMD_DIG_MODE_SS:
3189
RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set DIG Mode to SS.\n");
3190
FwCmdMap &= ~FW_FA_CTL;
3191
FW_CMD_IO_SET(priv, FwCmdMap);
3192
break;
3193
3194
case FW_CMD_PAPE_CONTROL:
3195
RT_TRACE(COMP_CMD, "[FW CMD] Set PAPE Control \n");
3196
#ifdef MERGE_TO_DO
3197
if(pHalData->bt_coexist.BT_PapeCtrl)
3198
{
3199
RTPRINT(FBT, BT_TRACE, ("BT set PAPE Control to SW/HW dynamically. \n"));
3200
FwCmdMap |= FW_PAPE_CTL_BY_SW_HW;
3201
}
3202
else
3203
#endif
3204
{
3205
printk("BT set PAPE Control to SW\n");
3206
FwCmdMap &= ~FW_PAPE_CTL_BY_SW_HW;
3207
}
3208
FW_CMD_IO_SET(priv, FwCmdMap);
3209
break;
3210
3211
default:
3212
bPostProcessing = true;
3213
break;
3214
}
3215
}while(false);
3216
3217
RT_TRACE(COMP_CMD, "[FW CMD] Current FwCmdMap(%#x)\n", priv->FwCmdIOMap);
3218
RT_TRACE(COMP_CMD, "[FW CMD] Current FwCmdIOParam(%#x)\n", priv->FwCmdIOParam);
3219
3220
if(bPostProcessing && !priv->SetFwCmdInProgress)
3221
{
3222
priv->SetFwCmdInProgress = true;
3223
priv->CurrentFwCmdIO = FwCmdIO;
3224
}
3225
else
3226
{
3227
return false;
3228
}
3229
3230
#if 0
3231
#ifdef USE_WORKITEM
3232
PlatformScheduleWorkItem(&(pHalData->FwCmdIOWorkItem));
3233
#else
3234
PlatformSetTimer(Adapter, &(pHalData->SetFwCmdIOTimer), 0);
3235
#endif
3236
#endif
3237
rtl8192_SetFwCmdIOCallback(dev);
3238
return true;
3239
}
3240
void ChkFwCmdIoDone(struct net_device* dev)
3241
{
3242
u16 PollingCnt = 10000;
3243
u32 tmpValue;
3244
3245
do
3246
{
3247
3248
udelay(10);
3249
3250
tmpValue = read_nic_dword(dev, WFM5);
3251
if(tmpValue == 0)
3252
{
3253
RT_TRACE(COMP_CMD, "[FW CMD] Set FW Cmd success!!\n");
3254
break;
3255
}
3256
else
3257
{
3258
RT_TRACE(COMP_CMD, "[FW CMD] Polling FW Cmd PollingCnt(%d)!!\n", PollingCnt);
3259
}
3260
}while( --PollingCnt );
3261
3262
if(PollingCnt == 0)
3263
{
3264
RT_TRACE(COMP_ERR, "[FW CMD] Set FW Cmd fail!!\n");
3265
}
3266
}
3267
void rtl8192_SetFwCmdIOCallback(struct net_device* dev)
3268
{
3269
struct r8192_priv *priv = rtllib_priv(dev);
3270
u32 input,CurrentAID = 0;
3271
3272
#ifdef _RTL8192_EXT_PATCH_
3273
if((!priv->up) && (!priv->mesh_up))
3274
#else
3275
if(!priv->up)
3276
#endif
3277
{
3278
RT_TRACE(COMP_CMD, "SetFwCmdIOTimerCallback(): driver is going to unload\n");
3279
return;
3280
}
3281
3282
RT_TRACE(COMP_CMD, "--->SetFwCmdIOTimerCallback(): Cmd(%#x), SetFwCmdInProgress(%d)\n", priv->CurrentFwCmdIO, priv->SetFwCmdInProgress);
3283
3284
if(HalGetFirmwareVerison(priv) >= 0x34)
3285
{
3286
switch(priv->CurrentFwCmdIO)
3287
{
3288
case FW_CMD_RA_REFRESH_N:
3289
priv->CurrentFwCmdIO = FW_CMD_RA_REFRESH_N_COMB;
3290
break;
3291
case FW_CMD_RA_REFRESH_BG:
3292
priv->CurrentFwCmdIO = FW_CMD_RA_REFRESH_BG_COMB;
3293
break;
3294
default:
3295
break;
3296
}
3297
}
3298
3299
switch(priv->CurrentFwCmdIO)
3300
{
3301
3302
case FW_CMD_RA_RESET:
3303
RT_TRACE(COMP_CMD, "[FW CMD] Set RA Reset!!\n");
3304
write_nic_dword(dev, WFM5, FW_RA_RESET);
3305
ChkFwCmdIoDone(dev);
3306
break;
3307
3308
case FW_CMD_RA_ACTIVE:
3309
RT_TRACE(COMP_CMD, "[FW CMD] Set RA Active!!\n");
3310
write_nic_dword(dev, WFM5, FW_RA_ACTIVE);
3311
ChkFwCmdIoDone(dev);
3312
break;
3313
3314
case FW_CMD_RA_REFRESH_N:
3315
RT_TRACE(COMP_CMD, "[FW CMD] Set RA n refresh!!\n");
3316
if(priv->rtllib->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
3317
input = FW_RA_REFRESH;
3318
else
3319
input = FW_RA_REFRESH | (priv->rtllib->pHTInfo->IOTRaFunc << 8);
3320
write_nic_dword(dev, WFM5, input);
3321
ChkFwCmdIoDone(dev);
3322
write_nic_dword(dev, WFM5, FW_RA_ENABLE_RSSI_MASK);
3323
ChkFwCmdIoDone(dev);
3324
break;
3325
3326
case FW_CMD_RA_REFRESH_BG:
3327
RT_TRACE(COMP_CMD, "[FW CMD] Set RA BG refresh!!\n");
3328
write_nic_dword(dev, WFM5, FW_RA_REFRESH);
3329
ChkFwCmdIoDone(dev);
3330
write_nic_dword(dev, WFM5, FW_RA_DISABLE_RSSI_MASK);
3331
ChkFwCmdIoDone(dev);
3332
break;
3333
3334
case FW_CMD_RA_REFRESH_N_COMB:
3335
RT_TRACE(COMP_CMD, "[FW CMD] Set RA n Combo refresh!!\n");
3336
if(priv->rtllib->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
3337
input = FW_RA_IOT_N_COMB;
3338
else
3339
input = FW_RA_IOT_N_COMB | (((priv->rtllib->pHTInfo->IOTRaFunc)&0x0f) << 8);
3340
input = input |((priv->rtllib->pHTInfo->IOTPeer & 0xf) <<12);
3341
RT_TRACE(COMP_CMD, "[FW CMD] Set RA/IOT Comb in n mode!! input(%#x)\n", input);
3342
write_nic_dword(dev, WFM5, input);
3343
ChkFwCmdIoDone(dev);
3344
break;
3345
3346
case FW_CMD_RA_REFRESH_BG_COMB:
3347
RT_TRACE(COMP_CMD, "[FW CMD] Set RA B/G Combo refresh!!\n");
3348
if(priv->rtllib->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
3349
input = FW_RA_IOT_BG_COMB;
3350
else
3351
input = FW_RA_IOT_BG_COMB | (((priv->rtllib->pHTInfo->IOTRaFunc)&0x0f) << 8);
3352
input = input |((priv->rtllib->pHTInfo->IOTPeer & 0xf) <<12);
3353
RT_TRACE(COMP_CMD, "[FW CMD] Set RA/IOT Comb in B/G mode!! input(%#x)\n", input);
3354
write_nic_dword(dev, WFM5, input);
3355
ChkFwCmdIoDone(dev);
3356
break;
3357
3358
case FW_CMD_IQK_ENABLE:
3359
RT_TRACE(COMP_CMD, "[FW CMD] IQK Enable!!\n");
3360
write_nic_dword(dev, WFM5, FW_IQK_ENABLE);
3361
ChkFwCmdIoDone(dev);
3362
break;
3363
3364
case FW_CMD_PAUSE_DM_BY_SCAN:
3365
RT_TRACE(COMP_CMD, "[FW CMD] Pause DM by Scan!!\n");
3366
rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
3367
rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
3368
rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);
3369
break;
3370
3371
case FW_CMD_RESUME_DM_BY_SCAN:
3372
RT_TRACE(COMP_CMD, "[FW CMD] Resume DM by Scan!!\n");
3373
rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83);
3374
rtl8192_phy_setTxPower(dev, priv->rtllib->current_network.channel);
3375
break;
3376
3377
case FW_CMD_HIGH_PWR_DISABLE:
3378
RT_TRACE(COMP_CMD, "[FW CMD] High Pwr Disable!!\n");
3379
if(priv->DMFlag & HAL_DM_HIPWR_DISABLE)
3380
break;
3381
rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
3382
rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
3383
rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);
3384
break;
3385
3386
case FW_CMD_HIGH_PWR_ENABLE:
3387
RT_TRACE(COMP_CMD, "[FW CMD] High Pwr Enable!!\n");
3388
if((priv->DMFlag & HAL_DM_HIPWR_DISABLE) ||
3389
(priv->rtllib->bdynamic_txpower_enable == true))
3390
break;
3391
rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83);
3392
break;
3393
3394
case FW_CMD_LPS_ENTER:
3395
RT_TRACE(COMP_CMD, "[FW CMD] Enter LPS mode!!\n");
3396
CurrentAID = priv->rtllib->assoc_id;
3397
write_nic_dword(dev, WFM5, (FW_LPS_ENTER| ((CurrentAID|0xc000)<<8)) );
3398
ChkFwCmdIoDone(dev);
3399
priv->rtllib->pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_EDCA_TURBO;
3400
break;
3401
3402
case FW_CMD_LPS_LEAVE:
3403
RT_TRACE(COMP_CMD, "[FW CMD] Leave LPS mode!!\n");
3404
write_nic_dword(dev, WFM5, FW_LPS_LEAVE );
3405
ChkFwCmdIoDone(dev);
3406
priv->rtllib->pHTInfo->IOTAction &= (~HT_IOT_ACT_DISABLE_EDCA_TURBO);
3407
break;
3408
3409
case FW_CMD_ADD_A2_ENTRY:
3410
RT_TRACE(COMP_CMD, "[FW CMD] ADD A2 entry!!\n");
3411
write_nic_dword(dev, WFM5, FW_ADD_A2_ENTRY);
3412
ChkFwCmdIoDone(dev);
3413
break;
3414
3415
case FW_CMD_CTRL_DM_BY_DRIVER:
3416
RT_TRACE(COMP_CMD, "[FW CMD] Inform fw driver will do some dm at driver\n");
3417
write_nic_dword(dev, WFM5, FW_CTRL_DM_BY_DRIVER);
3418
ChkFwCmdIoDone(dev);
3419
break;
3420
case FW_CMD_CHAN_SET:
3421
input = FW_CHAN_SET | (((priv->chan)&0xff) << 8);
3422
RT_TRACE(COMP_CMD, "[FW CMD] Inform fw to set channel to %x!!, input(%#x):\n", priv->chan,input);
3423
write_nic_dword(dev, WFM5, input);
3424
ChkFwCmdIoDone(dev);
3425
break;
3426
3427
default:
3428
break;
3429
}
3430
3431
3432
ChkFwCmdIoDone(dev);
3433
3434
3435
priv->SetFwCmdInProgress = false;
3436
RT_TRACE(COMP_CMD, "<---SetFwCmdIOWorkItemCallback()\n");
3437
}
3438
3439
static void
3440
phy_CheckEphySwitchReady(struct net_device* dev)
3441
{
3442
u32 delay = 100;
3443
u8 regu1;
3444
3445
regu1 = read_nic_byte(dev, 0x554);
3446
while ((regu1 & BIT5) && (delay > 0))
3447
{
3448
regu1 = read_nic_byte(dev, 0x554);
3449
delay--;
3450
udelay(50);
3451
}
3452
RT_TRACE(COMP_INIT, "regu1=%02x delay = %d\n", regu1, delay);
3453
3454
}
3455
3456
#ifdef TO_DO_LIST
3457
void
3458
HW_RadioGpioChk92SE(
3459
IN PADAPTER pAdapter
3460
)
3461
{
3462
PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
3463
u1Byte u1Tmp = 0;
3464
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3465
RT_RF_POWER_STATE eRfPowerStateToSet;
3466
BOOLEAN bActuallySet = false;
3467
3468
#if 0
3469
if (!RT_IN_PS_LEVEL(pAdapter, RT_RF_OFF_LEVL_PCI_D3) &&
3470
pMgntInfo->RfOffReason != RF_CHANGE_BY_HW)
3471
{
3472
return;
3473
}
3474
3475
PlatformSwitchClkReq(pAdapter, 0x00);
3476
3477
if (RT_IN_PS_LEVEL(pAdapter, RT_RF_OFF_LEVL_PCI_D3))
3478
{
3479
RT_LEAVE_D3(pAdapter, false);
3480
RT_CLEAR_PS_LEVEL(pAdapter, RT_RF_OFF_LEVL_PCI_D3);
3481
Power_DomainInit92SE(pAdapter);
3482
}
3483
3484
PlatformEFIOWrite1Byte(pAdapter, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
3485
3486
u1Tmp = PlatformEFIORead1Byte(pAdapter, GPIO_IO_SEL);
3487
u1Tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
3488
PlatformEFIOWrite1Byte(pAdapter, GPIO_IO_SEL, u1Tmp);
3489
3490
RT_TRACE(COMP_CMD, DBG_LOUD,
3491
("HW_RadioGpioChk92SE HW_RadioGpioChk92SE=%02x\n", HW_RadioGpioChk92SE));
3492
3493
u1Tmp = PlatformEFIORead1Byte(pAdapter, GPIO_IN);
3494
3495
eRfPowerStateToSet = (u1Tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? eRfOn : eRfOff;
3496
3497
if( (pHalData->bHwRadioOff == true) && (eRfPowerStateToSet == eRfOn))
3498
{
3499
RT_TRACE(COMP_RF, DBG_LOUD, ("HW_RadioGpioChk92SE - HW Radio ON\n"));
3500
pHalData->bHwRadioOff = false;
3501
bActuallySet = true;
3502
}
3503
else if ( (pHalData->bHwRadioOff == false) && (eRfPowerStateToSet == eRfOff))
3504
{
3505
RT_TRACE(COMP_RF, DBG_LOUD, ("HW_RadioGpioChk92SE - HW Radio OFF\n"));
3506
pHalData->bHwRadioOff = true;
3507
bActuallySet = true;
3508
}
3509
3510
if(bActuallySet)
3511
{
3512
pHalData->bHwRfOffAction = 1;
3513
MgntActSet_RF_State(pAdapter, eRfPowerStateToSet, RF_CHANGE_BY_HW);
3514
DrvIFIndicateCurrentPhyStatus(pAdapter);
3515
3516
3517
{
3518
PMP_ADAPTER pDevice = &(pAdapter->NdisAdapter);
3519
if(pDevice->RegHwSwRfOffD3 == 1 || pDevice->RegHwSwRfOffD3 == 2)
3520
(eRfPowerStateToSet == eRfOff) ? RT_ENABLE_ASPM(pAdapter) : RT_DISABLE_ASPM(pAdapter);
3521
}
3522
}
3523
RT_TRACE(COMP_RF, DBG_TRACE, ("HW_RadioGpioChk92SE() <--------- \n"));
3524
#endif
3525
}/* HW_RadioGpioChk92SE */
3526
#endif
3527
#endif
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Version: 2.0.1