1
/* Copyright, 1988-1992, Russell Nelson, Crynwr Software
3
This program is free software; you can redistribute it and/or modify
4
it under the terms of the GNU General Public License as published by
5
the Free Software Foundation, version 1.
7
This program is distributed in the hope that it will be useful,
8
but WITHOUT ANY WARRANTY; without even the implied warranty of
9
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10
GNU General Public License for more details.
12
You should have received a copy of the GNU General Public License
13
along with this program; if not, write to the Free Software
14
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
16
#define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
17
/* offset 2h -> Model/Product Number */
18
/* offset 3h -> Chip Revision Number */
20
#define PP_ISAIOB 0x0020 /* IO base address */
21
#define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
22
#define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
23
#define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
24
#define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
25
#define PP_ISASOF 0x0026 /* ISA DMA offset */
26
#define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
27
#define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
28
#define PP_CS8900_ISAMemB 0x002C /* Memory base */
29
#define PP_CS8920_ISAMemB 0x0348 /* */
31
#define PP_ISABootBase 0x0030 /* Boot Prom base */
32
#define PP_ISABootMask 0x0034 /* Boot Prom Mask */
34
/* EEPROM data and command registers */
35
#define PP_EECMD 0x0040 /* NVR Interface Command register */
36
#define PP_EEData 0x0042 /* NVR Interface Data Register */
37
#define PP_DebugReg 0x0044 /* Debug Register */
39
#define PP_RxCFG 0x0102 /* Rx Bus config */
40
#define PP_RxCTL 0x0104 /* Receive Control Register */
41
#define PP_TxCFG 0x0106 /* Transmit Config Register */
42
#define PP_TxCMD 0x0108 /* Transmit Command Register */
43
#define PP_BufCFG 0x010A /* Bus configuration Register */
44
#define PP_LineCTL 0x0112 /* Line Config Register */
45
#define PP_SelfCTL 0x0114 /* Self Command Register */
46
#define PP_BusCTL 0x0116 /* ISA bus control Register */
47
#define PP_TestCTL 0x0118 /* Test Register */
48
#define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */
50
#define PP_ISQ 0x0120 /* Interrupt Status */
51
#define PP_RxEvent 0x0124 /* Rx Event Register */
52
#define PP_TxEvent 0x0128 /* Tx Event Register */
53
#define PP_BufEvent 0x012C /* Bus Event Register */
54
#define PP_RxMiss 0x0130 /* Receive Miss Count */
55
#define PP_TxCol 0x0132 /* Transmit Collision Count */
56
#define PP_LineST 0x0134 /* Line State Register */
57
#define PP_SelfST 0x0136 /* Self State register */
58
#define PP_BusST 0x0138 /* Bus Status */
59
#define PP_TDR 0x013C /* Time Domain Reflectometry */
60
#define PP_AutoNegST 0x013E /* Auto Neg Status */
61
#define PP_TxCommand 0x0144 /* Tx Command */
62
#define PP_TxLength 0x0146 /* Tx Length */
63
#define PP_LAF 0x0150 /* Hash Table */
64
#define PP_IA 0x0158 /* Physical Address Register */
66
#define PP_RxStatus 0x0400 /* Receive start of frame */
67
#define PP_RxLength 0x0402 /* Receive Length of frame */
68
#define PP_RxFrame 0x0404 /* Receive frame pointer */
69
#define PP_TxFrame 0x0A00 /* Transmit frame pointer */
71
/* Primary I/O Base Address. If no I/O base is supplied by the user, then this */
72
/* can be used as the default I/O base to access the PacketPage Area. */
73
#define DEFAULTIOBASE 0x0300
74
#define FIRST_IO 0x020C /* First I/O port to check */
75
#define LAST_IO 0x037C /* Last I/O port to check (+10h) */
76
#define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */
77
#define ADD_SIG 0x3000 /* Expected ID signature */
79
#define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */
82
#define EISA_ID_SIG 0x4D24 /* IBM */
83
#define PART_NO_SIG 0x1010 /* IBM */
84
#define MONGOOSE_BIT 0x0000 /* IBM */
86
#define EISA_ID_SIG 0x630E /* PnP Vendor ID (same as chip id for Crystal board) */
87
#define PART_NO_SIG 0x4000 /* ID code CS8920 board (PnP Vendor Product code) */
88
#define MONGOOSE_BIT 0x2000 /* PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */
91
#define PRODUCT_ID_ADD 0x0002 /* Address of product ID */
93
/* Mask to find out the types of registers */
94
#define REG_TYPE_MASK 0x001F
97
#define ERSE_WR_ENBL 0x00F0
98
#define ERSE_WR_DISABLE 0x0000
100
/* Defines Control/Config register quintuplet numbers */
101
#define RX_BUF_CFG 0x0003
102
#define RX_CONTROL 0x0005
103
#define TX_CFG 0x0007
104
#define TX_COMMAND 0x0009
105
#define BUF_CFG 0x000B
106
#define LINE_CONTROL 0x0013
107
#define SELF_CONTROL 0x0015
108
#define BUS_CONTROL 0x0017
109
#define TEST_CONTROL 0x0019
111
/* Defines Status/Count registers quintuplet numbers */
112
#define RX_EVENT 0x0004
113
#define TX_EVENT 0x0008
114
#define BUF_EVENT 0x000C
115
#define RX_MISS_COUNT 0x0010
116
#define TX_COL_COUNT 0x0012
117
#define LINE_STATUS 0x0014
118
#define SELF_STATUS 0x0016
119
#define BUS_STATUS 0x0018
122
/* PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write */
123
#define SKIP_1 0x0040
124
#define RX_STREAM_ENBL 0x0080
125
#define RX_OK_ENBL 0x0100
126
#define RX_DMA_ONLY 0x0200
127
#define AUTO_RX_DMA 0x0400
128
#define BUFFER_CRC 0x0800
129
#define RX_CRC_ERROR_ENBL 0x1000
130
#define RX_RUNT_ENBL 0x2000
131
#define RX_EXTRA_DATA_ENBL 0x4000
133
/* PP_RxCTL - Receive Control bit definition - Read/write */
134
#define RX_IA_HASH_ACCEPT 0x0040
135
#define RX_PROM_ACCEPT 0x0080
136
#define RX_OK_ACCEPT 0x0100
137
#define RX_MULTCAST_ACCEPT 0x0200
138
#define RX_IA_ACCEPT 0x0400
139
#define RX_BROADCAST_ACCEPT 0x0800
140
#define RX_BAD_CRC_ACCEPT 0x1000
141
#define RX_RUNT_ACCEPT 0x2000
142
#define RX_EXTRA_DATA_ACCEPT 0x4000
143
#define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT)
144
/* Default receive mode - individually addressed, broadcast, and error free */
145
#define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT)
147
/* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */
148
#define TX_LOST_CRS_ENBL 0x0040
149
#define TX_SQE_ERROR_ENBL 0x0080
150
#define TX_OK_ENBL 0x0100
151
#define TX_LATE_COL_ENBL 0x0200
152
#define TX_JBR_ENBL 0x0400
153
#define TX_ANY_COL_ENBL 0x0800
154
#define TX_16_COL_ENBL 0x8000
156
/* PP_TxCMD - Transmit Command bit definition - Read-only */
157
#define TX_START_4_BYTES 0x0000
158
#define TX_START_64_BYTES 0x0040
159
#define TX_START_128_BYTES 0x0080
160
#define TX_START_ALL_BYTES 0x00C0
161
#define TX_FORCE 0x0100
162
#define TX_ONE_COL 0x0200
163
#define TX_TWO_PART_DEFF_DISABLE 0x0400
164
#define TX_NO_CRC 0x1000
165
#define TX_RUNT 0x2000
167
/* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */
168
#define GENERATE_SW_INTERRUPT 0x0040
169
#define RX_DMA_ENBL 0x0080
170
#define READY_FOR_TX_ENBL 0x0100
171
#define TX_UNDERRUN_ENBL 0x0200
172
#define RX_MISS_ENBL 0x0400
173
#define RX_128_BYTE_ENBL 0x0800
174
#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
175
#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
176
#define RX_DEST_MATCH_ENBL 0x8000
178
/* PP_LineCTL - Line Control bit definition - Read/write */
179
#define SERIAL_RX_ON 0x0040
180
#define SERIAL_TX_ON 0x0080
181
#define AUI_ONLY 0x0100
182
#define AUTO_AUI_10BASET 0x0200
183
#define MODIFIED_BACKOFF 0x0800
184
#define NO_AUTO_POLARITY 0x1000
185
#define TWO_PART_DEFDIS 0x2000
186
#define LOW_RX_SQUELCH 0x4000
188
/* PP_SelfCTL - Software Self Control bit definition - Read/write */
189
#define POWER_ON_RESET 0x0040
190
#define SW_STOP 0x0100
191
#define SLEEP_ON 0x0200
192
#define AUTO_WAKEUP 0x0400
193
#define HCB0_ENBL 0x1000
194
#define HCB1_ENBL 0x2000
198
/* PP_BusCTL - ISA Bus Control bit definition - Read/write */
199
#define RESET_RX_DMA 0x0040
200
#define MEMORY_ON 0x0400
201
#define DMA_BURST_MODE 0x0800
202
#define IO_CHANNEL_READY_ON 0x1000
203
#define RX_DMA_SIZE_64K 0x2000
204
#define ENABLE_IRQ 0x8000
206
/* PP_TestCTL - Test Control bit definition - Read/write */
207
#define LINK_OFF 0x0080
208
#define ENDEC_LOOPBACK 0x0200
209
#define AUI_LOOPBACK 0x0400
210
#define BACKOFF_OFF 0x0800
211
#define FAST_TEST 0x8000
213
/* PP_RxEvent - Receive Event Bit definition - Read-only */
214
#define RX_IA_HASHED 0x0040
215
#define RX_DRIBBLE 0x0080
217
#define RX_HASHED 0x0200
219
#define RX_BROADCAST 0x0800
220
#define RX_CRC_ERROR 0x1000
221
#define RX_RUNT 0x2000
222
#define RX_EXTRA_DATA 0x4000
224
#define HASH_INDEX_MASK 0x0FC00
226
/* PP_TxEvent - Transmit Event Bit definition - Read-only */
227
#define TX_LOST_CRS 0x0040
228
#define TX_SQE_ERROR 0x0080
230
#define TX_LATE_COL 0x0200
231
#define TX_JBR 0x0400
232
#define TX_16_COL 0x8000
233
#define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS)
234
#define TX_COL_COUNT_MASK 0x7800
236
/* PP_BufEvent - Buffer Event Bit definition - Read-only */
237
#define SW_INTERRUPT 0x0040
238
#define RX_DMA 0x0080
239
#define READY_FOR_TX 0x0100
240
#define TX_UNDERRUN 0x0200
241
#define RX_MISS 0x0400
242
#define RX_128_BYTE 0x0800
243
#define TX_COL_OVRFLW 0x1000
244
#define RX_MISS_OVRFLW 0x2000
245
#define RX_DEST_MATCH 0x8000
247
/* PP_LineST - Ethernet Line Status bit definition - Read-only */
248
#define LINK_OK 0x0080
249
#define AUI_ON 0x0100
250
#define TENBASET_ON 0x0200
251
#define POLARITY_OK 0x1000
252
#define CRS_OK 0x4000
254
/* PP_SelfST - Chip Software Status bit definition */
255
#define ACTIVE_33V 0x0040
256
#define INIT_DONE 0x0080
257
#define SI_BUSY 0x0100
258
#define EEPROM_PRESENT 0x0200
259
#define EEPROM_OK 0x0400
260
#define EL_PRESENT 0x0800
261
#define EE_SIZE_64 0x1000
263
/* PP_BusST - ISA Bus Status bit definition */
264
#define TX_BID_ERROR 0x0080
265
#define READY_FOR_TX_NOW 0x0100
267
/* PP_AutoNegCTL - Auto Negotiation Control bit definition */
268
#define RE_NEG_NOW 0x0040
269
#define ALLOW_FDX 0x0080
270
#define AUTO_NEG_ENABLE 0x0100
271
#define NLP_ENABLE 0x0200
272
#define FORCE_FDX 0x8000
273
#define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE)
274
#define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW)
276
/* PP_AutoNegST - Auto Negotiation Status bit definition */
277
#define AUTO_NEG_BUSY 0x0080
278
#define FLP_LINK 0x0100
279
#define FLP_LINK_GOOD 0x0800
280
#define LINK_FAULT 0x1000
281
#define HDX_ACTIVE 0x4000
282
#define FDX_ACTIVE 0x8000
284
/* The following block defines the ISQ event types */
285
#define ISQ_RECEIVER_EVENT 0x04
286
#define ISQ_TRANSMITTER_EVENT 0x08
287
#define ISQ_BUFFER_EVENT 0x0c
288
#define ISQ_RX_MISS_EVENT 0x10
289
#define ISQ_TX_COL_EVENT 0x12
291
#define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */
292
#define ISQ_HIST 16 /* small history buffer */
293
#define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */
295
#define TXRXBUFSIZE 0x0600
296
#define RXDMABUFSIZE 0x8000
297
#define RXDMASIZE 0x4000
298
#define TXRX_LENGTH_MASK 0x07FF
300
/* rx options bits */
301
#define RCV_WITH_RXON 1 /* Set SerRx ON */
302
#define RCV_COUNTS 2 /* Use Framecnt1 */
303
#define RCV_PONG 4 /* Pong respondent */
304
#define RCV_DONG 8 /* Dong operation */
305
#define RCV_POLLING 0x10 /* Poll RxEvent */
306
#define RCV_ISQ 0x20 /* Use ISQ, int */
307
#define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */
308
#define RCV_DMA 0x200 /* Set RxDMA only */
309
#define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */
310
#define RCV_FIXED_DATA 0x800 /* Every frame same */
311
#define RCV_IO 0x1000 /* Use ISA IO only */
312
#define RCV_MEMORY 0x2000 /* Use ISA Memory */
314
#define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */
315
#define PKT_START PP_TxFrame /* Start of packet RAM */
317
#define RX_FRAME_PORT 0x0000
318
#define TX_FRAME_PORT RX_FRAME_PORT
319
#define TX_CMD_PORT 0x0004
320
#define TX_NOW 0x0000 /* Tx packet after 5 bytes copied */
321
#define TX_AFTER_381 0x0020 /* Tx packet after 381 bytes copied */
322
#define TX_AFTER_ALL 0x0060 /* Tx packet after all bytes copied */
323
#define TX_LEN_PORT 0x0006
324
#define ISQ_PORT 0x0008
325
#define ADD_PORT 0x000A
326
#define DATA_PORT 0x000C
328
#define EEPROM_WRITE_EN 0x00F0
329
#define EEPROM_WRITE_DIS 0x0000
330
#define EEPROM_WRITE_CMD 0x0100
331
#define EEPROM_READ_CMD 0x0200
334
/* Description of header of each packet in receive area of memory */
335
#define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */
336
#define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */
337
#define RBUF_LEN_LOW 2 /* Length of received data - low byte */
338
#define RBUF_LEN_HI 3 /* Length of received data - high byte */
339
#define RBUF_HEAD_LEN 4 /* Length of this header */
341
#define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */
342
#define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */
347
/* use these values for debugging bios scan */
348
#define BIOS_START_SEG 0x00000
349
#define BIOS_OFFSET_INC 0x0010
351
#define BIOS_START_SEG 0x0c000
352
#define BIOS_OFFSET_INC 0x0200
355
#define BIOS_LAST_OFFSET 0x0fc00
357
/* Byte offsets into the EEPROM configuration buffer */
358
#define ISA_CNF_OFFSET 0x6
359
#define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) /* 8900 eeprom */
360
#define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) /* 8920 eeprom */
362
/* the assumption here is that the bits in the eeprom are generally */
363
/* in the same position as those in the autonegctl register. */
364
/* Of course the IMM bit is not in that register so it must be */
366
#define EE_FORCE_FDX 0x8000
367
#define EE_NLP_ENABLE 0x0200
368
#define EE_AUTO_NEG_ENABLE 0x0100
369
#define EE_ALLOW_FDX 0x0080
370
#define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX)
372
#define IMM_BIT 0x0040 /* ignore missing media */
374
#define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2)
375
#define A_CNF_10B_T 0x0001
376
#define A_CNF_AUI 0x0002
377
#define A_CNF_10B_2 0x0004
378
#define A_CNF_MEDIA_TYPE 0x0060
379
#define A_CNF_MEDIA_AUTO 0x0000
380
#define A_CNF_MEDIA_10B_T 0x0020
381
#define A_CNF_MEDIA_AUI 0x0040
382
#define A_CNF_MEDIA_10B_2 0x0060
383
#define A_CNF_DC_DC_POLARITY 0x0080
384
#define A_CNF_NO_AUTO_POLARITY 0x2000
385
#define A_CNF_LOW_RX_SQUELCH 0x4000
386
#define A_CNF_EXTND_10B_2 0x8000
388
#define PACKET_PAGE_OFFSET 0x8
390
/* Bit definitions for the ISA configuration word from the EEPROM */
391
#define INT_NO_MASK 0x000F
392
#define DMA_NO_MASK 0x0070
393
#define ISA_DMA_SIZE 0x0200
394
#define ISA_AUTO_RxDMA 0x0400
395
#define ISA_RxDMA 0x0800
396
#define DMA_BURST 0x1000
397
#define STREAM_TRANSFER 0x2000
398
#define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA)
400
/* DMA controller registers */
401
#define DMA_BASE 0x00 /* DMA controller base */
402
#define DMA_BASE_2 0x0C0 /* DMA controller base */
404
#define DMA_STAT 0x0D0 /* DMA controller status register */
405
#define DMA_MASK 0x0D4 /* DMA controller mask register */
406
#define DMA_MODE 0x0D6 /* DMA controller mode register */
407
#define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */
410
#define DMA_DISABLE 0x04 /* Disable channel n */
411
#define DMA_ENABLE 0x00 /* Enable channel n */
412
/* Demand transfers, incr. address, auto init, writes, ch. n */
413
#define DMA_RX_MODE 0x14
414
/* Demand transfers, incr. address, auto init, reads, ch. n */
415
#define DMA_TX_MODE 0x18
417
#define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */
419
#define CS8900 0x0000
420
#define CS8920 0x4000
421
#define CS8920M 0x6000
422
#define REVISON_BITS 0x1F00
423
#define EEVER_NUMBER 0x12
424
#define CHKSUM_LEN 0x14
425
#define CHKSUM_VAL 0x0000
426
#define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */
427
#define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */
428
#define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */
429
#define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */
430
#define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */
432
#define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */
434
#define PNP_ADD_PORT 0x0279
435
#define PNP_WRITE_PORT 0x0A79
437
#define GET_PNP_ISA_STRUCT 0x40
438
#define PNP_ISA_STRUCT_LEN 0x06
439
#define PNP_CSN_CNT_OFF 0x01
440
#define PNP_RD_PORT_OFF 0x02
441
#define PNP_FUNCTION_OK 0x00
442
#define PNP_WAKE 0x03
443
#define PNP_RSRC_DATA 0x04
444
#define PNP_RSRC_READY 0x01
445
#define PNP_STATUS 0x05
446
#define PNP_ACTIVATE 0x30
447
#define PNP_CNF_IO_H 0x60
448
#define PNP_CNF_IO_L 0x61
449
#define PNP_CNF_INT 0x70
450
#define PNP_CNF_DMA 0x74
451
#define PNP_CNF_MEM 0x48
added
removed
netboot/cs89x0.h
