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* Copyright 2006 Dave Airlie <airlied@linux.ie>
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* Copyright © 2006-2009 Intel Corporation
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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* Eric Anholt <eric@anholt.net>
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* Jesse Barnes <jesse.barnes@intel.com>
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#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
36
#include "intel_drv.h"
40
static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
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return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
46
assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
48
struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
49
struct drm_i915_private *dev_priv = dev->dev_private;
50
uint32_t enabled_bits;
52
enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
54
WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits,
55
"HDMI port enabled, expecting disabled\n");
58
struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
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struct intel_digital_port *intel_dig_port =
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container_of(encoder, struct intel_digital_port, base.base);
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return &intel_dig_port->hdmi;
65
static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
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return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
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void intel_dip_infoframe_csum(struct dip_infoframe *frame)
72
uint8_t *data = (uint8_t *)frame;
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for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
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frame->checksum = 0x100 - sum;
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static u32 g4x_infoframe_index(struct dip_infoframe *frame)
87
switch (frame->type) {
89
return VIDEO_DIP_SELECT_AVI;
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return VIDEO_DIP_SELECT_SPD;
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
100
switch (frame->type) {
102
return VIDEO_DIP_ENABLE_AVI;
104
return VIDEO_DIP_ENABLE_SPD;
106
DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
111
static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
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switch (frame->type) {
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return VIDEO_DIP_ENABLE_AVI_HSW;
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return VIDEO_DIP_ENABLE_SPD_HSW;
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
124
static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
126
switch (frame->type) {
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return HSW_TVIDEO_DIP_AVI_DATA(pipe);
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return HSW_TVIDEO_DIP_SPD_DATA(pipe);
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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static void g4x_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
143
u32 val = I915_READ(VIDEO_DIP_CTL);
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(frame);
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val &= ~g4x_infoframe_enable(frame);
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I915_WRITE(VIDEO_DIP_CTL, val);
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for (i = 0; i < len; i += 4) {
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I915_WRITE(VIDEO_DIP_DATA, *data);
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/* Write every possible data byte to force correct ECC calculation. */
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for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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I915_WRITE(VIDEO_DIP_DATA, 0);
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val |= g4x_infoframe_enable(frame);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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I915_WRITE(VIDEO_DIP_CTL, val);
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POSTING_READ(VIDEO_DIP_CTL);
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static void ibx_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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u32 val = I915_READ(reg);
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(frame);
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val &= ~g4x_infoframe_enable(frame);
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I915_WRITE(reg, val);
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for (i = 0; i < len; i += 4) {
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I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
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/* Write every possible data byte to force correct ECC calculation. */
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for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
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val |= g4x_infoframe_enable(frame);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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I915_WRITE(reg, val);
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static void cpt_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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u32 val = I915_READ(reg);
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(frame);
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/* The DIP control register spec says that we need to update the AVI
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* infoframe without clearing its enable bit */
229
if (frame->type != DIP_TYPE_AVI)
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val &= ~g4x_infoframe_enable(frame);
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I915_WRITE(reg, val);
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for (i = 0; i < len; i += 4) {
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I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
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/* Write every possible data byte to force correct ECC calculation. */
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for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
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val |= g4x_infoframe_enable(frame);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
248
I915_WRITE(reg, val);
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static void vlv_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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u32 val = I915_READ(reg);
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
265
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(frame);
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val &= ~g4x_infoframe_enable(frame);
270
I915_WRITE(reg, val);
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for (i = 0; i < len; i += 4) {
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I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
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/* Write every possible data byte to force correct ECC calculation. */
278
for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
282
val |= g4x_infoframe_enable(frame);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
286
I915_WRITE(reg, val);
290
static void hsw_write_infoframe(struct drm_encoder *encoder,
291
struct dip_infoframe *frame)
293
uint32_t *data = (uint32_t *)frame;
294
struct drm_device *dev = encoder->dev;
295
struct drm_i915_private *dev_priv = dev->dev_private;
296
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
297
u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
298
u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
299
unsigned int i, len = DIP_HEADER_SIZE + frame->len;
300
u32 val = I915_READ(ctl_reg);
305
val &= ~hsw_infoframe_enable(frame);
306
I915_WRITE(ctl_reg, val);
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for (i = 0; i < len; i += 4) {
310
I915_WRITE(data_reg + i, *data);
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/* Write every possible data byte to force correct ECC calculation. */
314
for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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I915_WRITE(data_reg + i, 0);
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val |= hsw_infoframe_enable(frame);
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I915_WRITE(ctl_reg, val);
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POSTING_READ(ctl_reg);
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static void intel_set_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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intel_dip_infoframe_csum(frame);
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intel_hdmi->write_infoframe(encoder, frame);
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static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
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struct drm_display_mode *adjusted_mode)
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struct dip_infoframe avi_if = {
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.type = DIP_TYPE_AVI,
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.ver = DIP_VERSION_AVI,
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if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
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avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
344
intel_set_infoframe(encoder, &avi_if);
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static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
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struct dip_infoframe spd_if;
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memset(&spd_if, 0, sizeof(spd_if));
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spd_if.type = DIP_TYPE_SPD;
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spd_if.ver = DIP_VERSION_SPD;
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spd_if.len = DIP_LEN_SPD;
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strcpy(spd_if.body.spd.vn, "Intel");
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strcpy(spd_if.body.spd.pd, "Integrated gfx");
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spd_if.body.spd.sdi = DIP_SPD_PC;
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intel_set_infoframe(encoder, &spd_if);
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static void g4x_set_infoframes(struct drm_encoder *encoder,
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struct drm_display_mode *adjusted_mode)
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struct drm_i915_private *dev_priv = encoder->dev->dev_private;
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struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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u32 reg = VIDEO_DIP_CTL;
368
u32 val = I915_READ(reg);
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assert_hdmi_port_disabled(intel_hdmi);
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/* If the registers were not initialized yet, they might be zeroes,
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* which means we're selecting the AVI DIP and we're setting its
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* frequency to once. This seems to really confuse the HW and make
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* things stop working (the register spec says the AVI always needs to
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* be sent every VSync). So here we avoid writing to the register more
378
* than we need and also explicitly select the AVI DIP and explicitly
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* set its frequency to every VSync. Avoiding to write it twice seems to
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* be enough to solve the problem, but being defensive shouldn't hurt us
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val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
384
if (!intel_hdmi->has_hdmi_sink) {
385
if (!(val & VIDEO_DIP_ENABLE))
387
val &= ~VIDEO_DIP_ENABLE;
388
I915_WRITE(reg, val);
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switch (intel_hdmi->sdvox_reg) {
395
port = VIDEO_DIP_PORT_B;
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port = VIDEO_DIP_PORT_C;
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if (port != (val & VIDEO_DIP_PORT_MASK)) {
406
if (val & VIDEO_DIP_ENABLE) {
407
val &= ~VIDEO_DIP_ENABLE;
408
I915_WRITE(reg, val);
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val &= ~VIDEO_DIP_PORT_MASK;
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val |= VIDEO_DIP_ENABLE;
416
val &= ~VIDEO_DIP_ENABLE_VENDOR;
418
I915_WRITE(reg, val);
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intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
422
intel_hdmi_set_spd_infoframe(encoder);
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static void ibx_set_infoframes(struct drm_encoder *encoder,
426
struct drm_display_mode *adjusted_mode)
428
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
429
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
430
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
431
u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
432
u32 val = I915_READ(reg);
435
assert_hdmi_port_disabled(intel_hdmi);
437
/* See the big comment in g4x_set_infoframes() */
438
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
440
if (!intel_hdmi->has_hdmi_sink) {
441
if (!(val & VIDEO_DIP_ENABLE))
443
val &= ~VIDEO_DIP_ENABLE;
444
I915_WRITE(reg, val);
449
switch (intel_hdmi->sdvox_reg) {
451
port = VIDEO_DIP_PORT_B;
454
port = VIDEO_DIP_PORT_C;
457
port = VIDEO_DIP_PORT_D;
464
if (port != (val & VIDEO_DIP_PORT_MASK)) {
465
if (val & VIDEO_DIP_ENABLE) {
466
val &= ~VIDEO_DIP_ENABLE;
467
I915_WRITE(reg, val);
470
val &= ~VIDEO_DIP_PORT_MASK;
474
val |= VIDEO_DIP_ENABLE;
475
val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
476
VIDEO_DIP_ENABLE_GCP);
478
I915_WRITE(reg, val);
481
intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
482
intel_hdmi_set_spd_infoframe(encoder);
485
static void cpt_set_infoframes(struct drm_encoder *encoder,
486
struct drm_display_mode *adjusted_mode)
488
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
489
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
490
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
491
u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
492
u32 val = I915_READ(reg);
494
assert_hdmi_port_disabled(intel_hdmi);
496
/* See the big comment in g4x_set_infoframes() */
497
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
499
if (!intel_hdmi->has_hdmi_sink) {
500
if (!(val & VIDEO_DIP_ENABLE))
502
val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
503
I915_WRITE(reg, val);
508
/* Set both together, unset both together: see the spec. */
509
val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
510
val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
511
VIDEO_DIP_ENABLE_GCP);
513
I915_WRITE(reg, val);
516
intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
517
intel_hdmi_set_spd_infoframe(encoder);
520
static void vlv_set_infoframes(struct drm_encoder *encoder,
521
struct drm_display_mode *adjusted_mode)
523
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
524
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
525
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
526
u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
527
u32 val = I915_READ(reg);
529
assert_hdmi_port_disabled(intel_hdmi);
531
/* See the big comment in g4x_set_infoframes() */
532
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
534
if (!intel_hdmi->has_hdmi_sink) {
535
if (!(val & VIDEO_DIP_ENABLE))
537
val &= ~VIDEO_DIP_ENABLE;
538
I915_WRITE(reg, val);
543
val |= VIDEO_DIP_ENABLE;
544
val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
545
VIDEO_DIP_ENABLE_GCP);
547
I915_WRITE(reg, val);
550
intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
551
intel_hdmi_set_spd_infoframe(encoder);
554
static void hsw_set_infoframes(struct drm_encoder *encoder,
555
struct drm_display_mode *adjusted_mode)
557
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
558
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
559
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
560
u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
561
u32 val = I915_READ(reg);
563
assert_hdmi_port_disabled(intel_hdmi);
565
if (!intel_hdmi->has_hdmi_sink) {
571
val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
572
VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
574
I915_WRITE(reg, val);
577
intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
578
intel_hdmi_set_spd_infoframe(encoder);
581
static void intel_hdmi_mode_set(struct drm_encoder *encoder,
582
struct drm_display_mode *mode,
583
struct drm_display_mode *adjusted_mode)
585
struct drm_device *dev = encoder->dev;
586
struct drm_i915_private *dev_priv = dev->dev_private;
587
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
588
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
591
sdvox = SDVO_ENCODING_HDMI;
592
if (!HAS_PCH_SPLIT(dev))
593
sdvox |= intel_hdmi->color_range;
594
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
595
sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
596
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
597
sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
599
if (intel_crtc->bpp > 24)
600
sdvox |= COLOR_FORMAT_12bpc;
602
sdvox |= COLOR_FORMAT_8bpc;
604
/* Required on CPT */
605
if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
606
sdvox |= HDMI_MODE_SELECT;
608
if (intel_hdmi->has_audio) {
609
DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
610
pipe_name(intel_crtc->pipe));
611
sdvox |= SDVO_AUDIO_ENABLE;
612
sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
613
intel_write_eld(encoder, adjusted_mode);
616
if (HAS_PCH_CPT(dev))
617
sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
618
else if (intel_crtc->pipe == PIPE_B)
619
sdvox |= SDVO_PIPE_B_SELECT;
621
I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
622
POSTING_READ(intel_hdmi->sdvox_reg);
624
intel_hdmi->set_infoframes(encoder, adjusted_mode);
627
static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
630
struct drm_device *dev = encoder->base.dev;
631
struct drm_i915_private *dev_priv = dev->dev_private;
632
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
635
tmp = I915_READ(intel_hdmi->sdvox_reg);
637
if (!(tmp & SDVO_ENABLE))
640
if (HAS_PCH_CPT(dev))
641
*pipe = PORT_TO_PIPE_CPT(tmp);
643
*pipe = PORT_TO_PIPE(tmp);
648
static void intel_enable_hdmi(struct intel_encoder *encoder)
650
struct drm_device *dev = encoder->base.dev;
651
struct drm_i915_private *dev_priv = dev->dev_private;
652
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
654
u32 enable_bits = SDVO_ENABLE;
656
if (intel_hdmi->has_audio)
657
enable_bits |= SDVO_AUDIO_ENABLE;
659
temp = I915_READ(intel_hdmi->sdvox_reg);
661
/* HW workaround for IBX, we need to move the port to transcoder A
662
* before disabling it. */
663
if (HAS_PCH_IBX(dev)) {
664
struct drm_crtc *crtc = encoder->base.crtc;
665
int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
667
/* Restore the transcoder select bit. */
669
enable_bits |= SDVO_PIPE_B_SELECT;
672
/* HW workaround, need to toggle enable bit off and on for 12bpc, but
673
* we do this anyway which shows more stable in testing.
675
if (HAS_PCH_SPLIT(dev)) {
676
I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
677
POSTING_READ(intel_hdmi->sdvox_reg);
682
I915_WRITE(intel_hdmi->sdvox_reg, temp);
683
POSTING_READ(intel_hdmi->sdvox_reg);
685
/* HW workaround, need to write this twice for issue that may result
686
* in first write getting masked.
688
if (HAS_PCH_SPLIT(dev)) {
689
I915_WRITE(intel_hdmi->sdvox_reg, temp);
690
POSTING_READ(intel_hdmi->sdvox_reg);
694
static void intel_disable_hdmi(struct intel_encoder *encoder)
696
struct drm_device *dev = encoder->base.dev;
697
struct drm_i915_private *dev_priv = dev->dev_private;
698
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
700
u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
702
temp = I915_READ(intel_hdmi->sdvox_reg);
704
/* HW workaround for IBX, we need to move the port to transcoder A
705
* before disabling it. */
706
if (HAS_PCH_IBX(dev)) {
707
struct drm_crtc *crtc = encoder->base.crtc;
708
int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
710
if (temp & SDVO_PIPE_B_SELECT) {
711
temp &= ~SDVO_PIPE_B_SELECT;
712
I915_WRITE(intel_hdmi->sdvox_reg, temp);
713
POSTING_READ(intel_hdmi->sdvox_reg);
715
/* Again we need to write this twice. */
716
I915_WRITE(intel_hdmi->sdvox_reg, temp);
717
POSTING_READ(intel_hdmi->sdvox_reg);
719
/* Transcoder selection bits only update
720
* effectively on vblank. */
722
intel_wait_for_vblank(dev, pipe);
728
/* HW workaround, need to toggle enable bit off and on for 12bpc, but
729
* we do this anyway which shows more stable in testing.
731
if (HAS_PCH_SPLIT(dev)) {
732
I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
733
POSTING_READ(intel_hdmi->sdvox_reg);
736
temp &= ~enable_bits;
738
I915_WRITE(intel_hdmi->sdvox_reg, temp);
739
POSTING_READ(intel_hdmi->sdvox_reg);
741
/* HW workaround, need to write this twice for issue that may result
742
* in first write getting masked.
744
if (HAS_PCH_SPLIT(dev)) {
745
I915_WRITE(intel_hdmi->sdvox_reg, temp);
746
POSTING_READ(intel_hdmi->sdvox_reg);
750
static int intel_hdmi_mode_valid(struct drm_connector *connector,
751
struct drm_display_mode *mode)
753
if (mode->clock > 165000)
754
return MODE_CLOCK_HIGH;
755
if (mode->clock < 20000)
756
return MODE_CLOCK_LOW;
758
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
759
return MODE_NO_DBLESCAN;
764
bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
765
struct drm_display_mode *mode,
766
struct drm_display_mode *adjusted_mode)
771
static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
773
struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
774
struct drm_i915_private *dev_priv = dev->dev_private;
777
switch (intel_hdmi->sdvox_reg) {
779
bit = HDMIB_HOTPLUG_LIVE_STATUS;
782
bit = HDMIC_HOTPLUG_LIVE_STATUS;
789
return I915_READ(PORT_HOTPLUG_STAT) & bit;
792
static enum drm_connector_status
793
intel_hdmi_detect(struct drm_connector *connector, bool force)
795
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
796
struct intel_digital_port *intel_dig_port =
797
hdmi_to_dig_port(intel_hdmi);
798
struct intel_encoder *intel_encoder = &intel_dig_port->base;
799
struct drm_i915_private *dev_priv = connector->dev->dev_private;
801
enum drm_connector_status status = connector_status_disconnected;
803
if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
806
intel_hdmi->has_hdmi_sink = false;
807
intel_hdmi->has_audio = false;
808
edid = drm_get_edid(connector,
809
intel_gmbus_get_adapter(dev_priv,
810
intel_hdmi->ddc_bus));
813
if (edid->input & DRM_EDID_INPUT_DIGITAL) {
814
status = connector_status_connected;
815
if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
816
intel_hdmi->has_hdmi_sink =
817
drm_detect_hdmi_monitor(edid);
818
intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
823
if (status == connector_status_connected) {
824
if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
825
intel_hdmi->has_audio =
826
(intel_hdmi->force_audio == HDMI_AUDIO_ON);
827
intel_encoder->type = INTEL_OUTPUT_HDMI;
833
static int intel_hdmi_get_modes(struct drm_connector *connector)
835
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
836
struct drm_i915_private *dev_priv = connector->dev->dev_private;
838
/* We should parse the EDID data and find out if it's an HDMI sink so
839
* we can send audio to it.
842
return intel_ddc_get_modes(connector,
843
intel_gmbus_get_adapter(dev_priv,
844
intel_hdmi->ddc_bus));
848
intel_hdmi_detect_audio(struct drm_connector *connector)
850
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
851
struct drm_i915_private *dev_priv = connector->dev->dev_private;
853
bool has_audio = false;
855
edid = drm_get_edid(connector,
856
intel_gmbus_get_adapter(dev_priv,
857
intel_hdmi->ddc_bus));
859
if (edid->input & DRM_EDID_INPUT_DIGITAL)
860
has_audio = drm_detect_monitor_audio(edid);
868
intel_hdmi_set_property(struct drm_connector *connector,
869
struct drm_property *property,
872
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
873
struct intel_digital_port *intel_dig_port =
874
hdmi_to_dig_port(intel_hdmi);
875
struct drm_i915_private *dev_priv = connector->dev->dev_private;
878
ret = drm_connector_property_set_value(connector, property, val);
882
if (property == dev_priv->force_audio_property) {
883
enum hdmi_force_audio i = val;
886
if (i == intel_hdmi->force_audio)
889
intel_hdmi->force_audio = i;
891
if (i == HDMI_AUDIO_AUTO)
892
has_audio = intel_hdmi_detect_audio(connector);
894
has_audio = (i == HDMI_AUDIO_ON);
896
if (i == HDMI_AUDIO_OFF_DVI)
897
intel_hdmi->has_hdmi_sink = 0;
899
intel_hdmi->has_audio = has_audio;
903
if (property == dev_priv->broadcast_rgb_property) {
904
if (val == !!intel_hdmi->color_range)
907
intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
914
if (intel_dig_port->base.base.crtc) {
915
struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
916
intel_set_mode(crtc, &crtc->mode,
917
crtc->x, crtc->y, crtc->fb);
923
static void intel_hdmi_destroy(struct drm_connector *connector)
925
drm_sysfs_connector_remove(connector);
926
drm_connector_cleanup(connector);
930
static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
931
.mode_fixup = intel_hdmi_mode_fixup,
932
.mode_set = intel_hdmi_mode_set,
933
.disable = intel_encoder_noop,
936
static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
937
.dpms = intel_connector_dpms,
938
.detect = intel_hdmi_detect,
939
.fill_modes = drm_helper_probe_single_connector_modes,
940
.set_property = intel_hdmi_set_property,
941
.destroy = intel_hdmi_destroy,
944
static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
945
.get_modes = intel_hdmi_get_modes,
946
.mode_valid = intel_hdmi_mode_valid,
947
.best_encoder = intel_best_encoder,
950
static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
951
.destroy = intel_encoder_destroy,
955
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
957
intel_attach_force_audio_property(connector);
958
intel_attach_broadcast_rgb_property(connector);
961
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
962
struct intel_connector *intel_connector)
964
struct drm_connector *connector = &intel_connector->base;
965
struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
966
struct intel_encoder *intel_encoder = &intel_dig_port->base;
967
struct drm_device *dev = intel_encoder->base.dev;
968
struct drm_i915_private *dev_priv = dev->dev_private;
969
enum port port = intel_dig_port->port;
971
drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
972
DRM_MODE_CONNECTOR_HDMIA);
973
drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
975
connector->polled = DRM_CONNECTOR_POLL_HPD;
976
connector->interlace_allowed = 1;
977
connector->doublescan_allowed = 0;
981
intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
982
dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
985
intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
986
dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
989
intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
990
dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
993
/* Internal port only for eDP. */
998
if (!HAS_PCH_SPLIT(dev)) {
999
intel_hdmi->write_infoframe = g4x_write_infoframe;
1000
intel_hdmi->set_infoframes = g4x_set_infoframes;
1001
} else if (IS_VALLEYVIEW(dev)) {
1002
intel_hdmi->write_infoframe = vlv_write_infoframe;
1003
intel_hdmi->set_infoframes = vlv_set_infoframes;
1004
} else if (IS_HASWELL(dev)) {
1005
intel_hdmi->write_infoframe = hsw_write_infoframe;
1006
intel_hdmi->set_infoframes = hsw_set_infoframes;
1007
} else if (HAS_PCH_IBX(dev)) {
1008
intel_hdmi->write_infoframe = ibx_write_infoframe;
1009
intel_hdmi->set_infoframes = ibx_set_infoframes;
1011
intel_hdmi->write_infoframe = cpt_write_infoframe;
1012
intel_hdmi->set_infoframes = cpt_set_infoframes;
1015
if (IS_HASWELL(dev))
1016
intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1018
intel_connector->get_hw_state = intel_connector_get_hw_state;
1020
intel_hdmi_add_properties(intel_hdmi, connector);
1022
intel_connector_attach_encoder(intel_connector, intel_encoder);
1023
drm_sysfs_connector_add(connector);
1025
/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1026
* 0xd. Failure to do so will result in spurious interrupts being
1027
* generated on the port when a cable is not attached.
1029
if (IS_G4X(dev) && !IS_GM45(dev)) {
1030
u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1031
I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1035
void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port)
1037
struct intel_digital_port *intel_dig_port;
1038
struct intel_encoder *intel_encoder;
1039
struct drm_encoder *encoder;
1040
struct intel_connector *intel_connector;
1042
intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
1043
if (!intel_dig_port)
1046
intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1047
if (!intel_connector) {
1048
kfree(intel_dig_port);
1052
intel_encoder = &intel_dig_port->base;
1053
encoder = &intel_encoder->base;
1055
drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1056
DRM_MODE_ENCODER_TMDS);
1057
drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
1059
intel_encoder->enable = intel_enable_hdmi;
1060
intel_encoder->disable = intel_disable_hdmi;
1061
intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1063
intel_encoder->type = INTEL_OUTPUT_HDMI;
1064
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1065
intel_encoder->cloneable = false;
1067
intel_dig_port->port = port;
1068
intel_dig_port->hdmi.sdvox_reg = sdvox_reg;
1069
intel_dig_port->dp.output_reg = 0;
1071
intel_hdmi_init_connector(intel_dig_port, intel_connector);