1
/* Driver for Realtek PCI-Express card reader
3
* Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5
* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
7
* Free Software Foundation; either version 2, or (at your option) any
10
* This program is distributed in the hope that it will be useful, but
11
* WITHOUT ANY WARRANTY; without even the implied warranty of
12
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13
* General Public License for more details.
15
* You should have received a copy of the GNU General Public License along
16
* with this program; if not, see <http://www.gnu.org/licenses/>.
19
* Wei WANG <wei_wang@realsil.com.cn>
20
* No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
23
#include <linux/pci.h>
24
#include <linux/module.h>
25
#include <linux/dma-mapping.h>
26
#include <linux/highmem.h>
27
#include <linux/interrupt.h>
28
#include <linux/delay.h>
29
#include <linux/idr.h>
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#include <linux/platform_device.h>
31
#include <linux/mfd/core.h>
32
#include <linux/mfd/rtsx_pci.h>
33
#include <asm/unaligned.h>
37
static bool msi_en = true;
38
module_param(msi_en, bool, S_IRUGO | S_IWUSR);
39
MODULE_PARM_DESC(msi_en, "Enable MSI");
41
static DEFINE_IDR(rtsx_pci_idr);
42
static DEFINE_SPINLOCK(rtsx_pci_lock);
44
static struct mfd_cell rtsx_pcr_cells[] = {
46
.name = DRV_NAME_RTSX_PCI_SDMMC,
49
.name = DRV_NAME_RTSX_PCI_MS,
53
static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids) = {
54
{ PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
55
{ PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
60
MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
62
void rtsx_pci_start_run(struct rtsx_pcr *pcr)
64
/* If pci device removed, don't queue idle work any more */
68
if (pcr->state != PDEV_STAT_RUN) {
69
pcr->state = PDEV_STAT_RUN;
70
if (pcr->ops->enable_auto_blink)
71
pcr->ops->enable_auto_blink(pcr);
74
cancel_delayed_work(&pcr->idle_work);
75
queue_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
77
EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
79
int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
82
u32 val = HAIMR_WRITE_START;
84
val |= (u32)(addr & 0x3FFF) << 16;
85
val |= (u32)mask << 8;
88
rtsx_pci_writel(pcr, RTSX_HAIMR, val);
90
for (i = 0; i < MAX_RW_REG_CNT; i++) {
91
val = rtsx_pci_readl(pcr, RTSX_HAIMR);
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if ((val & HAIMR_TRANS_END) == 0) {
101
EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
103
int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
105
u32 val = HAIMR_READ_START;
108
val |= (u32)(addr & 0x3FFF) << 16;
109
rtsx_pci_writel(pcr, RTSX_HAIMR, val);
111
for (i = 0; i < MAX_RW_REG_CNT; i++) {
112
val = rtsx_pci_readl(pcr, RTSX_HAIMR);
113
if ((val & HAIMR_TRANS_END) == 0)
117
if (i >= MAX_RW_REG_CNT)
121
*data = (u8)(val & 0xFF);
125
EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
127
int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
129
int err, i, finished = 0;
132
rtsx_pci_init_cmd(pcr);
134
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
135
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
136
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
137
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
139
err = rtsx_pci_send_cmd(pcr, 100);
143
for (i = 0; i < 100000; i++) {
144
err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
159
EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
161
int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
163
int err, i, finished = 0;
167
rtsx_pci_init_cmd(pcr);
169
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
170
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
172
err = rtsx_pci_send_cmd(pcr, 100);
176
for (i = 0; i < 100000; i++) {
177
err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
190
rtsx_pci_init_cmd(pcr);
192
rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
193
rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
195
err = rtsx_pci_send_cmd(pcr, 100);
199
ptr = rtsx_pci_get_cmd_data(pcr);
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data = ((u16)ptr[1] << 8) | ptr[0];
207
EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
209
void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
211
rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
212
rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
214
rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
215
rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
217
EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
219
void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
220
u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
224
u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
226
val |= (u32)(cmd_type & 0x03) << 30;
227
val |= (u32)(reg_addr & 0x3FFF) << 16;
228
val |= (u32)mask << 8;
231
spin_lock_irqsave(&pcr->lock, flags);
233
if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
234
put_unaligned_le32(val, ptr);
238
spin_unlock_irqrestore(&pcr->lock, flags);
240
EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
242
void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
246
rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
248
val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
249
/* Hardware Auto Response */
251
rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
253
EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
255
int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
257
struct completion trans_done;
263
spin_lock_irqsave(&pcr->lock, flags);
265
/* set up data structures for the wakeup system */
266
pcr->done = &trans_done;
267
pcr->trans_result = TRANS_NOT_READY;
268
init_completion(&trans_done);
270
rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
272
val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
273
/* Hardware Auto Response */
275
rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
277
spin_unlock_irqrestore(&pcr->lock, flags);
279
/* Wait for TRANS_OK_INT */
280
timeleft = wait_for_completion_interruptible_timeout(
281
&trans_done, msecs_to_jiffies(timeout));
283
dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
286
goto finish_send_cmd;
289
spin_lock_irqsave(&pcr->lock, flags);
290
if (pcr->trans_result == TRANS_RESULT_FAIL)
292
else if (pcr->trans_result == TRANS_RESULT_OK)
294
else if (pcr->trans_result == TRANS_NO_DEVICE)
296
spin_unlock_irqrestore(&pcr->lock, flags);
299
spin_lock_irqsave(&pcr->lock, flags);
301
spin_unlock_irqrestore(&pcr->lock, flags);
303
if ((err < 0) && (err != -ENODEV))
304
rtsx_pci_stop_cmd(pcr);
307
complete(pcr->finish_me);
311
EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
313
static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
314
dma_addr_t addr, unsigned int len, int end)
316
u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
318
u8 option = SG_VALID | SG_TRANS_DATA;
320
dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n",
321
(unsigned int)addr, len);
325
val = ((u64)addr << 32) | ((u64)len << 12) | option;
327
put_unaligned_le64(val, ptr);
332
int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
333
int num_sg, bool read, int timeout)
335
struct completion trans_done;
337
int err = 0, i, count;
340
struct scatterlist *sg;
341
enum dma_data_direction dma_dir;
346
dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg);
348
/* don't transfer data during abort processing */
352
if ((sglist == NULL) || (num_sg <= 0))
356
dir = DEVICE_TO_HOST;
357
dma_dir = DMA_FROM_DEVICE;
359
dir = HOST_TO_DEVICE;
360
dma_dir = DMA_TO_DEVICE;
363
count = dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
365
dev_err(&(pcr->pci->dev), "scatterlist map failed\n");
368
dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count);
370
val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
372
for_each_sg(sglist, sg, count, i) {
373
addr = sg_dma_address(sg);
374
len = sg_dma_len(sg);
375
rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
378
spin_lock_irqsave(&pcr->lock, flags);
380
pcr->done = &trans_done;
381
pcr->trans_result = TRANS_NOT_READY;
382
init_completion(&trans_done);
383
rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
384
rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
386
spin_unlock_irqrestore(&pcr->lock, flags);
388
timeleft = wait_for_completion_interruptible_timeout(
389
&trans_done, msecs_to_jiffies(timeout));
391
dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
397
spin_lock_irqsave(&pcr->lock, flags);
399
if (pcr->trans_result == TRANS_RESULT_FAIL)
401
else if (pcr->trans_result == TRANS_NO_DEVICE)
404
spin_unlock_irqrestore(&pcr->lock, flags);
407
spin_lock_irqsave(&pcr->lock, flags);
409
spin_unlock_irqrestore(&pcr->lock, flags);
411
dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
413
if ((err < 0) && (err != -ENODEV))
414
rtsx_pci_stop_cmd(pcr);
417
complete(pcr->finish_me);
421
EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
423
int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
435
for (i = 0; i < buf_len / 256; i++) {
436
rtsx_pci_init_cmd(pcr);
438
for (j = 0; j < 256; j++)
439
rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
441
err = rtsx_pci_send_cmd(pcr, 250);
445
memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
450
rtsx_pci_init_cmd(pcr);
452
for (j = 0; j < buf_len % 256; j++)
453
rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
455
err = rtsx_pci_send_cmd(pcr, 250);
460
memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
464
EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
466
int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
478
for (i = 0; i < buf_len / 256; i++) {
479
rtsx_pci_init_cmd(pcr);
481
for (j = 0; j < 256; j++) {
482
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
487
err = rtsx_pci_send_cmd(pcr, 250);
493
rtsx_pci_init_cmd(pcr);
495
for (j = 0; j < buf_len % 256; j++) {
496
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
501
err = rtsx_pci_send_cmd(pcr, 250);
508
EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
510
static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
514
rtsx_pci_init_cmd(pcr);
516
while (*tbl & 0xFFFF0000) {
517
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
518
(u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
522
err = rtsx_pci_send_cmd(pcr, 100);
529
int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
533
if (card == RTSX_SD_CARD)
534
tbl = pcr->sd_pull_ctl_enable_tbl;
535
else if (card == RTSX_MS_CARD)
536
tbl = pcr->ms_pull_ctl_enable_tbl;
540
return rtsx_pci_set_pull_ctl(pcr, tbl);
542
EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
544
int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
548
if (card == RTSX_SD_CARD)
549
tbl = pcr->sd_pull_ctl_disable_tbl;
550
else if (card == RTSX_MS_CARD)
551
tbl = pcr->ms_pull_ctl_disable_tbl;
556
return rtsx_pci_set_pull_ctl(pcr, tbl);
558
EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
560
static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
562
pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
564
if (pcr->num_slots > 1)
565
pcr->bier |= MS_INT_EN;
567
/* Enable Bus Interrupt */
568
rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
570
dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier);
573
static inline u8 double_ssc_depth(u8 depth)
575
return ((depth > 1) ? (depth - 1) : depth);
578
static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
580
if (div > CLK_DIV_1) {
581
if (ssc_depth > (div - 1))
582
ssc_depth -= (div - 1);
584
ssc_depth = SSC_DEPTH_4M;
590
int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
591
u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
594
u8 N, min_N, max_N, clk_divider;
595
u8 mcu_cnt, div, max_div;
597
[RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
598
[RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
599
[RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
600
[RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
601
[RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
605
/* We use 250k(around) here, in initial stage */
606
clk_divider = SD_CLK_DIVIDE_128;
607
card_clock = 30000000;
609
clk_divider = SD_CLK_DIVIDE_0;
611
err = rtsx_pci_write_register(pcr, SD_CFG1,
612
SD_CLK_DIVIDE_MASK, clk_divider);
616
card_clock /= 1000000;
617
dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
624
if (!initial_mode && double_clk)
625
clk = card_clock * 2;
626
dev_dbg(&(pcr->pci->dev),
627
"Internal SSC clock: %dMHz (cur_clock = %d)\n",
628
clk, pcr->cur_clock);
630
if (clk == pcr->cur_clock)
634
if ((clk <= 2) || (N > max_N))
637
mcu_cnt = (u8)(125/clk + 3);
641
/* Make sure that the SSC clock div_n is equal or greater than min_N */
643
while ((N < min_N) && (div < max_div)) {
647
dev_dbg(&(pcr->pci->dev), "N = %d, div = %d\n", N, div);
649
ssc_depth = depth[ssc_depth];
651
ssc_depth = double_ssc_depth(ssc_depth);
653
ssc_depth = revise_ssc_depth(ssc_depth, div);
654
dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
656
rtsx_pci_init_cmd(pcr);
657
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
658
CLK_LOW_FREQ, CLK_LOW_FREQ);
659
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
660
0xFF, (div << 4) | mcu_cnt);
661
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
662
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
663
SSC_DEPTH_MASK, ssc_depth);
664
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N);
665
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
667
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
669
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
670
PHASE_NOT_RESET, PHASE_NOT_RESET);
673
err = rtsx_pci_send_cmd(pcr, 2000);
677
/* Wait SSC clock stable */
679
err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
683
pcr->cur_clock = clk;
686
EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
688
int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
690
if (pcr->ops->card_power_on)
691
return pcr->ops->card_power_on(pcr, card);
695
EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
697
int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
699
if (pcr->ops->card_power_off)
700
return pcr->ops->card_power_off(pcr, card);
704
EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
706
int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
708
if (pcr->ops->switch_output_voltage)
709
return pcr->ops->switch_output_voltage(pcr, voltage);
713
EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
715
unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
719
val = rtsx_pci_readl(pcr, RTSX_BIPR);
720
if (pcr->ops->cd_deglitch)
721
val = pcr->ops->cd_deglitch(pcr);
725
EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
727
void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
729
struct completion finish;
731
pcr->finish_me = &finish;
732
init_completion(&finish);
737
if (!pcr->remove_pci)
738
rtsx_pci_stop_cmd(pcr);
740
wait_for_completion_interruptible_timeout(&finish,
741
msecs_to_jiffies(2));
742
pcr->finish_me = NULL;
744
EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
746
static void rtsx_pci_card_detect(struct work_struct *work)
748
struct delayed_work *dwork;
749
struct rtsx_pcr *pcr;
751
unsigned int card_detect = 0;
754
dwork = to_delayed_work(work);
755
pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
757
dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
759
spin_lock_irqsave(&pcr->lock, flags);
761
irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
762
dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
764
if (pcr->card_inserted || pcr->card_removed) {
765
dev_dbg(&(pcr->pci->dev),
766
"card_inserted: 0x%x, card_removed: 0x%x\n",
767
pcr->card_inserted, pcr->card_removed);
769
if (pcr->ops->cd_deglitch)
770
pcr->card_inserted = pcr->ops->cd_deglitch(pcr);
772
card_detect = pcr->card_inserted | pcr->card_removed;
773
pcr->card_inserted = 0;
774
pcr->card_removed = 0;
777
spin_unlock_irqrestore(&pcr->lock, flags);
779
if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
780
pcr->slots[RTSX_SD_CARD].card_event(
781
pcr->slots[RTSX_SD_CARD].p_dev);
782
if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
783
pcr->slots[RTSX_MS_CARD].card_event(
784
pcr->slots[RTSX_MS_CARD].p_dev);
787
static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
789
struct rtsx_pcr *pcr = dev_id;
795
spin_lock(&pcr->lock);
797
int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
798
/* Clear interrupt flag */
799
rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
800
if ((int_reg & pcr->bier) == 0) {
801
spin_unlock(&pcr->lock);
804
if (int_reg == 0xFFFFFFFF) {
805
spin_unlock(&pcr->lock);
809
int_reg &= (pcr->bier | 0x7FFFFF);
811
if (int_reg & SD_INT) {
812
if (int_reg & SD_EXIST) {
813
pcr->card_inserted |= SD_EXIST;
815
pcr->card_removed |= SD_EXIST;
816
pcr->card_inserted &= ~SD_EXIST;
820
if (int_reg & MS_INT) {
821
if (int_reg & MS_EXIST) {
822
pcr->card_inserted |= MS_EXIST;
824
pcr->card_removed |= MS_EXIST;
825
pcr->card_inserted &= ~MS_EXIST;
829
if (pcr->card_inserted || pcr->card_removed)
830
schedule_delayed_work(&pcr->carddet_work,
831
msecs_to_jiffies(200));
833
if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
834
if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
835
pcr->trans_result = TRANS_RESULT_FAIL;
838
} else if (int_reg & TRANS_OK_INT) {
839
pcr->trans_result = TRANS_RESULT_OK;
845
spin_unlock(&pcr->lock);
849
static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
851
dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
852
__func__, pcr->msi_en, pcr->pci->irq);
854
if (request_irq(pcr->pci->irq, rtsx_pci_isr,
855
pcr->msi_en ? 0 : IRQF_SHARED,
856
DRV_NAME_RTSX_PCI, pcr)) {
857
dev_err(&(pcr->pci->dev),
858
"rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
863
pcr->irq = pcr->pci->irq;
864
pci_intx(pcr->pci, !pcr->msi_en);
869
static void rtsx_pci_idle_work(struct work_struct *work)
871
struct delayed_work *dwork = to_delayed_work(work);
872
struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
874
dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
876
mutex_lock(&pcr->pcr_mutex);
878
pcr->state = PDEV_STAT_IDLE;
880
if (pcr->ops->disable_auto_blink)
881
pcr->ops->disable_auto_blink(pcr);
882
if (pcr->ops->turn_off_led)
883
pcr->ops->turn_off_led(pcr);
885
mutex_unlock(&pcr->pcr_mutex);
888
static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
892
rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
894
rtsx_pci_enable_bus_int(pcr);
897
err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
901
/* Wait SSC power stable */
904
if (pcr->ops->optimize_phy) {
905
err = pcr->ops->optimize_phy(pcr);
910
rtsx_pci_init_cmd(pcr);
912
/* Set mcu_cnt to 7 to ensure data can be sampled properly */
913
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
915
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
916
/* Disable card clock */
917
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
918
/* Reset ASPM state to default value */
919
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
920
/* Reset delink mode */
921
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
922
/* Card driving select */
923
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
924
0x07, DRIVER_TYPE_D);
925
/* Enable SSC Clock */
926
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
927
0xFF, SSC_8X_EN | SSC_SEL_4M);
928
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
929
/* Disable cd_pwr_save */
930
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
931
/* Clear Link Ready Interrupt */
932
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
933
LINK_RDY_INT, LINK_RDY_INT);
934
/* Enlarge the estimation window of PERST# glitch
935
* to reduce the chance of invalid card interrupt
937
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
938
/* Update RC oscillator to 400k
939
* bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
942
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
943
/* Set interrupt write clear
944
* bit 1: U_elbi_if_rd_clr_en
945
* 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
946
* 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
948
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
949
/* Force CLKREQ# PIN to drive 0 to request clock */
950
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
952
err = rtsx_pci_send_cmd(pcr, 100);
956
/* Enable clk_request_n to enable clock power management */
957
rtsx_pci_write_config_byte(pcr, 0x81, 1);
958
/* Enter L1 when host tx idle */
959
rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
961
if (pcr->ops->extra_init_hw) {
962
err = pcr->ops->extra_init_hw(pcr);
970
static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
974
spin_lock_init(&pcr->lock);
975
mutex_init(&pcr->pcr_mutex);
977
switch (PCI_PID(pcr)) {
980
rts5209_init_params(pcr);
984
rts5229_init_params(pcr);
988
rtl8411_init_params(pcr);
992
dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
993
PCI_PID(pcr), pcr->ic_version);
995
pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1000
pcr->state = PDEV_STAT_IDLE;
1001
err = rtsx_pci_init_hw(pcr);
1010
static int __devinit rtsx_pci_probe(struct pci_dev *pcidev,
1011
const struct pci_device_id *id)
1013
struct rtsx_pcr *pcr;
1014
struct pcr_handle *handle;
1018
dev_dbg(&(pcidev->dev),
1019
": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1020
pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1021
(int)pcidev->revision);
1023
ret = pci_enable_device(pcidev);
1027
ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1031
pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1037
handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1044
if (!idr_pre_get(&rtsx_pci_idr, GFP_KERNEL)) {
1049
spin_lock(&rtsx_pci_lock);
1050
ret = idr_get_new(&rtsx_pci_idr, pcr, &pcr->id);
1051
spin_unlock(&rtsx_pci_lock);
1056
dev_set_drvdata(&pcidev->dev, handle);
1058
len = pci_resource_len(pcidev, 0);
1059
base = pci_resource_start(pcidev, 0);
1060
pcr->remap_addr = ioremap_nocache(base, len);
1061
if (!pcr->remap_addr) {
1066
pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1067
RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1069
if (pcr->rtsx_resv_buf == NULL) {
1073
pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1074
pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1075
pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1076
pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1078
pcr->card_inserted = 0;
1079
pcr->card_removed = 0;
1080
INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1081
INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1083
pcr->msi_en = msi_en;
1085
ret = pci_enable_msi(pcidev);
1087
pcr->msi_en = false;
1090
ret = rtsx_pci_acquire_irq(pcr);
1094
pci_set_master(pcidev);
1095
synchronize_irq(pcr->irq);
1097
ret = rtsx_pci_init_chip(pcr);
1101
for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1102
rtsx_pcr_cells[i].platform_data = handle;
1103
rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1105
ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1106
ARRAY_SIZE(rtsx_pcr_cells), NULL, 0);
1110
schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1115
free_irq(pcr->irq, (void *)pcr);
1117
dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1118
pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1120
iounmap(pcr->remap_addr);
1122
dev_set_drvdata(&pcidev->dev, NULL);
1128
pci_release_regions(pcidev);
1130
pci_disable_device(pcidev);
1135
static void __devexit rtsx_pci_remove(struct pci_dev *pcidev)
1137
struct pcr_handle *handle = pci_get_drvdata(pcidev);
1138
struct rtsx_pcr *pcr = handle->pcr;
1140
pcr->remove_pci = true;
1142
cancel_delayed_work(&pcr->carddet_work);
1143
cancel_delayed_work(&pcr->idle_work);
1145
mfd_remove_devices(&pcidev->dev);
1147
dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1148
pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1149
free_irq(pcr->irq, (void *)pcr);
1151
pci_disable_msi(pcr->pci);
1152
iounmap(pcr->remap_addr);
1154
dev_set_drvdata(&pcidev->dev, NULL);
1155
pci_release_regions(pcidev);
1156
pci_disable_device(pcidev);
1158
spin_lock(&rtsx_pci_lock);
1159
idr_remove(&rtsx_pci_idr, pcr->id);
1160
spin_unlock(&rtsx_pci_lock);
1166
dev_dbg(&(pcidev->dev),
1167
": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1168
pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1173
static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1175
struct pcr_handle *handle;
1176
struct rtsx_pcr *pcr;
1179
dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1181
handle = pci_get_drvdata(pcidev);
1184
cancel_delayed_work(&pcr->carddet_work);
1185
cancel_delayed_work(&pcr->idle_work);
1187
mutex_lock(&pcr->pcr_mutex);
1189
if (pcr->ops->turn_off_led)
1190
pcr->ops->turn_off_led(pcr);
1192
rtsx_pci_writel(pcr, RTSX_BIER, 0);
1195
rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
1196
rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x02);
1198
pci_save_state(pcidev);
1199
pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1200
pci_disable_device(pcidev);
1201
pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1203
mutex_unlock(&pcr->pcr_mutex);
1207
static int rtsx_pci_resume(struct pci_dev *pcidev)
1209
struct pcr_handle *handle;
1210
struct rtsx_pcr *pcr;
1213
dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1215
handle = pci_get_drvdata(pcidev);
1218
mutex_lock(&pcr->pcr_mutex);
1220
pci_set_power_state(pcidev, PCI_D0);
1221
pci_restore_state(pcidev);
1222
ret = pci_enable_device(pcidev);
1225
pci_set_master(pcidev);
1227
ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1231
ret = rtsx_pci_init_hw(pcr);
1235
schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1238
mutex_unlock(&pcr->pcr_mutex);
1242
#else /* CONFIG_PM */
1244
#define rtsx_pci_suspend NULL
1245
#define rtsx_pci_resume NULL
1247
#endif /* CONFIG_PM */
1249
static struct pci_driver rtsx_pci_driver = {
1250
.name = DRV_NAME_RTSX_PCI,
1251
.id_table = rtsx_pci_ids,
1252
.probe = rtsx_pci_probe,
1253
.remove = __devexit_p(rtsx_pci_remove),
1254
.suspend = rtsx_pci_suspend,
1255
.resume = rtsx_pci_resume,
1257
module_pci_driver(rtsx_pci_driver);
1259
MODULE_LICENSE("GPL");
1260
MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1261
MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");