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Viewing changes to src/V3LinkResolve.cpp

Committer: Package Import Robot
Author(s): أحمد المحمودي (Ahmed El-Mahmoudy)
Date: 2014-06-17 19:59:50 UTC
mfrom: (1.2.28)
Revision ID: package-import@ubuntu.com-20140617195950-cikhbkjg8x545qdy

Tags: 3.862-1

New upstream release.

files added:
test_regress/t/t_detectarray_3.pl

test_regress/t/t_detectarray_3.v

test_regress/t/t_flag_woff.pl

test_regress/t/t_flag_woff.v

test_regress/t/t_gate_array.pl

test_regress/t/t_gate_array.v

test_regress/t/t_gen_for_overlap.pl

test_regress/t/t_gen_for_overlap.v

test_regress/t/t_interface_param1.pl

test_regress/t/t_interface_param1.v

test_regress/t/t_math_div0.pl

test_regress/t/t_math_div0.v

test_regress/t/t_math_shift_rep.pl

test_regress/t/t_math_shift_rep.v

test_regress/t/t_preproc_noline.out

test_regress/t/t_preproc_noline.pl

test_regress/t/t_preproc_noline.v

test_regress/t/t_tri_array.pl

test_regress/t/t_tri_array.v

files modified:
.pc/shebang.diff/bin/verilator

Changes

README.pdf

bin/verilator

configure

configure.ac

debian/changelog

include/verilated.cpp

include/verilated.h

include/verilated_config.h

include/verilated_save.cpp

include/verilated_vcd_c.cpp

include/verilated_vpi.h

internals.pdf

src/V3Ast.cpp

src/V3AstNodes.h

src/V3Changed.cpp

src/V3Const.cpp

src/V3EmitC.cpp

src/V3EmitCSyms.cpp

src/V3EmitMk.cpp

src/V3Error.cpp

src/V3Error.h

src/V3Expand.cpp

src/V3File.cpp

src/V3File.h

src/V3Gate.cpp

src/V3Global.h

src/V3LinkDot.cpp

src/V3LinkResolve.cpp

src/V3Number.cpp

src/V3Number.h

src/V3Options.cpp

src/V3Options.h

src/V3Order.cpp

src/V3ParseImp.cpp

src/V3PreLex.l

src/V3PreProc.cpp

src/V3PreProc.h

src/V3TraceDecl.cpp

src/V3Tristate.cpp

src/V3Undriven.cpp

src/V3Width.cpp

src/Verilator.cpp

src/config_build.h

src/config_rev.h

src/verilog.y

test_regress/t/t_array_pattern_packed.v

test_regress/t/t_dist_portability.pl

test_regress/t/t_hierarchy_identifier.v

test_regress/t/t_math_signed5.v

test_regress/t/t_package_twodeep.v

test_regress/t/t_struct_init.v

test_regress/t/t_sv_cpu.pl

test_regress/t/t_sv_cpu.v

test_regress/t/t_sv_cpu_code/chip.sv

test_regress/t/t_sv_cpu_code/pad_gpio.sv

test_regress/t/t_sv_cpu_code/pads.sv

test_regress/t/t_var_rsvd_bad.pl

verilator.1

verilator.html

verilator.pdf

verilator.txt

Show diffs side-by-side

added added

removed removed

src/V3LinkResolve.cpp

250

void expectFormat(AstNode* nodep, const string& format, AstNode* argp, bool isScan) {

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// Check display arguments

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bool inPct = false;

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for (const char* inp = format.c_str(); *inp; inp++) {

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char ch = tolower(*inp); // Breaks with iterators...

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for (string::const_iterator it = format.begin(); it != format.end(); ++it) {

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char ch = tolower(*it);

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if (!inPct && ch=='%') {

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inPct = true;

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} else if (inPct) {

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