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// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Varun Koyyalagunta.
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typedef struct packed {
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module m1 (output s_data data[1:0]);
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module top (output s_data data[2:0]);
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m1 m1_inst (.data(data[1:0]));