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// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Wilson Snyder.
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initial struct1 = 64'h123456789_abcdef0;
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always_comb s1 = struct1;
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initial struct2 = 64'h123456789_abcdef0;
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always_comb s2 = struct2;