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  • Committer: pbrook
  • Date: 2007-04-07 18:14:41 UTC
  • Revision ID: git-v1:d537cf6c8624b27ce2b63431d2f8937f6356f652
Unify IRQ handling.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2635 c046a42c-6fe2-441c-8c8c-71466251a162

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Lines of Context:
hw/arm_gic.c
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typedef struct gic_state
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{
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    arm_pic_handler handler;
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    uint32_t base;
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    void *parent;
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    int parent_irq;
 
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    qemu_irq parent_irq;
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    int enabled;
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    int cpu_enabled;
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    s->current_pending = 1023;
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    if (!s->enabled || !s->cpu_enabled) {
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        pic_set_irq_new(s->parent, s->parent_irq, 0);
 
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        qemu_irq_lower(s->parent_irq);
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        return;
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    }
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    best_prio = 0x100;
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        }
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    }
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    if (best_prio > s->priority_mask) {
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        pic_set_irq_new(s->parent, s->parent_irq, 0);
 
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        qemu_irq_lower(s->parent_irq);
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    } else {
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        s->current_pending = best_irq;
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        if (best_prio < s->running_priority) {
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            DPRINTF("Raised pending IRQ %d\n", best_irq);
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            pic_set_irq_new(s->parent, s->parent_irq, 1);
 
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            qemu_irq_raise(s->parent_irq);
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        }
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    }
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}
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        DPRINTF("ACK no pending IRQ\n");
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        return 1023;
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    }
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    pic_set_irq_new(s->parent, s->parent_irq, 0);
 
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    qemu_irq_lower(s->parent_irq);
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    s->last_active[new_irq] = s->running_irq;
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    /* For level triggered interrupts we clear the pending bit while
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       the interrupt is active.  */
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    s->cpu_enabled = 0;
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}
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void *arm_gic_init(uint32_t base, void *parent, int parent_irq)
 
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qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq)
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{
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    gic_state *s;
 
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    qemu_irq *qi;
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    int iomemtype;
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    s = (gic_state *)qemu_mallocz(sizeof(gic_state));
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    if (!s)
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        return NULL;
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    s->handler = gic_set_irq;
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    s->parent = parent;
 
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    qi = qemu_allocate_irqs(gic_set_irq, s, GIC_NIRQ);
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    s->parent_irq = parent_irq;
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    if (base != 0xffffffff) {
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        iomemtype = cpu_register_io_memory(0, gic_cpu_readfn,
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        s->base = 0;
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    }
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    gic_reset(s);
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    return s;
 
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    return qi;
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}