2
* Copyright (c) 2008-2011 Atheros Communications Inc.
4
* Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5
* Original from Linux kernel 3.0.1
7
* Permission to use, copy, modify, and/or distribute this software for any
8
* purpose with or without fee is hereby granted, provided that the above
9
* copyright notice and this permission notice appear in all copies.
11
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20
#include <ipxe/malloc.h>
21
#include <ipxe/pci_io.h>
26
int is_ath9k_unloaded;
27
/* We use the hw_value as an index into our private channel structure */
29
#define CHAN2G(_freq, _idx) { \
30
.band = NET80211_BAND_2GHZ, \
31
.center_freq = (_freq), \
36
#define CHAN5G(_freq, _idx) { \
37
.band = NET80211_BAND_5GHZ, \
38
.center_freq = (_freq), \
43
/* Some 2 GHz radios are actually tunable on 2312-2732
44
* on 5 MHz steps, we support the channels which we know
45
* we have calibration data for all cards though to make
47
static const struct net80211_channel ath9k_2ghz_chantable[] = {
48
CHAN2G(2412, 0), /* Channel 1 */
49
CHAN2G(2417, 1), /* Channel 2 */
50
CHAN2G(2422, 2), /* Channel 3 */
51
CHAN2G(2427, 3), /* Channel 4 */
52
CHAN2G(2432, 4), /* Channel 5 */
53
CHAN2G(2437, 5), /* Channel 6 */
54
CHAN2G(2442, 6), /* Channel 7 */
55
CHAN2G(2447, 7), /* Channel 8 */
56
CHAN2G(2452, 8), /* Channel 9 */
57
CHAN2G(2457, 9), /* Channel 10 */
58
CHAN2G(2462, 10), /* Channel 11 */
59
CHAN2G(2467, 11), /* Channel 12 */
60
CHAN2G(2472, 12), /* Channel 13 */
61
CHAN2G(2484, 13), /* Channel 14 */
64
/* Some 5 GHz radios are actually tunable on XXXX-YYYY
65
* on 5 MHz steps, we support the channels which we know
66
* we have calibration data for all cards though to make
68
static const struct net80211_channel ath9k_5ghz_chantable[] = {
69
/* _We_ call this UNII 1 */
70
CHAN5G(5180, 14), /* Channel 36 */
71
CHAN5G(5200, 15), /* Channel 40 */
72
CHAN5G(5220, 16), /* Channel 44 */
73
CHAN5G(5240, 17), /* Channel 48 */
74
/* _We_ call this UNII 2 */
75
CHAN5G(5260, 18), /* Channel 52 */
76
CHAN5G(5280, 19), /* Channel 56 */
77
CHAN5G(5300, 20), /* Channel 60 */
78
CHAN5G(5320, 21), /* Channel 64 */
79
/* _We_ call this "Middle band" */
80
CHAN5G(5500, 22), /* Channel 100 */
81
CHAN5G(5520, 23), /* Channel 104 */
82
CHAN5G(5540, 24), /* Channel 108 */
83
CHAN5G(5560, 25), /* Channel 112 */
84
CHAN5G(5580, 26), /* Channel 116 */
85
CHAN5G(5600, 27), /* Channel 120 */
86
CHAN5G(5620, 28), /* Channel 124 */
87
CHAN5G(5640, 29), /* Channel 128 */
88
CHAN5G(5660, 30), /* Channel 132 */
89
CHAN5G(5680, 31), /* Channel 136 */
90
CHAN5G(5700, 32), /* Channel 140 */
91
/* _We_ call this UNII 3 */
92
CHAN5G(5745, 33), /* Channel 149 */
93
CHAN5G(5765, 34), /* Channel 153 */
94
CHAN5G(5785, 35), /* Channel 157 */
95
CHAN5G(5805, 36), /* Channel 161 */
96
CHAN5G(5825, 37), /* Channel 165 */
99
/* Atheros hardware rate code addition for short premble */
100
#define SHPCHECK(__hw_rate, __flags) \
101
((__flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
103
#define RATE(_bitrate, _hw_rate, _flags) { \
104
.bitrate = (_bitrate), \
106
.hw_value = (_hw_rate), \
107
.hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
110
static struct ath9k_legacy_rate ath9k_legacy_rates[] = {
112
RATE(20, 0x1a, IEEE80211_TX_RC_USE_SHORT_PREAMBLE),
113
RATE(55, 0x19, IEEE80211_TX_RC_USE_SHORT_PREAMBLE),
114
RATE(110, 0x18, IEEE80211_TX_RC_USE_SHORT_PREAMBLE),
125
static void ath9k_deinit_softc(struct ath_softc *sc);
128
* Read and write, they both share the same lock. We do this to serialize
129
* reads and writes on Atheros 802.11n PCI devices only. This is required
130
* as the FIFO on these devices can only accept sanely 2 requests.
133
static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
135
struct ath_hw *ah = (struct ath_hw *) hw_priv;
136
struct ath_common *common = ath9k_hw_common(ah);
137
struct ath_softc *sc = (struct ath_softc *) common->priv;
139
writel(val, sc->mem + reg_offset);
142
static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
144
struct ath_hw *ah = (struct ath_hw *) hw_priv;
145
struct ath_common *common = ath9k_hw_common(ah);
146
struct ath_softc *sc = (struct ath_softc *) common->priv;
149
val = readl(sc->mem + reg_offset);
153
static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
155
struct ath_hw *ah = (struct ath_hw *) hw_priv;
156
struct ath_common *common = ath9k_hw_common(ah);
157
struct ath_softc *sc = (struct ath_softc *) common->priv;
160
val = readl(sc->mem + reg_offset);
163
writel(val, sc->mem + reg_offset);
168
/**************************/
170
/**************************/
173
* This function will allocate both the DMA descriptor structure, and the
174
* buffers it contains. These are used to contain the descriptors used
177
int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
178
struct list_head *head, const char *name,
179
int nbuf, int ndesc, int is_tx)
181
#define DS2PHYS(_dd, _ds) \
182
((_dd)->dd_desc_paddr + ((char *)(_ds) - (char *)(_dd)->dd_desc))
183
#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF9F) ? 1 : 0)
186
int i, bsize, error, desc_len;
188
DBG2("ath9k: %s DMA: %d buffers %d desc/buf\n",
191
INIT_LIST_HEAD(head);
194
desc_len = sc->sc_ah->caps.tx_desc_len;
196
desc_len = sizeof(struct ath_desc);
198
/* ath_desc must be a multiple of DWORDs */
199
if ((desc_len % 4) != 0) {
200
DBG("ath9k: ath_desc not DWORD aligned\n");
205
dd->dd_desc_len = desc_len * nbuf * ndesc;
208
* Need additional DMA memory because we can't use
209
* descriptors that cross the 4K page boundary.
210
* However, iPXE only utilizes 16 buffers, which
211
* will never make up more than half of one page,
212
* so we will only ever skip 1 descriptor, if that.
214
if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
215
u32 ndesc_skipped = 1;
218
dma_len = ndesc_skipped * desc_len;
219
dd->dd_desc_len += dma_len;
222
/* allocate descriptors */
223
dd->dd_desc = malloc_dma(dd->dd_desc_len, 16);
224
if (dd->dd_desc == NULL) {
228
dd->dd_desc_paddr = virt_to_bus(dd->dd_desc);
229
ds = (u8 *) dd->dd_desc;
230
DBG2("ath9k: %s DMA map: %p (%d) -> %llx (%d)\n",
231
name, ds, (u32) dd->dd_desc_len,
232
ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
234
/* allocate buffers */
235
bsize = sizeof(struct ath_buf) * nbuf;
243
for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
245
bf->bf_daddr = DS2PHYS(dd, ds);
247
if (!(sc->sc_ah->caps.hw_caps &
248
ATH9K_HW_CAP_4KB_SPLITTRANS)) {
250
* Skip descriptor addresses which can cause 4KB
251
* boundary crossing (addr + length) with a 32 dword
254
while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
255
ds += (desc_len * ndesc);
257
bf->bf_daddr = DS2PHYS(dd, ds);
260
list_add_tail(&bf->list, head);
264
free_dma(dd->dd_desc, dd->dd_desc_len);
266
memset(dd, 0, sizeof(*dd));
268
#undef ATH_DESC_4KB_BOUND_CHECK
272
void ath9k_init_crypto(struct ath_softc *sc)
274
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
277
/* Get the hardware key cache size. */
278
common->keymax = AR_KEYTABLE_SIZE;
281
* Reset the key cache since some parts do not
282
* reset the contents on initial power up.
284
for (i = 0; i < common->keymax; i++)
285
ath_hw_keyreset(common, (u16) i);
288
* Check whether the separate key cache entries
289
* are required to handle both tx+rx MIC keys.
290
* With split mic keys the number of stations is limited
291
* to 27 otherwise 59.
293
if (sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
294
common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
297
static int ath9k_init_queues(struct ath_softc *sc)
301
for (i = 0; i < WME_NUM_AC; i++) {
302
sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
303
sc->tx.txq_map[i]->mac80211_qnum = i;
308
static int ath9k_init_channels_rates(struct ath_softc *sc)
312
memcpy(&sc->rates, ath9k_legacy_rates, sizeof(ath9k_legacy_rates));
314
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
315
memcpy(&sc->hwinfo->channels[sc->hwinfo->nr_channels], ath9k_2ghz_chantable, sizeof(ath9k_2ghz_chantable));
317
sc->hwinfo->nr_channels += ARRAY_SIZE(ath9k_2ghz_chantable);
319
for (i = 0; i < ARRAY_SIZE(ath9k_legacy_rates); i++)
320
sc->hwinfo->rates[NET80211_BAND_2GHZ][i] = ath9k_legacy_rates[i].bitrate;
321
sc->hwinfo->nr_rates[NET80211_BAND_2GHZ] = ARRAY_SIZE(ath9k_legacy_rates);
324
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
325
memcpy(&sc->hwinfo->channels[sc->hwinfo->nr_channels], ath9k_5ghz_chantable, sizeof(ath9k_5ghz_chantable));
327
sc->hwinfo->nr_channels += ARRAY_SIZE(ath9k_5ghz_chantable);
329
for (i = 4; i < ARRAY_SIZE(ath9k_legacy_rates); i++)
330
sc->hwinfo->rates[NET80211_BAND_5GHZ][i - 4] = ath9k_legacy_rates[i].bitrate;
331
sc->hwinfo->nr_rates[NET80211_BAND_5GHZ] = ARRAY_SIZE(ath9k_legacy_rates) - 4;
336
static void ath9k_init_misc(struct ath_softc *sc)
338
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
340
common->ani.timer = 0;
342
sc->config.txpowlimit = ATH_TXPOWER_MAX;
344
common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
345
common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
347
ath9k_hw_set_diversity(sc->sc_ah, 1);
348
sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
350
memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
353
static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
354
const struct ath_bus_ops *bus_ops)
356
struct ath_hw *ah = NULL;
357
struct ath_common *common;
361
ah = zalloc(sizeof(struct ath_hw));
366
ah->hw_version.devid = devid;
367
ah->hw_version.subsysid = subsysid;
368
ah->reg_ops.read = ath9k_ioread32;
369
ah->reg_ops.write = ath9k_iowrite32;
370
ah->reg_ops.rmw = ath9k_reg_rmw;
373
sc->hwinfo = zalloc(sizeof(*sc->hwinfo));
375
DBG("ath9k: cannot allocate 802.11 hardware info structure\n");
379
ah->ah_flags |= AH_USE_EEPROM;
380
sc->sc_ah->led_pin = -1;
382
common = ath9k_hw_common(ah);
383
common->ops = &ah->reg_ops;
384
common->bus_ops = bus_ops;
386
common->dev = sc->dev;
389
sc->intr_tq = ath9k_tasklet;
392
* Cache line size is used to size and align various
393
* structures used to communicate with the hardware.
395
ath_read_cachesize(common, &csz);
396
common->cachelsz = csz << 2; /* convert to bytes */
398
/* Initializes the hardware for all supported chipsets */
399
ret = ath9k_hw_init(ah);
403
memcpy(sc->hwinfo->hwaddr, common->macaddr, ETH_ALEN);
405
ret = ath9k_init_queues(sc);
409
ret = ath9k_init_channels_rates(sc);
413
ath9k_init_crypto(sc);
419
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
420
if (ATH_TXQ_SETUP(sc, i))
421
ath_tx_cleanupq(sc, &sc->tx.txq[i]);
434
static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
436
struct net80211_channel *chan;
437
struct ath_hw *ah = sc->sc_ah;
438
struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
441
for (i = 0; i < sc->hwinfo->nr_channels; i++) {
442
chan = &sc->hwinfo->channels[i];
443
if(chan->band != band)
445
ah->curchan = &ah->channels[chan->hw_value];
446
ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, 1);
447
chan->maxpower = reg->max_power_level / 2;
451
static void ath9k_init_txpower_limits(struct ath_softc *sc)
453
struct ath_hw *ah = sc->sc_ah;
454
struct ath9k_channel *curchan = ah->curchan;
456
if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
457
ath9k_init_band_txpower(sc, NET80211_BAND_2GHZ);
458
if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
459
ath9k_init_band_txpower(sc, NET80211_BAND_5GHZ);
461
ah->curchan = curchan;
464
void ath9k_set_hw_capab(struct ath_softc *sc, struct net80211_device *dev __unused)
466
sc->hwinfo->flags = NET80211_HW_RX_HAS_FCS;
467
sc->hwinfo->signal_type = NET80211_SIGNAL_DB;
468
sc->hwinfo->signal_max = 40; /* 35dB should give perfect 54Mbps */
469
sc->hwinfo->channel_change_time = 5000;
471
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
473
sc->hwinfo->bands |= NET80211_BAND_BIT_2GHZ;
474
sc->hwinfo->modes |= NET80211_MODE_B | NET80211_MODE_G;
476
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
478
sc->hwinfo->bands |= NET80211_BAND_BIT_5GHZ;
479
sc->hwinfo->modes |= NET80211_MODE_A;
483
int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
484
const struct ath_bus_ops *bus_ops)
486
struct net80211_device *dev = sc->dev;
487
/*struct ath_common *common;
490
/*struct ath_regulatory *reg;*/
492
/* Bring up device */
493
error = ath9k_init_softc(devid, sc, subsysid, bus_ops);
498
common = ath9k_hw_common(ah);*/
499
ath9k_set_hw_capab(sc, dev);
500
/* TODO Cottsay: reg */
501
/* Initialize regulatory */
502
/*error = ath_regd_init(&common->regulatory, sc->dev->wiphy,
507
reg = &common->regulatory;*/
510
error = ath_tx_init(sc, ATH_TXBUF);
515
error = ath_rx_init(sc, ATH_RXBUF);
519
ath9k_init_txpower_limits(sc);
521
/* Register with mac80211 */
522
error = net80211_register(dev, &ath9k_ops, sc->hwinfo);
526
/* TODO Cottsay: reg */
527
/* Handle world regulatory */
528
/*if (!ath_is_world_regd(reg)) {
529
error = regulatory_hint(hw->wiphy, reg->alpha2);
534
sc->hw_pll_work = ath_hw_pll_work;
535
sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
537
/* TODO Cottsay: rfkill */
538
/*ath_start_rfkill_poll(sc);*/
543
// net80211_unregister(dev);
549
ath9k_deinit_softc(sc);
554
/*****************************/
555
/* De-Initialization */
556
/*****************************/
558
static void ath9k_deinit_softc(struct ath_softc *sc)
562
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
563
if (ATH_TXQ_SETUP(sc, i))
564
ath_tx_cleanupq(sc, &sc->tx.txq[i]);
566
ath9k_hw_deinit(sc->sc_ah);
574
void ath9k_deinit_device(struct ath_softc *sc)
576
struct net80211_device *dev = sc->dev;
578
net80211_unregister(dev);
581
ath9k_deinit_softc(sc);
584
void ath_descdma_cleanup(struct ath_softc *sc __unused,
585
struct ath_descdma *dd,
586
struct list_head *head)
588
free_dma(dd->dd_desc, dd->dd_desc_len);
590
INIT_LIST_HEAD(head);
592
memset(dd, 0, sizeof(*dd));
added
removed
src/drivers/net/ath/ath9k/ath9k_init.c
