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/* Copyright (c) 2007 Atmel Corporation
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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* Neither the name of the copyright holders nor the names of
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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/* $Id: io90pwm2b.h,v 1.1.2.2 2007/10/19 23:16:30 arcanum Exp $ */
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/* avr/io90pwm2b.h - definitions for AT90PWM2B */
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/* This file should only be included from <avr/io.h>, never directly. */
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# error "Include <avr/io.h> instead of this file."
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# define _AVR_IOXXX_H_ "io90pwm2b.h"
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# error "Attempt to include more than one <avr/ioXXX.h> file."
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#ifndef _AVR_IO90PWM2B_H_
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#define _AVR_IO90PWM2B_H_ 1
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/* Registers and associated bit numbers */
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#define PINB _SFR_IO8(0x03)
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#define DDRB _SFR_IO8(0x04)
74
#define PORTB _SFR_IO8(0x05)
84
#define PINC _SFR_IO8(0x06)
86
#define DDRC _SFR_IO8(0x07)
88
#define PORTC _SFR_IO8(0x08)
90
#define PIND _SFR_IO8(0x09)
100
#define DDRD _SFR_IO8(0x0A)
110
#define PORTD _SFR_IO8(0x0B)
120
#define PINE _SFR_IO8(0x0C)
125
#define DDRE _SFR_IO8(0x0D)
130
#define PORTE _SFR_IO8(0x0E)
135
#define TIFR0 _SFR_IO8(0x15)
140
#define TIFR1 _SFR_IO8(0x16)
146
#define GPIOR1 _SFR_IO8(0x19)
156
#define GPIOR2 _SFR_IO8(0x1A)
166
#define GPIOR3 _SFR_IO8(0x1B)
176
#define EIFR _SFR_IO8(0x1C)
181
#define EIMSK _SFR_IO8(0x1D)
186
#define GPIOR0 _SFR_IO8(0x1E)
196
#define EECR _SFR_IO8(0x1F)
204
#define EEDR _SFR_IO8(0x20)
214
#define EEARL _SFR_IO8(0x21)
224
#define EEARH _SFR_IO8(0x22)
230
#define GTCCR _SFR_IO8(0x23)
236
#define TCCR0A _SFR_IO8(0x24)
244
#define TCCR0B _SFR_IO8(0x25)
252
#define TCNT0 _SFR_IO8(0x26)
262
#define OCR0A _SFR_IO8(0x27)
272
#define OCR0B _SFR_IO8(0x28)
282
#define PLLCSR _SFR_IO8(0x29)
287
#define SPCR _SFR_IO8(0x2C)
297
#define SPSR _SFR_IO8(0x2D)
302
#define SPDR _SFR_IO8(0x2E)
312
#define ACSR _SFR_IO8(0x30)
321
#define SMCR _SFR_IO8(0x33)
327
#define MCUSR _SFR_IO8(0x34)
333
#define MCUCR _SFR_IO8(0x35)
339
#define SPMCSR _SFR_IO8(0x37)
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#define WDTCSR _SFR_MEM8(0x60)
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#define CLKPR _SFR_MEM8(0x61)
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#define PRR _SFR_MEM8(0x64)
375
#define OSCCAL _SFR_MEM8(0x66)
384
#define EICRA _SFR_MEM8(0x69)
392
#define TIMSK0 _SFR_MEM8(0x6E)
397
#define TIMSK1 _SFR_MEM8(0x6F)
403
#define AMP0CSR _SFR_MEM8(0x76)
405
#define AMP1CSR _SFR_MEM8(0x77)
407
#define ADCL _SFR_MEM8(0x78)
417
#define ADCSRA _SFR_MEM8(0x7A)
427
#define ADCSRB _SFR_MEM8(0x7B)
435
#define ADMUX _SFR_MEM8(0x7C)
444
#define DIDR0 _SFR_MEM8(0x7E)
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#define DIDR1 _SFR_MEM8(0x7F)
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#define TCCR1A _SFR_MEM8(0x80)
470
#define TCCR1B _SFR_MEM8(0x81)
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#define TCCR1C _SFR_MEM8(0x82)
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#define TCNT1 _SFR_MEM16(0x84)
485
#define TCNT1L _SFR_MEM8(0x84)
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#define TCNT1H _SFR_MEM8(0x85)
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#define ICR1 _SFR_MEM8(0x86)
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#define ICR1L _SFR_MEM8(0x86)
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#define ICR1H _SFR_MEM8(0x87)
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#define OCR1A _SFR_MEM16(0x88)
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#define OCR1AL _SFR_MEM8(0x88)
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#define OCR1AH _SFR_MEM8(0x89)
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#define OCR1B _SFR_MEM16(0x8A)
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#define OCR1BL _SFR_MEM8(0x8A)
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#define OCR1BH _SFR_MEM8(0x8B)
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#define PIFR0 _SFR_MEM8(0xA0)
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#define PIM0 _SFR_MEM8(0xA1)
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#define PIFR1 _SFR_MEM8(0xA2)
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#define PIM1 _SFR_MEM8(0xA3)
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#define PIFR2 _SFR_MEM8(0xA4)
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#define PIM2 _SFR_MEM8(0xA5)
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#define DACON _SFR_MEM8(0xAA)
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#define DAC _SFR_MEM16(0xAB)
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#define DACL _SFR_MEM8(0xAB)
628
#define DACH _SFR_MEM8(0xAC)
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#define AC0CON _SFR_MEM8(0xAD)
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#define AC1CON _SFR_MEM8(0xAE)
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#define AC2CON _SFR_MEM8(0xAF)
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#define UCSRA _SFR_MEM8(0xC0)
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#define UCSRB _SFR_MEM8(0xC1)
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#define UCSRC _SFR_MEM8(0xC2)
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#define UBRR _SFR_MEM16(0xC4)
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#define UBRRL _SFR_MEM8(0xC4)
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#define UBRRH _SFR_MEM8(0xC5)
713
#define UDR _SFR_MEM8(0xC6)
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#define EUCSRA _SFR_MEM8(0xC8)
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#define EUCSRB _SFR_MEM8(0xC9)
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#define EUCSRC _SFR_MEM8(0xCA)
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#define MUBRR _SFR_MEM16(0xCC)
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#define MUBRRL _SFR_MEM8(0xCC)
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#define MUBRRH _SFR_MEM8(0xCD)
767
#define EUDR _SFR_MEM8(0xCE)
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#define PSOC0 _SFR_MEM8(0xD0)
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#define OCR0SA _SFR_MEM16(0xD2)
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#define OCR0SAL _SFR_MEM8(0xD2)
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#define OCR0SAH _SFR_MEM8(0xD3)
801
#define OCR0RA _SFR_MEM16(0xD4)
803
#define OCR0RAL _SFR_MEM8(0xD4)
813
#define OCR0RAH _SFR_MEM8(0xD5)
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#define OCR0SB _SFR_MEM16(0xD6)
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#define OCR0SBL _SFR_MEM8(0xD6)
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#define OCR0SBH _SFR_MEM8(0xD7)
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#define OCR0RB _SFR_MEM16(0xD8)
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#define OCR0RBL _SFR_MEM8(0xD8)
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#define OCR0RBH _SFR_MEM8(0xD9)
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#define PCNF0 _SFR_MEM8(0xDA)
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#define PCTL0 _SFR_MEM8(0xDB)
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#define PFRC0A _SFR_MEM8(0xDC)
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#define PFRC0B _SFR_MEM8(0xDD)
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#define PICR0 _SFR_MEM16(0xDE)
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#define PICR0L _SFR_MEM8(0xDE)
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#define PICR0H _SFR_MEM8(0xDF)
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#define PSOC1 _SFR_MEM8(0xE0)
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#define OCR1SA _SFR_MEM16(0xE2)
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#define OCR1SAL _SFR_MEM8(0xE2)
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#define OCR1SAH _SFR_MEM8(0xE3)
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#define OCR1RA _SFR_MEM16(0xE4)
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#define OCR1RAL _SFR_MEM8(0xE4)
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#define OCR1RAH _SFR_MEM8(0xE5)
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#define OCR1SB _SFR_MEM16(0xE6)
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#define OCR1SBL _SFR_MEM8(0xE6)
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#define OCR1SBH _SFR_MEM8(0xE7)
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#define OCR1RB _SFR_MEM16(0xE8)
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#define OCR1RBL _SFR_MEM8(0xE8)
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#define OCR1RBH _SFR_MEM8(0xE9)
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#define PCNF1 _SFR_MEM8(0xEA)
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#define PCTL1 _SFR_MEM8(0xEB)
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#define PFRC1A _SFR_MEM8(0xEC)
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#define PFRC1B _SFR_MEM8(0xED)
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#define PICR1 _SFR_MEM16(0xEE)
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#define PICR1L _SFR_MEM8(0xEE)
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#define PICR1H _SFR_MEM8(0xEF)
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#define PSOC2 _SFR_MEM8(0xF0)
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#define POM2 _SFR_MEM8(0xF1)
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#define OCR2SA _SFR_MEM16(0xF2)
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#define OCR2SAL _SFR_MEM8(0xF2)
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#define OCR2SAH _SFR_MEM8(0xF3)
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#define OCR2RA _SFR_MEM16(0xF4)
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#define OCR2RAL _SFR_MEM8(0xF4)
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#define OCR2RA_4 4#define OCR2RA_5 5
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#define OCR2RAH _SFR_MEM8(0xF5)
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#define OCR2SB _SFR_MEM16(0xF6)
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#define OCR2SBL _SFR_MEM8(0xF6)
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#define OCR2SBH _SFR_MEM8(0xF7)
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#define OCR2RB _SFR_MEM16(0xF8)
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#define OCR2RBL _SFR_MEM8(0xF8)
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#define OCR2RBH _SFR_MEM8(0xF9)
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#define PCNF2 _SFR_MEM8(0xFA)
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#define PCTL2 _SFR_MEM8(0xFB)
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#define PFRC2A _SFR_MEM8(0xFC)
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#define PFRC2B _SFR_MEM8(0xFD)
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#define PICR2 _SFR_MEM16(0xFE)
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#define PICR2L _SFR_MEM8(0xFE)
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#define PICR2H _SFR_MEM8(0xFF)
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/* Interrupt Vectors */
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/* Interrupt vector 0 is the reset vector. */
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#define PSC2_CAPT_vect _VECTOR(1) /* PSC2 Capture Event */
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#define PSC2_EC_vect _VECTOR(2) /* PSC2 End Cycle */
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#define PSC1_CAPT_vect _VECTOR(3) /* PSC1 Capture Event */
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#define PSC1_EC_vect _VECTOR(4) /* PSC1 End Cycle */
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#define PSC0_CAPT_vect _VECTOR(5) /* PSC0 Capture Event */
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#define PSC0_EC_vect _VECTOR(6) /* PSC0 End Cycle */
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#define ANALOG_COMP_0_vect _VECTOR(7) /* Analog Comparator 0 */
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#define ANALOG_COMP_1_vect _VECTOR(8) /* Analog Comparator 1 */
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#define ANALOG_COMP_2_vect _VECTOR(9) /* Analog Comparator 2 */
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#define INT0_vect _VECTOR(10) /* External Interrupt Request 0 */
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#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */
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#define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */
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#define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter Compare Match B */
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/* Vector 14, Reserved */
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#define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */
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#define TIMER0_COMP A_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */
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#define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */
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#define ADC_vect _VECTOR(18) /* ADC Conversion Complete */
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#define INT1_vect _VECTOR(19) /* External Interrupt Request 1 */
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#define SPI_STC_vect _VECTOR(20) /* SPI Serial Transfer Complete */
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#define USART_RX_vect _VECTOR(21) /* USART, Rx Complete */
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#define USART_UDRE_vect _VECTOR(22) /* USART Data Register Empty */
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#define USART_TX_vect _VECTOR(23) /* USART, Tx Complete */
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#define INT2_vect _VECTOR(24) /* External Interrupt Request 2 */
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#define WDT_vect _VECTOR(25) /* Watchdog Timeout Interrupt */
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#define EE_READY_vect _VECTOR(26) /* EEPROM Ready */
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#define TIMER0_COMPB_vect _VECTOR(27) /* Timer Counter 0 Compare Match B */
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#define INT3_vect _VECTOR(28) /* External Interrupt Request 3 */
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/* Vector 29, Reserved */
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/* Vector 30, Reserved */
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#define SPM_READY_vect _VECTOR(31) /* Store Program Memory Read */
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#define _VECTORS_SIZE 64
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#define RAMEND 0x1FF
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#define XRAMEND 0x00
1155
#define FLASHEND 0x1FFF
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#define SPM_PAGESIZE 32
1160
/* Fuse Information */
1162
#define FUSE_MEMORY_SIZE 3
1165
#define CKSEL0 ~_BV(0) /* Select Clock Source */
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#define CKSEL1 ~_BV(1) /* Select Clock Source */
1167
#define CKSEL2 ~_BV(2) /* Select Clock Source */
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#define CKSEL3 ~_BV(3) /* Select Clock Source */
1169
#define SUT0 ~_BV(4) /* Select start-up time */
1170
#define SUT1 ~_BV(5) /* Select start-up time */
1171
#define CKOUT ~_BV(6) /* Oscillator output option */
1172
#define CLKDIV8 ~_BV(7) /* Divide clock by 8 */
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#define LFUSE_DEFAULT (CKSEL1 & CKSEL2 & CKSEL3 & SUT0 & SUT1 & CKDIV8)
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/* High Fuse Byte */
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#define BODLEVEL0 ~_BV(0) /* Brown-out Detector trigger level */
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#define BODLEVEL1 ~_BV(1) /* Brown-out Detector trigger level */
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#define BODLEVEL2 ~_BV(2) /* Brown out detector trigger level */
1180
#define EESAVE ~_BV(3) /* EEPROM memory is preserved through chip erase */
1181
#define WDTON ~_BV(4) /* Watchdog timer always on */
1182
#define SPIEN ~_BV(5) /* Enable Serial programming and Data Downloading */
1183
#define DWEN ~_BV(6) /* debugWIRE Enable */
1184
#define RSTDISBL ~_BV(7) /* External Reset Disable */
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#define HFUSE_DEFAULT (SPIEN)
1188
/* Extended Fuse Byte */
1189
#define BOOTRST ~_BV(0) /* Select Reset Vector */
1190
#define BOOTSZ0 ~_BV(1) /* Select Boot Size */
1191
#define BOOTSZ1 ~_BV(2) /* Select Boot Size */
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#define PSCRV ~_BV(4) /* PSCOUT Reset Value */
1193
#define PSC0RB ~_BV(5) /* PSC0 Reset Behaviour */
1194
#define PSC1RB ~_BV(6) /* PSC1 Reset Behaviour */
1195
#define PSC2RB ~_BV(7) /* PSC2 Reset Behaviour */
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#define EFUSE_DEFAULT (BOOTSZ0 & BOOTSZ1)
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#endif /* _AVR_IO90PWM2B_H_ */
added
removed
include/avr/io90pwm2b.h
