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Viewing changes to soc/codecs/tscs42xx.h

  • Committer: Hui Wang
  • Date: 2018-06-07 01:04:04 UTC
  • Revision ID: git-v1:baf13208df10376d9e4588ad3524aeb3c9973bdf
sync the alsa hda driver from Takashi's tree

Signed-off-by: Hui Wang <hui.wang@canonical.com>

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soc/codecs/tscs42xx.h
 
1
// SPDX-License-Identifier: GPL-2.0
 
2
// tscs42xx.h -- TSCS42xx ALSA SoC Audio driver
 
3
// Copyright 2017 Tempo Semiconductor, Inc.
 
4
// Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com>
 
5
 
 
6
#ifndef __WOOKIE_H__
 
7
#define __WOOKIE_H__
 
8
 
 
9
enum {
 
10
        TSCS42XX_PLL_SRC_XTAL,
 
11
        TSCS42XX_PLL_SRC_MCLK1,
 
12
        TSCS42XX_PLL_SRC_MCLK2,
 
13
        TSCS42XX_PLL_SRC_CNT,
 
14
};
 
15
 
 
16
#define R_HPVOLL        0x0
 
17
#define R_HPVOLR        0x1
 
18
#define R_SPKVOLL       0x2
 
19
#define R_SPKVOLR       0x3
 
20
#define R_DACVOLL       0x4
 
21
#define R_DACVOLR       0x5
 
22
#define R_ADCVOLL       0x6
 
23
#define R_ADCVOLR       0x7
 
24
#define R_INVOLL        0x8
 
25
#define R_INVOLR        0x9
 
26
#define R_INMODE        0x0B
 
27
#define R_INSELL        0x0C
 
28
#define R_INSELR        0x0D
 
29
#define R_AIC1          0x13
 
30
#define R_AIC2          0x14
 
31
#define R_CNVRTR0       0x16
 
32
#define R_ADCSR         0x17
 
33
#define R_CNVRTR1       0x18
 
34
#define R_DACSR         0x19
 
35
#define R_PWRM1         0x1A
 
36
#define R_PWRM2         0x1B
 
37
#define R_CONFIG0       0x1F
 
38
#define R_CONFIG1       0x20
 
39
#define R_DMICCTL       0x24
 
40
#define R_CLECTL        0x25
 
41
#define R_MUGAIN        0x26
 
42
#define R_COMPTH        0x27
 
43
#define R_CMPRAT        0x28
 
44
#define R_CATKTCL       0x29
 
45
#define R_CATKTCH       0x2A
 
46
#define R_CRELTCL       0x2B
 
47
#define R_CRELTCH       0x2C
 
48
#define R_LIMTH         0x2D
 
49
#define R_LIMTGT        0x2E
 
50
#define R_LATKTCL       0x2F
 
51
#define R_LATKTCH       0x30
 
52
#define R_LRELTCL       0x31
 
53
#define R_LRELTCH       0x32
 
54
#define R_EXPTH         0x33
 
55
#define R_EXPRAT        0x34
 
56
#define R_XATKTCL       0x35
 
57
#define R_XATKTCH       0x36
 
58
#define R_XRELTCL       0x37
 
59
#define R_XRELTCH       0x38
 
60
#define R_FXCTL         0x39
 
61
#define R_DACCRWRL      0x3A
 
62
#define R_DACCRWRM      0x3B
 
63
#define R_DACCRWRH      0x3C
 
64
#define R_DACCRRDL      0x3D
 
65
#define R_DACCRRDM      0x3E
 
66
#define R_DACCRRDH      0x3F
 
67
#define R_DACCRADDR     0x40
 
68
#define R_DCOFSEL       0x41
 
69
#define R_PLLCTL9       0x4E
 
70
#define R_PLLCTLA       0x4F
 
71
#define R_PLLCTLB       0x50
 
72
#define R_PLLCTLC       0x51
 
73
#define R_PLLCTLD       0x52
 
74
#define R_PLLCTLE       0x53
 
75
#define R_PLLCTLF       0x54
 
76
#define R_PLLCTL10      0x55
 
77
#define R_PLLCTL11      0x56
 
78
#define R_PLLCTL12      0x57
 
79
#define R_PLLCTL1B      0x60
 
80
#define R_PLLCTL1C      0x61
 
81
#define R_TIMEBASE      0x77
 
82
#define R_DEVIDL        0x7D
 
83
#define R_DEVIDH        0x7E
 
84
#define R_RESET         0x80
 
85
#define R_DACCRSTAT     0x8A
 
86
#define R_PLLCTL0       0x8E
 
87
#define R_PLLREFSEL     0x8F
 
88
#define R_DACMBCEN      0xC7
 
89
#define R_DACMBCCTL     0xC8
 
90
#define R_DACMBCMUG1    0xC9
 
91
#define R_DACMBCTHR1    0xCA
 
92
#define R_DACMBCRAT1    0xCB
 
93
#define R_DACMBCATK1L   0xCC
 
94
#define R_DACMBCATK1H   0xCD
 
95
#define R_DACMBCREL1L   0xCE
 
96
#define R_DACMBCREL1H   0xCF
 
97
#define R_DACMBCMUG2    0xD0
 
98
#define R_DACMBCTHR2    0xD1
 
99
#define R_DACMBCRAT2    0xD2
 
100
#define R_DACMBCATK2L   0xD3
 
101
#define R_DACMBCATK2H   0xD4
 
102
#define R_DACMBCREL2L   0xD5
 
103
#define R_DACMBCREL2H   0xD6
 
104
#define R_DACMBCMUG3    0xD7
 
105
#define R_DACMBCTHR3    0xD8
 
106
#define R_DACMBCRAT3    0xD9
 
107
#define R_DACMBCATK3L   0xDA
 
108
#define R_DACMBCATK3H   0xDB
 
109
#define R_DACMBCREL3L   0xDC
 
110
#define R_DACMBCREL3H   0xDD
 
111
 
 
112
/* Helpers */
 
113
#define RM(m, b) ((m)<<(b))
 
114
#define RV(v, b) ((v)<<(b))
 
115
 
 
116
/****************************
 
117
 *      R_HPVOLL (0x0)      *
 
118
 ****************************/
 
119
 
 
120
/* Field Offsets */
 
121
#define FB_HPVOLL                            0
 
122
 
 
123
/* Field Masks */
 
124
#define FM_HPVOLL                            0X7F
 
125
 
 
126
/* Field Values */
 
127
#define FV_HPVOLL_P6DB                       0x7F
 
128
#define FV_HPVOLL_N88PT5DB                   0x1
 
129
#define FV_HPVOLL_MUTE                       0x0
 
130
 
 
131
/* Register Masks */
 
132
#define RM_HPVOLL                            RM(FM_HPVOLL, FB_HPVOLL)
 
133
 
 
134
/* Register Values */
 
135
#define RV_HPVOLL_P6DB                       RV(FV_HPVOLL_P6DB, FB_HPVOLL)
 
136
#define RV_HPVOLL_N88PT5DB                   RV(FV_HPVOLL_N88PT5DB, FB_HPVOLL)
 
137
#define RV_HPVOLL_MUTE                       RV(FV_HPVOLL_MUTE, FB_HPVOLL)
 
138
 
 
139
/****************************
 
140
 *      R_HPVOLR (0x1)      *
 
141
 ****************************/
 
142
 
 
143
/* Field Offsets */
 
144
#define FB_HPVOLR                            0
 
145
 
 
146
/* Field Masks */
 
147
#define FM_HPVOLR                            0X7F
 
148
 
 
149
/* Field Values */
 
150
#define FV_HPVOLR_P6DB                       0x7F
 
151
#define FV_HPVOLR_N88PT5DB                   0x1
 
152
#define FV_HPVOLR_MUTE                       0x0
 
153
 
 
154
/* Register Masks */
 
155
#define RM_HPVOLR                            RM(FM_HPVOLR, FB_HPVOLR)
 
156
 
 
157
/* Register Values */
 
158
#define RV_HPVOLR_P6DB                       RV(FV_HPVOLR_P6DB, FB_HPVOLR)
 
159
#define RV_HPVOLR_N88PT5DB                   RV(FV_HPVOLR_N88PT5DB, FB_HPVOLR)
 
160
#define RV_HPVOLR_MUTE                       RV(FV_HPVOLR_MUTE, FB_HPVOLR)
 
161
 
 
162
/*****************************
 
163
 *      R_SPKVOLL (0x2)      *
 
164
 *****************************/
 
165
 
 
166
/* Field Offsets */
 
167
#define FB_SPKVOLL                           0
 
168
 
 
169
/* Field Masks */
 
170
#define FM_SPKVOLL                           0X7F
 
171
 
 
172
/* Field Values */
 
173
#define FV_SPKVOLL_P12DB                     0x7F
 
174
#define FV_SPKVOLL_N77PT25DB                 0x8
 
175
#define FV_SPKVOLL_MUTE                      0x0
 
176
 
 
177
/* Register Masks */
 
178
#define RM_SPKVOLL                           RM(FM_SPKVOLL, FB_SPKVOLL)
 
179
 
 
180
/* Register Values */
 
181
#define RV_SPKVOLL_P12DB                     RV(FV_SPKVOLL_P12DB, FB_SPKVOLL)
 
182
#define RV_SPKVOLL_N77PT25DB \
 
183
         RV(FV_SPKVOLL_N77PT25DB, FB_SPKVOLL)
 
184
 
 
185
#define RV_SPKVOLL_MUTE                      RV(FV_SPKVOLL_MUTE, FB_SPKVOLL)
 
186
 
 
187
/*****************************
 
188
 *      R_SPKVOLR (0x3)      *
 
189
 *****************************/
 
190
 
 
191
/* Field Offsets */
 
192
#define FB_SPKVOLR                           0
 
193
 
 
194
/* Field Masks */
 
195
#define FM_SPKVOLR                           0X7F
 
196
 
 
197
/* Field Values */
 
198
#define FV_SPKVOLR_P12DB                     0x7F
 
199
#define FV_SPKVOLR_N77PT25DB                 0x8
 
200
#define FV_SPKVOLR_MUTE                      0x0
 
201
 
 
202
/* Register Masks */
 
203
#define RM_SPKVOLR                           RM(FM_SPKVOLR, FB_SPKVOLR)
 
204
 
 
205
/* Register Values */
 
206
#define RV_SPKVOLR_P12DB                     RV(FV_SPKVOLR_P12DB, FB_SPKVOLR)
 
207
#define RV_SPKVOLR_N77PT25DB \
 
208
         RV(FV_SPKVOLR_N77PT25DB, FB_SPKVOLR)
 
209
 
 
210
#define RV_SPKVOLR_MUTE                      RV(FV_SPKVOLR_MUTE, FB_SPKVOLR)
 
211
 
 
212
/*****************************
 
213
 *      R_DACVOLL (0x4)      *
 
214
 *****************************/
 
215
 
 
216
/* Field Offsets */
 
217
#define FB_DACVOLL                           0
 
218
 
 
219
/* Field Masks */
 
220
#define FM_DACVOLL                           0XFF
 
221
 
 
222
/* Field Values */
 
223
#define FV_DACVOLL_0DB                       0xFF
 
224
#define FV_DACVOLL_N95PT625DB                0x1
 
225
#define FV_DACVOLL_MUTE                      0x0
 
226
 
 
227
/* Register Masks */
 
228
#define RM_DACVOLL                           RM(FM_DACVOLL, FB_DACVOLL)
 
229
 
 
230
/* Register Values */
 
231
#define RV_DACVOLL_0DB                       RV(FV_DACVOLL_0DB, FB_DACVOLL)
 
232
#define RV_DACVOLL_N95PT625DB \
 
233
         RV(FV_DACVOLL_N95PT625DB, FB_DACVOLL)
 
234
 
 
235
#define RV_DACVOLL_MUTE                      RV(FV_DACVOLL_MUTE, FB_DACVOLL)
 
236
 
 
237
/*****************************
 
238
 *      R_DACVOLR (0x5)      *
 
239
 *****************************/
 
240
 
 
241
/* Field Offsets */
 
242
#define FB_DACVOLR                           0
 
243
 
 
244
/* Field Masks */
 
245
#define FM_DACVOLR                           0XFF
 
246
 
 
247
/* Field Values */
 
248
#define FV_DACVOLR_0DB                       0xFF
 
249
#define FV_DACVOLR_N95PT625DB                0x1
 
250
#define FV_DACVOLR_MUTE                      0x0
 
251
 
 
252
/* Register Masks */
 
253
#define RM_DACVOLR                           RM(FM_DACVOLR, FB_DACVOLR)
 
254
 
 
255
/* Register Values */
 
256
#define RV_DACVOLR_0DB                       RV(FV_DACVOLR_0DB, FB_DACVOLR)
 
257
#define RV_DACVOLR_N95PT625DB \
 
258
         RV(FV_DACVOLR_N95PT625DB, FB_DACVOLR)
 
259
 
 
260
#define RV_DACVOLR_MUTE                      RV(FV_DACVOLR_MUTE, FB_DACVOLR)
 
261
 
 
262
/*****************************
 
263
 *      R_ADCVOLL (0x6)      *
 
264
 *****************************/
 
265
 
 
266
/* Field Offsets */
 
267
#define FB_ADCVOLL                           0
 
268
 
 
269
/* Field Masks */
 
270
#define FM_ADCVOLL                           0XFF
 
271
 
 
272
/* Field Values */
 
273
#define FV_ADCVOLL_P24DB                     0xFF
 
274
#define FV_ADCVOLL_N71PT25DB                 0x1
 
275
#define FV_ADCVOLL_MUTE                      0x0
 
276
 
 
277
/* Register Masks */
 
278
#define RM_ADCVOLL                           RM(FM_ADCVOLL, FB_ADCVOLL)
 
279
 
 
280
/* Register Values */
 
281
#define RV_ADCVOLL_P24DB                     RV(FV_ADCVOLL_P24DB, FB_ADCVOLL)
 
282
#define RV_ADCVOLL_N71PT25DB \
 
283
         RV(FV_ADCVOLL_N71PT25DB, FB_ADCVOLL)
 
284
 
 
285
#define RV_ADCVOLL_MUTE                      RV(FV_ADCVOLL_MUTE, FB_ADCVOLL)
 
286
 
 
287
/*****************************
 
288
 *      R_ADCVOLR (0x7)      *
 
289
 *****************************/
 
290
 
 
291
/* Field Offsets */
 
292
#define FB_ADCVOLR                           0
 
293
 
 
294
/* Field Masks */
 
295
#define FM_ADCVOLR                           0XFF
 
296
 
 
297
/* Field Values */
 
298
#define FV_ADCVOLR_P24DB                     0xFF
 
299
#define FV_ADCVOLR_N71PT25DB                 0x1
 
300
#define FV_ADCVOLR_MUTE                      0x0
 
301
 
 
302
/* Register Masks */
 
303
#define RM_ADCVOLR                           RM(FM_ADCVOLR, FB_ADCVOLR)
 
304
 
 
305
/* Register Values */
 
306
#define RV_ADCVOLR_P24DB                     RV(FV_ADCVOLR_P24DB, FB_ADCVOLR)
 
307
#define RV_ADCVOLR_N71PT25DB \
 
308
         RV(FV_ADCVOLR_N71PT25DB, FB_ADCVOLR)
 
309
 
 
310
#define RV_ADCVOLR_MUTE                      RV(FV_ADCVOLR_MUTE, FB_ADCVOLR)
 
311
 
 
312
/****************************
 
313
 *      R_INVOLL (0x8)      *
 
314
 ****************************/
 
315
 
 
316
/* Field Offsets */
 
317
#define FB_INVOLL_INMUTEL                    7
 
318
#define FB_INVOLL_IZCL                       6
 
319
#define FB_INVOLL                            0
 
320
 
 
321
/* Field Masks */
 
322
#define FM_INVOLL_INMUTEL                    0X1
 
323
#define FM_INVOLL_IZCL                       0X1
 
324
#define FM_INVOLL                            0X3F
 
325
 
 
326
/* Field Values */
 
327
#define FV_INVOLL_INMUTEL_ENABLE             0x1
 
328
#define FV_INVOLL_INMUTEL_DISABLE            0x0
 
329
#define FV_INVOLL_IZCL_ENABLE                0x1
 
330
#define FV_INVOLL_IZCL_DISABLE               0x0
 
331
#define FV_INVOLL_P30DB                      0x3F
 
332
#define FV_INVOLL_N17PT25DB                  0x0
 
333
 
 
334
/* Register Masks */
 
335
#define RM_INVOLL_INMUTEL \
 
336
         RM(FM_INVOLL_INMUTEL, FB_INVOLL_INMUTEL)
 
337
 
 
338
#define RM_INVOLL_IZCL                       RM(FM_INVOLL_IZCL, FB_INVOLL_IZCL)
 
339
#define RM_INVOLL                            RM(FM_INVOLL, FB_INVOLL)
 
340
 
 
341
/* Register Values */
 
342
#define RV_INVOLL_INMUTEL_ENABLE \
 
343
         RV(FV_INVOLL_INMUTEL_ENABLE, FB_INVOLL_INMUTEL)
 
344
 
 
345
#define RV_INVOLL_INMUTEL_DISABLE \
 
346
         RV(FV_INVOLL_INMUTEL_DISABLE, FB_INVOLL_INMUTEL)
 
347
 
 
348
#define RV_INVOLL_IZCL_ENABLE \
 
349
         RV(FV_INVOLL_IZCL_ENABLE, FB_INVOLL_IZCL)
 
350
 
 
351
#define RV_INVOLL_IZCL_DISABLE \
 
352
         RV(FV_INVOLL_IZCL_DISABLE, FB_INVOLL_IZCL)
 
353
 
 
354
#define RV_INVOLL_P30DB                      RV(FV_INVOLL_P30DB, FB_INVOLL)
 
355
#define RV_INVOLL_N17PT25DB                  RV(FV_INVOLL_N17PT25DB, FB_INVOLL)
 
356
 
 
357
/****************************
 
358
 *      R_INVOLR (0x9)      *
 
359
 ****************************/
 
360
 
 
361
/* Field Offsets */
 
362
#define FB_INVOLR_INMUTER                    7
 
363
#define FB_INVOLR_IZCR                       6
 
364
#define FB_INVOLR                            0
 
365
 
 
366
/* Field Masks */
 
367
#define FM_INVOLR_INMUTER                    0X1
 
368
#define FM_INVOLR_IZCR                       0X1
 
369
#define FM_INVOLR                            0X3F
 
370
 
 
371
/* Field Values */
 
372
#define FV_INVOLR_INMUTER_ENABLE             0x1
 
373
#define FV_INVOLR_INMUTER_DISABLE            0x0
 
374
#define FV_INVOLR_IZCR_ENABLE                0x1
 
375
#define FV_INVOLR_IZCR_DISABLE               0x0
 
376
#define FV_INVOLR_P30DB                      0x3F
 
377
#define FV_INVOLR_N17PT25DB                  0x0
 
378
 
 
379
/* Register Masks */
 
380
#define RM_INVOLR_INMUTER \
 
381
         RM(FM_INVOLR_INMUTER, FB_INVOLR_INMUTER)
 
382
 
 
383
#define RM_INVOLR_IZCR                       RM(FM_INVOLR_IZCR, FB_INVOLR_IZCR)
 
384
#define RM_INVOLR                            RM(FM_INVOLR, FB_INVOLR)
 
385
 
 
386
/* Register Values */
 
387
#define RV_INVOLR_INMUTER_ENABLE \
 
388
         RV(FV_INVOLR_INMUTER_ENABLE, FB_INVOLR_INMUTER)
 
389
 
 
390
#define RV_INVOLR_INMUTER_DISABLE \
 
391
         RV(FV_INVOLR_INMUTER_DISABLE, FB_INVOLR_INMUTER)
 
392
 
 
393
#define RV_INVOLR_IZCR_ENABLE \
 
394
         RV(FV_INVOLR_IZCR_ENABLE, FB_INVOLR_IZCR)
 
395
 
 
396
#define RV_INVOLR_IZCR_DISABLE \
 
397
         RV(FV_INVOLR_IZCR_DISABLE, FB_INVOLR_IZCR)
 
398
 
 
399
#define RV_INVOLR_P30DB                      RV(FV_INVOLR_P30DB, FB_INVOLR)
 
400
#define RV_INVOLR_N17PT25DB                  RV(FV_INVOLR_N17PT25DB, FB_INVOLR)
 
401
 
 
402
/*****************************
 
403
 *      R_INMODE (0x0B)      *
 
404
 *****************************/
 
405
 
 
406
/* Field Offsets */
 
407
#define FB_INMODE_DS                         0
 
408
 
 
409
/* Field Masks */
 
410
#define FM_INMODE_DS                         0X1
 
411
 
 
412
/* Field Values */
 
413
#define FV_INMODE_DS_LRIN1                   0x0
 
414
#define FV_INMODE_DS_LRIN2                   0x1
 
415
 
 
416
/* Register Masks */
 
417
#define RM_INMODE_DS                         RM(FM_INMODE_DS, FB_INMODE_DS)
 
418
 
 
419
/* Register Values */
 
420
#define RV_INMODE_DS_LRIN1 \
 
421
         RV(FV_INMODE_DS_LRIN1, FB_INMODE_DS)
 
422
 
 
423
#define RV_INMODE_DS_LRIN2 \
 
424
         RV(FV_INMODE_DS_LRIN2, FB_INMODE_DS)
 
425
 
 
426
 
 
427
/*****************************
 
428
 *      R_INSELL (0x0C)      *
 
429
 *****************************/
 
430
 
 
431
/* Field Offsets */
 
432
#define FB_INSELL                            6
 
433
#define FB_INSELL_MICBSTL                    4
 
434
 
 
435
/* Field Masks */
 
436
#define FM_INSELL                            0X3
 
437
#define FM_INSELL_MICBSTL                    0X3
 
438
 
 
439
/* Field Values */
 
440
#define FV_INSELL_IN1                        0x0
 
441
#define FV_INSELL_IN2                        0x1
 
442
#define FV_INSELL_IN3                        0x2
 
443
#define FV_INSELL_D2S                        0x3
 
444
#define FV_INSELL_MICBSTL_OFF                0x0
 
445
#define FV_INSELL_MICBSTL_10DB               0x1
 
446
#define FV_INSELL_MICBSTL_20DB               0x2
 
447
#define FV_INSELL_MICBSTL_30DB               0x3
 
448
 
 
449
/* Register Masks */
 
450
#define RM_INSELL                            RM(FM_INSELL, FB_INSELL)
 
451
#define RM_INSELL_MICBSTL \
 
452
         RM(FM_INSELL_MICBSTL, FB_INSELL_MICBSTL)
 
453
 
 
454
 
 
455
/* Register Values */
 
456
#define RV_INSELL_IN1                        RV(FV_INSELL_IN1, FB_INSELL)
 
457
#define RV_INSELL_IN2                        RV(FV_INSELL_IN2, FB_INSELL)
 
458
#define RV_INSELL_IN3                        RV(FV_INSELL_IN3, FB_INSELL)
 
459
#define RV_INSELL_D2S                        RV(FV_INSELL_D2S, FB_INSELL)
 
460
#define RV_INSELL_MICBSTL_OFF \
 
461
         RV(FV_INSELL_MICBSTL_OFF, FB_INSELL_MICBSTL)
 
462
 
 
463
#define RV_INSELL_MICBSTL_10DB \
 
464
         RV(FV_INSELL_MICBSTL_10DB, FB_INSELL_MICBSTL)
 
465
 
 
466
#define RV_INSELL_MICBSTL_20DB \
 
467
         RV(FV_INSELL_MICBSTL_20DB, FB_INSELL_MICBSTL)
 
468
 
 
469
#define RV_INSELL_MICBSTL_30DB \
 
470
         RV(FV_INSELL_MICBSTL_30DB, FB_INSELL_MICBSTL)
 
471
 
 
472
 
 
473
/*****************************
 
474
 *      R_INSELR (0x0D)      *
 
475
 *****************************/
 
476
 
 
477
/* Field Offsets */
 
478
#define FB_INSELR                            6
 
479
#define FB_INSELR_MICBSTR                    4
 
480
 
 
481
/* Field Masks */
 
482
#define FM_INSELR                            0X3
 
483
#define FM_INSELR_MICBSTR                    0X3
 
484
 
 
485
/* Field Values */
 
486
#define FV_INSELR_IN1                        0x0
 
487
#define FV_INSELR_IN2                        0x1
 
488
#define FV_INSELR_IN3                        0x2
 
489
#define FV_INSELR_D2S                        0x3
 
490
#define FV_INSELR_MICBSTR_OFF                0x0
 
491
#define FV_INSELR_MICBSTR_10DB               0x1
 
492
#define FV_INSELR_MICBSTR_20DB               0x2
 
493
#define FV_INSELR_MICBSTR_30DB               0x3
 
494
 
 
495
/* Register Masks */
 
496
#define RM_INSELR                            RM(FM_INSELR, FB_INSELR)
 
497
#define RM_INSELR_MICBSTR \
 
498
         RM(FM_INSELR_MICBSTR, FB_INSELR_MICBSTR)
 
499
 
 
500
 
 
501
/* Register Values */
 
502
#define RV_INSELR_IN1                        RV(FV_INSELR_IN1, FB_INSELR)
 
503
#define RV_INSELR_IN2                        RV(FV_INSELR_IN2, FB_INSELR)
 
504
#define RV_INSELR_IN3                        RV(FV_INSELR_IN3, FB_INSELR)
 
505
#define RV_INSELR_D2S                        RV(FV_INSELR_D2S, FB_INSELR)
 
506
#define RV_INSELR_MICBSTR_OFF \
 
507
         RV(FV_INSELR_MICBSTR_OFF, FB_INSELR_MICBSTR)
 
508
 
 
509
#define RV_INSELR_MICBSTR_10DB \
 
510
         RV(FV_INSELR_MICBSTR_10DB, FB_INSELR_MICBSTR)
 
511
 
 
512
#define RV_INSELR_MICBSTR_20DB \
 
513
         RV(FV_INSELR_MICBSTR_20DB, FB_INSELR_MICBSTR)
 
514
 
 
515
#define RV_INSELR_MICBSTR_30DB \
 
516
         RV(FV_INSELR_MICBSTR_30DB, FB_INSELR_MICBSTR)
 
517
 
 
518
 
 
519
/***************************
 
520
 *      R_AIC1 (0x13)      *
 
521
 ***************************/
 
522
 
 
523
/* Field Offsets */
 
524
#define FB_AIC1_BCLKINV                      6
 
525
#define FB_AIC1_MS                           5
 
526
#define FB_AIC1_LRP                          4
 
527
#define FB_AIC1_WL                           2
 
528
#define FB_AIC1_FORMAT                       0
 
529
 
 
530
/* Field Masks */
 
531
#define FM_AIC1_BCLKINV                      0X1
 
532
#define FM_AIC1_MS                           0X1
 
533
#define FM_AIC1_LRP                          0X1
 
534
#define FM_AIC1_WL                           0X3
 
535
#define FM_AIC1_FORMAT                       0X3
 
536
 
 
537
/* Field Values */
 
538
#define FV_AIC1_BCLKINV_ENABLE               0x1
 
539
#define FV_AIC1_BCLKINV_DISABLE              0x0
 
540
#define FV_AIC1_MS_MASTER                    0x1
 
541
#define FV_AIC1_MS_SLAVE                     0x0
 
542
#define FV_AIC1_LRP_INVERT                   0x1
 
543
#define FV_AIC1_LRP_NORMAL                   0x0
 
544
#define FV_AIC1_WL_16                        0x0
 
545
#define FV_AIC1_WL_20                        0x1
 
546
#define FV_AIC1_WL_24                        0x2
 
547
#define FV_AIC1_WL_32                        0x3
 
548
#define FV_AIC1_FORMAT_RIGHT                 0x0
 
549
#define FV_AIC1_FORMAT_LEFT                  0x1
 
550
#define FV_AIC1_FORMAT_I2S                   0x2
 
551
 
 
552
/* Register Masks */
 
553
#define RM_AIC1_BCLKINV \
 
554
         RM(FM_AIC1_BCLKINV, FB_AIC1_BCLKINV)
 
555
 
 
556
#define RM_AIC1_MS                           RM(FM_AIC1_MS, FB_AIC1_MS)
 
557
#define RM_AIC1_LRP                          RM(FM_AIC1_LRP, FB_AIC1_LRP)
 
558
#define RM_AIC1_WL                           RM(FM_AIC1_WL, FB_AIC1_WL)
 
559
#define RM_AIC1_FORMAT                       RM(FM_AIC1_FORMAT, FB_AIC1_FORMAT)
 
560
 
 
561
/* Register Values */
 
562
#define RV_AIC1_BCLKINV_ENABLE \
 
563
         RV(FV_AIC1_BCLKINV_ENABLE, FB_AIC1_BCLKINV)
 
564
 
 
565
#define RV_AIC1_BCLKINV_DISABLE \
 
566
         RV(FV_AIC1_BCLKINV_DISABLE, FB_AIC1_BCLKINV)
 
567
 
 
568
#define RV_AIC1_MS_MASTER                    RV(FV_AIC1_MS_MASTER, FB_AIC1_MS)
 
569
#define RV_AIC1_MS_SLAVE                     RV(FV_AIC1_MS_SLAVE, FB_AIC1_MS)
 
570
#define RV_AIC1_LRP_INVERT \
 
571
         RV(FV_AIC1_LRP_INVERT, FB_AIC1_LRP)
 
572
 
 
573
#define RV_AIC1_LRP_NORMAL \
 
574
         RV(FV_AIC1_LRP_NORMAL, FB_AIC1_LRP)
 
575
 
 
576
#define RV_AIC1_WL_16                        RV(FV_AIC1_WL_16, FB_AIC1_WL)
 
577
#define RV_AIC1_WL_20                        RV(FV_AIC1_WL_20, FB_AIC1_WL)
 
578
#define RV_AIC1_WL_24                        RV(FV_AIC1_WL_24, FB_AIC1_WL)
 
579
#define RV_AIC1_WL_32                        RV(FV_AIC1_WL_32, FB_AIC1_WL)
 
580
#define RV_AIC1_FORMAT_RIGHT \
 
581
         RV(FV_AIC1_FORMAT_RIGHT, FB_AIC1_FORMAT)
 
582
 
 
583
#define RV_AIC1_FORMAT_LEFT \
 
584
         RV(FV_AIC1_FORMAT_LEFT, FB_AIC1_FORMAT)
 
585
 
 
586
#define RV_AIC1_FORMAT_I2S \
 
587
         RV(FV_AIC1_FORMAT_I2S, FB_AIC1_FORMAT)
 
588
 
 
589
 
 
590
/***************************
 
591
 *      R_AIC2 (0x14)      *
 
592
 ***************************/
 
593
 
 
594
/* Field Offsets */
 
595
#define FB_AIC2_DACDSEL                      6
 
596
#define FB_AIC2_ADCDSEL                      4
 
597
#define FB_AIC2_TRI                          3
 
598
#define FB_AIC2_BLRCM                        0
 
599
 
 
600
/* Field Masks */
 
601
#define FM_AIC2_DACDSEL                      0X3
 
602
#define FM_AIC2_ADCDSEL                      0X3
 
603
#define FM_AIC2_TRI                          0X1
 
604
#define FM_AIC2_BLRCM                        0X7
 
605
 
 
606
/* Field Values */
 
607
#define FV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED  0x3
 
608
 
 
609
/* Register Masks */
 
610
#define RM_AIC2_DACDSEL \
 
611
         RM(FM_AIC2_DACDSEL, FB_AIC2_DACDSEL)
 
612
 
 
613
#define RM_AIC2_ADCDSEL \
 
614
         RM(FM_AIC2_ADCDSEL, FB_AIC2_ADCDSEL)
 
615
 
 
616
#define RM_AIC2_TRI                          RM(FM_AIC2_TRI, FB_AIC2_TRI)
 
617
#define RM_AIC2_BLRCM                        RM(FM_AIC2_BLRCM, FB_AIC2_BLRCM)
 
618
 
 
619
/* Register Values */
 
620
#define RV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED \
 
621
         RV(FV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED, FB_AIC2_BLRCM)
 
622
 
 
623
 
 
624
/******************************
 
625
 *      R_CNVRTR0 (0x16)      *
 
626
 ******************************/
 
627
 
 
628
/* Field Offsets */
 
629
#define FB_CNVRTR0_ADCPOLR                   7
 
630
#define FB_CNVRTR0_ADCPOLL                   6
 
631
#define FB_CNVRTR0_AMONOMIX                  4
 
632
#define FB_CNVRTR0_ADCMU                     3
 
633
#define FB_CNVRTR0_HPOR                      2
 
634
#define FB_CNVRTR0_ADCHPDR                   1
 
635
#define FB_CNVRTR0_ADCHPDL                   0
 
636
 
 
637
/* Field Masks */
 
638
#define FM_CNVRTR0_ADCPOLR                   0X1
 
639
#define FM_CNVRTR0_ADCPOLL                   0X1
 
640
#define FM_CNVRTR0_AMONOMIX                  0X3
 
641
#define FM_CNVRTR0_ADCMU                     0X1
 
642
#define FM_CNVRTR0_HPOR                      0X1
 
643
#define FM_CNVRTR0_ADCHPDR                   0X1
 
644
#define FM_CNVRTR0_ADCHPDL                   0X1
 
645
 
 
646
/* Field Values */
 
647
#define FV_CNVRTR0_ADCPOLR_INVERT            0x1
 
648
#define FV_CNVRTR0_ADCPOLR_NORMAL            0x0
 
649
#define FV_CNVRTR0_ADCPOLL_INVERT            0x1
 
650
#define FV_CNVRTR0_ADCPOLL_NORMAL            0x0
 
651
#define FV_CNVRTR0_ADCMU_ENABLE              0x1
 
652
#define FV_CNVRTR0_ADCMU_DISABLE             0x0
 
653
#define FV_CNVRTR0_ADCHPDR_ENABLE            0x1
 
654
#define FV_CNVRTR0_ADCHPDR_DISABLE           0x0
 
655
#define FV_CNVRTR0_ADCHPDL_ENABLE            0x1
 
656
#define FV_CNVRTR0_ADCHPDL_DISABLE           0x0
 
657
 
 
658
/* Register Masks */
 
659
#define RM_CNVRTR0_ADCPOLR \
 
660
         RM(FM_CNVRTR0_ADCPOLR, FB_CNVRTR0_ADCPOLR)
 
661
 
 
662
#define RM_CNVRTR0_ADCPOLL \
 
663
         RM(FM_CNVRTR0_ADCPOLL, FB_CNVRTR0_ADCPOLL)
 
664
 
 
665
#define RM_CNVRTR0_AMONOMIX \
 
666
         RM(FM_CNVRTR0_AMONOMIX, FB_CNVRTR0_AMONOMIX)
 
667
 
 
668
#define RM_CNVRTR0_ADCMU \
 
669
         RM(FM_CNVRTR0_ADCMU, FB_CNVRTR0_ADCMU)
 
670
 
 
671
#define RM_CNVRTR0_HPOR \
 
672
         RM(FM_CNVRTR0_HPOR, FB_CNVRTR0_HPOR)
 
673
 
 
674
#define RM_CNVRTR0_ADCHPDR \
 
675
         RM(FM_CNVRTR0_ADCHPDR, FB_CNVRTR0_ADCHPDR)
 
676
 
 
677
#define RM_CNVRTR0_ADCHPDL \
 
678
         RM(FM_CNVRTR0_ADCHPDL, FB_CNVRTR0_ADCHPDL)
 
679
 
 
680
 
 
681
/* Register Values */
 
682
#define RV_CNVRTR0_ADCPOLR_INVERT \
 
683
         RV(FV_CNVRTR0_ADCPOLR_INVERT, FB_CNVRTR0_ADCPOLR)
 
684
 
 
685
#define RV_CNVRTR0_ADCPOLR_NORMAL \
 
686
         RV(FV_CNVRTR0_ADCPOLR_NORMAL, FB_CNVRTR0_ADCPOLR)
 
687
 
 
688
#define RV_CNVRTR0_ADCPOLL_INVERT \
 
689
         RV(FV_CNVRTR0_ADCPOLL_INVERT, FB_CNVRTR0_ADCPOLL)
 
690
 
 
691
#define RV_CNVRTR0_ADCPOLL_NORMAL \
 
692
         RV(FV_CNVRTR0_ADCPOLL_NORMAL, FB_CNVRTR0_ADCPOLL)
 
693
 
 
694
#define RV_CNVRTR0_ADCMU_ENABLE \
 
695
         RV(FV_CNVRTR0_ADCMU_ENABLE, FB_CNVRTR0_ADCMU)
 
696
 
 
697
#define RV_CNVRTR0_ADCMU_DISABLE \
 
698
         RV(FV_CNVRTR0_ADCMU_DISABLE, FB_CNVRTR0_ADCMU)
 
699
 
 
700
#define RV_CNVRTR0_ADCHPDR_ENABLE \
 
701
         RV(FV_CNVRTR0_ADCHPDR_ENABLE, FB_CNVRTR0_ADCHPDR)
 
702
 
 
703
#define RV_CNVRTR0_ADCHPDR_DISABLE \
 
704
         RV(FV_CNVRTR0_ADCHPDR_DISABLE, FB_CNVRTR0_ADCHPDR)
 
705
 
 
706
#define RV_CNVRTR0_ADCHPDL_ENABLE \
 
707
         RV(FV_CNVRTR0_ADCHPDL_ENABLE, FB_CNVRTR0_ADCHPDL)
 
708
 
 
709
#define RV_CNVRTR0_ADCHPDL_DISABLE \
 
710
         RV(FV_CNVRTR0_ADCHPDL_DISABLE, FB_CNVRTR0_ADCHPDL)
 
711
 
 
712
 
 
713
/****************************
 
714
 *      R_ADCSR (0x17)      *
 
715
 ****************************/
 
716
 
 
717
/* Field Offsets */
 
718
#define FB_ADCSR_ABCM                        6
 
719
#define FB_ADCSR_ABR                         3
 
720
#define FB_ADCSR_ABM                         0
 
721
 
 
722
/* Field Masks */
 
723
#define FM_ADCSR_ABCM                        0X3
 
724
#define FM_ADCSR_ABR                         0X3
 
725
#define FM_ADCSR_ABM                         0X7
 
726
 
 
727
/* Field Values */
 
728
#define FV_ADCSR_ABCM_AUTO                   0x0
 
729
#define FV_ADCSR_ABCM_32                     0x1
 
730
#define FV_ADCSR_ABCM_40                     0x2
 
731
#define FV_ADCSR_ABCM_64                     0x3
 
732
#define FV_ADCSR_ABR_32                      0x0
 
733
#define FV_ADCSR_ABR_44_1                    0x1
 
734
#define FV_ADCSR_ABR_48                      0x2
 
735
#define FV_ADCSR_ABM_PT25                    0x0
 
736
#define FV_ADCSR_ABM_PT5                     0x1
 
737
#define FV_ADCSR_ABM_1                       0x2
 
738
#define FV_ADCSR_ABM_2                       0x3
 
739
 
 
740
/* Register Masks */
 
741
#define RM_ADCSR_ABCM                        RM(FM_ADCSR_ABCM, FB_ADCSR_ABCM)
 
742
#define RM_ADCSR_ABR                         RM(FM_ADCSR_ABR, FB_ADCSR_ABR)
 
743
#define RM_ADCSR_ABM                         RM(FM_ADCSR_ABM, FB_ADCSR_ABM)
 
744
 
 
745
/* Register Values */
 
746
#define RV_ADCSR_ABCM_AUTO \
 
747
         RV(FV_ADCSR_ABCM_AUTO, FB_ADCSR_ABCM)
 
748
 
 
749
#define RV_ADCSR_ABCM_32 \
 
750
         RV(FV_ADCSR_ABCM_32, FB_ADCSR_ABCM)
 
751
 
 
752
#define RV_ADCSR_ABCM_40 \
 
753
         RV(FV_ADCSR_ABCM_40, FB_ADCSR_ABCM)
 
754
 
 
755
#define RV_ADCSR_ABCM_64 \
 
756
         RV(FV_ADCSR_ABCM_64, FB_ADCSR_ABCM)
 
757
 
 
758
#define RV_ADCSR_ABR_32                      RV(FV_ADCSR_ABR_32, FB_ADCSR_ABR)
 
759
#define RV_ADCSR_ABR_44_1 \
 
760
         RV(FV_ADCSR_ABR_44_1, FB_ADCSR_ABR)
 
761
 
 
762
#define RV_ADCSR_ABR_48                      RV(FV_ADCSR_ABR_48, FB_ADCSR_ABR)
 
763
#define RV_ADCSR_ABR_                        RV(FV_ADCSR_ABR_, FB_ADCSR_ABR)
 
764
#define RV_ADCSR_ABM_PT25 \
 
765
         RV(FV_ADCSR_ABM_PT25, FB_ADCSR_ABM)
 
766
 
 
767
#define RV_ADCSR_ABM_PT5                     RV(FV_ADCSR_ABM_PT5, FB_ADCSR_ABM)
 
768
#define RV_ADCSR_ABM_1                       RV(FV_ADCSR_ABM_1, FB_ADCSR_ABM)
 
769
#define RV_ADCSR_ABM_2                       RV(FV_ADCSR_ABM_2, FB_ADCSR_ABM)
 
770
 
 
771
/******************************
 
772
 *      R_CNVRTR1 (0x18)      *
 
773
 ******************************/
 
774
 
 
775
/* Field Offsets */
 
776
#define FB_CNVRTR1_DACPOLR                   7
 
777
#define FB_CNVRTR1_DACPOLL                   6
 
778
#define FB_CNVRTR1_DMONOMIX                  4
 
779
#define FB_CNVRTR1_DACMU                     3
 
780
#define FB_CNVRTR1_DEEMPH                    2
 
781
#define FB_CNVRTR1_DACDITH                   0
 
782
 
 
783
/* Field Masks */
 
784
#define FM_CNVRTR1_DACPOLR                   0X1
 
785
#define FM_CNVRTR1_DACPOLL                   0X1
 
786
#define FM_CNVRTR1_DMONOMIX                  0X3
 
787
#define FM_CNVRTR1_DACMU                     0X1
 
788
#define FM_CNVRTR1_DEEMPH                    0X1
 
789
#define FM_CNVRTR1_DACDITH                   0X3
 
790
 
 
791
/* Field Values */
 
792
#define FV_CNVRTR1_DACPOLR_INVERT            0x1
 
793
#define FV_CNVRTR1_DACPOLR_NORMAL            0x0
 
794
#define FV_CNVRTR1_DACPOLL_INVERT            0x1
 
795
#define FV_CNVRTR1_DACPOLL_NORMAL            0x0
 
796
#define FV_CNVRTR1_DMONOMIX_ENABLE           0x1
 
797
#define FV_CNVRTR1_DMONOMIX_DISABLE          0x0
 
798
#define FV_CNVRTR1_DACMU_ENABLE              0x1
 
799
#define FV_CNVRTR1_DACMU_DISABLE             0x0
 
800
 
 
801
/* Register Masks */
 
802
#define RM_CNVRTR1_DACPOLR \
 
803
         RM(FM_CNVRTR1_DACPOLR, FB_CNVRTR1_DACPOLR)
 
804
 
 
805
#define RM_CNVRTR1_DACPOLL \
 
806
         RM(FM_CNVRTR1_DACPOLL, FB_CNVRTR1_DACPOLL)
 
807
 
 
808
#define RM_CNVRTR1_DMONOMIX \
 
809
         RM(FM_CNVRTR1_DMONOMIX, FB_CNVRTR1_DMONOMIX)
 
810
 
 
811
#define RM_CNVRTR1_DACMU \
 
812
         RM(FM_CNVRTR1_DACMU, FB_CNVRTR1_DACMU)
 
813
 
 
814
#define RM_CNVRTR1_DEEMPH \
 
815
         RM(FM_CNVRTR1_DEEMPH, FB_CNVRTR1_DEEMPH)
 
816
 
 
817
#define RM_CNVRTR1_DACDITH \
 
818
         RM(FM_CNVRTR1_DACDITH, FB_CNVRTR1_DACDITH)
 
819
 
 
820
 
 
821
/* Register Values */
 
822
#define RV_CNVRTR1_DACPOLR_INVERT \
 
823
         RV(FV_CNVRTR1_DACPOLR_INVERT, FB_CNVRTR1_DACPOLR)
 
824
 
 
825
#define RV_CNVRTR1_DACPOLR_NORMAL \
 
826
         RV(FV_CNVRTR1_DACPOLR_NORMAL, FB_CNVRTR1_DACPOLR)
 
827
 
 
828
#define RV_CNVRTR1_DACPOLL_INVERT \
 
829
         RV(FV_CNVRTR1_DACPOLL_INVERT, FB_CNVRTR1_DACPOLL)
 
830
 
 
831
#define RV_CNVRTR1_DACPOLL_NORMAL \
 
832
         RV(FV_CNVRTR1_DACPOLL_NORMAL, FB_CNVRTR1_DACPOLL)
 
833
 
 
834
#define RV_CNVRTR1_DMONOMIX_ENABLE \
 
835
         RV(FV_CNVRTR1_DMONOMIX_ENABLE, FB_CNVRTR1_DMONOMIX)
 
836
 
 
837
#define RV_CNVRTR1_DMONOMIX_DISABLE \
 
838
         RV(FV_CNVRTR1_DMONOMIX_DISABLE, FB_CNVRTR1_DMONOMIX)
 
839
 
 
840
#define RV_CNVRTR1_DACMU_ENABLE \
 
841
         RV(FV_CNVRTR1_DACMU_ENABLE, FB_CNVRTR1_DACMU)
 
842
 
 
843
#define RV_CNVRTR1_DACMU_DISABLE \
 
844
         RV(FV_CNVRTR1_DACMU_DISABLE, FB_CNVRTR1_DACMU)
 
845
 
 
846
 
 
847
/****************************
 
848
 *      R_DACSR (0x19)      *
 
849
 ****************************/
 
850
 
 
851
/* Field Offsets */
 
852
#define FB_DACSR_DBCM                        6
 
853
#define FB_DACSR_DBR                         3
 
854
#define FB_DACSR_DBM                         0
 
855
 
 
856
/* Field Masks */
 
857
#define FM_DACSR_DBCM                        0X3
 
858
#define FM_DACSR_DBR                         0X3
 
859
#define FM_DACSR_DBM                         0X7
 
860
 
 
861
/* Field Values */
 
862
#define FV_DACSR_DBCM_AUTO                   0x0
 
863
#define FV_DACSR_DBCM_32                     0x1
 
864
#define FV_DACSR_DBCM_40                     0x2
 
865
#define FV_DACSR_DBCM_64                     0x3
 
866
#define FV_DACSR_DBR_32                      0x0
 
867
#define FV_DACSR_DBR_44_1                    0x1
 
868
#define FV_DACSR_DBR_48                      0x2
 
869
#define FV_DACSR_DBM_PT25                    0x0
 
870
#define FV_DACSR_DBM_PT5                     0x1
 
871
#define FV_DACSR_DBM_1                       0x2
 
872
#define FV_DACSR_DBM_2                       0x3
 
873
 
 
874
/* Register Masks */
 
875
#define RM_DACSR_DBCM                        RM(FM_DACSR_DBCM, FB_DACSR_DBCM)
 
876
#define RM_DACSR_DBR                         RM(FM_DACSR_DBR, FB_DACSR_DBR)
 
877
#define RM_DACSR_DBM                         RM(FM_DACSR_DBM, FB_DACSR_DBM)
 
878
 
 
879
/* Register Values */
 
880
#define RV_DACSR_DBCM_AUTO \
 
881
         RV(FV_DACSR_DBCM_AUTO, FB_DACSR_DBCM)
 
882
 
 
883
#define RV_DACSR_DBCM_32 \
 
884
         RV(FV_DACSR_DBCM_32, FB_DACSR_DBCM)
 
885
 
 
886
#define RV_DACSR_DBCM_40 \
 
887
         RV(FV_DACSR_DBCM_40, FB_DACSR_DBCM)
 
888
 
 
889
#define RV_DACSR_DBCM_64 \
 
890
         RV(FV_DACSR_DBCM_64, FB_DACSR_DBCM)
 
891
 
 
892
#define RV_DACSR_DBR_32                      RV(FV_DACSR_DBR_32, FB_DACSR_DBR)
 
893
#define RV_DACSR_DBR_44_1 \
 
894
         RV(FV_DACSR_DBR_44_1, FB_DACSR_DBR)
 
895
 
 
896
#define RV_DACSR_DBR_48                      RV(FV_DACSR_DBR_48, FB_DACSR_DBR)
 
897
#define RV_DACSR_DBM_PT25 \
 
898
         RV(FV_DACSR_DBM_PT25, FB_DACSR_DBM)
 
899
 
 
900
#define RV_DACSR_DBM_PT5                     RV(FV_DACSR_DBM_PT5, FB_DACSR_DBM)
 
901
#define RV_DACSR_DBM_1                       RV(FV_DACSR_DBM_1, FB_DACSR_DBM)
 
902
#define RV_DACSR_DBM_2                       RV(FV_DACSR_DBM_2, FB_DACSR_DBM)
 
903
 
 
904
/****************************
 
905
 *      R_PWRM1 (0x1A)      *
 
906
 ****************************/
 
907
 
 
908
/* Field Offsets */
 
909
#define FB_PWRM1_BSTL                        7
 
910
#define FB_PWRM1_BSTR                        6
 
911
#define FB_PWRM1_PGAL                        5
 
912
#define FB_PWRM1_PGAR                        4
 
913
#define FB_PWRM1_ADCL                        3
 
914
#define FB_PWRM1_ADCR                        2
 
915
#define FB_PWRM1_MICB                        1
 
916
#define FB_PWRM1_DIGENB                      0
 
917
 
 
918
/* Field Masks */
 
919
#define FM_PWRM1_BSTL                        0X1
 
920
#define FM_PWRM1_BSTR                        0X1
 
921
#define FM_PWRM1_PGAL                        0X1
 
922
#define FM_PWRM1_PGAR                        0X1
 
923
#define FM_PWRM1_ADCL                        0X1
 
924
#define FM_PWRM1_ADCR                        0X1
 
925
#define FM_PWRM1_MICB                        0X1
 
926
#define FM_PWRM1_DIGENB                      0X1
 
927
 
 
928
/* Field Values */
 
929
#define FV_PWRM1_BSTL_ENABLE                 0x1
 
930
#define FV_PWRM1_BSTL_DISABLE                0x0
 
931
#define FV_PWRM1_BSTR_ENABLE                 0x1
 
932
#define FV_PWRM1_BSTR_DISABLE                0x0
 
933
#define FV_PWRM1_PGAL_ENABLE                 0x1
 
934
#define FV_PWRM1_PGAL_DISABLE                0x0
 
935
#define FV_PWRM1_PGAR_ENABLE                 0x1
 
936
#define FV_PWRM1_PGAR_DISABLE                0x0
 
937
#define FV_PWRM1_ADCL_ENABLE                 0x1
 
938
#define FV_PWRM1_ADCL_DISABLE                0x0
 
939
#define FV_PWRM1_ADCR_ENABLE                 0x1
 
940
#define FV_PWRM1_ADCR_DISABLE                0x0
 
941
#define FV_PWRM1_MICB_ENABLE                 0x1
 
942
#define FV_PWRM1_MICB_DISABLE                0x0
 
943
#define FV_PWRM1_DIGENB_DISABLE              0x1
 
944
#define FV_PWRM1_DIGENB_ENABLE               0x0
 
945
 
 
946
/* Register Masks */
 
947
#define RM_PWRM1_BSTL                        RM(FM_PWRM1_BSTL, FB_PWRM1_BSTL)
 
948
#define RM_PWRM1_BSTR                        RM(FM_PWRM1_BSTR, FB_PWRM1_BSTR)
 
949
#define RM_PWRM1_PGAL                        RM(FM_PWRM1_PGAL, FB_PWRM1_PGAL)
 
950
#define RM_PWRM1_PGAR                        RM(FM_PWRM1_PGAR, FB_PWRM1_PGAR)
 
951
#define RM_PWRM1_ADCL                        RM(FM_PWRM1_ADCL, FB_PWRM1_ADCL)
 
952
#define RM_PWRM1_ADCR                        RM(FM_PWRM1_ADCR, FB_PWRM1_ADCR)
 
953
#define RM_PWRM1_MICB                        RM(FM_PWRM1_MICB, FB_PWRM1_MICB)
 
954
#define RM_PWRM1_DIGENB \
 
955
         RM(FM_PWRM1_DIGENB, FB_PWRM1_DIGENB)
 
956
 
 
957
 
 
958
/* Register Values */
 
959
#define RV_PWRM1_BSTL_ENABLE \
 
960
         RV(FV_PWRM1_BSTL_ENABLE, FB_PWRM1_BSTL)
 
961
 
 
962
#define RV_PWRM1_BSTL_DISABLE \
 
963
         RV(FV_PWRM1_BSTL_DISABLE, FB_PWRM1_BSTL)
 
964
 
 
965
#define RV_PWRM1_BSTR_ENABLE \
 
966
         RV(FV_PWRM1_BSTR_ENABLE, FB_PWRM1_BSTR)
 
967
 
 
968
#define RV_PWRM1_BSTR_DISABLE \
 
969
         RV(FV_PWRM1_BSTR_DISABLE, FB_PWRM1_BSTR)
 
970
 
 
971
#define RV_PWRM1_PGAL_ENABLE \
 
972
         RV(FV_PWRM1_PGAL_ENABLE, FB_PWRM1_PGAL)
 
973
 
 
974
#define RV_PWRM1_PGAL_DISABLE \
 
975
         RV(FV_PWRM1_PGAL_DISABLE, FB_PWRM1_PGAL)
 
976
 
 
977
#define RV_PWRM1_PGAR_ENABLE \
 
978
         RV(FV_PWRM1_PGAR_ENABLE, FB_PWRM1_PGAR)
 
979
 
 
980
#define RV_PWRM1_PGAR_DISABLE \
 
981
         RV(FV_PWRM1_PGAR_DISABLE, FB_PWRM1_PGAR)
 
982
 
 
983
#define RV_PWRM1_ADCL_ENABLE \
 
984
         RV(FV_PWRM1_ADCL_ENABLE, FB_PWRM1_ADCL)
 
985
 
 
986
#define RV_PWRM1_ADCL_DISABLE \
 
987
         RV(FV_PWRM1_ADCL_DISABLE, FB_PWRM1_ADCL)
 
988
 
 
989
#define RV_PWRM1_ADCR_ENABLE \
 
990
         RV(FV_PWRM1_ADCR_ENABLE, FB_PWRM1_ADCR)
 
991
 
 
992
#define RV_PWRM1_ADCR_DISABLE \
 
993
         RV(FV_PWRM1_ADCR_DISABLE, FB_PWRM1_ADCR)
 
994
 
 
995
#define RV_PWRM1_MICB_ENABLE \
 
996
         RV(FV_PWRM1_MICB_ENABLE, FB_PWRM1_MICB)
 
997
 
 
998
#define RV_PWRM1_MICB_DISABLE \
 
999
         RV(FV_PWRM1_MICB_DISABLE, FB_PWRM1_MICB)
 
1000
 
 
1001
#define RV_PWRM1_DIGENB_DISABLE \
 
1002
         RV(FV_PWRM1_DIGENB_DISABLE, FB_PWRM1_DIGENB)
 
1003
 
 
1004
#define RV_PWRM1_DIGENB_ENABLE \
 
1005
         RV(FV_PWRM1_DIGENB_ENABLE, FB_PWRM1_DIGENB)
 
1006
 
 
1007
 
 
1008
/****************************
 
1009
 *      R_PWRM2 (0x1B)      *
 
1010
 ****************************/
 
1011
 
 
1012
/* Field Offsets */
 
1013
#define FB_PWRM2_D2S                         7
 
1014
#define FB_PWRM2_HPL                         6
 
1015
#define FB_PWRM2_HPR                         5
 
1016
#define FB_PWRM2_SPKL                        4
 
1017
#define FB_PWRM2_SPKR                        3
 
1018
#define FB_PWRM2_INSELL                      2
 
1019
#define FB_PWRM2_INSELR                      1
 
1020
#define FB_PWRM2_VREF                        0
 
1021
 
 
1022
/* Field Masks */
 
1023
#define FM_PWRM2_D2S                         0X1
 
1024
#define FM_PWRM2_HPL                         0X1
 
1025
#define FM_PWRM2_HPR                         0X1
 
1026
#define FM_PWRM2_SPKL                        0X1
 
1027
#define FM_PWRM2_SPKR                        0X1
 
1028
#define FM_PWRM2_INSELL                      0X1
 
1029
#define FM_PWRM2_INSELR                      0X1
 
1030
#define FM_PWRM2_VREF                        0X1
 
1031
 
 
1032
/* Field Values */
 
1033
#define FV_PWRM2_D2S_ENABLE                  0x1
 
1034
#define FV_PWRM2_D2S_DISABLE                 0x0
 
1035
#define FV_PWRM2_HPL_ENABLE                  0x1
 
1036
#define FV_PWRM2_HPL_DISABLE                 0x0
 
1037
#define FV_PWRM2_HPR_ENABLE                  0x1
 
1038
#define FV_PWRM2_HPR_DISABLE                 0x0
 
1039
#define FV_PWRM2_SPKL_ENABLE                 0x1
 
1040
#define FV_PWRM2_SPKL_DISABLE                0x0
 
1041
#define FV_PWRM2_SPKR_ENABLE                 0x1
 
1042
#define FV_PWRM2_SPKR_DISABLE                0x0
 
1043
#define FV_PWRM2_INSELL_ENABLE               0x1
 
1044
#define FV_PWRM2_INSELL_DISABLE              0x0
 
1045
#define FV_PWRM2_INSELR_ENABLE               0x1
 
1046
#define FV_PWRM2_INSELR_DISABLE              0x0
 
1047
#define FV_PWRM2_VREF_ENABLE                 0x1
 
1048
#define FV_PWRM2_VREF_DISABLE                0x0
 
1049
 
 
1050
/* Register Masks */
 
1051
#define RM_PWRM2_D2S                         RM(FM_PWRM2_D2S, FB_PWRM2_D2S)
 
1052
#define RM_PWRM2_HPL                         RM(FM_PWRM2_HPL, FB_PWRM2_HPL)
 
1053
#define RM_PWRM2_HPR                         RM(FM_PWRM2_HPR, FB_PWRM2_HPR)
 
1054
#define RM_PWRM2_SPKL                        RM(FM_PWRM2_SPKL, FB_PWRM2_SPKL)
 
1055
#define RM_PWRM2_SPKR                        RM(FM_PWRM2_SPKR, FB_PWRM2_SPKR)
 
1056
#define RM_PWRM2_INSELL \
 
1057
         RM(FM_PWRM2_INSELL, FB_PWRM2_INSELL)
 
1058
 
 
1059
#define RM_PWRM2_INSELR \
 
1060
         RM(FM_PWRM2_INSELR, FB_PWRM2_INSELR)
 
1061
 
 
1062
#define RM_PWRM2_VREF                        RM(FM_PWRM2_VREF, FB_PWRM2_VREF)
 
1063
 
 
1064
/* Register Values */
 
1065
#define RV_PWRM2_D2S_ENABLE \
 
1066
         RV(FV_PWRM2_D2S_ENABLE, FB_PWRM2_D2S)
 
1067
 
 
1068
#define RV_PWRM2_D2S_DISABLE \
 
1069
         RV(FV_PWRM2_D2S_DISABLE, FB_PWRM2_D2S)
 
1070
 
 
1071
#define RV_PWRM2_HPL_ENABLE \
 
1072
         RV(FV_PWRM2_HPL_ENABLE, FB_PWRM2_HPL)
 
1073
 
 
1074
#define RV_PWRM2_HPL_DISABLE \
 
1075
         RV(FV_PWRM2_HPL_DISABLE, FB_PWRM2_HPL)
 
1076
 
 
1077
#define RV_PWRM2_HPR_ENABLE \
 
1078
         RV(FV_PWRM2_HPR_ENABLE, FB_PWRM2_HPR)
 
1079
 
 
1080
#define RV_PWRM2_HPR_DISABLE \
 
1081
         RV(FV_PWRM2_HPR_DISABLE, FB_PWRM2_HPR)
 
1082
 
 
1083
#define RV_PWRM2_SPKL_ENABLE \
 
1084
         RV(FV_PWRM2_SPKL_ENABLE, FB_PWRM2_SPKL)
 
1085
 
 
1086
#define RV_PWRM2_SPKL_DISABLE \
 
1087
         RV(FV_PWRM2_SPKL_DISABLE, FB_PWRM2_SPKL)
 
1088
 
 
1089
#define RV_PWRM2_SPKR_ENABLE \
 
1090
         RV(FV_PWRM2_SPKR_ENABLE, FB_PWRM2_SPKR)
 
1091
 
 
1092
#define RV_PWRM2_SPKR_DISABLE \
 
1093
         RV(FV_PWRM2_SPKR_DISABLE, FB_PWRM2_SPKR)
 
1094
 
 
1095
#define RV_PWRM2_INSELL_ENABLE \
 
1096
         RV(FV_PWRM2_INSELL_ENABLE, FB_PWRM2_INSELL)
 
1097
 
 
1098
#define RV_PWRM2_INSELL_DISABLE \
 
1099
         RV(FV_PWRM2_INSELL_DISABLE, FB_PWRM2_INSELL)
 
1100
 
 
1101
#define RV_PWRM2_INSELR_ENABLE \
 
1102
         RV(FV_PWRM2_INSELR_ENABLE, FB_PWRM2_INSELR)
 
1103
 
 
1104
#define RV_PWRM2_INSELR_DISABLE \
 
1105
         RV(FV_PWRM2_INSELR_DISABLE, FB_PWRM2_INSELR)
 
1106
 
 
1107
#define RV_PWRM2_VREF_ENABLE \
 
1108
         RV(FV_PWRM2_VREF_ENABLE, FB_PWRM2_VREF)
 
1109
 
 
1110
#define RV_PWRM2_VREF_DISABLE \
 
1111
         RV(FV_PWRM2_VREF_DISABLE, FB_PWRM2_VREF)
 
1112
 
 
1113
 
 
1114
/******************************
 
1115
 *      R_CONFIG0 (0x1F)      *
 
1116
 ******************************/
 
1117
 
 
1118
/* Field Offsets */
 
1119
#define FB_CONFIG0_ASDM                      6
 
1120
#define FB_CONFIG0_DSDM                      4
 
1121
#define FB_CONFIG0_DC_BYPASS                 1
 
1122
#define FB_CONFIG0_SD_FORCE_ON               0
 
1123
 
 
1124
/* Field Masks */
 
1125
#define FM_CONFIG0_ASDM                      0X3
 
1126
#define FM_CONFIG0_DSDM                      0X3
 
1127
#define FM_CONFIG0_DC_BYPASS                 0X1
 
1128
#define FM_CONFIG0_SD_FORCE_ON               0X1
 
1129
 
 
1130
/* Field Values */
 
1131
#define FV_CONFIG0_ASDM_HALF                 0x1
 
1132
#define FV_CONFIG0_ASDM_FULL                 0x2
 
1133
#define FV_CONFIG0_ASDM_AUTO                 0x3
 
1134
#define FV_CONFIG0_DSDM_HALF                 0x1
 
1135
#define FV_CONFIG0_DSDM_FULL                 0x2
 
1136
#define FV_CONFIG0_DSDM_AUTO                 0x3
 
1137
#define FV_CONFIG0_DC_BYPASS_ENABLE          0x1
 
1138
#define FV_CONFIG0_DC_BYPASS_DISABLE         0x0
 
1139
#define FV_CONFIG0_SD_FORCE_ON_ENABLE        0x1
 
1140
#define FV_CONFIG0_SD_FORCE_ON_DISABLE       0x0
 
1141
 
 
1142
/* Register Masks */
 
1143
#define RM_CONFIG0_ASDM \
 
1144
         RM(FM_CONFIG0_ASDM, FB_CONFIG0_ASDM)
 
1145
 
 
1146
#define RM_CONFIG0_DSDM \
 
1147
         RM(FM_CONFIG0_DSDM, FB_CONFIG0_DSDM)
 
1148
 
 
1149
#define RM_CONFIG0_DC_BYPASS \
 
1150
         RM(FM_CONFIG0_DC_BYPASS, FB_CONFIG0_DC_BYPASS)
 
1151
 
 
1152
#define RM_CONFIG0_SD_FORCE_ON \
 
1153
         RM(FM_CONFIG0_SD_FORCE_ON, FB_CONFIG0_SD_FORCE_ON)
 
1154
 
 
1155
 
 
1156
/* Register Values */
 
1157
#define RV_CONFIG0_ASDM_HALF \
 
1158
         RV(FV_CONFIG0_ASDM_HALF, FB_CONFIG0_ASDM)
 
1159
 
 
1160
#define RV_CONFIG0_ASDM_FULL \
 
1161
         RV(FV_CONFIG0_ASDM_FULL, FB_CONFIG0_ASDM)
 
1162
 
 
1163
#define RV_CONFIG0_ASDM_AUTO \
 
1164
         RV(FV_CONFIG0_ASDM_AUTO, FB_CONFIG0_ASDM)
 
1165
 
 
1166
#define RV_CONFIG0_DSDM_HALF \
 
1167
         RV(FV_CONFIG0_DSDM_HALF, FB_CONFIG0_DSDM)
 
1168
 
 
1169
#define RV_CONFIG0_DSDM_FULL \
 
1170
         RV(FV_CONFIG0_DSDM_FULL, FB_CONFIG0_DSDM)
 
1171
 
 
1172
#define RV_CONFIG0_DSDM_AUTO \
 
1173
         RV(FV_CONFIG0_DSDM_AUTO, FB_CONFIG0_DSDM)
 
1174
 
 
1175
#define RV_CONFIG0_DC_BYPASS_ENABLE \
 
1176
         RV(FV_CONFIG0_DC_BYPASS_ENABLE, FB_CONFIG0_DC_BYPASS)
 
1177
 
 
1178
#define RV_CONFIG0_DC_BYPASS_DISABLE \
 
1179
         RV(FV_CONFIG0_DC_BYPASS_DISABLE, FB_CONFIG0_DC_BYPASS)
 
1180
 
 
1181
#define RV_CONFIG0_SD_FORCE_ON_ENABLE \
 
1182
         RV(FV_CONFIG0_SD_FORCE_ON_ENABLE, FB_CONFIG0_SD_FORCE_ON)
 
1183
 
 
1184
#define RV_CONFIG0_SD_FORCE_ON_DISABLE \
 
1185
         RV(FV_CONFIG0_SD_FORCE_ON_DISABLE, FB_CONFIG0_SD_FORCE_ON)
 
1186
 
 
1187
 
 
1188
/******************************
 
1189
 *      R_CONFIG1 (0x20)      *
 
1190
 ******************************/
 
1191
 
 
1192
/* Field Offsets */
 
1193
#define FB_CONFIG1_EQ2_EN                    7
 
1194
#define FB_CONFIG1_EQ2_BE                    4
 
1195
#define FB_CONFIG1_EQ1_EN                    3
 
1196
#define FB_CONFIG1_EQ1_BE                    0
 
1197
 
 
1198
/* Field Masks */
 
1199
#define FM_CONFIG1_EQ2_EN                    0X1
 
1200
#define FM_CONFIG1_EQ2_BE                    0X7
 
1201
#define FM_CONFIG1_EQ1_EN                    0X1
 
1202
#define FM_CONFIG1_EQ1_BE                    0X7
 
1203
 
 
1204
/* Field Values */
 
1205
#define FV_CONFIG1_EQ2_EN_ENABLE             0x1
 
1206
#define FV_CONFIG1_EQ2_EN_DISABLE            0x0
 
1207
#define FV_CONFIG1_EQ2_BE_PRE                0x0
 
1208
#define FV_CONFIG1_EQ2_BE_PRE_EQ_0           0x1
 
1209
#define FV_CONFIG1_EQ2_BE_PRE_EQ0_1          0x2
 
1210
#define FV_CONFIG1_EQ2_BE_PRE_EQ0_2          0x3
 
1211
#define FV_CONFIG1_EQ2_BE_PRE_EQ0_3          0x4
 
1212
#define FV_CONFIG1_EQ2_BE_PRE_EQ0_4          0x5
 
1213
#define FV_CONFIG1_EQ2_BE_PRE_EQ0_5          0x6
 
1214
#define FV_CONFIG1_EQ1_EN_ENABLE             0x1
 
1215
#define FV_CONFIG1_EQ1_EN_DISABLE            0x0
 
1216
#define FV_CONFIG1_EQ1_BE_PRE                0x0
 
1217
#define FV_CONFIG1_EQ1_BE_PRE_EQ_0           0x1
 
1218
#define FV_CONFIG1_EQ1_BE_PRE_EQ0_1          0x2
 
1219
#define FV_CONFIG1_EQ1_BE_PRE_EQ0_2          0x3
 
1220
#define FV_CONFIG1_EQ1_BE_PRE_EQ0_3          0x4
 
1221
#define FV_CONFIG1_EQ1_BE_PRE_EQ0_4          0x5
 
1222
#define FV_CONFIG1_EQ1_BE_PRE_EQ0_5          0x6
 
1223
 
 
1224
/* Register Masks */
 
1225
#define RM_CONFIG1_EQ2_EN \
 
1226
         RM(FM_CONFIG1_EQ2_EN, FB_CONFIG1_EQ2_EN)
 
1227
 
 
1228
#define RM_CONFIG1_EQ2_BE \
 
1229
         RM(FM_CONFIG1_EQ2_BE, FB_CONFIG1_EQ2_BE)
 
1230
 
 
1231
#define RM_CONFIG1_EQ1_EN \
 
1232
         RM(FM_CONFIG1_EQ1_EN, FB_CONFIG1_EQ1_EN)
 
1233
 
 
1234
#define RM_CONFIG1_EQ1_BE \
 
1235
         RM(FM_CONFIG1_EQ1_BE, FB_CONFIG1_EQ1_BE)
 
1236
 
 
1237
 
 
1238
/* Register Values */
 
1239
#define RV_CONFIG1_EQ2_EN_ENABLE \
 
1240
         RV(FV_CONFIG1_EQ2_EN_ENABLE, FB_CONFIG1_EQ2_EN)
 
1241
 
 
1242
#define RV_CONFIG1_EQ2_EN_DISABLE \
 
1243
         RV(FV_CONFIG1_EQ2_EN_DISABLE, FB_CONFIG1_EQ2_EN)
 
1244
 
 
1245
#define RV_CONFIG1_EQ2_BE_PRE \
 
1246
         RV(FV_CONFIG1_EQ2_BE_PRE, FB_CONFIG1_EQ2_BE)
 
1247
 
 
1248
#define RV_CONFIG1_EQ2_BE_PRE_EQ_0 \
 
1249
         RV(FV_CONFIG1_EQ2_BE_PRE_EQ_0, FB_CONFIG1_EQ2_BE)
 
1250
 
 
1251
#define RV_CONFIG1_EQ2_BE_PRE_EQ0_1 \
 
1252
         RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_1, FB_CONFIG1_EQ2_BE)
 
1253
 
 
1254
#define RV_CONFIG1_EQ2_BE_PRE_EQ0_2 \
 
1255
         RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_2, FB_CONFIG1_EQ2_BE)
 
1256
 
 
1257
#define RV_CONFIG1_EQ2_BE_PRE_EQ0_3 \
 
1258
         RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_3, FB_CONFIG1_EQ2_BE)
 
1259
 
 
1260
#define RV_CONFIG1_EQ2_BE_PRE_EQ0_4 \
 
1261
         RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_4, FB_CONFIG1_EQ2_BE)
 
1262
 
 
1263
#define RV_CONFIG1_EQ2_BE_PRE_EQ0_5 \
 
1264
         RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_5, FB_CONFIG1_EQ2_BE)
 
1265
 
 
1266
#define RV_CONFIG1_EQ1_EN_ENABLE \
 
1267
         RV(FV_CONFIG1_EQ1_EN_ENABLE, FB_CONFIG1_EQ1_EN)
 
1268
 
 
1269
#define RV_CONFIG1_EQ1_EN_DISABLE \
 
1270
         RV(FV_CONFIG1_EQ1_EN_DISABLE, FB_CONFIG1_EQ1_EN)
 
1271
 
 
1272
#define RV_CONFIG1_EQ1_BE_PRE \
 
1273
         RV(FV_CONFIG1_EQ1_BE_PRE, FB_CONFIG1_EQ1_BE)
 
1274
 
 
1275
#define RV_CONFIG1_EQ1_BE_PRE_EQ_0 \
 
1276
         RV(FV_CONFIG1_EQ1_BE_PRE_EQ_0, FB_CONFIG1_EQ1_BE)
 
1277
 
 
1278
#define RV_CONFIG1_EQ1_BE_PRE_EQ0_1 \
 
1279
         RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_1, FB_CONFIG1_EQ1_BE)
 
1280
 
 
1281
#define RV_CONFIG1_EQ1_BE_PRE_EQ0_2 \
 
1282
         RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_2, FB_CONFIG1_EQ1_BE)
 
1283
 
 
1284
#define RV_CONFIG1_EQ1_BE_PRE_EQ0_3 \
 
1285
         RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_3, FB_CONFIG1_EQ1_BE)
 
1286
 
 
1287
#define RV_CONFIG1_EQ1_BE_PRE_EQ0_4 \
 
1288
         RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_4, FB_CONFIG1_EQ1_BE)
 
1289
 
 
1290
#define RV_CONFIG1_EQ1_BE_PRE_EQ0_5 \
 
1291
         RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_5, FB_CONFIG1_EQ1_BE)
 
1292
 
 
1293
 
 
1294
/******************************
 
1295
 *      R_DMICCTL (0x24)      *
 
1296
 ******************************/
 
1297
 
 
1298
/* Field Offsets */
 
1299
#define FB_DMICCTL_DMICEN                    7
 
1300
#define FB_DMICCTL_DMONO                     4
 
1301
#define FB_DMICCTL_DMPHADJ                   2
 
1302
#define FB_DMICCTL_DMRATE                    0
 
1303
 
 
1304
/* Field Masks */
 
1305
#define FM_DMICCTL_DMICEN                    0X1
 
1306
#define FM_DMICCTL_DMONO                     0X1
 
1307
#define FM_DMICCTL_DMPHADJ                   0X3
 
1308
#define FM_DMICCTL_DMRATE                    0X3
 
1309
 
 
1310
/* Field Values */
 
1311
#define FV_DMICCTL_DMICEN_ENABLE             0x1
 
1312
#define FV_DMICCTL_DMICEN_DISABLE            0x0
 
1313
#define FV_DMICCTL_DMONO_STEREO              0x0
 
1314
#define FV_DMICCTL_DMONO_MONO                0x1
 
1315
 
 
1316
/* Register Masks */
 
1317
#define RM_DMICCTL_DMICEN \
 
1318
         RM(FM_DMICCTL_DMICEN, FB_DMICCTL_DMICEN)
 
1319
 
 
1320
#define RM_DMICCTL_DMONO \
 
1321
         RM(FM_DMICCTL_DMONO, FB_DMICCTL_DMONO)
 
1322
 
 
1323
#define RM_DMICCTL_DMPHADJ \
 
1324
         RM(FM_DMICCTL_DMPHADJ, FB_DMICCTL_DMPHADJ)
 
1325
 
 
1326
#define RM_DMICCTL_DMRATE \
 
1327
         RM(FM_DMICCTL_DMRATE, FB_DMICCTL_DMRATE)
 
1328
 
 
1329
 
 
1330
/* Register Values */
 
1331
#define RV_DMICCTL_DMICEN_ENABLE \
 
1332
         RV(FV_DMICCTL_DMICEN_ENABLE, FB_DMICCTL_DMICEN)
 
1333
 
 
1334
#define RV_DMICCTL_DMICEN_DISABLE \
 
1335
         RV(FV_DMICCTL_DMICEN_DISABLE, FB_DMICCTL_DMICEN)
 
1336
 
 
1337
#define RV_DMICCTL_DMONO_STEREO \
 
1338
         RV(FV_DMICCTL_DMONO_STEREO, FB_DMICCTL_DMONO)
 
1339
 
 
1340
#define RV_DMICCTL_DMONO_MONO \
 
1341
         RV(FV_DMICCTL_DMONO_MONO, FB_DMICCTL_DMONO)
 
1342
 
 
1343
 
 
1344
/*****************************
 
1345
 *      R_CLECTL (0x25)      *
 
1346
 *****************************/
 
1347
 
 
1348
/* Field Offsets */
 
1349
#define FB_CLECTL_LVL_MODE                   4
 
1350
#define FB_CLECTL_WINDOWSEL                  3
 
1351
#define FB_CLECTL_EXP_EN                     2
 
1352
#define FB_CLECTL_LIMIT_EN                   1
 
1353
#define FB_CLECTL_COMP_EN                    0
 
1354
 
 
1355
/* Field Masks */
 
1356
#define FM_CLECTL_LVL_MODE                   0X1
 
1357
#define FM_CLECTL_WINDOWSEL                  0X1
 
1358
#define FM_CLECTL_EXP_EN                     0X1
 
1359
#define FM_CLECTL_LIMIT_EN                   0X1
 
1360
#define FM_CLECTL_COMP_EN                    0X1
 
1361
 
 
1362
/* Field Values */
 
1363
#define FV_CLECTL_LVL_MODE_AVG               0x0
 
1364
#define FV_CLECTL_LVL_MODE_PEAK              0x1
 
1365
#define FV_CLECTL_WINDOWSEL_512              0x0
 
1366
#define FV_CLECTL_WINDOWSEL_64               0x1
 
1367
#define FV_CLECTL_EXP_EN_ENABLE              0x1
 
1368
#define FV_CLECTL_EXP_EN_DISABLE             0x0
 
1369
#define FV_CLECTL_LIMIT_EN_ENABLE            0x1
 
1370
#define FV_CLECTL_LIMIT_EN_DISABLE           0x0
 
1371
#define FV_CLECTL_COMP_EN_ENABLE             0x1
 
1372
#define FV_CLECTL_COMP_EN_DISABLE            0x0
 
1373
 
 
1374
/* Register Masks */
 
1375
#define RM_CLECTL_LVL_MODE \
 
1376
         RM(FM_CLECTL_LVL_MODE, FB_CLECTL_LVL_MODE)
 
1377
 
 
1378
#define RM_CLECTL_WINDOWSEL \
 
1379
         RM(FM_CLECTL_WINDOWSEL, FB_CLECTL_WINDOWSEL)
 
1380
 
 
1381
#define RM_CLECTL_EXP_EN \
 
1382
         RM(FM_CLECTL_EXP_EN, FB_CLECTL_EXP_EN)
 
1383
 
 
1384
#define RM_CLECTL_LIMIT_EN \
 
1385
         RM(FM_CLECTL_LIMIT_EN, FB_CLECTL_LIMIT_EN)
 
1386
 
 
1387
#define RM_CLECTL_COMP_EN \
 
1388
         RM(FM_CLECTL_COMP_EN, FB_CLECTL_COMP_EN)
 
1389
 
 
1390
 
 
1391
/* Register Values */
 
1392
#define RV_CLECTL_LVL_MODE_AVG \
 
1393
         RV(FV_CLECTL_LVL_MODE_AVG, FB_CLECTL_LVL_MODE)
 
1394
 
 
1395
#define RV_CLECTL_LVL_MODE_PEAK \
 
1396
         RV(FV_CLECTL_LVL_MODE_PEAK, FB_CLECTL_LVL_MODE)
 
1397
 
 
1398
#define RV_CLECTL_WINDOWSEL_512 \
 
1399
         RV(FV_CLECTL_WINDOWSEL_512, FB_CLECTL_WINDOWSEL)
 
1400
 
 
1401
#define RV_CLECTL_WINDOWSEL_64 \
 
1402
         RV(FV_CLECTL_WINDOWSEL_64, FB_CLECTL_WINDOWSEL)
 
1403
 
 
1404
#define RV_CLECTL_EXP_EN_ENABLE \
 
1405
         RV(FV_CLECTL_EXP_EN_ENABLE, FB_CLECTL_EXP_EN)
 
1406
 
 
1407
#define RV_CLECTL_EXP_EN_DISABLE \
 
1408
         RV(FV_CLECTL_EXP_EN_DISABLE, FB_CLECTL_EXP_EN)
 
1409
 
 
1410
#define RV_CLECTL_LIMIT_EN_ENABLE \
 
1411
         RV(FV_CLECTL_LIMIT_EN_ENABLE, FB_CLECTL_LIMIT_EN)
 
1412
 
 
1413
#define RV_CLECTL_LIMIT_EN_DISABLE \
 
1414
         RV(FV_CLECTL_LIMIT_EN_DISABLE, FB_CLECTL_LIMIT_EN)
 
1415
 
 
1416
#define RV_CLECTL_COMP_EN_ENABLE \
 
1417
         RV(FV_CLECTL_COMP_EN_ENABLE, FB_CLECTL_COMP_EN)
 
1418
 
 
1419
#define RV_CLECTL_COMP_EN_DISABLE \
 
1420
         RV(FV_CLECTL_COMP_EN_DISABLE, FB_CLECTL_COMP_EN)
 
1421
 
 
1422
 
 
1423
/*****************************
 
1424
 *      R_MUGAIN (0x26)      *
 
1425
 *****************************/
 
1426
 
 
1427
/* Field Offsets */
 
1428
#define FB_MUGAIN_CLEMUG                     0
 
1429
 
 
1430
/* Field Masks */
 
1431
#define FM_MUGAIN_CLEMUG                     0X1F
 
1432
 
 
1433
/* Field Values */
 
1434
#define FV_MUGAIN_CLEMUG_46PT5DB             0x1F
 
1435
#define FV_MUGAIN_CLEMUG_0DB                 0x0
 
1436
 
 
1437
/* Register Masks */
 
1438
#define RM_MUGAIN_CLEMUG \
 
1439
         RM(FM_MUGAIN_CLEMUG, FB_MUGAIN_CLEMUG)
 
1440
 
 
1441
 
 
1442
/* Register Values */
 
1443
#define RV_MUGAIN_CLEMUG_46PT5DB \
 
1444
         RV(FV_MUGAIN_CLEMUG_46PT5DB, FB_MUGAIN_CLEMUG)
 
1445
 
 
1446
#define RV_MUGAIN_CLEMUG_0DB \
 
1447
         RV(FV_MUGAIN_CLEMUG_0DB, FB_MUGAIN_CLEMUG)
 
1448
 
 
1449
 
 
1450
/*****************************
 
1451
 *      R_COMPTH (0x27)      *
 
1452
 *****************************/
 
1453
 
 
1454
/* Field Offsets */
 
1455
#define FB_COMPTH                            0
 
1456
 
 
1457
/* Field Masks */
 
1458
#define FM_COMPTH                            0XFF
 
1459
 
 
1460
/* Field Values */
 
1461
#define FV_COMPTH_0DB                        0xFF
 
1462
#define FV_COMPTH_N95PT625DB                 0x0
 
1463
 
 
1464
/* Register Masks */
 
1465
#define RM_COMPTH                            RM(FM_COMPTH, FB_COMPTH)
 
1466
 
 
1467
/* Register Values */
 
1468
#define RV_COMPTH_0DB                        RV(FV_COMPTH_0DB, FB_COMPTH)
 
1469
#define RV_COMPTH_N95PT625DB \
 
1470
         RV(FV_COMPTH_N95PT625DB, FB_COMPTH)
 
1471
 
 
1472
 
 
1473
/*****************************
 
1474
 *      R_CMPRAT (0x28)      *
 
1475
 *****************************/
 
1476
 
 
1477
/* Field Offsets */
 
1478
#define FB_CMPRAT                            0
 
1479
 
 
1480
/* Field Masks */
 
1481
#define FM_CMPRAT                            0X1F
 
1482
 
 
1483
/* Register Masks */
 
1484
#define RM_CMPRAT                            RM(FM_CMPRAT, FB_CMPRAT)
 
1485
 
 
1486
/******************************
 
1487
 *      R_CATKTCL (0x29)      *
 
1488
 ******************************/
 
1489
 
 
1490
/* Field Offsets */
 
1491
#define FB_CATKTCL                           0
 
1492
 
 
1493
/* Field Masks */
 
1494
#define FM_CATKTCL                           0XFF
 
1495
 
 
1496
/* Register Masks */
 
1497
#define RM_CATKTCL                           RM(FM_CATKTCL, FB_CATKTCL)
 
1498
 
 
1499
/******************************
 
1500
 *      R_CATKTCH (0x2A)      *
 
1501
 ******************************/
 
1502
 
 
1503
/* Field Offsets */
 
1504
#define FB_CATKTCH                           0
 
1505
 
 
1506
/* Field Masks */
 
1507
#define FM_CATKTCH                           0XFF
 
1508
 
 
1509
/* Register Masks */
 
1510
#define RM_CATKTCH                           RM(FM_CATKTCH, FB_CATKTCH)
 
1511
 
 
1512
/******************************
 
1513
 *      R_CRELTCL (0x2B)      *
 
1514
 ******************************/
 
1515
 
 
1516
/* Field Offsets */
 
1517
#define FB_CRELTCL                           0
 
1518
 
 
1519
/* Field Masks */
 
1520
#define FM_CRELTCL                           0XFF
 
1521
 
 
1522
/* Register Masks */
 
1523
#define RM_CRELTCL                           RM(FM_CRELTCL, FB_CRELTCL)
 
1524
 
 
1525
/******************************
 
1526
 *      R_CRELTCH (0x2C)      *
 
1527
 ******************************/
 
1528
 
 
1529
/* Field Offsets */
 
1530
#define FB_CRELTCH                           0
 
1531
 
 
1532
/* Field Masks */
 
1533
#define FM_CRELTCH                           0XFF
 
1534
 
 
1535
/* Register Masks */
 
1536
#define RM_CRELTCH                           RM(FM_CRELTCH, FB_CRELTCH)
 
1537
 
 
1538
/****************************
 
1539
 *      R_LIMTH (0x2D)      *
 
1540
 ****************************/
 
1541
 
 
1542
/* Field Offsets */
 
1543
#define FB_LIMTH                             0
 
1544
 
 
1545
/* Field Masks */
 
1546
#define FM_LIMTH                             0XFF
 
1547
 
 
1548
/* Field Values */
 
1549
#define FV_LIMTH_0DB                         0xFF
 
1550
#define FV_LIMTH_N95PT625DB                  0x0
 
1551
 
 
1552
/* Register Masks */
 
1553
#define RM_LIMTH                             RM(FM_LIMTH, FB_LIMTH)
 
1554
 
 
1555
/* Register Values */
 
1556
#define RV_LIMTH_0DB                         RV(FV_LIMTH_0DB, FB_LIMTH)
 
1557
#define RV_LIMTH_N95PT625DB                  RV(FV_LIMTH_N95PT625DB, FB_LIMTH)
 
1558
 
 
1559
/*****************************
 
1560
 *      R_LIMTGT (0x2E)      *
 
1561
 *****************************/
 
1562
 
 
1563
/* Field Offsets */
 
1564
#define FB_LIMTGT                            0
 
1565
 
 
1566
/* Field Masks */
 
1567
#define FM_LIMTGT                            0XFF
 
1568
 
 
1569
/* Field Values */
 
1570
#define FV_LIMTGT_0DB                        0xFF
 
1571
#define FV_LIMTGT_N95PT625DB                 0x0
 
1572
 
 
1573
/* Register Masks */
 
1574
#define RM_LIMTGT                            RM(FM_LIMTGT, FB_LIMTGT)
 
1575
 
 
1576
/* Register Values */
 
1577
#define RV_LIMTGT_0DB                        RV(FV_LIMTGT_0DB, FB_LIMTGT)
 
1578
#define RV_LIMTGT_N95PT625DB \
 
1579
         RV(FV_LIMTGT_N95PT625DB, FB_LIMTGT)
 
1580
 
 
1581
 
 
1582
/******************************
 
1583
 *      R_LATKTCL (0x2F)      *
 
1584
 ******************************/
 
1585
 
 
1586
/* Field Offsets */
 
1587
#define FB_LATKTCL                           0
 
1588
 
 
1589
/* Field Masks */
 
1590
#define FM_LATKTCL                           0XFF
 
1591
 
 
1592
/* Register Masks */
 
1593
#define RM_LATKTCL                           RM(FM_LATKTCL, FB_LATKTCL)
 
1594
 
 
1595
/******************************
 
1596
 *      R_LATKTCH (0x30)      *
 
1597
 ******************************/
 
1598
 
 
1599
/* Field Offsets */
 
1600
#define FB_LATKTCH                           0
 
1601
 
 
1602
/* Field Masks */
 
1603
#define FM_LATKTCH                           0XFF
 
1604
 
 
1605
/* Register Masks */
 
1606
#define RM_LATKTCH                           RM(FM_LATKTCH, FB_LATKTCH)
 
1607
 
 
1608
/******************************
 
1609
 *      R_LRELTCL (0x31)      *
 
1610
 ******************************/
 
1611
 
 
1612
/* Field Offsets */
 
1613
#define FB_LRELTCL                           0
 
1614
 
 
1615
/* Field Masks */
 
1616
#define FM_LRELTCL                           0XFF
 
1617
 
 
1618
/* Register Masks */
 
1619
#define RM_LRELTCL                           RM(FM_LRELTCL, FB_LRELTCL)
 
1620
 
 
1621
/******************************
 
1622
 *      R_LRELTCH (0x32)      *
 
1623
 ******************************/
 
1624
 
 
1625
/* Field Offsets */
 
1626
#define FB_LRELTCH                           0
 
1627
 
 
1628
/* Field Masks */
 
1629
#define FM_LRELTCH                           0XFF
 
1630
 
 
1631
/* Register Masks */
 
1632
#define RM_LRELTCH                           RM(FM_LRELTCH, FB_LRELTCH)
 
1633
 
 
1634
/****************************
 
1635
 *      R_EXPTH (0x33)      *
 
1636
 ****************************/
 
1637
 
 
1638
/* Field Offsets */
 
1639
#define FB_EXPTH                             0
 
1640
 
 
1641
/* Field Masks */
 
1642
#define FM_EXPTH                             0XFF
 
1643
 
 
1644
/* Field Values */
 
1645
#define FV_EXPTH_0DB                         0xFF
 
1646
#define FV_EXPTH_N95PT625DB                  0x0
 
1647
 
 
1648
/* Register Masks */
 
1649
#define RM_EXPTH                             RM(FM_EXPTH, FB_EXPTH)
 
1650
 
 
1651
/* Register Values */
 
1652
#define RV_EXPTH_0DB                         RV(FV_EXPTH_0DB, FB_EXPTH)
 
1653
#define RV_EXPTH_N95PT625DB                  RV(FV_EXPTH_N95PT625DB, FB_EXPTH)
 
1654
 
 
1655
/*****************************
 
1656
 *      R_EXPRAT (0x34)      *
 
1657
 *****************************/
 
1658
 
 
1659
/* Field Offsets */
 
1660
#define FB_EXPRAT                            0
 
1661
 
 
1662
/* Field Masks */
 
1663
#define FM_EXPRAT                            0X7
 
1664
 
 
1665
/* Register Masks */
 
1666
#define RM_EXPRAT                            RM(FM_EXPRAT, FB_EXPRAT)
 
1667
 
 
1668
/******************************
 
1669
 *      R_XATKTCL (0x35)      *
 
1670
 ******************************/
 
1671
 
 
1672
/* Field Offsets */
 
1673
#define FB_XATKTCL                           0
 
1674
 
 
1675
/* Field Masks */
 
1676
#define FM_XATKTCL                           0XFF
 
1677
 
 
1678
/* Register Masks */
 
1679
#define RM_XATKTCL                           RM(FM_XATKTCL, FB_XATKTCL)
 
1680
 
 
1681
/******************************
 
1682
 *      R_XATKTCH (0x36)      *
 
1683
 ******************************/
 
1684
 
 
1685
/* Field Offsets */
 
1686
#define FB_XATKTCH                           0
 
1687
 
 
1688
/* Field Masks */
 
1689
#define FM_XATKTCH                           0XFF
 
1690
 
 
1691
/* Register Masks */
 
1692
#define RM_XATKTCH                           RM(FM_XATKTCH, FB_XATKTCH)
 
1693
 
 
1694
/******************************
 
1695
 *      R_XRELTCL (0x37)      *
 
1696
 ******************************/
 
1697
 
 
1698
/* Field Offsets */
 
1699
#define FB_XRELTCL                           0
 
1700
 
 
1701
/* Field Masks */
 
1702
#define FM_XRELTCL                           0XFF
 
1703
 
 
1704
/* Register Masks */
 
1705
#define RM_XRELTCL                           RM(FM_XRELTCL, FB_XRELTCL)
 
1706
 
 
1707
/******************************
 
1708
 *      R_XRELTCH (0x38)      *
 
1709
 ******************************/
 
1710
 
 
1711
/* Field Offsets */
 
1712
#define FB_XRELTCH                           0
 
1713
 
 
1714
/* Field Masks */
 
1715
#define FM_XRELTCH                           0XFF
 
1716
 
 
1717
/* Register Masks */
 
1718
#define RM_XRELTCH                           RM(FM_XRELTCH, FB_XRELTCH)
 
1719
 
 
1720
/****************************
 
1721
 *      R_FXCTL (0x39)      *
 
1722
 ****************************/
 
1723
 
 
1724
/* Field Offsets */
 
1725
#define FB_FXCTL_3DEN                        4
 
1726
#define FB_FXCTL_TEEN                        3
 
1727
#define FB_FXCTL_TNLFBYPASS                  2
 
1728
#define FB_FXCTL_BEEN                        1
 
1729
#define FB_FXCTL_BNLFBYPASS                  0
 
1730
 
 
1731
/* Field Masks */
 
1732
#define FM_FXCTL_3DEN                        0X1
 
1733
#define FM_FXCTL_TEEN                        0X1
 
1734
#define FM_FXCTL_TNLFBYPASS                  0X1
 
1735
#define FM_FXCTL_BEEN                        0X1
 
1736
#define FM_FXCTL_BNLFBYPASS                  0X1
 
1737
 
 
1738
/* Field Values */
 
1739
#define FV_FXCTL_3DEN_ENABLE                 0x1
 
1740
#define FV_FXCTL_3DEN_DISABLE                0x0
 
1741
#define FV_FXCTL_TEEN_ENABLE                 0x1
 
1742
#define FV_FXCTL_TEEN_DISABLE                0x0
 
1743
#define FV_FXCTL_TNLFBYPASS_ENABLE           0x1
 
1744
#define FV_FXCTL_TNLFBYPASS_DISABLE          0x0
 
1745
#define FV_FXCTL_BEEN_ENABLE                 0x1
 
1746
#define FV_FXCTL_BEEN_DISABLE                0x0
 
1747
#define FV_FXCTL_BNLFBYPASS_ENABLE           0x1
 
1748
#define FV_FXCTL_BNLFBYPASS_DISABLE          0x0
 
1749
 
 
1750
/* Register Masks */
 
1751
#define RM_FXCTL_3DEN                        RM(FM_FXCTL_3DEN, FB_FXCTL_3DEN)
 
1752
#define RM_FXCTL_TEEN                        RM(FM_FXCTL_TEEN, FB_FXCTL_TEEN)
 
1753
#define RM_FXCTL_TNLFBYPASS \
 
1754
         RM(FM_FXCTL_TNLFBYPASS, FB_FXCTL_TNLFBYPASS)
 
1755
 
 
1756
#define RM_FXCTL_BEEN                        RM(FM_FXCTL_BEEN, FB_FXCTL_BEEN)
 
1757
#define RM_FXCTL_BNLFBYPASS \
 
1758
         RM(FM_FXCTL_BNLFBYPASS, FB_FXCTL_BNLFBYPASS)
 
1759
 
 
1760
 
 
1761
/* Register Values */
 
1762
#define RV_FXCTL_3DEN_ENABLE \
 
1763
         RV(FV_FXCTL_3DEN_ENABLE, FB_FXCTL_3DEN)
 
1764
 
 
1765
#define RV_FXCTL_3DEN_DISABLE \
 
1766
         RV(FV_FXCTL_3DEN_DISABLE, FB_FXCTL_3DEN)
 
1767
 
 
1768
#define RV_FXCTL_TEEN_ENABLE \
 
1769
         RV(FV_FXCTL_TEEN_ENABLE, FB_FXCTL_TEEN)
 
1770
 
 
1771
#define RV_FXCTL_TEEN_DISABLE \
 
1772
         RV(FV_FXCTL_TEEN_DISABLE, FB_FXCTL_TEEN)
 
1773
 
 
1774
#define RV_FXCTL_TNLFBYPASS_ENABLE \
 
1775
         RV(FV_FXCTL_TNLFBYPASS_ENABLE, FB_FXCTL_TNLFBYPASS)
 
1776
 
 
1777
#define RV_FXCTL_TNLFBYPASS_DISABLE \
 
1778
         RV(FV_FXCTL_TNLFBYPASS_DISABLE, FB_FXCTL_TNLFBYPASS)
 
1779
 
 
1780
#define RV_FXCTL_BEEN_ENABLE \
 
1781
         RV(FV_FXCTL_BEEN_ENABLE, FB_FXCTL_BEEN)
 
1782
 
 
1783
#define RV_FXCTL_BEEN_DISABLE \
 
1784
         RV(FV_FXCTL_BEEN_DISABLE, FB_FXCTL_BEEN)
 
1785
 
 
1786
#define RV_FXCTL_BNLFBYPASS_ENABLE \
 
1787
         RV(FV_FXCTL_BNLFBYPASS_ENABLE, FB_FXCTL_BNLFBYPASS)
 
1788
 
 
1789
#define RV_FXCTL_BNLFBYPASS_DISABLE \
 
1790
         RV(FV_FXCTL_BNLFBYPASS_DISABLE, FB_FXCTL_BNLFBYPASS)
 
1791
 
 
1792
 
 
1793
/*******************************
 
1794
 *      R_DACCRWRL (0x3A)      *
 
1795
 *******************************/
 
1796
 
 
1797
/* Field Offsets */
 
1798
#define FB_DACCRWRL_DACCRWDL                 0
 
1799
 
 
1800
/* Field Masks */
 
1801
#define FM_DACCRWRL_DACCRWDL                 0XFF
 
1802
 
 
1803
/* Register Masks */
 
1804
#define RM_DACCRWRL_DACCRWDL \
 
1805
         RM(FM_DACCRWRL_DACCRWDL, FB_DACCRWRL_DACCRWDL)
 
1806
 
 
1807
 
 
1808
/*******************************
 
1809
 *      R_DACCRWRM (0x3B)      *
 
1810
 *******************************/
 
1811
 
 
1812
/* Field Offsets */
 
1813
#define FB_DACCRWRM_DACCRWDM                 0
 
1814
 
 
1815
/* Field Masks */
 
1816
#define FM_DACCRWRM_DACCRWDM                 0XFF
 
1817
 
 
1818
/* Register Masks */
 
1819
#define RM_DACCRWRM_DACCRWDM \
 
1820
         RM(FM_DACCRWRM_DACCRWDM, FB_DACCRWRM_DACCRWDM)
 
1821
 
 
1822
 
 
1823
/*******************************
 
1824
 *      R_DACCRWRH (0x3C)      *
 
1825
 *******************************/
 
1826
 
 
1827
/* Field Offsets */
 
1828
#define FB_DACCRWRH_DACCRWDH                 0
 
1829
 
 
1830
/* Field Masks */
 
1831
#define FM_DACCRWRH_DACCRWDH                 0XFF
 
1832
 
 
1833
/* Register Masks */
 
1834
#define RM_DACCRWRH_DACCRWDH \
 
1835
         RM(FM_DACCRWRH_DACCRWDH, FB_DACCRWRH_DACCRWDH)
 
1836
 
 
1837
 
 
1838
/*******************************
 
1839
 *      R_DACCRRDL (0x3D)      *
 
1840
 *******************************/
 
1841
 
 
1842
/* Field Offsets */
 
1843
#define FB_DACCRRDL                          0
 
1844
 
 
1845
/* Field Masks */
 
1846
#define FM_DACCRRDL                          0XFF
 
1847
 
 
1848
/* Register Masks */
 
1849
#define RM_DACCRRDL                          RM(FM_DACCRRDL, FB_DACCRRDL)
 
1850
 
 
1851
/*******************************
 
1852
 *      R_DACCRRDM (0x3E)      *
 
1853
 *******************************/
 
1854
 
 
1855
/* Field Offsets */
 
1856
#define FB_DACCRRDM                          0
 
1857
 
 
1858
/* Field Masks */
 
1859
#define FM_DACCRRDM                          0XFF
 
1860
 
 
1861
/* Register Masks */
 
1862
#define RM_DACCRRDM                          RM(FM_DACCRRDM, FB_DACCRRDM)
 
1863
 
 
1864
/*******************************
 
1865
 *      R_DACCRRDH (0x3F)      *
 
1866
 *******************************/
 
1867
 
 
1868
/* Field Offsets */
 
1869
#define FB_DACCRRDH                          0
 
1870
 
 
1871
/* Field Masks */
 
1872
#define FM_DACCRRDH                          0XFF
 
1873
 
 
1874
/* Register Masks */
 
1875
#define RM_DACCRRDH                          RM(FM_DACCRRDH, FB_DACCRRDH)
 
1876
 
 
1877
/********************************
 
1878
 *      R_DACCRADDR (0x40)      *
 
1879
 ********************************/
 
1880
 
 
1881
/* Field Offsets */
 
1882
#define FB_DACCRADDR_DACCRADD                0
 
1883
 
 
1884
/* Field Masks */
 
1885
#define FM_DACCRADDR_DACCRADD                0XFF
 
1886
 
 
1887
/* Register Masks */
 
1888
#define RM_DACCRADDR_DACCRADD \
 
1889
         RM(FM_DACCRADDR_DACCRADD, FB_DACCRADDR_DACCRADD)
 
1890
 
 
1891
 
 
1892
/******************************
 
1893
 *      R_DCOFSEL (0x41)      *
 
1894
 ******************************/
 
1895
 
 
1896
/* Field Offsets */
 
1897
#define FB_DCOFSEL_DC_COEF_SEL               0
 
1898
 
 
1899
/* Field Masks */
 
1900
#define FM_DCOFSEL_DC_COEF_SEL               0X7
 
1901
 
 
1902
/* Field Values */
 
1903
#define FV_DCOFSEL_DC_COEF_SEL_2_N8          0x0
 
1904
#define FV_DCOFSEL_DC_COEF_SEL_2_N9          0x1
 
1905
#define FV_DCOFSEL_DC_COEF_SEL_2_N10         0x2
 
1906
#define FV_DCOFSEL_DC_COEF_SEL_2_N11         0x3
 
1907
#define FV_DCOFSEL_DC_COEF_SEL_2_N12         0x4
 
1908
#define FV_DCOFSEL_DC_COEF_SEL_2_N13         0x5
 
1909
#define FV_DCOFSEL_DC_COEF_SEL_2_N14         0x6
 
1910
#define FV_DCOFSEL_DC_COEF_SEL_2_N15         0x7
 
1911
 
 
1912
/* Register Masks */
 
1913
#define RM_DCOFSEL_DC_COEF_SEL \
 
1914
         RM(FM_DCOFSEL_DC_COEF_SEL, FB_DCOFSEL_DC_COEF_SEL)
 
1915
 
 
1916
 
 
1917
/* Register Values */
 
1918
#define RV_DCOFSEL_DC_COEF_SEL_2_N8 \
 
1919
         RV(FV_DCOFSEL_DC_COEF_SEL_2_N8, FB_DCOFSEL_DC_COEF_SEL)
 
1920
 
 
1921
#define RV_DCOFSEL_DC_COEF_SEL_2_N9 \
 
1922
         RV(FV_DCOFSEL_DC_COEF_SEL_2_N9, FB_DCOFSEL_DC_COEF_SEL)
 
1923
 
 
1924
#define RV_DCOFSEL_DC_COEF_SEL_2_N10 \
 
1925
         RV(FV_DCOFSEL_DC_COEF_SEL_2_N10, FB_DCOFSEL_DC_COEF_SEL)
 
1926
 
 
1927
#define RV_DCOFSEL_DC_COEF_SEL_2_N11 \
 
1928
         RV(FV_DCOFSEL_DC_COEF_SEL_2_N11, FB_DCOFSEL_DC_COEF_SEL)
 
1929
 
 
1930
#define RV_DCOFSEL_DC_COEF_SEL_2_N12 \
 
1931
         RV(FV_DCOFSEL_DC_COEF_SEL_2_N12, FB_DCOFSEL_DC_COEF_SEL)
 
1932
 
 
1933
#define RV_DCOFSEL_DC_COEF_SEL_2_N13 \
 
1934
         RV(FV_DCOFSEL_DC_COEF_SEL_2_N13, FB_DCOFSEL_DC_COEF_SEL)
 
1935
 
 
1936
#define RV_DCOFSEL_DC_COEF_SEL_2_N14 \
 
1937
         RV(FV_DCOFSEL_DC_COEF_SEL_2_N14, FB_DCOFSEL_DC_COEF_SEL)
 
1938
 
 
1939
#define RV_DCOFSEL_DC_COEF_SEL_2_N15 \
 
1940
         RV(FV_DCOFSEL_DC_COEF_SEL_2_N15, FB_DCOFSEL_DC_COEF_SEL)
 
1941
 
 
1942
 
 
1943
/******************************
 
1944
 *      R_PLLCTL9 (0x4E)      *
 
1945
 ******************************/
 
1946
 
 
1947
/* Field Offsets */
 
1948
#define FB_PLLCTL9_REFDIV_PLL1               0
 
1949
 
 
1950
/* Field Masks */
 
1951
#define FM_PLLCTL9_REFDIV_PLL1               0XFF
 
1952
 
 
1953
/* Register Masks */
 
1954
#define RM_PLLCTL9_REFDIV_PLL1 \
 
1955
         RM(FM_PLLCTL9_REFDIV_PLL1, FB_PLLCTL9_REFDIV_PLL1)
 
1956
 
 
1957
 
 
1958
/******************************
 
1959
 *      R_PLLCTLA (0x4F)      *
 
1960
 ******************************/
 
1961
 
 
1962
/* Field Offsets */
 
1963
#define FB_PLLCTLA_OUTDIV_PLL1               0
 
1964
 
 
1965
/* Field Masks */
 
1966
#define FM_PLLCTLA_OUTDIV_PLL1               0XFF
 
1967
 
 
1968
/* Register Masks */
 
1969
#define RM_PLLCTLA_OUTDIV_PLL1 \
 
1970
         RM(FM_PLLCTLA_OUTDIV_PLL1, FB_PLLCTLA_OUTDIV_PLL1)
 
1971
 
 
1972
 
 
1973
/******************************
 
1974
 *      R_PLLCTLB (0x50)      *
 
1975
 ******************************/
 
1976
 
 
1977
/* Field Offsets */
 
1978
#define FB_PLLCTLB_FBDIV_PLL1L               0
 
1979
 
 
1980
/* Field Masks */
 
1981
#define FM_PLLCTLB_FBDIV_PLL1L               0XFF
 
1982
 
 
1983
/* Register Masks */
 
1984
#define RM_PLLCTLB_FBDIV_PLL1L \
 
1985
         RM(FM_PLLCTLB_FBDIV_PLL1L, FB_PLLCTLB_FBDIV_PLL1L)
 
1986
 
 
1987
 
 
1988
/******************************
 
1989
 *      R_PLLCTLC (0x51)      *
 
1990
 ******************************/
 
1991
 
 
1992
/* Field Offsets */
 
1993
#define FB_PLLCTLC_FBDIV_PLL1H               0
 
1994
 
 
1995
/* Field Masks */
 
1996
#define FM_PLLCTLC_FBDIV_PLL1H               0X7
 
1997
 
 
1998
/* Register Masks */
 
1999
#define RM_PLLCTLC_FBDIV_PLL1H \
 
2000
         RM(FM_PLLCTLC_FBDIV_PLL1H, FB_PLLCTLC_FBDIV_PLL1H)
 
2001
 
 
2002
 
 
2003
/******************************
 
2004
 *      R_PLLCTLD (0x52)      *
 
2005
 ******************************/
 
2006
 
 
2007
/* Field Offsets */
 
2008
#define FB_PLLCTLD_RZ_PLL1                   3
 
2009
#define FB_PLLCTLD_CP_PLL1                   0
 
2010
 
 
2011
/* Field Masks */
 
2012
#define FM_PLLCTLD_RZ_PLL1                   0X7
 
2013
#define FM_PLLCTLD_CP_PLL1                   0X7
 
2014
 
 
2015
/* Register Masks */
 
2016
#define RM_PLLCTLD_RZ_PLL1 \
 
2017
         RM(FM_PLLCTLD_RZ_PLL1, FB_PLLCTLD_RZ_PLL1)
 
2018
 
 
2019
#define RM_PLLCTLD_CP_PLL1 \
 
2020
         RM(FM_PLLCTLD_CP_PLL1, FB_PLLCTLD_CP_PLL1)
 
2021
 
 
2022
 
 
2023
/******************************
 
2024
 *      R_PLLCTLE (0x53)      *
 
2025
 ******************************/
 
2026
 
 
2027
/* Field Offsets */
 
2028
#define FB_PLLCTLE_REFDIV_PLL2               0
 
2029
 
 
2030
/* Field Masks */
 
2031
#define FM_PLLCTLE_REFDIV_PLL2               0XFF
 
2032
 
 
2033
/* Register Masks */
 
2034
#define RM_PLLCTLE_REFDIV_PLL2 \
 
2035
         RM(FM_PLLCTLE_REFDIV_PLL2, FB_PLLCTLE_REFDIV_PLL2)
 
2036
 
 
2037
 
 
2038
/******************************
 
2039
 *      R_PLLCTLF (0x54)      *
 
2040
 ******************************/
 
2041
 
 
2042
/* Field Offsets */
 
2043
#define FB_PLLCTLF_OUTDIV_PLL2               0
 
2044
 
 
2045
/* Field Masks */
 
2046
#define FM_PLLCTLF_OUTDIV_PLL2               0XFF
 
2047
 
 
2048
/* Register Masks */
 
2049
#define RM_PLLCTLF_OUTDIV_PLL2 \
 
2050
         RM(FM_PLLCTLF_OUTDIV_PLL2, FB_PLLCTLF_OUTDIV_PLL2)
 
2051
 
 
2052
 
 
2053
/*******************************
 
2054
 *      R_PLLCTL10 (0x55)      *
 
2055
 *******************************/
 
2056
 
 
2057
/* Field Offsets */
 
2058
#define FB_PLLCTL10_FBDIV_PLL2L              0
 
2059
 
 
2060
/* Field Masks */
 
2061
#define FM_PLLCTL10_FBDIV_PLL2L              0XFF
 
2062
 
 
2063
/* Register Masks */
 
2064
#define RM_PLLCTL10_FBDIV_PLL2L \
 
2065
         RM(FM_PLLCTL10_FBDIV_PLL2L, FB_PLLCTL10_FBDIV_PLL2L)
 
2066
 
 
2067
 
 
2068
/*******************************
 
2069
 *      R_PLLCTL11 (0x56)      *
 
2070
 *******************************/
 
2071
 
 
2072
/* Field Offsets */
 
2073
#define FB_PLLCTL11_FBDIV_PLL2H              0
 
2074
 
 
2075
/* Field Masks */
 
2076
#define FM_PLLCTL11_FBDIV_PLL2H              0X7
 
2077
 
 
2078
/* Register Masks */
 
2079
#define RM_PLLCTL11_FBDIV_PLL2H \
 
2080
         RM(FM_PLLCTL11_FBDIV_PLL2H, FB_PLLCTL11_FBDIV_PLL2H)
 
2081
 
 
2082
 
 
2083
/*******************************
 
2084
 *      R_PLLCTL12 (0x57)      *
 
2085
 *******************************/
 
2086
 
 
2087
/* Field Offsets */
 
2088
#define FB_PLLCTL12_RZ_PLL2                  3
 
2089
#define FB_PLLCTL12_CP_PLL2                  0
 
2090
 
 
2091
/* Field Masks */
 
2092
#define FM_PLLCTL12_RZ_PLL2                  0X7
 
2093
#define FM_PLLCTL12_CP_PLL2                  0X7
 
2094
 
 
2095
/* Register Masks */
 
2096
#define RM_PLLCTL12_RZ_PLL2 \
 
2097
         RM(FM_PLLCTL12_RZ_PLL2, FB_PLLCTL12_RZ_PLL2)
 
2098
 
 
2099
#define RM_PLLCTL12_CP_PLL2 \
 
2100
         RM(FM_PLLCTL12_CP_PLL2, FB_PLLCTL12_CP_PLL2)
 
2101
 
 
2102
 
 
2103
/*******************************
 
2104
 *      R_PLLCTL1B (0x60)      *
 
2105
 *******************************/
 
2106
 
 
2107
/* Field Offsets */
 
2108
#define FB_PLLCTL1B_VCOI_PLL2                4
 
2109
#define FB_PLLCTL1B_VCOI_PLL1                2
 
2110
 
 
2111
/* Field Masks */
 
2112
#define FM_PLLCTL1B_VCOI_PLL2                0X3
 
2113
#define FM_PLLCTL1B_VCOI_PLL1                0X3
 
2114
 
 
2115
/* Register Masks */
 
2116
#define RM_PLLCTL1B_VCOI_PLL2 \
 
2117
         RM(FM_PLLCTL1B_VCOI_PLL2, FB_PLLCTL1B_VCOI_PLL2)
 
2118
 
 
2119
#define RM_PLLCTL1B_VCOI_PLL1 \
 
2120
         RM(FM_PLLCTL1B_VCOI_PLL1, FB_PLLCTL1B_VCOI_PLL1)
 
2121
 
 
2122
 
 
2123
/*******************************
 
2124
 *      R_PLLCTL1C (0x61)      *
 
2125
 *******************************/
 
2126
 
 
2127
/* Field Offsets */
 
2128
#define FB_PLLCTL1C_PDB_PLL2                 2
 
2129
#define FB_PLLCTL1C_PDB_PLL1                 1
 
2130
 
 
2131
/* Field Masks */
 
2132
#define FM_PLLCTL1C_PDB_PLL2                 0X1
 
2133
#define FM_PLLCTL1C_PDB_PLL1                 0X1
 
2134
 
 
2135
/* Field Values */
 
2136
#define FV_PLLCTL1C_PDB_PLL2_ENABLE          0x1
 
2137
#define FV_PLLCTL1C_PDB_PLL2_DISABLE         0x0
 
2138
#define FV_PLLCTL1C_PDB_PLL1_ENABLE          0x1
 
2139
#define FV_PLLCTL1C_PDB_PLL1_DISABLE         0x0
 
2140
 
 
2141
/* Register Masks */
 
2142
#define RM_PLLCTL1C_PDB_PLL2 \
 
2143
         RM(FM_PLLCTL1C_PDB_PLL2, FB_PLLCTL1C_PDB_PLL2)
 
2144
 
 
2145
#define RM_PLLCTL1C_PDB_PLL1 \
 
2146
         RM(FM_PLLCTL1C_PDB_PLL1, FB_PLLCTL1C_PDB_PLL1)
 
2147
 
 
2148
 
 
2149
/* Register Values */
 
2150
#define RV_PLLCTL1C_PDB_PLL2_ENABLE \
 
2151
         RV(FV_PLLCTL1C_PDB_PLL2_ENABLE, FB_PLLCTL1C_PDB_PLL2)
 
2152
 
 
2153
#define RV_PLLCTL1C_PDB_PLL2_DISABLE \
 
2154
         RV(FV_PLLCTL1C_PDB_PLL2_DISABLE, FB_PLLCTL1C_PDB_PLL2)
 
2155
 
 
2156
#define RV_PLLCTL1C_PDB_PLL1_ENABLE \
 
2157
         RV(FV_PLLCTL1C_PDB_PLL1_ENABLE, FB_PLLCTL1C_PDB_PLL1)
 
2158
 
 
2159
#define RV_PLLCTL1C_PDB_PLL1_DISABLE \
 
2160
         RV(FV_PLLCTL1C_PDB_PLL1_DISABLE, FB_PLLCTL1C_PDB_PLL1)
 
2161
 
 
2162
 
 
2163
/*******************************
 
2164
 *      R_TIMEBASE (0x77)      *
 
2165
 *******************************/
 
2166
 
 
2167
/* Field Offsets */
 
2168
#define FB_TIMEBASE_DIVIDER                  0
 
2169
 
 
2170
/* Field Masks */
 
2171
#define FM_TIMEBASE_DIVIDER                  0XFF
 
2172
 
 
2173
/* Register Masks */
 
2174
#define RM_TIMEBASE_DIVIDER \
 
2175
         RM(FM_TIMEBASE_DIVIDER, FB_TIMEBASE_DIVIDER)
 
2176
 
 
2177
 
 
2178
/*****************************
 
2179
 *      R_DEVIDL (0x7D)      *
 
2180
 *****************************/
 
2181
 
 
2182
/* Field Offsets */
 
2183
#define FB_DEVIDL_DIDL                       0
 
2184
 
 
2185
/* Field Masks */
 
2186
#define FM_DEVIDL_DIDL                       0XFF
 
2187
 
 
2188
/* Register Masks */
 
2189
#define RM_DEVIDL_DIDL                       RM(FM_DEVIDL_DIDL, FB_DEVIDL_DIDL)
 
2190
 
 
2191
/*****************************
 
2192
 *      R_DEVIDH (0x7E)      *
 
2193
 *****************************/
 
2194
 
 
2195
/* Field Offsets */
 
2196
#define FB_DEVIDH_DIDH                       0
 
2197
 
 
2198
/* Field Masks */
 
2199
#define FM_DEVIDH_DIDH                       0XFF
 
2200
 
 
2201
/* Register Masks */
 
2202
#define RM_DEVIDH_DIDH                       RM(FM_DEVIDH_DIDH, FB_DEVIDH_DIDH)
 
2203
 
 
2204
/****************************
 
2205
 *      R_RESET (0x80)      *
 
2206
 ****************************/
 
2207
 
 
2208
/* Field Offsets */
 
2209
#define FB_RESET                             0
 
2210
 
 
2211
/* Field Masks */
 
2212
#define FM_RESET                             0XFF
 
2213
 
 
2214
/* Field Values */
 
2215
#define FV_RESET_ENABLE                      0x85
 
2216
 
 
2217
/* Register Masks */
 
2218
#define RM_RESET                             RM(FM_RESET, FB_RESET)
 
2219
 
 
2220
/* Register Values */
 
2221
#define RV_RESET_ENABLE                      RV(FV_RESET_ENABLE, FB_RESET)
 
2222
 
 
2223
/********************************
 
2224
 *      R_DACCRSTAT (0x8A)      *
 
2225
 ********************************/
 
2226
 
 
2227
/* Field Offsets */
 
2228
#define FB_DACCRSTAT_DACCR_BUSY              7
 
2229
 
 
2230
/* Field Masks */
 
2231
#define FM_DACCRSTAT_DACCR_BUSY              0X1
 
2232
 
 
2233
/* Register Masks */
 
2234
#define RM_DACCRSTAT_DACCR_BUSY \
 
2235
         RM(FM_DACCRSTAT_DACCR_BUSY, FB_DACCRSTAT_DACCR_BUSY)
 
2236
 
 
2237
 
 
2238
/******************************
 
2239
 *      R_PLLCTL0 (0x8E)      *
 
2240
 ******************************/
 
2241
 
 
2242
/* Field Offsets */
 
2243
#define FB_PLLCTL0_PLL2_LOCK                 1
 
2244
#define FB_PLLCTL0_PLL1_LOCK                 0
 
2245
 
 
2246
/* Field Masks */
 
2247
#define FM_PLLCTL0_PLL2_LOCK                 0X1
 
2248
#define FM_PLLCTL0_PLL1_LOCK                 0X1
 
2249
 
 
2250
/* Register Masks */
 
2251
#define RM_PLLCTL0_PLL2_LOCK \
 
2252
         RM(FM_PLLCTL0_PLL2_LOCK, FB_PLLCTL0_PLL2_LOCK)
 
2253
 
 
2254
#define RM_PLLCTL0_PLL1_LOCK \
 
2255
         RM(FM_PLLCTL0_PLL1_LOCK, FB_PLLCTL0_PLL1_LOCK)
 
2256
 
 
2257
 
 
2258
/********************************
 
2259
 *      R_PLLREFSEL (0x8F)      *
 
2260
 ********************************/
 
2261
 
 
2262
/* Field Offsets */
 
2263
#define FB_PLLREFSEL_PLL2_REF_SEL            4
 
2264
#define FB_PLLREFSEL_PLL1_REF_SEL            0
 
2265
 
 
2266
/* Field Masks */
 
2267
#define FM_PLLREFSEL_PLL2_REF_SEL            0X7
 
2268
#define FM_PLLREFSEL_PLL1_REF_SEL            0X7
 
2269
 
 
2270
/* Field Values */
 
2271
#define FV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1 0x0
 
2272
#define FV_PLLREFSEL_PLL2_REF_SEL_MCLK2      0x1
 
2273
#define FV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1 0x0
 
2274
#define FV_PLLREFSEL_PLL1_REF_SEL_MCLK2      0x1
 
2275
 
 
2276
/* Register Masks */
 
2277
#define RM_PLLREFSEL_PLL2_REF_SEL \
 
2278
         RM(FM_PLLREFSEL_PLL2_REF_SEL, FB_PLLREFSEL_PLL2_REF_SEL)
 
2279
 
 
2280
#define RM_PLLREFSEL_PLL1_REF_SEL \
 
2281
         RM(FM_PLLREFSEL_PLL1_REF_SEL, FB_PLLREFSEL_PLL1_REF_SEL)
 
2282
 
 
2283
 
 
2284
/* Register Values */
 
2285
#define RV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1 \
 
2286
         RV(FV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1, FB_PLLREFSEL_PLL2_REF_SEL)
 
2287
 
 
2288
#define RV_PLLREFSEL_PLL2_REF_SEL_MCLK2 \
 
2289
         RV(FV_PLLREFSEL_PLL2_REF_SEL_MCLK2, FB_PLLREFSEL_PLL2_REF_SEL)
 
2290
 
 
2291
#define RV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1 \
 
2292
         RV(FV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1, FB_PLLREFSEL_PLL1_REF_SEL)
 
2293
 
 
2294
#define RV_PLLREFSEL_PLL1_REF_SEL_MCLK2 \
 
2295
         RV(FV_PLLREFSEL_PLL1_REF_SEL_MCLK2, FB_PLLREFSEL_PLL1_REF_SEL)
 
2296
 
 
2297
 
 
2298
/*******************************
 
2299
 *      R_DACMBCEN (0xC7)      *
 
2300
 *******************************/
 
2301
 
 
2302
/* Field Offsets */
 
2303
#define FB_DACMBCEN_MBCEN3                   2
 
2304
#define FB_DACMBCEN_MBCEN2                   1
 
2305
#define FB_DACMBCEN_MBCEN1                   0
 
2306
 
 
2307
/* Field Masks */
 
2308
#define FM_DACMBCEN_MBCEN3                   0X1
 
2309
#define FM_DACMBCEN_MBCEN2                   0X1
 
2310
#define FM_DACMBCEN_MBCEN1                   0X1
 
2311
 
 
2312
/* Register Masks */
 
2313
#define RM_DACMBCEN_MBCEN3 \
 
2314
         RM(FM_DACMBCEN_MBCEN3, FB_DACMBCEN_MBCEN3)
 
2315
 
 
2316
#define RM_DACMBCEN_MBCEN2 \
 
2317
         RM(FM_DACMBCEN_MBCEN2, FB_DACMBCEN_MBCEN2)
 
2318
 
 
2319
#define RM_DACMBCEN_MBCEN1 \
 
2320
         RM(FM_DACMBCEN_MBCEN1, FB_DACMBCEN_MBCEN1)
 
2321
 
 
2322
 
 
2323
/********************************
 
2324
 *      R_DACMBCCTL (0xC8)      *
 
2325
 ********************************/
 
2326
 
 
2327
/* Field Offsets */
 
2328
#define FB_DACMBCCTL_LVLMODE3                5
 
2329
#define FB_DACMBCCTL_WINSEL3                 4
 
2330
#define FB_DACMBCCTL_LVLMODE2                3
 
2331
#define FB_DACMBCCTL_WINSEL2                 2
 
2332
#define FB_DACMBCCTL_LVLMODE1                1
 
2333
#define FB_DACMBCCTL_WINSEL1                 0
 
2334
 
 
2335
/* Field Masks */
 
2336
#define FM_DACMBCCTL_LVLMODE3                0X1
 
2337
#define FM_DACMBCCTL_WINSEL3                 0X1
 
2338
#define FM_DACMBCCTL_LVLMODE2                0X1
 
2339
#define FM_DACMBCCTL_WINSEL2                 0X1
 
2340
#define FM_DACMBCCTL_LVLMODE1                0X1
 
2341
#define FM_DACMBCCTL_WINSEL1                 0X1
 
2342
 
 
2343
/* Register Masks */
 
2344
#define RM_DACMBCCTL_LVLMODE3 \
 
2345
         RM(FM_DACMBCCTL_LVLMODE3, FB_DACMBCCTL_LVLMODE3)
 
2346
 
 
2347
#define RM_DACMBCCTL_WINSEL3 \
 
2348
         RM(FM_DACMBCCTL_WINSEL3, FB_DACMBCCTL_WINSEL3)
 
2349
 
 
2350
#define RM_DACMBCCTL_LVLMODE2 \
 
2351
         RM(FM_DACMBCCTL_LVLMODE2, FB_DACMBCCTL_LVLMODE2)
 
2352
 
 
2353
#define RM_DACMBCCTL_WINSEL2 \
 
2354
         RM(FM_DACMBCCTL_WINSEL2, FB_DACMBCCTL_WINSEL2)
 
2355
 
 
2356
#define RM_DACMBCCTL_LVLMODE1 \
 
2357
         RM(FM_DACMBCCTL_LVLMODE1, FB_DACMBCCTL_LVLMODE1)
 
2358
 
 
2359
#define RM_DACMBCCTL_WINSEL1 \
 
2360
         RM(FM_DACMBCCTL_WINSEL1, FB_DACMBCCTL_WINSEL1)
 
2361
 
 
2362
 
 
2363
/*********************************
 
2364
 *      R_DACMBCMUG1 (0xC9)      *
 
2365
 *********************************/
 
2366
 
 
2367
/* Field Offsets */
 
2368
#define FB_DACMBCMUG1_PHASE                  5
 
2369
#define FB_DACMBCMUG1_MUGAIN                 0
 
2370
 
 
2371
/* Field Masks */
 
2372
#define FM_DACMBCMUG1_PHASE                  0X1
 
2373
#define FM_DACMBCMUG1_MUGAIN                 0X1F
 
2374
 
 
2375
/* Register Masks */
 
2376
#define RM_DACMBCMUG1_PHASE \
 
2377
         RM(FM_DACMBCMUG1_PHASE, FB_DACMBCMUG1_PHASE)
 
2378
 
 
2379
#define RM_DACMBCMUG1_MUGAIN \
 
2380
         RM(FM_DACMBCMUG1_MUGAIN, FB_DACMBCMUG1_MUGAIN)
 
2381
 
 
2382
 
 
2383
/*********************************
 
2384
 *      R_DACMBCTHR1 (0xCA)      *
 
2385
 *********************************/
 
2386
 
 
2387
/* Field Offsets */
 
2388
#define FB_DACMBCTHR1_THRESH                 0
 
2389
 
 
2390
/* Field Masks */
 
2391
#define FM_DACMBCTHR1_THRESH                 0XFF
 
2392
 
 
2393
/* Register Masks */
 
2394
#define RM_DACMBCTHR1_THRESH \
 
2395
         RM(FM_DACMBCTHR1_THRESH, FB_DACMBCTHR1_THRESH)
 
2396
 
 
2397
 
 
2398
/*********************************
 
2399
 *      R_DACMBCRAT1 (0xCB)      *
 
2400
 *********************************/
 
2401
 
 
2402
/* Field Offsets */
 
2403
#define FB_DACMBCRAT1_RATIO                  0
 
2404
 
 
2405
/* Field Masks */
 
2406
#define FM_DACMBCRAT1_RATIO                  0X1F
 
2407
 
 
2408
/* Register Masks */
 
2409
#define RM_DACMBCRAT1_RATIO \
 
2410
         RM(FM_DACMBCRAT1_RATIO, FB_DACMBCRAT1_RATIO)
 
2411
 
 
2412
 
 
2413
/**********************************
 
2414
 *      R_DACMBCATK1L (0xCC)      *
 
2415
 **********************************/
 
2416
 
 
2417
/* Field Offsets */
 
2418
#define FB_DACMBCATK1L_TCATKL                0
 
2419
 
 
2420
/* Field Masks */
 
2421
#define FM_DACMBCATK1L_TCATKL                0XFF
 
2422
 
 
2423
/* Register Masks */
 
2424
#define RM_DACMBCATK1L_TCATKL \
 
2425
         RM(FM_DACMBCATK1L_TCATKL, FB_DACMBCATK1L_TCATKL)
 
2426
 
 
2427
 
 
2428
/**********************************
 
2429
 *      R_DACMBCATK1H (0xCD)      *
 
2430
 **********************************/
 
2431
 
 
2432
/* Field Offsets */
 
2433
#define FB_DACMBCATK1H_TCATKH                0
 
2434
 
 
2435
/* Field Masks */
 
2436
#define FM_DACMBCATK1H_TCATKH                0XFF
 
2437
 
 
2438
/* Register Masks */
 
2439
#define RM_DACMBCATK1H_TCATKH \
 
2440
         RM(FM_DACMBCATK1H_TCATKH, FB_DACMBCATK1H_TCATKH)
 
2441
 
 
2442
 
 
2443
/**********************************
 
2444
 *      R_DACMBCREL1L (0xCE)      *
 
2445
 **********************************/
 
2446
 
 
2447
/* Field Offsets */
 
2448
#define FB_DACMBCREL1L_TCRELL                0
 
2449
 
 
2450
/* Field Masks */
 
2451
#define FM_DACMBCREL1L_TCRELL                0XFF
 
2452
 
 
2453
/* Register Masks */
 
2454
#define RM_DACMBCREL1L_TCRELL \
 
2455
         RM(FM_DACMBCREL1L_TCRELL, FB_DACMBCREL1L_TCRELL)
 
2456
 
 
2457
 
 
2458
/**********************************
 
2459
 *      R_DACMBCREL1H (0xCF)      *
 
2460
 **********************************/
 
2461
 
 
2462
/* Field Offsets */
 
2463
#define FB_DACMBCREL1H_TCRELH                0
 
2464
 
 
2465
/* Field Masks */
 
2466
#define FM_DACMBCREL1H_TCRELH                0XFF
 
2467
 
 
2468
/* Register Masks */
 
2469
#define RM_DACMBCREL1H_TCRELH \
 
2470
         RM(FM_DACMBCREL1H_TCRELH, FB_DACMBCREL1H_TCRELH)
 
2471
 
 
2472
 
 
2473
/*********************************
 
2474
 *      R_DACMBCMUG2 (0xD0)      *
 
2475
 *********************************/
 
2476
 
 
2477
/* Field Offsets */
 
2478
#define FB_DACMBCMUG2_PHASE                  5
 
2479
#define FB_DACMBCMUG2_MUGAIN                 0
 
2480
 
 
2481
/* Field Masks */
 
2482
#define FM_DACMBCMUG2_PHASE                  0X1
 
2483
#define FM_DACMBCMUG2_MUGAIN                 0X1F
 
2484
 
 
2485
/* Register Masks */
 
2486
#define RM_DACMBCMUG2_PHASE \
 
2487
         RM(FM_DACMBCMUG2_PHASE, FB_DACMBCMUG2_PHASE)
 
2488
 
 
2489
#define RM_DACMBCMUG2_MUGAIN \
 
2490
         RM(FM_DACMBCMUG2_MUGAIN, FB_DACMBCMUG2_MUGAIN)
 
2491
 
 
2492
 
 
2493
/*********************************
 
2494
 *      R_DACMBCTHR2 (0xD1)      *
 
2495
 *********************************/
 
2496
 
 
2497
/* Field Offsets */
 
2498
#define FB_DACMBCTHR2_THRESH                 0
 
2499
 
 
2500
/* Field Masks */
 
2501
#define FM_DACMBCTHR2_THRESH                 0XFF
 
2502
 
 
2503
/* Register Masks */
 
2504
#define RM_DACMBCTHR2_THRESH \
 
2505
         RM(FM_DACMBCTHR2_THRESH, FB_DACMBCTHR2_THRESH)
 
2506
 
 
2507
 
 
2508
/*********************************
 
2509
 *      R_DACMBCRAT2 (0xD2)      *
 
2510
 *********************************/
 
2511
 
 
2512
/* Field Offsets */
 
2513
#define FB_DACMBCRAT2_RATIO                  0
 
2514
 
 
2515
/* Field Masks */
 
2516
#define FM_DACMBCRAT2_RATIO                  0X1F
 
2517
 
 
2518
/* Register Masks */
 
2519
#define RM_DACMBCRAT2_RATIO \
 
2520
         RM(FM_DACMBCRAT2_RATIO, FB_DACMBCRAT2_RATIO)
 
2521
 
 
2522
 
 
2523
/**********************************
 
2524
 *      R_DACMBCATK2L (0xD3)      *
 
2525
 **********************************/
 
2526
 
 
2527
/* Field Offsets */
 
2528
#define FB_DACMBCATK2L_TCATKL                0
 
2529
 
 
2530
/* Field Masks */
 
2531
#define FM_DACMBCATK2L_TCATKL                0XFF
 
2532
 
 
2533
/* Register Masks */
 
2534
#define RM_DACMBCATK2L_TCATKL \
 
2535
         RM(FM_DACMBCATK2L_TCATKL, FB_DACMBCATK2L_TCATKL)
 
2536
 
 
2537
 
 
2538
/**********************************
 
2539
 *      R_DACMBCATK2H (0xD4)      *
 
2540
 **********************************/
 
2541
 
 
2542
/* Field Offsets */
 
2543
#define FB_DACMBCATK2H_TCATKH                0
 
2544
 
 
2545
/* Field Masks */
 
2546
#define FM_DACMBCATK2H_TCATKH                0XFF
 
2547
 
 
2548
/* Register Masks */
 
2549
#define RM_DACMBCATK2H_TCATKH \
 
2550
         RM(FM_DACMBCATK2H_TCATKH, FB_DACMBCATK2H_TCATKH)
 
2551
 
 
2552
 
 
2553
/**********************************
 
2554
 *      R_DACMBCREL2L (0xD5)      *
 
2555
 **********************************/
 
2556
 
 
2557
/* Field Offsets */
 
2558
#define FB_DACMBCREL2L_TCRELL                0
 
2559
 
 
2560
/* Field Masks */
 
2561
#define FM_DACMBCREL2L_TCRELL                0XFF
 
2562
 
 
2563
/* Register Masks */
 
2564
#define RM_DACMBCREL2L_TCRELL \
 
2565
         RM(FM_DACMBCREL2L_TCRELL, FB_DACMBCREL2L_TCRELL)
 
2566
 
 
2567
 
 
2568
/**********************************
 
2569
 *      R_DACMBCREL2H (0xD6)      *
 
2570
 **********************************/
 
2571
 
 
2572
/* Field Offsets */
 
2573
#define FB_DACMBCREL2H_TCRELH                0
 
2574
 
 
2575
/* Field Masks */
 
2576
#define FM_DACMBCREL2H_TCRELH                0XFF
 
2577
 
 
2578
/* Register Masks */
 
2579
#define RM_DACMBCREL2H_TCRELH \
 
2580
         RM(FM_DACMBCREL2H_TCRELH, FB_DACMBCREL2H_TCRELH)
 
2581
 
 
2582
 
 
2583
/*********************************
 
2584
 *      R_DACMBCMUG3 (0xD7)      *
 
2585
 *********************************/
 
2586
 
 
2587
/* Field Offsets */
 
2588
#define FB_DACMBCMUG3_PHASE                  5
 
2589
#define FB_DACMBCMUG3_MUGAIN                 0
 
2590
 
 
2591
/* Field Masks */
 
2592
#define FM_DACMBCMUG3_PHASE                  0X1
 
2593
#define FM_DACMBCMUG3_MUGAIN                 0X1F
 
2594
 
 
2595
/* Register Masks */
 
2596
#define RM_DACMBCMUG3_PHASE \
 
2597
         RM(FM_DACMBCMUG3_PHASE, FB_DACMBCMUG3_PHASE)
 
2598
 
 
2599
#define RM_DACMBCMUG3_MUGAIN \
 
2600
         RM(FM_DACMBCMUG3_MUGAIN, FB_DACMBCMUG3_MUGAIN)
 
2601
 
 
2602
 
 
2603
/*********************************
 
2604
 *      R_DACMBCTHR3 (0xD8)      *
 
2605
 *********************************/
 
2606
 
 
2607
/* Field Offsets */
 
2608
#define FB_DACMBCTHR3_THRESH                 0
 
2609
 
 
2610
/* Field Masks */
 
2611
#define FM_DACMBCTHR3_THRESH                 0XFF
 
2612
 
 
2613
/* Register Masks */
 
2614
#define RM_DACMBCTHR3_THRESH \
 
2615
         RM(FM_DACMBCTHR3_THRESH, FB_DACMBCTHR3_THRESH)
 
2616
 
 
2617
 
 
2618
/*********************************
 
2619
 *      R_DACMBCRAT3 (0xD9)      *
 
2620
 *********************************/
 
2621
 
 
2622
/* Field Offsets */
 
2623
#define FB_DACMBCRAT3_RATIO                  0
 
2624
 
 
2625
/* Field Masks */
 
2626
#define FM_DACMBCRAT3_RATIO                  0X1F
 
2627
 
 
2628
/* Register Masks */
 
2629
#define RM_DACMBCRAT3_RATIO \
 
2630
         RM(FM_DACMBCRAT3_RATIO, FB_DACMBCRAT3_RATIO)
 
2631
 
 
2632
 
 
2633
/**********************************
 
2634
 *      R_DACMBCATK3L (0xDA)      *
 
2635
 **********************************/
 
2636
 
 
2637
/* Field Offsets */
 
2638
#define FB_DACMBCATK3L_TCATKL                0
 
2639
 
 
2640
/* Field Masks */
 
2641
#define FM_DACMBCATK3L_TCATKL                0XFF
 
2642
 
 
2643
/* Register Masks */
 
2644
#define RM_DACMBCATK3L_TCATKL \
 
2645
         RM(FM_DACMBCATK3L_TCATKL, FB_DACMBCATK3L_TCATKL)
 
2646
 
 
2647
 
 
2648
/**********************************
 
2649
 *      R_DACMBCATK3H (0xDB)      *
 
2650
 **********************************/
 
2651
 
 
2652
/* Field Offsets */
 
2653
#define FB_DACMBCATK3H_TCATKH                0
 
2654
 
 
2655
/* Field Masks */
 
2656
#define FM_DACMBCATK3H_TCATKH                0XFF
 
2657
 
 
2658
/* Register Masks */
 
2659
#define RM_DACMBCATK3H_TCATKH \
 
2660
         RM(FM_DACMBCATK3H_TCATKH, FB_DACMBCATK3H_TCATKH)
 
2661
 
 
2662
 
 
2663
/**********************************
 
2664
 *      R_DACMBCREL3L (0xDC)      *
 
2665
 **********************************/
 
2666
 
 
2667
/* Field Offsets */
 
2668
#define FB_DACMBCREL3L_TCRELL                0
 
2669
 
 
2670
/* Field Masks */
 
2671
#define FM_DACMBCREL3L_TCRELL                0XFF
 
2672
 
 
2673
/* Register Masks */
 
2674
#define RM_DACMBCREL3L_TCRELL \
 
2675
         RM(FM_DACMBCREL3L_TCRELL, FB_DACMBCREL3L_TCRELL)
 
2676
 
 
2677
 
 
2678
/**********************************
 
2679
 *      R_DACMBCREL3H (0xDD)      *
 
2680
 **********************************/
 
2681
 
 
2682
/* Field Offsets */
 
2683
#define FB_DACMBCREL3H_TCRELH                0
 
2684
 
 
2685
/* Field Masks */
 
2686
#define FM_DACMBCREL3H_TCRELH                0XFF
 
2687
 
 
2688
/* Register Masks */
 
2689
#define RM_DACMBCREL3H_TCRELH \
 
2690
         RM(FM_DACMBCREL3H_TCRELH, FB_DACMBCREL3H_TCRELH)
 
2691
 
 
2692
 
 
2693
#endif /* __WOOKIE_H__ */