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* Driver for C-Media CMI8338 and 8738 PCI soundcards.
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* Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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/* Does not work. Warning may block system in capture mode */
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/* #define USE_VAR48KRATE */
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/gameport.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <sound/core.h>
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#include <sound/info.h>
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#include <sound/control.h>
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#include <sound/pcm.h>
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#include <sound/rawmidi.h>
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#include <sound/mpu401.h>
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#include <sound/opl3.h>
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#include <sound/asoundef.h>
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#include <sound/initval.h>
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MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
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MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
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MODULE_LICENSE("GPL");
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MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
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"{C-Media,CMI8338B}}");
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#if IS_REACHABLE(CONFIG_GAMEPORT)
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#define SUPPORT_JOYSTICK 1
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static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
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static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
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static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
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static long mpu_port[SNDRV_CARDS];
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static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
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static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
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#ifdef SUPPORT_JOYSTICK
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static int joystick_port[SNDRV_CARDS];
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module_param_array(index, int, NULL, 0444);
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MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
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module_param_array(id, charp, NULL, 0444);
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MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
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module_param_array(enable, bool, NULL, 0444);
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MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
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module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
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MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
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module_param_hw_array(fm_port, long, ioport, NULL, 0444);
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MODULE_PARM_DESC(fm_port, "FM port.");
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module_param_array(soft_ac3, bool, NULL, 0444);
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MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
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#ifdef SUPPORT_JOYSTICK
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module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
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MODULE_PARM_DESC(joystick_port, "Joystick port address.");
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* CM8x38 registers definition
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#define CM_REG_FUNCTRL0 0x00
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#define CM_RST_CH1 0x00080000
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#define CM_RST_CH0 0x00040000
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#define CM_CHEN1 0x00020000 /* ch1: enable */
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#define CM_CHEN0 0x00010000 /* ch0: enable */
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#define CM_PAUSE1 0x00000008 /* ch1: pause */
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#define CM_PAUSE0 0x00000004 /* ch0: pause */
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#define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
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#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
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#define CM_REG_FUNCTRL1 0x04
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#define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
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#define CM_DSFC_SHIFT 13
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#define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
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#define CM_ASFC_SHIFT 10
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#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
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#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
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#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
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#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
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#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
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#define CM_BREQ 0x00000010 /* bus master enabled */
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#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
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#define CM_UART_EN 0x00000004 /* legacy UART */
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#define CM_JYSTK_EN 0x00000002 /* legacy joystick */
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#define CM_ZVPORT 0x00000001 /* ZVPORT */
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#define CM_REG_CHFORMAT 0x08
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#define CM_CHB3D5C 0x80000000 /* 5,6 channels */
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#define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
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#define CM_CHB3D 0x20000000 /* 4 channels */
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#define CM_CHIP_MASK1 0x1f000000
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#define CM_CHIP_037 0x01000000
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#define CM_SETLAT48 0x00800000 /* set latency timer 48h */
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#define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
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#define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
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#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
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#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
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#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
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/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
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#define CM_ADCBITLEN_MASK 0x0000C000
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#define CM_ADCBITLEN_16 0x00000000
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#define CM_ADCBITLEN_15 0x00004000
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#define CM_ADCBITLEN_14 0x00008000
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#define CM_ADCBITLEN_13 0x0000C000
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#define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
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#define CM_ADCDACLEN_060 0x00000000
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#define CM_ADCDACLEN_066 0x00001000
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#define CM_ADCDACLEN_130 0x00002000
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#define CM_ADCDACLEN_280 0x00003000
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#define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
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#define CM_ADCDLEN_ORIGINAL 0x00000000
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#define CM_ADCDLEN_EXTRA 0x00001000
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#define CM_ADCDLEN_24K 0x00002000
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#define CM_ADCDLEN_WEIGHT 0x00003000
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#define CM_CH1_SRATE_176K 0x00000800
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#define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
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#define CM_CH1_SRATE_88K 0x00000400
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#define CM_CH0_SRATE_176K 0x00000200
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#define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
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#define CM_CH0_SRATE_88K 0x00000100
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#define CM_CH0_SRATE_128K 0x00000300
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#define CM_CH0_SRATE_MASK 0x00000300
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#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
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#define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
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#define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
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#define CM_SPDLOCKED 0x00000010
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#define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
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#define CM_CH1FMT_SHIFT 2
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#define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
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#define CM_CH0FMT_SHIFT 0
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#define CM_REG_INT_HLDCLR 0x0C
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#define CM_CHIP_MASK2 0xff000000
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#define CM_CHIP_8768 0x20000000
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#define CM_CHIP_055 0x08000000
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#define CM_CHIP_039 0x04000000
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#define CM_CHIP_039_6CH 0x01000000
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#define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
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#define CM_TDMA_INT_EN 0x00040000
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#define CM_CH1_INT_EN 0x00020000
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#define CM_CH0_INT_EN 0x00010000
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#define CM_REG_INT_STATUS 0x10
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#define CM_INTR 0x80000000
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#define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
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#define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
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#define CM_UARTINT 0x00010000
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#define CM_LTDMAINT 0x00008000
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#define CM_HTDMAINT 0x00004000
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#define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
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#define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
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#define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
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#define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
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#define CM_CH1BUSY 0x00000008
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#define CM_CH0BUSY 0x00000004
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#define CM_CHINT1 0x00000002
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#define CM_CHINT0 0x00000001
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#define CM_REG_LEGACY_CTRL 0x14
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#define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
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#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
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#define CM_VMPU_330 0x00000000
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#define CM_VMPU_320 0x20000000
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#define CM_VMPU_310 0x40000000
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#define CM_VMPU_300 0x60000000
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#define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
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#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
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#define CM_VSBSEL_220 0x00000000
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#define CM_VSBSEL_240 0x04000000
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#define CM_VSBSEL_260 0x08000000
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#define CM_VSBSEL_280 0x0C000000
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#define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
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#define CM_FMSEL_388 0x00000000
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#define CM_FMSEL_3C8 0x01000000
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#define CM_FMSEL_3E0 0x02000000
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#define CM_FMSEL_3E8 0x03000000
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#define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
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#define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
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#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
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#define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
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#define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
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#define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
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#define CM_C_EECS 0x00040000
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#define CM_C_EEDI46 0x00020000
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#define CM_C_EECK46 0x00010000
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#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
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#define CM_CENTR2LIN 0x00004000 /* line-in as center out */
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#define CM_BASE2LIN 0x00002000 /* line-in as bass out */
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#define CM_EXBASEN 0x00001000 /* external bass input enable */
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#define CM_REG_MISC_CTRL 0x18
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#define CM_PWD 0x80000000 /* power down */
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#define CM_RESET 0x40000000
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#define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
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#define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
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#define CM_TXVX 0x08000000 /* model 037? */
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#define CM_N4SPK3D 0x04000000 /* copy front to rear */
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#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
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#define CM_SPDIF48K 0x01000000 /* write */
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#define CM_SPATUS48K 0x01000000 /* read */
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#define CM_ENDBDAC 0x00800000 /* enable double dac */
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#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
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#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
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#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
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#define CM_FM_EN 0x00080000 /* enable legacy FM */
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#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
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#define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
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#define CM_VIDWPDSB 0x00010000 /* model 037? */
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#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
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#define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
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#define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
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#define CM_VIDWPPRT 0x00002000 /* model 037? */
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#define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
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#define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
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#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
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#define CM_ENCENTER 0x00000080
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#define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
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#define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
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#define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
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#define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
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#define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
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#define CM_UPDDMA_2048 0x00000000
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#define CM_UPDDMA_1024 0x00000004
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#define CM_UPDDMA_512 0x00000008
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#define CM_UPDDMA_256 0x0000000C
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#define CM_TWAIT_MASK 0x00000003 /* model 037 */
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#define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
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#define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
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#define CM_REG_TDMA_POSITION 0x1C
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#define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
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#define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
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#define CM_REG_MIXER0 0x20
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#define CM_REG_SBVR 0x20 /* write: sb16 version */
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#define CM_REG_DEV 0x20 /* read: hardware device version */
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#define CM_REG_MIXER21 0x21
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#define CM_UNKNOWN_21_MASK 0x78 /* ? */
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#define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
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#define CM_PROINV 0x02 /* SBPro left/right channel switching */
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#define CM_X_SB16 0x01 /* SB16 compatible */
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#define CM_REG_SB16_DATA 0x22
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#define CM_REG_SB16_ADDR 0x23
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#define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
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#define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
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#define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
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#define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
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#define CM_REG_MIXER1 0x24
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#define CM_FMMUTE 0x80 /* mute FM */
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#define CM_FMMUTE_SHIFT 7
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#define CM_WSMUTE 0x40 /* mute PCM */
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#define CM_WSMUTE_SHIFT 6
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#define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
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#define CM_REAR2LIN_SHIFT 5
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#define CM_REAR2FRONT 0x10 /* exchange rear/front */
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#define CM_REAR2FRONT_SHIFT 4
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#define CM_WAVEINL 0x08 /* digital wave rec. left chan */
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#define CM_WAVEINL_SHIFT 3
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#define CM_WAVEINR 0x04 /* digical wave rec. right */
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#define CM_WAVEINR_SHIFT 2
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#define CM_X3DEN 0x02 /* 3D surround enable */
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#define CM_X3DEN_SHIFT 1
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#define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
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#define CM_CDPLAY_SHIFT 0
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#define CM_REG_MIXER2 0x25
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#define CM_RAUXREN 0x80 /* AUX right capture */
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#define CM_RAUXREN_SHIFT 7
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#define CM_RAUXLEN 0x40 /* AUX left capture */
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#define CM_RAUXLEN_SHIFT 6
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#define CM_VAUXRM 0x20 /* AUX right mute */
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#define CM_VAUXRM_SHIFT 5
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#define CM_VAUXLM 0x10 /* AUX left mute */
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#define CM_VAUXLM_SHIFT 4
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#define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
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#define CM_VADMIC_SHIFT 1
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#define CM_MICGAINZ 0x01 /* mic boost */
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#define CM_MICGAINZ_SHIFT 0
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#define CM_REG_MIXER3 0x24
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#define CM_REG_AUX_VOL 0x26
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#define CM_VAUXL_MASK 0xf0
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#define CM_VAUXR_MASK 0x0f
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#define CM_REG_MISC 0x27
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#define CM_UNKNOWN_27_MASK 0xd8 /* ? */
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#define CM_XGPO1 0x20
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// #define CM_XGPBIO 0x04
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#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
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#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
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#define CM_SPDVALID 0x02 /* spdif input valid check */
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#define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
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#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
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* For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
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* or identical with AC97 codec?
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#define CM_REG_EXTERN_CODEC CM_REG_AC97
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* MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
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#define CM_REG_MPU_PCI 0x40
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* FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
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#define CM_REG_FM_PCI 0x50
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* access from SB-mixer port
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#define CM_REG_EXTENT_IND 0xf0
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#define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
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#define CM_VPHONE_SHIFT 5
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#define CM_VPHOM 0x10 /* Phone mute control */
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#define CM_VSPKM 0x08 /* Speaker mute control, default high */
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#define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
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#define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
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#define CM_VADMIC3 0x01 /* Mic record boost */
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* CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
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* the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
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#define CM_REG_PLL 0xf8
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#define CM_REG_CH0_FRAME1 0x80 /* write: base address */
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#define CM_REG_CH0_FRAME2 0x84 /* read: current address */
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#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
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#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
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#define CM_REG_EXT_MISC 0x90
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#define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
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#define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
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#define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
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#define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
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#define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
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#define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
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#define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
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#define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
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#define CM_EXTENT_CODEC 0x100
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#define CM_EXTENT_MIDI 0x2
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#define CM_EXTENT_SYNTH 0x4
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* channels for playback / capture
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* flags to check device open/close
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#define CM_OPEN_NONE 0
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#define CM_OPEN_CH_MASK 0x01
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#define CM_OPEN_DAC 0x10
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#define CM_OPEN_ADC 0x20
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#define CM_OPEN_SPDIF 0x40
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#define CM_OPEN_MCHAN 0x80
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#define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
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#define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
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#define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
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#define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
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#define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
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#define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
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#define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
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#define CM_PLAYBACK_SPDF CM_SPDF_1
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#define CM_CAPTURE_SPDF CM_SPDF_0
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#define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
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#define CM_PLAYBACK_SPDF CM_SPDF_0
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#define CM_CAPTURE_SPDF CM_SPDF_1
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struct snd_pcm_substream *substream;
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u8 running; /* dac/adc running? */
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u8 fmt; /* format bits */
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unsigned int dma_size; /* in frames */
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unsigned int ch; /* channel (0/1) */
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unsigned int offset; /* physical address of the buffer */
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/* mixer elements toggled/resumed during ac3 playback */
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struct cmipci_mixer_auto_switches {
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const char *name; /* switch to toggle */
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int toggle_on; /* value to change when ac3 mode */
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static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
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{"PCM Playback Switch", 0},
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{"IEC958 Output Switch", 1},
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{"IEC958 Mix Analog", 0},
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// {"IEC958 Out To DAC", 1}, // no longer used
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#define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
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struct snd_card *card;
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unsigned int device; /* device ID */
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unsigned long iobase;
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unsigned int ctrl; /* FUNCTRL0 current value */
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struct snd_pcm *pcm; /* DAC/ADC PCM */
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struct snd_pcm *pcm2; /* 2nd DAC */
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struct snd_pcm *pcm_spdif; /* SPDIF */
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unsigned int can_ac3_sw: 1;
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unsigned int can_ac3_hw: 1;
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unsigned int can_multi_ch: 1;
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unsigned int can_96k: 1; /* samplerate above 48k */
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unsigned int do_soft_ac3: 1;
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unsigned int spdif_playback_avail: 1; /* spdif ready? */
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unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
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int spdif_counter; /* for software AC3 */
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unsigned int dig_status;
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unsigned int dig_pcm_status;
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struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
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int opened[2]; /* open mode */
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struct mutex open_mutex;
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unsigned int mixer_insensitive: 1;
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struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
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int mixer_res_status[CM_SAVED_MIXERS];
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struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
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struct snd_rawmidi *rmidi;
501
#ifdef SUPPORT_JOYSTICK
502
struct gameport *gameport;
507
#ifdef CONFIG_PM_SLEEP
508
unsigned int saved_regs[0x20];
509
unsigned char saved_mixers[0x20];
514
/* read/write operations for dword register */
515
static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
517
outl(data, cm->iobase + cmd);
520
static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
522
return inl(cm->iobase + cmd);
525
/* read/write operations for word register */
526
static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
528
outw(data, cm->iobase + cmd);
531
static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
533
return inw(cm->iobase + cmd);
536
/* read/write operations for byte register */
537
static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
539
outb(data, cm->iobase + cmd);
542
static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
544
return inb(cm->iobase + cmd);
547
/* bit operations for dword register */
548
static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
550
unsigned int val, oval;
551
val = oval = inl(cm->iobase + cmd);
555
outl(val, cm->iobase + cmd);
559
static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
561
unsigned int val, oval;
562
val = oval = inl(cm->iobase + cmd);
566
outl(val, cm->iobase + cmd);
570
/* bit operations for byte register */
571
static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
573
unsigned char val, oval;
574
val = oval = inb(cm->iobase + cmd);
578
outb(val, cm->iobase + cmd);
582
static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
584
unsigned char val, oval;
585
val = oval = inb(cm->iobase + cmd);
589
outb(val, cm->iobase + cmd);
599
* calculate frequency
602
static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
604
static unsigned int snd_cmipci_rate_freq(unsigned int rate)
608
for (i = 0; i < ARRAY_SIZE(rates); i++) {
609
if (rates[i] == rate)
616
#ifdef USE_VAR48KRATE
618
* Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
619
* does it this way .. maybe not. Never get any information from C-Media about
620
* that <werner@suse.de>.
622
static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
624
unsigned int delta, tolerance;
627
for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
632
tolerance = rate*CM_TOLERANCE_RATE;
634
for (xn = (1+2); xn < (0x1f+2); xn++) {
635
for (xm = (1+2); xm < (0xff+2); xm++) {
636
xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
644
* If we found one, remember this,
645
* and try to find a closer one
647
if (delta < tolerance) {
659
* Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
660
* are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
661
* at the register CM_REG_FUNCTRL1 (0x04).
662
* Problem: other ways are also possible (any information about that?)
664
static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
666
unsigned int reg = CM_REG_PLL + slot;
668
* Guess that this programs at reg. 0x04 the pos 15:13/12:10
669
* for DSFC/ASFC (000 up to 111).
672
/* FIXME: Init (Do we've to set an other register first before programming?) */
674
/* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
675
snd_cmipci_write_b(cm, reg, rate>>8);
676
snd_cmipci_write_b(cm, reg, rate&0xff);
678
/* FIXME: Setup (Do we've to set an other register first to enable this?) */
680
#endif /* USE_VAR48KRATE */
682
static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
683
struct snd_pcm_hw_params *hw_params)
685
return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
688
static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
689
struct snd_pcm_hw_params *hw_params)
691
struct cmipci *cm = snd_pcm_substream_chip(substream);
692
if (params_channels(hw_params) > 2) {
693
mutex_lock(&cm->open_mutex);
694
if (cm->opened[CM_CH_PLAY]) {
695
mutex_unlock(&cm->open_mutex);
698
/* reserve the channel A */
699
cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
700
mutex_unlock(&cm->open_mutex);
702
return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
705
static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
707
int reset = CM_RST_CH0 << (cm->channel[ch].ch);
708
snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
709
snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
713
static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
715
return snd_pcm_lib_free_pages(substream);
722
static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
723
static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
728
static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
733
static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
739
static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
742
if (!cm->can_multi_ch || !rec->ch)
744
if (rec->fmt != 0x03) /* stereo 16bit only */
748
if (cm->can_multi_ch) {
749
spin_lock_irq(&cm->reg_lock);
751
snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
752
snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
754
snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
755
snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
758
snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
760
snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
762
snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
763
snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
765
snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
766
snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
769
snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
771
snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
772
spin_unlock_irq(&cm->reg_lock);
779
* prepare playback/capture channel
780
* channel to be used must have been set in rec->ch.
782
static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
783
struct snd_pcm_substream *substream)
785
unsigned int reg, freq, freq_ext, val;
786
unsigned int period_size;
787
struct snd_pcm_runtime *runtime = substream->runtime;
791
if (snd_pcm_format_width(runtime->format) >= 16) {
793
if (snd_pcm_format_width(runtime->format) > 16)
794
rec->shift++; /* 24/32bit */
796
if (runtime->channels > 1)
798
if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
799
dev_dbg(cm->card->dev, "cannot set dac channels\n");
803
rec->offset = runtime->dma_addr;
804
/* buffer and period sizes in frame */
805
rec->dma_size = runtime->buffer_size << rec->shift;
806
period_size = runtime->period_size << rec->shift;
807
if (runtime->channels > 2) {
809
rec->dma_size = (rec->dma_size * runtime->channels) / 2;
810
period_size = (period_size * runtime->channels) / 2;
813
spin_lock_irq(&cm->reg_lock);
815
/* set buffer address */
816
reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
817
snd_cmipci_write(cm, reg, rec->offset);
818
/* program sample counts */
819
reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
820
snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
821
snd_cmipci_write_w(cm, reg + 2, period_size - 1);
823
/* set adc/dac flag */
824
val = rec->ch ? CM_CHADC1 : CM_CHADC0;
829
snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
830
/* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
832
/* set sample rate */
835
if (runtime->rate > 48000)
836
switch (runtime->rate) {
837
case 88200: freq_ext = CM_CH0_SRATE_88K; break;
838
case 96000: freq_ext = CM_CH0_SRATE_96K; break;
839
case 128000: freq_ext = CM_CH0_SRATE_128K; break;
840
default: snd_BUG(); break;
843
freq = snd_cmipci_rate_freq(runtime->rate);
844
val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
846
val &= ~CM_DSFC_MASK;
847
val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
849
val &= ~CM_ASFC_MASK;
850
val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
852
snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
853
dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
856
val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
858
val &= ~CM_CH1FMT_MASK;
859
val |= rec->fmt << CM_CH1FMT_SHIFT;
861
val &= ~CM_CH0FMT_MASK;
862
val |= rec->fmt << CM_CH0FMT_SHIFT;
865
val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
866
val |= freq_ext << (rec->ch * 2);
868
snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
869
dev_dbg(cm->card->dev, "chformat = %08x\n", val);
871
if (!rec->is_dac && cm->chip_version) {
872
if (runtime->rate > 44100)
873
snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
875
snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
879
spin_unlock_irq(&cm->reg_lock);
887
static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
890
unsigned int inthld, chen, reset, pause;
893
inthld = CM_CH0_INT_EN << rec->ch;
894
chen = CM_CHEN0 << rec->ch;
895
reset = CM_RST_CH0 << rec->ch;
896
pause = CM_PAUSE0 << rec->ch;
898
spin_lock(&cm->reg_lock);
900
case SNDRV_PCM_TRIGGER_START:
903
snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
906
snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
907
dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
909
case SNDRV_PCM_TRIGGER_STOP:
911
/* disable interrupt */
912
snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
915
snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
916
snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
917
rec->needs_silencing = rec->is_dac;
919
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
920
case SNDRV_PCM_TRIGGER_SUSPEND:
922
snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
924
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
925
case SNDRV_PCM_TRIGGER_RESUME:
927
snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
933
spin_unlock(&cm->reg_lock);
938
* return the current pointer
940
static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
941
struct snd_pcm_substream *substream)
944
unsigned int reg, rem, tries;
948
#if 1 // this seems better..
949
reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
950
for (tries = 0; tries < 3; tries++) {
951
rem = snd_cmipci_read_w(cm, reg);
952
if (rem < rec->dma_size)
955
dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
956
return SNDRV_PCM_POS_XRUN;
958
ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
960
reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
961
ptr = snd_cmipci_read(cm, reg) - rec->offset;
962
ptr = bytes_to_frames(substream->runtime, ptr);
964
if (substream->runtime->channels > 2)
965
ptr = (ptr * 2) / substream->runtime->channels;
973
static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
976
struct cmipci *cm = snd_pcm_substream_chip(substream);
977
return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
980
static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
982
struct cmipci *cm = snd_pcm_substream_chip(substream);
983
return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
992
static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
995
struct cmipci *cm = snd_pcm_substream_chip(substream);
996
return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
999
static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
1001
struct cmipci *cm = snd_pcm_substream_chip(substream);
1002
return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
1007
* hw preparation for spdif
1010
static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
1011
struct snd_ctl_elem_info *uinfo)
1013
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1018
static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
1019
struct snd_ctl_elem_value *ucontrol)
1021
struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1024
spin_lock_irq(&chip->reg_lock);
1025
for (i = 0; i < 4; i++)
1026
ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1027
spin_unlock_irq(&chip->reg_lock);
1031
static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1032
struct snd_ctl_elem_value *ucontrol)
1034
struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1039
spin_lock_irq(&chip->reg_lock);
1040
for (i = 0; i < 4; i++)
1041
val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1042
change = val != chip->dig_status;
1043
chip->dig_status = val;
1044
spin_unlock_irq(&chip->reg_lock);
1048
static const struct snd_kcontrol_new snd_cmipci_spdif_default =
1050
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1051
.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1052
.info = snd_cmipci_spdif_default_info,
1053
.get = snd_cmipci_spdif_default_get,
1054
.put = snd_cmipci_spdif_default_put
1057
static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1058
struct snd_ctl_elem_info *uinfo)
1060
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1065
static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1066
struct snd_ctl_elem_value *ucontrol)
1068
ucontrol->value.iec958.status[0] = 0xff;
1069
ucontrol->value.iec958.status[1] = 0xff;
1070
ucontrol->value.iec958.status[2] = 0xff;
1071
ucontrol->value.iec958.status[3] = 0xff;
1075
static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
1077
.access = SNDRV_CTL_ELEM_ACCESS_READ,
1078
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1079
.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1080
.info = snd_cmipci_spdif_mask_info,
1081
.get = snd_cmipci_spdif_mask_get,
1084
static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1085
struct snd_ctl_elem_info *uinfo)
1087
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1092
static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1093
struct snd_ctl_elem_value *ucontrol)
1095
struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1098
spin_lock_irq(&chip->reg_lock);
1099
for (i = 0; i < 4; i++)
1100
ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1101
spin_unlock_irq(&chip->reg_lock);
1105
static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1106
struct snd_ctl_elem_value *ucontrol)
1108
struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1113
spin_lock_irq(&chip->reg_lock);
1114
for (i = 0; i < 4; i++)
1115
val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1116
change = val != chip->dig_pcm_status;
1117
chip->dig_pcm_status = val;
1118
spin_unlock_irq(&chip->reg_lock);
1122
static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
1124
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1125
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1126
.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1127
.info = snd_cmipci_spdif_stream_info,
1128
.get = snd_cmipci_spdif_stream_get,
1129
.put = snd_cmipci_spdif_stream_put
1135
/* save mixer setting and mute for AC3 playback */
1136
static int save_mixer_state(struct cmipci *cm)
1138
if (! cm->mixer_insensitive) {
1139
struct snd_ctl_elem_value *val;
1142
val = kmalloc(sizeof(*val), GFP_KERNEL);
1145
for (i = 0; i < CM_SAVED_MIXERS; i++) {
1146
struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1149
memset(val, 0, sizeof(*val));
1151
cm->mixer_res_status[i] = val->value.integer.value[0];
1152
val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1153
event = SNDRV_CTL_EVENT_MASK_INFO;
1154
if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1155
ctl->put(ctl, val); /* toggle */
1156
event |= SNDRV_CTL_EVENT_MASK_VALUE;
1158
ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1159
snd_ctl_notify(cm->card, event, &ctl->id);
1163
cm->mixer_insensitive = 1;
1169
/* restore the previously saved mixer status */
1170
static void restore_mixer_state(struct cmipci *cm)
1172
if (cm->mixer_insensitive) {
1173
struct snd_ctl_elem_value *val;
1176
val = kmalloc(sizeof(*val), GFP_KERNEL);
1179
cm->mixer_insensitive = 0; /* at first clear this;
1180
otherwise the changes will be ignored */
1181
for (i = 0; i < CM_SAVED_MIXERS; i++) {
1182
struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1186
memset(val, 0, sizeof(*val));
1187
ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1189
event = SNDRV_CTL_EVENT_MASK_INFO;
1190
if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1191
val->value.integer.value[0] = cm->mixer_res_status[i];
1193
event |= SNDRV_CTL_EVENT_MASK_VALUE;
1195
snd_ctl_notify(cm->card, event, &ctl->id);
1202
/* spinlock held! */
1203
static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1207
snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1209
snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1211
if (cm->can_ac3_hw) {
1212
/* SPD24SEL for 037, 0x02 */
1213
/* SPD24SEL for 039, 0x20, but cannot be set */
1214
snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1215
snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1216
} else { /* can_ac3_sw */
1217
/* SPD32SEL for 037 & 039, 0x20 */
1218
snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1219
/* set 176K sample rate to fix 033 HW bug */
1220
if (cm->chip_version == 33) {
1221
if (rate >= 48000) {
1222
snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1224
snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1230
snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1231
snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1233
if (cm->can_ac3_hw) {
1234
/* chip model >= 37 */
1235
if (snd_pcm_format_width(subs->runtime->format) > 16) {
1236
snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1237
snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1239
snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1240
snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1243
snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1244
snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1245
snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1250
static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1254
rate = subs->runtime->rate;
1257
if ((err = save_mixer_state(cm)) < 0)
1260
spin_lock_irq(&cm->reg_lock);
1261
cm->spdif_playback_avail = up;
1263
/* they are controlled via "IEC958 Output Switch" */
1264
/* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1265
/* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1266
if (cm->spdif_playback_enabled)
1267
snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1268
setup_ac3(cm, subs, do_ac3, rate);
1270
if (rate == 48000 || rate == 96000)
1271
snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1273
snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1275
snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1277
snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1279
/* they are controlled via "IEC958 Output Switch" */
1280
/* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1281
/* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1282
snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1283
snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1284
setup_ac3(cm, subs, 0, 0);
1286
spin_unlock_irq(&cm->reg_lock);
1295
/* playback - enable spdif only on the certain condition */
1296
static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1298
struct cmipci *cm = snd_pcm_substream_chip(substream);
1299
int rate = substream->runtime->rate;
1300
int err, do_spdif, do_ac3 = 0;
1302
do_spdif = (rate >= 44100 && rate <= 96000 &&
1303
substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1304
substream->runtime->channels == 2);
1305
if (do_spdif && cm->can_ac3_hw)
1306
do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1307
if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1309
return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1312
/* playback (via device #2) - enable spdif always */
1313
static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1315
struct cmipci *cm = snd_pcm_substream_chip(substream);
1319
do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1321
do_ac3 = 1; /* doesn't matter */
1322
if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1324
return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1328
* Apparently, the samples last played on channel A stay in some buffer, even
1329
* after the channel is reset, and get added to the data for the rear DACs when
1330
* playing a multichannel stream on channel B. This is likely to generate
1331
* wraparounds and thus distortions.
1332
* To avoid this, we play at least one zero sample after the actual stream has
1335
static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1337
struct snd_pcm_runtime *runtime = rec->substream->runtime;
1338
unsigned int reg, val;
1340
if (rec->needs_silencing && runtime && runtime->dma_area) {
1341
/* set up a small silence buffer */
1342
memset(runtime->dma_area, 0, PAGE_SIZE);
1343
reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1344
val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1345
snd_cmipci_write(cm, reg, val);
1347
/* configure for 16 bits, 2 channels, 8 kHz */
1348
if (runtime->channels > 2)
1349
set_dac_channels(cm, rec, 2);
1350
spin_lock_irq(&cm->reg_lock);
1351
val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1352
val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1353
val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1354
snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1355
val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1356
val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1357
val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1359
val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1360
snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1362
/* start stream (we don't need interrupts) */
1363
cm->ctrl |= CM_CHEN0 << rec->ch;
1364
snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1365
spin_unlock_irq(&cm->reg_lock);
1369
/* stop and reset stream */
1370
spin_lock_irq(&cm->reg_lock);
1371
cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1372
val = CM_RST_CH0 << rec->ch;
1373
snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1374
snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1375
spin_unlock_irq(&cm->reg_lock);
1377
rec->needs_silencing = 0;
1381
static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1383
struct cmipci *cm = snd_pcm_substream_chip(substream);
1384
setup_spdif_playback(cm, substream, 0, 0);
1385
restore_mixer_state(cm);
1386
snd_cmipci_silence_hack(cm, &cm->channel[0]);
1387
return snd_cmipci_hw_free(substream);
1390
static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1392
struct cmipci *cm = snd_pcm_substream_chip(substream);
1393
snd_cmipci_silence_hack(cm, &cm->channel[1]);
1394
return snd_cmipci_hw_free(substream);
1398
static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1400
struct cmipci *cm = snd_pcm_substream_chip(substream);
1401
return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1404
/* capture with spdif (via device #2) */
1405
static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1407
struct cmipci *cm = snd_pcm_substream_chip(substream);
1409
spin_lock_irq(&cm->reg_lock);
1410
snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1412
if (substream->runtime->rate > 48000)
1413
snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1415
snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1417
if (snd_pcm_format_width(substream->runtime->format) > 16)
1418
snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1420
snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1422
spin_unlock_irq(&cm->reg_lock);
1424
return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1427
static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1429
struct cmipci *cm = snd_pcm_substream_chip(subs);
1431
spin_lock_irq(&cm->reg_lock);
1432
snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1433
snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1434
spin_unlock_irq(&cm->reg_lock);
1436
return snd_cmipci_hw_free(subs);
1443
static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1445
struct cmipci *cm = dev_id;
1446
unsigned int status, mask = 0;
1448
/* fastpath out, to ease interrupt sharing */
1449
status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1450
if (!(status & CM_INTR))
1453
/* acknowledge interrupt */
1454
spin_lock(&cm->reg_lock);
1455
if (status & CM_CHINT0)
1456
mask |= CM_CH0_INT_EN;
1457
if (status & CM_CHINT1)
1458
mask |= CM_CH1_INT_EN;
1459
snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1460
snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1461
spin_unlock(&cm->reg_lock);
1463
if (cm->rmidi && (status & CM_UARTINT))
1464
snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1467
if ((status & CM_CHINT0) && cm->channel[0].running)
1468
snd_pcm_period_elapsed(cm->channel[0].substream);
1469
if ((status & CM_CHINT1) && cm->channel[1].running)
1470
snd_pcm_period_elapsed(cm->channel[1].substream);
1479
/* playback on channel A */
1480
static const struct snd_pcm_hardware snd_cmipci_playback =
1482
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1483
SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1484
SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1485
.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1486
.rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1491
.buffer_bytes_max = (128*1024),
1492
.period_bytes_min = 64,
1493
.period_bytes_max = (128*1024),
1495
.periods_max = 1024,
1499
/* capture on channel B */
1500
static const struct snd_pcm_hardware snd_cmipci_capture =
1502
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1503
SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1504
SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1505
.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1506
.rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1511
.buffer_bytes_max = (128*1024),
1512
.period_bytes_min = 64,
1513
.period_bytes_max = (128*1024),
1515
.periods_max = 1024,
1519
/* playback on channel B - stereo 16bit only? */
1520
static const struct snd_pcm_hardware snd_cmipci_playback2 =
1522
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1523
SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1524
SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1525
.formats = SNDRV_PCM_FMTBIT_S16_LE,
1526
.rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1531
.buffer_bytes_max = (128*1024),
1532
.period_bytes_min = 64,
1533
.period_bytes_max = (128*1024),
1535
.periods_max = 1024,
1539
/* spdif playback on channel A */
1540
static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
1542
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1543
SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1544
SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1545
.formats = SNDRV_PCM_FMTBIT_S16_LE,
1546
.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1551
.buffer_bytes_max = (128*1024),
1552
.period_bytes_min = 64,
1553
.period_bytes_max = (128*1024),
1555
.periods_max = 1024,
1559
/* spdif playback on channel A (32bit, IEC958 subframes) */
1560
static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1562
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1563
SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1564
SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1565
.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1566
.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1571
.buffer_bytes_max = (128*1024),
1572
.period_bytes_min = 64,
1573
.period_bytes_max = (128*1024),
1575
.periods_max = 1024,
1579
/* spdif capture on channel B */
1580
static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
1582
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1583
SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1584
SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1585
.formats = SNDRV_PCM_FMTBIT_S16_LE |
1586
SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1587
.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1592
.buffer_bytes_max = (128*1024),
1593
.period_bytes_min = 64,
1594
.period_bytes_max = (128*1024),
1596
.periods_max = 1024,
1600
static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1601
32000, 44100, 48000, 88200, 96000, 128000 };
1602
static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1603
.count = ARRAY_SIZE(rate_constraints),
1604
.list = rate_constraints,
1609
* check device open/close
1611
static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1613
int ch = mode & CM_OPEN_CH_MASK;
1615
/* FIXME: a file should wait until the device becomes free
1616
* when it's opened on blocking mode. however, since the current
1617
* pcm framework doesn't pass file pointer before actually opened,
1618
* we can't know whether blocking mode or not in open callback..
1620
mutex_lock(&cm->open_mutex);
1621
if (cm->opened[ch]) {
1622
mutex_unlock(&cm->open_mutex);
1625
cm->opened[ch] = mode;
1626
cm->channel[ch].substream = subs;
1627
if (! (mode & CM_OPEN_DAC)) {
1628
/* disable dual DAC mode */
1629
cm->channel[ch].is_dac = 0;
1630
spin_lock_irq(&cm->reg_lock);
1631
snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1632
spin_unlock_irq(&cm->reg_lock);
1634
mutex_unlock(&cm->open_mutex);
1638
static void close_device_check(struct cmipci *cm, int mode)
1640
int ch = mode & CM_OPEN_CH_MASK;
1642
mutex_lock(&cm->open_mutex);
1643
if (cm->opened[ch] == mode) {
1644
if (cm->channel[ch].substream) {
1645
snd_cmipci_ch_reset(cm, ch);
1646
cm->channel[ch].running = 0;
1647
cm->channel[ch].substream = NULL;
1650
if (! cm->channel[ch].is_dac) {
1651
/* enable dual DAC mode again */
1652
cm->channel[ch].is_dac = 1;
1653
spin_lock_irq(&cm->reg_lock);
1654
snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1655
spin_unlock_irq(&cm->reg_lock);
1658
mutex_unlock(&cm->open_mutex);
1664
static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1666
struct cmipci *cm = snd_pcm_substream_chip(substream);
1667
struct snd_pcm_runtime *runtime = substream->runtime;
1670
if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1672
runtime->hw = snd_cmipci_playback;
1673
if (cm->chip_version == 68) {
1674
runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1675
SNDRV_PCM_RATE_96000;
1676
runtime->hw.rate_max = 96000;
1677
} else if (cm->chip_version == 55) {
1678
err = snd_pcm_hw_constraint_list(runtime, 0,
1679
SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1682
runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1683
runtime->hw.rate_max = 128000;
1685
snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1686
cm->dig_pcm_status = cm->dig_status;
1690
static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1692
struct cmipci *cm = snd_pcm_substream_chip(substream);
1693
struct snd_pcm_runtime *runtime = substream->runtime;
1696
if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1698
runtime->hw = snd_cmipci_capture;
1699
if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1700
runtime->hw.rate_min = 41000;
1701
runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1702
} else if (cm->chip_version == 55) {
1703
err = snd_pcm_hw_constraint_list(runtime, 0,
1704
SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1707
runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1708
runtime->hw.rate_max = 128000;
1710
snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1714
static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1716
struct cmipci *cm = snd_pcm_substream_chip(substream);
1717
struct snd_pcm_runtime *runtime = substream->runtime;
1720
if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1722
runtime->hw = snd_cmipci_playback2;
1723
mutex_lock(&cm->open_mutex);
1724
if (! cm->opened[CM_CH_PLAY]) {
1725
if (cm->can_multi_ch) {
1726
runtime->hw.channels_max = cm->max_channels;
1727
if (cm->max_channels == 4)
1728
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1729
else if (cm->max_channels == 6)
1730
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1731
else if (cm->max_channels == 8)
1732
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1735
mutex_unlock(&cm->open_mutex);
1736
if (cm->chip_version == 68) {
1737
runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1738
SNDRV_PCM_RATE_96000;
1739
runtime->hw.rate_max = 96000;
1740
} else if (cm->chip_version == 55) {
1741
err = snd_pcm_hw_constraint_list(runtime, 0,
1742
SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1745
runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1746
runtime->hw.rate_max = 128000;
1748
snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1752
static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1754
struct cmipci *cm = snd_pcm_substream_chip(substream);
1755
struct snd_pcm_runtime *runtime = substream->runtime;
1758
if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1760
if (cm->can_ac3_hw) {
1761
runtime->hw = snd_cmipci_playback_spdif;
1762
if (cm->chip_version >= 37) {
1763
runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1764
snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1767
runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1768
SNDRV_PCM_RATE_96000;
1769
runtime->hw.rate_max = 96000;
1772
runtime->hw = snd_cmipci_playback_iec958_subframe;
1774
snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1775
cm->dig_pcm_status = cm->dig_status;
1779
static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1781
struct cmipci *cm = snd_pcm_substream_chip(substream);
1782
struct snd_pcm_runtime *runtime = substream->runtime;
1785
if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1787
runtime->hw = snd_cmipci_capture_spdif;
1788
if (cm->can_96k && !(cm->chip_version == 68)) {
1789
runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1790
SNDRV_PCM_RATE_96000;
1791
runtime->hw.rate_max = 96000;
1793
snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1801
static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1803
struct cmipci *cm = snd_pcm_substream_chip(substream);
1804
close_device_check(cm, CM_OPEN_PLAYBACK);
1808
static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1810
struct cmipci *cm = snd_pcm_substream_chip(substream);
1811
close_device_check(cm, CM_OPEN_CAPTURE);
1815
static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1817
struct cmipci *cm = snd_pcm_substream_chip(substream);
1818
close_device_check(cm, CM_OPEN_PLAYBACK2);
1819
close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1823
static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1825
struct cmipci *cm = snd_pcm_substream_chip(substream);
1826
close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1830
static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1832
struct cmipci *cm = snd_pcm_substream_chip(substream);
1833
close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1841
static const struct snd_pcm_ops snd_cmipci_playback_ops = {
1842
.open = snd_cmipci_playback_open,
1843
.close = snd_cmipci_playback_close,
1844
.ioctl = snd_pcm_lib_ioctl,
1845
.hw_params = snd_cmipci_hw_params,
1846
.hw_free = snd_cmipci_playback_hw_free,
1847
.prepare = snd_cmipci_playback_prepare,
1848
.trigger = snd_cmipci_playback_trigger,
1849
.pointer = snd_cmipci_playback_pointer,
1852
static const struct snd_pcm_ops snd_cmipci_capture_ops = {
1853
.open = snd_cmipci_capture_open,
1854
.close = snd_cmipci_capture_close,
1855
.ioctl = snd_pcm_lib_ioctl,
1856
.hw_params = snd_cmipci_hw_params,
1857
.hw_free = snd_cmipci_hw_free,
1858
.prepare = snd_cmipci_capture_prepare,
1859
.trigger = snd_cmipci_capture_trigger,
1860
.pointer = snd_cmipci_capture_pointer,
1863
static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
1864
.open = snd_cmipci_playback2_open,
1865
.close = snd_cmipci_playback2_close,
1866
.ioctl = snd_pcm_lib_ioctl,
1867
.hw_params = snd_cmipci_playback2_hw_params,
1868
.hw_free = snd_cmipci_playback2_hw_free,
1869
.prepare = snd_cmipci_capture_prepare, /* channel B */
1870
.trigger = snd_cmipci_capture_trigger, /* channel B */
1871
.pointer = snd_cmipci_capture_pointer, /* channel B */
1874
static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1875
.open = snd_cmipci_playback_spdif_open,
1876
.close = snd_cmipci_playback_spdif_close,
1877
.ioctl = snd_pcm_lib_ioctl,
1878
.hw_params = snd_cmipci_hw_params,
1879
.hw_free = snd_cmipci_playback_hw_free,
1880
.prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1881
.trigger = snd_cmipci_playback_trigger,
1882
.pointer = snd_cmipci_playback_pointer,
1885
static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1886
.open = snd_cmipci_capture_spdif_open,
1887
.close = snd_cmipci_capture_spdif_close,
1888
.ioctl = snd_pcm_lib_ioctl,
1889
.hw_params = snd_cmipci_hw_params,
1890
.hw_free = snd_cmipci_capture_spdif_hw_free,
1891
.prepare = snd_cmipci_capture_spdif_prepare,
1892
.trigger = snd_cmipci_capture_trigger,
1893
.pointer = snd_cmipci_capture_pointer,
1900
static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1902
struct snd_pcm *pcm;
1905
err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1909
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1910
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1912
pcm->private_data = cm;
1913
pcm->info_flags = 0;
1914
strcpy(pcm->name, "C-Media PCI DAC/ADC");
1917
snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1918
snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1923
static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1925
struct snd_pcm *pcm;
1928
err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1932
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1934
pcm->private_data = cm;
1935
pcm->info_flags = 0;
1936
strcpy(pcm->name, "C-Media PCI 2nd DAC");
1939
snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1940
snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1945
static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1947
struct snd_pcm *pcm;
1950
err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1954
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1955
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1957
pcm->private_data = cm;
1958
pcm->info_flags = 0;
1959
strcpy(pcm->name, "C-Media PCI IEC958");
1960
cm->pcm_spdif = pcm;
1962
snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1963
snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1965
err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1966
snd_pcm_alt_chmaps, cm->max_channels, 0,
1976
* - CM8338/8738 has a compatible mixer interface with SB16, but
1977
* lack of some elements like tone control, i/o gain and AGC.
1978
* - Access to native registers:
1980
* - Output mute switches
1983
static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1985
outb(idx, s->iobase + CM_REG_SB16_ADDR);
1986
outb(data, s->iobase + CM_REG_SB16_DATA);
1989
static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1993
outb(idx, s->iobase + CM_REG_SB16_ADDR);
1994
v = inb(s->iobase + CM_REG_SB16_DATA);
1999
* general mixer element
2001
struct cmipci_sb_reg {
2002
unsigned int left_reg, right_reg;
2003
unsigned int left_shift, right_shift;
2005
unsigned int invert: 1;
2006
unsigned int stereo: 1;
2009
#define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
2010
((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
2012
#define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
2013
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2014
.info = snd_cmipci_info_volume, \
2015
.get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
2016
.private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
2019
#define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
2020
#define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
2021
#define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
2022
#define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
2024
static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
2026
r->left_reg = val & 0xff;
2027
r->right_reg = (val >> 8) & 0xff;
2028
r->left_shift = (val >> 16) & 0x07;
2029
r->right_shift = (val >> 19) & 0x07;
2030
r->invert = (val >> 22) & 1;
2031
r->stereo = (val >> 23) & 1;
2032
r->mask = (val >> 24) & 0xff;
2035
static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2036
struct snd_ctl_elem_info *uinfo)
2038
struct cmipci_sb_reg reg;
2040
cmipci_sb_reg_decode(®, kcontrol->private_value);
2041
uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2042
uinfo->count = reg.stereo + 1;
2043
uinfo->value.integer.min = 0;
2044
uinfo->value.integer.max = reg.mask;
2048
static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2049
struct snd_ctl_elem_value *ucontrol)
2051
struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2052
struct cmipci_sb_reg reg;
2055
cmipci_sb_reg_decode(®, kcontrol->private_value);
2056
spin_lock_irq(&cm->reg_lock);
2057
val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2059
val = reg.mask - val;
2060
ucontrol->value.integer.value[0] = val;
2062
val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2064
val = reg.mask - val;
2065
ucontrol->value.integer.value[1] = val;
2067
spin_unlock_irq(&cm->reg_lock);
2071
static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2072
struct snd_ctl_elem_value *ucontrol)
2074
struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2075
struct cmipci_sb_reg reg;
2077
int left, right, oleft, oright;
2079
cmipci_sb_reg_decode(®, kcontrol->private_value);
2080
left = ucontrol->value.integer.value[0] & reg.mask;
2082
left = reg.mask - left;
2083
left <<= reg.left_shift;
2085
right = ucontrol->value.integer.value[1] & reg.mask;
2087
right = reg.mask - right;
2088
right <<= reg.right_shift;
2091
spin_lock_irq(&cm->reg_lock);
2092
oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2093
left |= oleft & ~(reg.mask << reg.left_shift);
2094
change = left != oleft;
2096
if (reg.left_reg != reg.right_reg) {
2097
snd_cmipci_mixer_write(cm, reg.left_reg, left);
2098
oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2101
right |= oright & ~(reg.mask << reg.right_shift);
2102
change |= right != oright;
2103
snd_cmipci_mixer_write(cm, reg.right_reg, right);
2105
snd_cmipci_mixer_write(cm, reg.left_reg, left);
2106
spin_unlock_irq(&cm->reg_lock);
2111
* input route (left,right) -> (left,right)
2113
#define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2114
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2115
.info = snd_cmipci_info_input_sw, \
2116
.get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2117
.private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2120
static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2121
struct snd_ctl_elem_info *uinfo)
2123
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2125
uinfo->value.integer.min = 0;
2126
uinfo->value.integer.max = 1;
2130
static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2131
struct snd_ctl_elem_value *ucontrol)
2133
struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2134
struct cmipci_sb_reg reg;
2137
cmipci_sb_reg_decode(®, kcontrol->private_value);
2138
spin_lock_irq(&cm->reg_lock);
2139
val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2140
val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2141
spin_unlock_irq(&cm->reg_lock);
2142
ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2143
ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2144
ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2145
ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2149
static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2150
struct snd_ctl_elem_value *ucontrol)
2152
struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2153
struct cmipci_sb_reg reg;
2155
int val1, val2, oval1, oval2;
2157
cmipci_sb_reg_decode(®, kcontrol->private_value);
2158
spin_lock_irq(&cm->reg_lock);
2159
oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2160
oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2161
val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2162
val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2163
val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2164
val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2165
val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2166
val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2167
change = val1 != oval1 || val2 != oval2;
2168
snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2169
snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2170
spin_unlock_irq(&cm->reg_lock);
2175
* native mixer switches/volumes
2178
#define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2179
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2180
.info = snd_cmipci_info_native_mixer, \
2181
.get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2182
.private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2185
#define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2186
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2187
.info = snd_cmipci_info_native_mixer, \
2188
.get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2189
.private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2192
#define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2193
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2194
.info = snd_cmipci_info_native_mixer, \
2195
.get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2196
.private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2199
#define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2200
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2201
.info = snd_cmipci_info_native_mixer, \
2202
.get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2203
.private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2206
static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2207
struct snd_ctl_elem_info *uinfo)
2209
struct cmipci_sb_reg reg;
2211
cmipci_sb_reg_decode(®, kcontrol->private_value);
2212
uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2213
uinfo->count = reg.stereo + 1;
2214
uinfo->value.integer.min = 0;
2215
uinfo->value.integer.max = reg.mask;
2220
static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2221
struct snd_ctl_elem_value *ucontrol)
2223
struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2224
struct cmipci_sb_reg reg;
2225
unsigned char oreg, val;
2227
cmipci_sb_reg_decode(®, kcontrol->private_value);
2228
spin_lock_irq(&cm->reg_lock);
2229
oreg = inb(cm->iobase + reg.left_reg);
2230
val = (oreg >> reg.left_shift) & reg.mask;
2232
val = reg.mask - val;
2233
ucontrol->value.integer.value[0] = val;
2235
val = (oreg >> reg.right_shift) & reg.mask;
2237
val = reg.mask - val;
2238
ucontrol->value.integer.value[1] = val;
2240
spin_unlock_irq(&cm->reg_lock);
2244
static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2245
struct snd_ctl_elem_value *ucontrol)
2247
struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2248
struct cmipci_sb_reg reg;
2249
unsigned char oreg, nreg, val;
2251
cmipci_sb_reg_decode(®, kcontrol->private_value);
2252
spin_lock_irq(&cm->reg_lock);
2253
oreg = inb(cm->iobase + reg.left_reg);
2254
val = ucontrol->value.integer.value[0] & reg.mask;
2256
val = reg.mask - val;
2257
nreg = oreg & ~(reg.mask << reg.left_shift);
2258
nreg |= (val << reg.left_shift);
2260
val = ucontrol->value.integer.value[1] & reg.mask;
2262
val = reg.mask - val;
2263
nreg &= ~(reg.mask << reg.right_shift);
2264
nreg |= (val << reg.right_shift);
2266
outb(nreg, cm->iobase + reg.left_reg);
2267
spin_unlock_irq(&cm->reg_lock);
2268
return (nreg != oreg);
2272
* special case - check mixer sensitivity
2274
static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2275
struct snd_ctl_elem_value *ucontrol)
2277
//struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2278
return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2281
static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2282
struct snd_ctl_elem_value *ucontrol)
2284
struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2285
if (cm->mixer_insensitive) {
2289
return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2293
static struct snd_kcontrol_new snd_cmipci_mixers[] = {
2294
CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2295
CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2296
CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2297
//CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2298
{ /* switch with sensitivity */
2299
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2300
.name = "PCM Playback Switch",
2301
.info = snd_cmipci_info_native_mixer,
2302
.get = snd_cmipci_get_native_mixer_sensitive,
2303
.put = snd_cmipci_put_native_mixer_sensitive,
2304
.private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2306
CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2307
CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2308
CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2309
CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2310
CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2311
CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2312
CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2313
CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2314
CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2315
CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2316
CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2317
CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2318
CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2319
CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2320
CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2321
CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2322
CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2323
CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2324
CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2325
CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2326
CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2327
CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2328
CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2335
struct cmipci_switch_args {
2336
int reg; /* register index */
2337
unsigned int mask; /* mask bits */
2338
unsigned int mask_on; /* mask bits to turn on */
2339
unsigned int is_byte: 1; /* byte access? */
2340
unsigned int ac3_sensitive: 1; /* access forbidden during
2341
* non-audio operation?
2345
#define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2347
static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2348
struct snd_ctl_elem_value *ucontrol,
2349
struct cmipci_switch_args *args)
2352
struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2354
spin_lock_irq(&cm->reg_lock);
2355
if (args->ac3_sensitive && cm->mixer_insensitive) {
2356
ucontrol->value.integer.value[0] = 0;
2357
spin_unlock_irq(&cm->reg_lock);
2361
val = inb(cm->iobase + args->reg);
2363
val = snd_cmipci_read(cm, args->reg);
2364
ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2365
spin_unlock_irq(&cm->reg_lock);
2369
static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2370
struct snd_ctl_elem_value *ucontrol)
2372
struct cmipci_switch_args *args;
2373
args = (struct cmipci_switch_args *)kcontrol->private_value;
2374
if (snd_BUG_ON(!args))
2376
return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2379
static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2380
struct snd_ctl_elem_value *ucontrol,
2381
struct cmipci_switch_args *args)
2385
struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2387
spin_lock_irq(&cm->reg_lock);
2388
if (args->ac3_sensitive && cm->mixer_insensitive) {
2390
spin_unlock_irq(&cm->reg_lock);
2394
val = inb(cm->iobase + args->reg);
2396
val = snd_cmipci_read(cm, args->reg);
2397
change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2398
args->mask_on : (args->mask & ~args->mask_on));
2401
if (ucontrol->value.integer.value[0])
2402
val |= args->mask_on;
2404
val |= (args->mask & ~args->mask_on);
2406
outb((unsigned char)val, cm->iobase + args->reg);
2408
snd_cmipci_write(cm, args->reg, val);
2410
spin_unlock_irq(&cm->reg_lock);
2414
static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2415
struct snd_ctl_elem_value *ucontrol)
2417
struct cmipci_switch_args *args;
2418
args = (struct cmipci_switch_args *)kcontrol->private_value;
2419
if (snd_BUG_ON(!args))
2421
return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2424
#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2425
static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2428
.mask_on = xmask_on, \
2429
.is_byte = xis_byte, \
2430
.ac3_sensitive = xac3, \
2433
#define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2434
DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2436
#if 0 /* these will be controlled in pcm device */
2437
DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2438
DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2440
DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2441
DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2442
DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2443
DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2444
DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2445
DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2446
DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2447
DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2448
// DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2449
DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2450
DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2451
/* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2452
DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2453
DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2455
DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2457
DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2459
DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2460
// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2461
// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2462
// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2463
DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2465
#define DEFINE_SWITCH(sname, stype, sarg) \
2468
.info = snd_cmipci_uswitch_info, \
2469
.get = snd_cmipci_uswitch_get, \
2470
.put = snd_cmipci_uswitch_put, \
2471
.private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2474
#define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2475
#define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2479
* callbacks for spdif output switch
2480
* needs toggle two registers..
2482
static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2483
struct snd_ctl_elem_value *ucontrol)
2486
changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2487
changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2491
static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2492
struct snd_ctl_elem_value *ucontrol)
2494
struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2496
changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2497
changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2499
if (ucontrol->value.integer.value[0]) {
2500
if (chip->spdif_playback_avail)
2501
snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2503
if (chip->spdif_playback_avail)
2504
snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2507
chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2512
static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2513
struct snd_ctl_elem_info *uinfo)
2515
struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2516
static const char *const texts[3] = {
2517
"Line-In", "Rear Output", "Bass Output"
2520
return snd_ctl_enum_info(uinfo, 1,
2521
cm->chip_version >= 39 ? 3 : 2, texts);
2524
static inline unsigned int get_line_in_mode(struct cmipci *cm)
2527
if (cm->chip_version >= 39) {
2528
val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2529
if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2532
val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2533
if (val & CM_REAR2LIN)
2538
static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2539
struct snd_ctl_elem_value *ucontrol)
2541
struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2543
spin_lock_irq(&cm->reg_lock);
2544
ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2545
spin_unlock_irq(&cm->reg_lock);
2549
static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2550
struct snd_ctl_elem_value *ucontrol)
2552
struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2555
spin_lock_irq(&cm->reg_lock);
2556
if (ucontrol->value.enumerated.item[0] == 2)
2557
change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2559
change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2560
if (ucontrol->value.enumerated.item[0] == 1)
2561
change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2563
change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2564
spin_unlock_irq(&cm->reg_lock);
2568
static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2569
struct snd_ctl_elem_info *uinfo)
2571
static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2573
return snd_ctl_enum_info(uinfo, 1, 2, texts);
2576
static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2577
struct snd_ctl_elem_value *ucontrol)
2579
struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2580
/* same bit as spdi_phase */
2581
spin_lock_irq(&cm->reg_lock);
2582
ucontrol->value.enumerated.item[0] =
2583
(snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2584
spin_unlock_irq(&cm->reg_lock);
2588
static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2589
struct snd_ctl_elem_value *ucontrol)
2591
struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2594
spin_lock_irq(&cm->reg_lock);
2595
if (ucontrol->value.enumerated.item[0])
2596
change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2598
change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2599
spin_unlock_irq(&cm->reg_lock);
2603
/* both for CM8338/8738 */
2604
static struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
2605
DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2607
.name = "Line-In Mode",
2608
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2609
.info = snd_cmipci_line_in_mode_info,
2610
.get = snd_cmipci_line_in_mode_get,
2611
.put = snd_cmipci_line_in_mode_put,
2615
/* for non-multichannel chips */
2616
static struct snd_kcontrol_new snd_cmipci_nomulti_switch =
2617
DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2619
/* only for CM8738 */
2620
static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
2621
#if 0 /* controlled in pcm device */
2622
DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2623
DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2624
DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2626
// DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2627
{ .name = "IEC958 Output Switch",
2628
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2629
.info = snd_cmipci_uswitch_info,
2630
.get = snd_cmipci_spdout_enable_get,
2631
.put = snd_cmipci_spdout_enable_put,
2633
DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2634
DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2635
DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2636
// DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2637
DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2638
DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2641
/* only for model 033/037 */
2642
static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
2643
DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2644
DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2645
DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2648
/* only for model 039 or later */
2649
static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
2650
DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2651
DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2653
.name = "Mic-In Mode",
2654
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2655
.info = snd_cmipci_mic_in_mode_info,
2656
.get = snd_cmipci_mic_in_mode_get,
2657
.put = snd_cmipci_mic_in_mode_put,
2661
/* card control switches */
2662
static struct snd_kcontrol_new snd_cmipci_modem_switch =
2663
DEFINE_CARD_SWITCH("Modem", modem);
2666
static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2668
struct snd_card *card;
2669
struct snd_kcontrol_new *sw;
2670
struct snd_kcontrol *kctl;
2674
if (snd_BUG_ON(!cm || !cm->card))
2679
strcpy(card->mixername, "CMedia PCI");
2681
spin_lock_irq(&cm->reg_lock);
2682
snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2683
spin_unlock_irq(&cm->reg_lock);
2685
for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2686
if (cm->chip_version == 68) { // 8768 has no PCM volume
2687
if (!strcmp(snd_cmipci_mixers[idx].name,
2688
"PCM Playback Volume"))
2691
if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2695
/* mixer switches */
2696
sw = snd_cmipci_mixer_switches;
2697
for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2698
err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2702
if (! cm->can_multi_ch) {
2703
err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2707
if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2708
cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2709
sw = snd_cmipci_8738_mixer_switches;
2710
for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2711
err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2715
if (cm->can_ac3_hw) {
2716
if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2718
kctl->id.device = pcm_spdif_device;
2719
if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2721
kctl->id.device = pcm_spdif_device;
2722
if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2724
kctl->id.device = pcm_spdif_device;
2726
if (cm->chip_version <= 37) {
2727
sw = snd_cmipci_old_mixer_switches;
2728
for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2729
err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2735
if (cm->chip_version >= 39) {
2736
sw = snd_cmipci_extra_mixer_switches;
2737
for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2738
err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2746
* newer chips don't have the register bits to force modem link
2747
* detection; the bit that was FLINKON now mutes CH1
2749
if (cm->chip_version < 39) {
2750
err = snd_ctl_add(cm->card,
2751
snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2756
for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2757
struct snd_ctl_elem_id elem_id;
2758
struct snd_kcontrol *ctl;
2759
memset(&elem_id, 0, sizeof(elem_id));
2760
elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2761
strcpy(elem_id.name, cm_saved_mixer[idx].name);
2762
ctl = snd_ctl_find_id(cm->card, &elem_id);
2764
cm->mixer_res_ctl[idx] = ctl;
2775
static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2776
struct snd_info_buffer *buffer)
2778
struct cmipci *cm = entry->private_data;
2781
snd_iprintf(buffer, "%s\n", cm->card->longname);
2782
for (i = 0; i < 0x94; i++) {
2785
v = inb(cm->iobase + i);
2787
snd_iprintf(buffer, "\n%02x:", i);
2788
snd_iprintf(buffer, " %02x", v);
2790
snd_iprintf(buffer, "\n");
2793
static void snd_cmipci_proc_init(struct cmipci *cm)
2795
struct snd_info_entry *entry;
2797
if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2798
snd_info_set_text_ops(entry, cm, snd_cmipci_proc_read);
2801
static const struct pci_device_id snd_cmipci_ids[] = {
2802
{PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2803
{PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2804
{PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2805
{PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2806
{PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2812
* check chip version and capabilities
2813
* driver name is modified according to the chip model
2815
static void query_chip(struct cmipci *cm)
2817
unsigned int detect;
2819
/* check reg 0Ch, bit 24-31 */
2820
detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2822
/* check reg 08h, bit 24-28 */
2823
detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2826
cm->chip_version = 33;
2827
if (cm->do_soft_ac3)
2833
cm->chip_version = 37;
2837
cm->chip_version = 39;
2841
cm->max_channels = 2;
2843
if (detect & CM_CHIP_039) {
2844
cm->chip_version = 39;
2845
if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2846
cm->max_channels = 6;
2848
cm->max_channels = 4;
2849
} else if (detect & CM_CHIP_8768) {
2850
cm->chip_version = 68;
2851
cm->max_channels = 8;
2854
cm->chip_version = 55;
2855
cm->max_channels = 6;
2859
cm->can_multi_ch = 1;
2863
#ifdef SUPPORT_JOYSTICK
2864
static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2866
static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2867
struct gameport *gp;
2868
struct resource *r = NULL;
2871
if (joystick_port[dev] == 0)
2874
if (joystick_port[dev] == 1) { /* auto-detect */
2875
for (i = 0; ports[i]; i++) {
2877
r = request_region(io_port, 1, "CMIPCI gameport");
2882
io_port = joystick_port[dev];
2883
r = request_region(io_port, 1, "CMIPCI gameport");
2887
dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2891
cm->gameport = gp = gameport_allocate_port();
2893
dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2894
release_and_free_resource(r);
2897
gameport_set_name(gp, "C-Media Gameport");
2898
gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2899
gameport_set_dev_parent(gp, &cm->pci->dev);
2901
gameport_set_port_data(gp, r);
2903
snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2905
gameport_register_port(cm->gameport);
2910
static void snd_cmipci_free_gameport(struct cmipci *cm)
2913
struct resource *r = gameport_get_port_data(cm->gameport);
2915
gameport_unregister_port(cm->gameport);
2916
cm->gameport = NULL;
2918
snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2919
release_and_free_resource(r);
2923
static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2924
static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2927
static int snd_cmipci_free(struct cmipci *cm)
2930
snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2931
snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2932
snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2933
snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2934
snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2935
snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2936
snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2939
snd_cmipci_mixer_write(cm, 0, 0);
2941
free_irq(cm->irq, cm);
2944
snd_cmipci_free_gameport(cm);
2945
pci_release_regions(cm->pci);
2946
pci_disable_device(cm->pci);
2951
static int snd_cmipci_dev_free(struct snd_device *device)
2953
struct cmipci *cm = device->device_data;
2954
return snd_cmipci_free(cm);
2957
static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2961
struct snd_opl3 *opl3;
2967
if (cm->chip_version >= 39) {
2968
/* first try FM regs in PCI port range */
2969
iosynth = cm->iobase + CM_REG_FM_PCI;
2970
err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2971
OPL3_HW_OPL3, 1, &opl3);
2976
/* then try legacy ports */
2977
val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2980
case 0x3E8: val |= CM_FMSEL_3E8; break;
2981
case 0x3E0: val |= CM_FMSEL_3E0; break;
2982
case 0x3C8: val |= CM_FMSEL_3C8; break;
2983
case 0x388: val |= CM_FMSEL_388; break;
2987
snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2989
snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2991
if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2992
OPL3_HW_OPL3, 0, &opl3) < 0) {
2993
dev_err(cm->card->dev,
2994
"no OPL device at %#lx, skipping...\n",
2999
if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
3000
dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
3006
snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
3007
snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
3011
static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
3012
int dev, struct cmipci **rcmipci)
3016
static struct snd_device_ops ops = {
3017
.dev_free = snd_cmipci_dev_free,
3021
int integrated_midi = 0;
3023
int pcm_index, pcm_spdif_index;
3024
static const struct pci_device_id intel_82437vx[] = {
3025
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
3031
if ((err = pci_enable_device(pci)) < 0)
3034
cm = kzalloc(sizeof(*cm), GFP_KERNEL);
3036
pci_disable_device(pci);
3040
spin_lock_init(&cm->reg_lock);
3041
mutex_init(&cm->open_mutex);
3042
cm->device = pci->device;
3046
cm->channel[0].ch = 0;
3047
cm->channel[1].ch = 1;
3048
cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3050
if ((err = pci_request_regions(pci, card->driver)) < 0) {
3052
pci_disable_device(pci);
3055
cm->iobase = pci_resource_start(pci, 0);
3057
if (request_irq(pci->irq, snd_cmipci_interrupt,
3058
IRQF_SHARED, KBUILD_MODNAME, cm)) {
3059
dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3060
snd_cmipci_free(cm);
3065
pci_set_master(cm->pci);
3068
* check chip version, max channels and capabilities
3071
cm->chip_version = 0;
3072
cm->max_channels = 2;
3073
cm->do_soft_ac3 = soft_ac3[dev];
3075
if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3076
pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3078
/* added -MCx suffix for chip supporting multi-channels */
3079
if (cm->can_multi_ch)
3080
sprintf(cm->card->driver + strlen(cm->card->driver),
3081
"-MC%d", cm->max_channels);
3082
else if (cm->can_ac3_sw)
3083
strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3085
cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3086
cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3089
cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3091
cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
3094
/* initialize codec registers */
3095
snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3096
snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3097
snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
3098
snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3099
snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3100
snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
3101
snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3103
snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3104
snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3106
snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3108
snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3110
if (cm->chip_version) {
3111
snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3112
snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3114
/* Set Bus Master Request */
3115
snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3117
/* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3118
switch (pci->device) {
3119
case PCI_DEVICE_ID_CMEDIA_CM8738:
3120
case PCI_DEVICE_ID_CMEDIA_CM8738B:
3121
if (!pci_dev_present(intel_82437vx))
3122
snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3128
if (cm->chip_version < 68) {
3129
val = pci->device < 0x110 ? 8338 : 8738;
3131
switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3139
switch ((pci->subsystem_vendor << 16) |
3140
pci->subsystem_device) {
3155
sprintf(card->shortname, "C-Media CMI%d", val);
3156
if (cm->chip_version < 68)
3157
sprintf(modelstr, " (model %d)", cm->chip_version);
3160
sprintf(card->longname, "%s%s at %#lx, irq %i",
3161
card->shortname, modelstr, cm->iobase, cm->irq);
3163
if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3164
snd_cmipci_free(cm);
3168
if (cm->chip_version >= 39) {
3169
val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3170
if (val != 0x00 && val != 0xff) {
3171
iomidi = cm->iobase + CM_REG_MPU_PCI;
3172
integrated_midi = 1;
3175
if (!integrated_midi) {
3177
iomidi = mpu_port[dev];
3179
case 0x320: val = CM_VMPU_320; break;
3180
case 0x310: val = CM_VMPU_310; break;
3181
case 0x300: val = CM_VMPU_300; break;
3182
case 0x330: val = CM_VMPU_330; break;
3187
snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3189
snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3190
if (inb(iomidi + 1) == 0xff) {
3191
dev_err(cm->card->dev,
3192
"cannot enable MPU-401 port at %#lx\n",
3194
snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3201
if (cm->chip_version < 68) {
3202
err = snd_cmipci_create_fm(cm, fm_port[dev]);
3208
snd_cmipci_mixer_write(cm, 0, 0);
3210
snd_cmipci_proc_init(cm);
3212
/* create pcm devices */
3213
pcm_index = pcm_spdif_index = 0;
3214
if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3217
if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3220
if (cm->can_ac3_hw || cm->can_ac3_sw) {
3221
pcm_spdif_index = pcm_index;
3222
if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3226
/* create mixer interface & switches */
3227
if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3231
if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3234
MPU401_INFO_INTEGRATED : 0) |
3235
MPU401_INFO_IRQ_HOOK,
3236
-1, &cm->rmidi)) < 0) {
3237
dev_err(cm->card->dev,
3238
"no UART401 device at 0x%lx\n", iomidi);
3242
#ifdef USE_VAR48KRATE
3243
for (val = 0; val < ARRAY_SIZE(rates); val++)
3244
snd_cmipci_set_pll(cm, rates[val], val);
3247
* (Re-)Enable external switch spdo_48k
3249
snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3250
#endif /* USE_VAR48KRATE */
3252
if (snd_cmipci_create_gameport(cm, dev) < 0)
3253
snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3262
MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3264
static int snd_cmipci_probe(struct pci_dev *pci,
3265
const struct pci_device_id *pci_id)
3268
struct snd_card *card;
3272
if (dev >= SNDRV_CARDS)
3274
if (! enable[dev]) {
3279
err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3284
switch (pci->device) {
3285
case PCI_DEVICE_ID_CMEDIA_CM8738:
3286
case PCI_DEVICE_ID_CMEDIA_CM8738B:
3287
strcpy(card->driver, "CMI8738");
3289
case PCI_DEVICE_ID_CMEDIA_CM8338A:
3290
case PCI_DEVICE_ID_CMEDIA_CM8338B:
3291
strcpy(card->driver, "CMI8338");
3294
strcpy(card->driver, "CMIPCI");
3298
err = snd_cmipci_create(card, pci, dev, &cm);
3302
card->private_data = cm;
3304
err = snd_card_register(card);
3308
pci_set_drvdata(pci, card);
3313
snd_card_free(card);
3317
static void snd_cmipci_remove(struct pci_dev *pci)
3319
snd_card_free(pci_get_drvdata(pci));
3323
#ifdef CONFIG_PM_SLEEP
3327
static unsigned char saved_regs[] = {
3328
CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3329
CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3330
CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3331
CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3332
CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3335
static unsigned char saved_mixers[] = {
3336
SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3337
SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3338
SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3339
SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3340
SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3341
SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3342
CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3343
SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3346
static int snd_cmipci_suspend(struct device *dev)
3348
struct snd_card *card = dev_get_drvdata(dev);
3349
struct cmipci *cm = card->private_data;
3352
snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3354
snd_pcm_suspend_all(cm->pcm);
3355
snd_pcm_suspend_all(cm->pcm2);
3356
snd_pcm_suspend_all(cm->pcm_spdif);
3358
/* save registers */
3359
for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3360
cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3361
for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3362
cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3365
snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3369
static int snd_cmipci_resume(struct device *dev)
3371
struct snd_card *card = dev_get_drvdata(dev);
3372
struct cmipci *cm = card->private_data;
3375
/* reset / initialize to a sane state */
3376
snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3377
snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3378
snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3379
snd_cmipci_mixer_write(cm, 0, 0);
3381
/* restore registers */
3382
for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3383
snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3384
for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3385
snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3387
snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3391
static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
3392
#define SND_CMIPCI_PM_OPS &snd_cmipci_pm
3394
#define SND_CMIPCI_PM_OPS NULL
3395
#endif /* CONFIG_PM_SLEEP */
3397
static struct pci_driver cmipci_driver = {
3398
.name = KBUILD_MODNAME,
3399
.id_table = snd_cmipci_ids,
3400
.probe = snd_cmipci_probe,
3401
.remove = snd_cmipci_remove,
3403
.pm = SND_CMIPCI_PM_OPS,
3407
module_pci_driver(cmipci_driver);
added
removed
pci/cmipci.c
