2
* pxa-ssp.c -- ALSA Soc Audio Layer
4
* Copyright 2005,2008 Wolfson Microelectronics PLC.
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* Author: Liam Girdwood
6
* Mark Brown <broonie@opensource.wolfsonmicro.com>
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
11
* option) any later version.
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* o Test network mode for > 16bit sample size
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/pxa2xx_ssp.h>
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#include <linux/dmaengine.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/initval.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/pxa2xx-lib.h>
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#include <sound/dmaengine_pcm.h>
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* SSP audio private data
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struct ssp_device *ssp;
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unsigned long ssp_clk;
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unsigned int configured_dai_fmt;
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static void dump_registers(struct ssp_device *ssp)
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dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
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pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
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pxa_ssp_read_reg(ssp, SSTO));
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dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
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pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
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pxa_ssp_read_reg(ssp, SSACD));
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static void pxa_ssp_enable(struct ssp_device *ssp)
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sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
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__raw_writel(sscr0, ssp->mmio_base + SSCR0);
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static void pxa_ssp_disable(struct ssp_device *ssp)
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sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
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__raw_writel(sscr0, ssp->mmio_base + SSCR0);
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static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4,
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int out, struct snd_dmaengine_dai_dma_data *dma)
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dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES :
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DMA_SLAVE_BUSWIDTH_2_BYTES;
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dma->addr = ssp->phys_base + SSDR;
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static int pxa_ssp_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
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struct ssp_device *ssp = priv->ssp;
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struct snd_dmaengine_dai_dma_data *dma;
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if (!cpu_dai->active) {
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clk_prepare_enable(ssp->clk);
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pxa_ssp_disable(ssp);
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dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL);
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dma->chan_name = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
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snd_soc_dai_set_dma_data(cpu_dai, substream, dma);
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static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
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struct ssp_device *ssp = priv->ssp;
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if (!cpu_dai->active) {
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pxa_ssp_disable(ssp);
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clk_disable_unprepare(ssp->clk);
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kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
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snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
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static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
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struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
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struct ssp_device *ssp = priv->ssp;
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if (!cpu_dai->active)
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clk_prepare_enable(ssp->clk);
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priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
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priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
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priv->to = __raw_readl(ssp->mmio_base + SSTO);
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priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
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pxa_ssp_disable(ssp);
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clk_disable_unprepare(ssp->clk);
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static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
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struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
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struct ssp_device *ssp = priv->ssp;
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uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
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clk_prepare_enable(ssp->clk);
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__raw_writel(sssr, ssp->mmio_base + SSSR);
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__raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
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__raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
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__raw_writel(priv->to, ssp->mmio_base + SSTO);
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__raw_writel(priv->psp, ssp->mmio_base + SSPSP);
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clk_disable_unprepare(ssp->clk);
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#define pxa_ssp_suspend NULL
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#define pxa_ssp_resume NULL
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* ssp_set_clkdiv - set SSP clock divider
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* @div: serial clock rate divider
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static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
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u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
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if (ssp->type == PXA25x_SSP) {
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sscr0 &= ~0x0000ff00;
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sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
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sscr0 &= ~0x000fff00;
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sscr0 |= (div - 1) << 8; /* 1..4096 */
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pxa_ssp_write_reg(ssp, SSCR0, sscr0);
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* Set the SSP ports SYSCLK.
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static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq, int dir)
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struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
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struct ssp_device *ssp = priv->ssp;
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u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
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~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
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* For DT based boards, if an extclk is given, use it
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* here and configure PXA_SSP_CLK_EXT.
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ret = clk_set_rate(priv->extclk, freq);
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clk_id = PXA_SSP_CLK_EXT;
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dev_dbg(&ssp->pdev->dev,
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"pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
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cpu_dai->id, clk_id, freq);
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case PXA_SSP_CLK_NET_PLL:
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case PXA_SSP_CLK_PLL:
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/* Internal PLL is fixed */
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if (ssp->type == PXA25x_SSP)
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priv->sysclk = 1843200;
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priv->sysclk = 13000000;
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case PXA_SSP_CLK_EXT:
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case PXA_SSP_CLK_NET:
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sscr0 |= SSCR0_NCS | SSCR0_MOD;
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case PXA_SSP_CLK_AUDIO:
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pxa_ssp_set_scr(ssp, 1);
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/* The SSP clock must be disabled when changing SSP clock mode
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* on PXA2xx. On PXA3xx it must be enabled when doing so. */
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if (ssp->type != PXA3xx_SSP)
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clk_disable_unprepare(ssp->clk);
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pxa_ssp_write_reg(ssp, SSCR0, sscr0);
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if (ssp->type != PXA3xx_SSP)
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clk_prepare_enable(ssp->clk);
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* Configure the PLL frequency pxa27x and (afaik - pxa320 only)
270
static int pxa_ssp_set_pll(struct ssp_priv *priv, unsigned int freq)
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struct ssp_device *ssp = priv->ssp;
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u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
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if (ssp->type == PXA3xx_SSP)
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pxa_ssp_write_reg(ssp, SSACDD, 0);
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/* PXA3xx has a clock ditherer which can be used to generate
302
* a wider range of frequencies - calculate a value for it.
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if (ssp->type == PXA3xx_SSP) {
312
val = (val << 16) | 64;
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pxa_ssp_write_reg(ssp, SSACDD, val);
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dev_dbg(&ssp->pdev->dev,
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"Using SSACDD %x to supply %uHz\n",
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pxa_ssp_write_reg(ssp, SSACD, ssacd);
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* Set the active slots in TDM/Network mode
334
static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
335
unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
337
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
338
struct ssp_device *ssp = priv->ssp;
341
sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
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sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
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sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
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sscr0 |= SSCR0_DataSize(slot_width);
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/* enable network mode */
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/* set number of active slots */
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sscr0 |= SSCR0_SlotsPerFrm(slots);
357
/* set active slot mask */
358
pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
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pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
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pxa_ssp_write_reg(ssp, SSCR0, sscr0);
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* Tristate the SSP DAI lines
369
static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
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struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
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struct ssp_device *ssp = priv->ssp;
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sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
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pxa_ssp_write_reg(ssp, SSCR1, sscr1);
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static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
391
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
392
case SND_SOC_DAIFMT_CBM_CFM:
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case SND_SOC_DAIFMT_CBM_CFS:
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case SND_SOC_DAIFMT_CBS_CFS:
400
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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case SND_SOC_DAIFMT_NB_IF:
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case SND_SOC_DAIFMT_IB_IF:
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case SND_SOC_DAIFMT_IB_NF:
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
412
case SND_SOC_DAIFMT_DSP_A:
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case SND_SOC_DAIFMT_DSP_B:
420
/* Settings will be applied in hw_params() */
427
* Set up the SSP DAI format.
428
* The SSP Port must be inactive before calling this function as the
429
* physical interface format is changed.
431
static int pxa_ssp_configure_dai_fmt(struct ssp_priv *priv)
433
struct ssp_device *ssp = priv->ssp;
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u32 sscr0, sscr1, sspsp, scfr;
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/* check if we need to change anything at all */
437
if (priv->configured_dai_fmt == priv->dai_fmt)
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/* reset port settings */
441
sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
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~(SSCR0_PSP | SSCR0_MOD);
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sscr1 = pxa_ssp_read_reg(ssp, SSCR1) &
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~(SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR |
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SSCR1_RWOT | SSCR1_TRAIL | SSCR1_TFT | SSCR1_RFT);
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sspsp = pxa_ssp_read_reg(ssp, SSPSP) &
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~(SSPSP_SFRMP | SSPSP_SCMODE(3));
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sscr1 |= SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
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switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
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case SND_SOC_DAIFMT_CBM_CFS:
456
sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
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case SND_SOC_DAIFMT_CBS_CFS:
464
switch (priv->dai_fmt & SND_SOC_DAIFMT_INV_MASK) {
465
case SND_SOC_DAIFMT_NB_NF:
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sspsp |= SSPSP_SFRMP;
468
case SND_SOC_DAIFMT_NB_IF:
470
case SND_SOC_DAIFMT_IB_IF:
471
sspsp |= SSPSP_SCMODE(2);
473
case SND_SOC_DAIFMT_IB_NF:
474
sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
480
switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
481
case SND_SOC_DAIFMT_I2S:
483
sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
484
/* See hw_params() */
487
case SND_SOC_DAIFMT_DSP_A:
490
case SND_SOC_DAIFMT_DSP_B:
491
sscr0 |= SSCR0_MOD | SSCR0_PSP;
492
sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
499
pxa_ssp_write_reg(ssp, SSCR0, sscr0);
500
pxa_ssp_write_reg(ssp, SSCR1, sscr1);
501
pxa_ssp_write_reg(ssp, SSPSP, sspsp);
503
switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) {
504
case SND_SOC_DAIFMT_CBM_CFM:
505
case SND_SOC_DAIFMT_CBM_CFS:
506
scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
507
pxa_ssp_write_reg(ssp, SSCR1, scfr);
509
while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
516
/* Since we are configuring the timings for the format by hand
517
* we have to defer some things until hw_params() where we
518
* know parameters like the sample size.
520
priv->configured_dai_fmt = priv->dai_fmt;
525
struct pxa_ssp_clock_mode {
532
static const struct pxa_ssp_clock_mode pxa_ssp_clock_modes[] = {
533
{ .rate = 8000, .pll = 32842000, .acds = SSACD_ACDS_32, .scdb = SSACD_SCDB_4X },
534
{ .rate = 11025, .pll = 5622000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_4X },
535
{ .rate = 16000, .pll = 32842000, .acds = SSACD_ACDS_16, .scdb = SSACD_SCDB_4X },
536
{ .rate = 22050, .pll = 5622000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
537
{ .rate = 44100, .pll = 11345000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
538
{ .rate = 48000, .pll = 12235000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
539
{ .rate = 96000, .pll = 12235000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_1X },
544
* Set the SSP audio DMA parameters and sample size.
545
* Can be called multiple times by oss emulation.
547
static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
548
struct snd_pcm_hw_params *params,
549
struct snd_soc_dai *cpu_dai)
551
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
552
struct ssp_device *ssp = priv->ssp;
553
int chn = params_channels(params);
555
int width = snd_pcm_format_physical_width(params_format(params));
556
int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
557
struct snd_dmaengine_dai_dma_data *dma_data;
558
int rate = params_rate(params);
559
int bclk = rate * chn * (width / 8);
562
dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
564
/* Network mode with one active slot (ttsa == 1) can be used
565
* to force 16-bit frame width on the wire (for S16_LE), even
566
* with two channels. Use 16-bit DMA transfers for this case.
568
pxa_ssp_set_dma_params(ssp,
569
((chn == 2) && (ttsa != 1)) || (width == 32),
570
substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data);
572
/* we can only change the settings if the port is not in use */
573
if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
576
ret = pxa_ssp_configure_dai_fmt(priv);
580
/* clear selected SSP bits */
581
sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
584
switch (params_format(params)) {
585
case SNDRV_PCM_FORMAT_S16_LE:
586
if (ssp->type == PXA3xx_SSP)
587
sscr0 |= SSCR0_FPCKE;
588
sscr0 |= SSCR0_DataSize(16);
590
case SNDRV_PCM_FORMAT_S24_LE:
591
sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
593
case SNDRV_PCM_FORMAT_S32_LE:
594
sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
597
pxa_ssp_write_reg(ssp, SSCR0, sscr0);
599
if (sscr0 & SSCR0_ACS) {
600
ret = pxa_ssp_set_pll(priv, bclk);
603
* If we were able to generate the bclk directly,
604
* all is fine. Otherwise, look up the closest rate
605
* from the table and also set the dividers.
609
const struct pxa_ssp_clock_mode *m;
612
for (m = pxa_ssp_clock_modes; m->rate; m++) {
622
/* The values in the table are for 16 bits */
626
ret = pxa_ssp_set_pll(priv, bclk);
630
ssacd = pxa_ssp_read_reg(ssp, SSACD);
631
ssacd &= ~(SSACD_ACDS(7) | SSACD_SCDB_1X);
632
ssacd |= SSACD_ACDS(m->acds);
634
pxa_ssp_write_reg(ssp, SSACD, ssacd);
636
} else if (sscr0 & SSCR0_ECS) {
638
* For setups with external clocking, the PLL and its diviers
639
* are not active. Instead, the SCR bits in SSCR0 can be used
640
* to divide the clock.
642
pxa_ssp_set_scr(ssp, bclk / rate);
645
switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
646
case SND_SOC_DAIFMT_I2S:
647
sspsp = pxa_ssp_read_reg(ssp, SSPSP);
649
if (((priv->sysclk / bclk) == 64) && (width == 16)) {
650
/* This is a special case where the bitclk is 64fs
651
* and we're not dealing with 2*32 bits of audio
654
* The SSP values used for that are all found out by
655
* trying and failing a lot; some of the registers
656
* needed for that mode are only available on PXA3xx.
658
if (ssp->type != PXA3xx_SSP)
661
sspsp |= SSPSP_SFRMWDTH(width * 2);
662
sspsp |= SSPSP_SFRMDLY(width * 4);
663
sspsp |= SSPSP_EDMYSTOP(3);
664
sspsp |= SSPSP_DMYSTOP(3);
665
sspsp |= SSPSP_DMYSTRT(1);
667
/* The frame width is the width the LRCLK is
668
* asserted for; the delay is expressed in
669
* half cycle units. We need the extra cycle
670
* because the data starts clocking out one BCLK
671
* after LRCLK changes polarity.
673
sspsp |= SSPSP_SFRMWDTH(width + 1);
674
sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
675
sspsp |= SSPSP_DMYSTRT(1);
678
pxa_ssp_write_reg(ssp, SSPSP, sspsp);
684
/* When we use a network mode, we always require TDM slots
685
* - complain loudly and fail if they've not been set up yet.
687
if ((sscr0 & SSCR0_MOD) && !ttsa) {
688
dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
697
static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
698
struct ssp_device *ssp, int value)
700
uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
701
uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
702
uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP);
703
uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR);
705
if (value && (sscr0 & SSCR0_SSE))
706
pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE);
708
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
712
sscr1 &= ~SSCR1_TSRE;
717
sscr1 &= ~SSCR1_RSRE;
720
pxa_ssp_write_reg(ssp, SSCR1, sscr1);
723
pxa_ssp_write_reg(ssp, SSSR, sssr);
724
pxa_ssp_write_reg(ssp, SSPSP, sspsp);
725
pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE);
729
static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
730
struct snd_soc_dai *cpu_dai)
733
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
734
struct ssp_device *ssp = priv->ssp;
738
case SNDRV_PCM_TRIGGER_RESUME:
741
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
742
pxa_ssp_set_running_bit(substream, ssp, 1);
743
val = pxa_ssp_read_reg(ssp, SSSR);
744
pxa_ssp_write_reg(ssp, SSSR, val);
746
case SNDRV_PCM_TRIGGER_START:
747
pxa_ssp_set_running_bit(substream, ssp, 1);
749
case SNDRV_PCM_TRIGGER_STOP:
750
pxa_ssp_set_running_bit(substream, ssp, 0);
752
case SNDRV_PCM_TRIGGER_SUSPEND:
753
pxa_ssp_disable(ssp);
755
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
756
pxa_ssp_set_running_bit(substream, ssp, 0);
768
static int pxa_ssp_probe(struct snd_soc_dai *dai)
770
struct device *dev = dai->dev;
771
struct ssp_priv *priv;
774
priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
779
struct device_node *ssp_handle;
781
ssp_handle = of_parse_phandle(dev->of_node, "port", 0);
783
dev_err(dev, "unable to get 'port' phandle\n");
788
priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio");
789
if (priv->ssp == NULL) {
794
priv->extclk = devm_clk_get(dev, "extclk");
795
if (IS_ERR(priv->extclk)) {
796
ret = PTR_ERR(priv->extclk);
797
if (ret == -EPROBE_DEFER)
803
priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
804
if (priv->ssp == NULL) {
810
priv->dai_fmt = (unsigned int) -1;
811
snd_soc_dai_set_drvdata(dai, priv);
820
static int pxa_ssp_remove(struct snd_soc_dai *dai)
822
struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
824
pxa_ssp_free(priv->ssp);
829
#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
830
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
831
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
832
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
833
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
835
#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
837
static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
838
.startup = pxa_ssp_startup,
839
.shutdown = pxa_ssp_shutdown,
840
.trigger = pxa_ssp_trigger,
841
.hw_params = pxa_ssp_hw_params,
842
.set_sysclk = pxa_ssp_set_dai_sysclk,
843
.set_fmt = pxa_ssp_set_dai_fmt,
844
.set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
845
.set_tristate = pxa_ssp_set_dai_tristate,
848
static struct snd_soc_dai_driver pxa_ssp_dai = {
849
.probe = pxa_ssp_probe,
850
.remove = pxa_ssp_remove,
851
.suspend = pxa_ssp_suspend,
852
.resume = pxa_ssp_resume,
856
.rates = PXA_SSP_RATES,
857
.formats = PXA_SSP_FORMATS,
862
.rates = PXA_SSP_RATES,
863
.formats = PXA_SSP_FORMATS,
865
.ops = &pxa_ssp_dai_ops,
868
static const struct snd_soc_component_driver pxa_ssp_component = {
870
.ops = &pxa2xx_pcm_ops,
871
.pcm_new = pxa2xx_soc_pcm_new,
872
.pcm_free = pxa2xx_pcm_free_dma_buffers,
876
static const struct of_device_id pxa_ssp_of_ids[] = {
877
{ .compatible = "mrvl,pxa-ssp-dai" },
880
MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids);
883
static int asoc_ssp_probe(struct platform_device *pdev)
885
return devm_snd_soc_register_component(&pdev->dev, &pxa_ssp_component,
889
static struct platform_driver asoc_ssp_driver = {
891
.name = "pxa-ssp-dai",
892
.of_match_table = of_match_ptr(pxa_ssp_of_ids),
895
.probe = asoc_ssp_probe,
898
module_platform_driver(asoc_ssp_driver);
900
/* Module information */
901
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
902
MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
903
MODULE_LICENSE("GPL");
904
MODULE_ALIAS("platform:pxa-ssp-dai");