40
#define DPRINTF(fmt, args...) \
41
do { printf("DMA: " fmt , ##args); } while (0)
42
#define DPRINTF(fmt, ...) \
43
do { printf("DMA: " fmt , ## __VA_ARGS__); } while (0)
43
#define DPRINTF(fmt, args...)
45
#define DPRINTF(fmt, ...)
244
247
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
245
void *iommu, qemu_irq **dev_irq, qemu_irq **reset)
248
void *iommu, qemu_irq *dev_irq, qemu_irq **reset)
254
dev = qdev_create(NULL, "sparc32_dma");
255
qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
257
s = sysbus_from_qdev(dev);
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sysbus_connect_irq(s, 0, parent_irq);
259
*dev_irq = qdev_get_gpio_in(dev, 0);
260
sysbus_mmio_map(s, 0, daddr);
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d = FROM_SYSBUS(DMAState, s);
263
*reset = &d->dev_reset;
268
static void sparc32_dma_init1(SysBusDevice *dev)
270
DMAState *s = FROM_SYSBUS(DMAState, dev);
248
271
int dma_io_memory;
250
s = qemu_mallocz(sizeof(DMAState));
255
dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s);
256
cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory);
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register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
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sysbus_init_irq(dev, &s->irq);
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dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s);
276
sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory);
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register_savevm("sparc32_dma", -1, 2, dma_save, dma_load, s);
259
279
qemu_register_reset(dma_reset, s);
260
*dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);
262
*reset = &s->dev_reset;
281
qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
284
static SysBusDeviceInfo sparc32_dma_info = {
285
.init = sparc32_dma_init1,
286
.qdev.name = "sparc32_dma",
287
.qdev.size = sizeof(DMAState),
288
.qdev.props = (Property[]) {
290
.name = "iommu_opaque",
291
.info = &qdev_prop_ptr,
292
.offset = offsetof(DMAState, iommu),
294
{/* end of property list */}
298
static void sparc32_dma_register_devices(void)
300
sysbus_register_withprop(&sparc32_dma_info);
303
device_init(sparc32_dma_register_devices)