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* Copyright (c) 2012 Jan Vesely
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* - The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* @defgroup root_amdm37x TI AM/DM37x platform driver.
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* @brief HelenOS TI AM/DM37x platform driver.
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static void log(const volatile void *place, uint32_t val, volatile void* base, size_t size, void *data, bool write)
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printf("PIO %s: %p(%p) %#"PRIx32"\n", write ? "WRITE" : "READ",
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(place - base) + data, place, val);
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int amdm37x_init(amdm37x_t *device, bool trace)
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ret = pio_enable((void*)USBHOST_CM_BASE_ADDRESS, USBHOST_CM_SIZE,
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(void**)&device->cm.usbhost);
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ret = pio_enable((void*)CORE_CM_BASE_ADDRESS, CORE_CM_SIZE,
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(void**)&device->cm.core);
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ret = pio_enable((void*)CLOCK_CONTROL_CM_BASE_ADDRESS,
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CLOCK_CONTROL_CM_SIZE, (void**)&device->cm.clocks);
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ret = pio_enable((void*)MPU_CM_BASE_ADDRESS,
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MPU_CM_SIZE, (void**)&device->cm.mpu);
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ret = pio_enable((void*)IVA2_CM_BASE_ADDRESS,
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IVA2_CM_SIZE, (void**)&device->cm.iva2);
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ret = pio_enable((void*)CLOCK_CONTROL_PRM_BASE_ADDRESS,
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CLOCK_CONTROL_PRM_SIZE, (void**)&device->prm.clocks);
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ret = pio_enable((void*)GLOBAL_REG_PRM_BASE_ADDRESS,
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GLOBAL_REG_PRM_SIZE, (void**)&device->prm.global);
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ret = pio_enable((void*)AMDM37x_USBTLL_BASE_ADDRESS,
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AMDM37x_USBTLL_SIZE, (void**)&device->tll);
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ret = pio_enable((void*)AMDM37x_UHH_BASE_ADDRESS,
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AMDM37x_UHH_SIZE, (void**)&device->uhh);
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pio_trace_enable(device->tll, AMDM37x_USBTLL_SIZE, log, (void*)AMDM37x_USBTLL_BASE_ADDRESS);
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pio_trace_enable(device->cm.clocks, CLOCK_CONTROL_CM_SIZE, log, (void*)CLOCK_CONTROL_CM_BASE_ADDRESS);
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pio_trace_enable(device->cm.core, CORE_CM_SIZE, log, (void*)CORE_CM_BASE_ADDRESS);
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pio_trace_enable(device->cm.mpu, MPU_CM_SIZE, log, (void*)MPU_CM_BASE_ADDRESS);
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pio_trace_enable(device->cm.iva2, IVA2_CM_SIZE, log, (void*)IVA2_CM_BASE_ADDRESS);
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pio_trace_enable(device->cm.usbhost, USBHOST_CM_SIZE, log, (void*)USBHOST_CM_BASE_ADDRESS);
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pio_trace_enable(device->uhh, AMDM37x_UHH_SIZE, log, (void*)AMDM37x_UHH_BASE_ADDRESS);
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pio_trace_enable(device->prm.clocks, CLOCK_CONTROL_PRM_SIZE, log, (void*)CLOCK_CONTROL_PRM_BASE_ADDRESS);
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pio_trace_enable(device->prm.global, GLOBAL_REG_PRM_SIZE, log, (void*)GLOBAL_REG_PRM_BASE_ADDRESS);
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/** Set DPLLs 1,2,3,4,5 to ON (locked) and autoidle.
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* @param device Register map.
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* The idea is to get all DPLLs running and make hw control their power mode,
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* based on the module requirements (module ICLKs and FCLKs).
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void amdm37x_setup_dpll_on_autoidle(amdm37x_t *device)
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/* Get SYS_CLK value, it is used as reference clock by all DPLLs,
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* NFI who sets this or why it is set to specific value. */
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const unsigned osc_clk = pio_read_32(&device->prm.clocks->clksel)
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& CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK;
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const unsigned clk_reg = pio_read_32(&device->prm.global->clksrc_ctrl);
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const unsigned base_freq = sys_clk_freq_kHz(osc_clk)
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/ GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_GET(clk_reg);
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ddf_msg(LVL_NOTE, "Base frequency: %d.%dMhz",
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base_freq / 1000, base_freq % 1000);
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/* DPLL1 provides MPU(CPU) clock.
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* It uses SYS_CLK as reference clock and core clock (DPLL3) as
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* high frequency bypass (MPU then runs on L3 interconnect freq).
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* It should be setup by fw or u-boot.*/
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mpu_cm_regs_t *mpu = device->cm.mpu;
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/* Current MPU frequency. */
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if (pio_read_32(&mpu->clkstst) & MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG) {
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if (pio_read_32(&mpu->idlest_pll) & MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG) {
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/* DPLL active and locked */
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const uint32_t reg = pio_read_32(&mpu->clksel1_pll);
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const unsigned multiplier =
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(reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK)
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>> MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT;
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const unsigned divisor =
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(reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_MASK)
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>> MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_SHIFT;
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const unsigned divisor2 =
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(pio_read_32(&mpu->clksel2_pll)
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& MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK);
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if (multiplier && divisor && divisor2) {
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/** See AMDM37x TRM p. 300 for the formula */
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const unsigned freq =
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((base_freq * multiplier) / (divisor + 1))
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ddf_msg(LVL_NOTE, "MPU running at %d.%d MHz",
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freq / 1000, freq % 1000);
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ddf_msg(LVL_WARN, "Frequency divisor and/or "
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"multiplier value invalid: %d %d %d",
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multiplier, divisor, divisor2);
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/* DPLL in LP bypass mode */
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const unsigned divisor =
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MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL(
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pio_read_32(&mpu->clksel1_pll));
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ddf_msg(LVL_NOTE, "MPU DPLL in bypass mode, running at"
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" CORE CLK / %d MHz", divisor);
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ddf_msg(LVL_WARN, "MPU clock domain is not active, we should not be running...");
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// TODO: Enable this (automatic MPU downclocking):
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/* Enable low power bypass mode, this will take effect the next lock or
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* relock sequence. */
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//TODO: We might need to force re-lock after enabling this
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pio_set_32(&mpu->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
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/* Enable automatic relocking */
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pio_change_32(&mpu->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
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/* DPLL2 provides IVA(video acceleration) clock.
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* It uses SYS_CLK as reference clokc and core clock (DPLL3) as
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* high frequency bypass (IVA runs on L3 freq).
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// TODO: We can probably turn this off entirely. IVA is left unused.
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/* Enable low power bypass mode, this will take effect the next lock or
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* relock sequence. */
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//TODO: We might need to force re-lock after enabling this
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pio_set_32(&device->cm.iva2->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
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/* Enable automatic relocking */
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pio_change_32(&device->cm.iva2->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
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/* DPLL3 provides tons of clocks:
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* CORE_CLK, COREX2_CLK, DSS_TV_CLK, 12M_CLK, 48M_CLK, 96M_CLK, L3_ICLK,
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* and L4_ICLK. It uses SYS_CLK as reference clock and low frequency
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* bypass. It should be setup by fw or u-boot as it controls critical
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if (pio_read_32(&device->cm.clocks->idlest_ckgen) & CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG) {
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/* DPLL active and locked */
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pio_read_32(&device->cm.clocks->clksel1_pll);
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const unsigned multiplier =
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CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(reg);
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const unsigned divisor =
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CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(reg);
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const unsigned divisor2 =
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CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(reg);
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if (multiplier && divisor && divisor2) {
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/** See AMDM37x TRM p. 300 for the formula */
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const unsigned freq =
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((base_freq * multiplier) / (divisor + 1)) / divisor2;
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ddf_msg(LVL_NOTE, "CORE CLK running at %d.%d MHz",
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freq / 1000, freq % 1000);
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const unsigned l3_div =
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pio_read_32(&device->cm.core->clksel)
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& CORE_CM_CLKSEL_CLKSEL_L3_MASK;
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if (l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 ||
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l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2) {
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ddf_msg(LVL_NOTE, "L3 interface at %d.%d MHz",
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(freq / l3_div) / 1000,
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(freq / l3_div) % 1000);
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ddf_msg(LVL_WARN,"L3 interface clock divisor is"
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" invalid: %d", l3_div);
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ddf_msg(LVL_WARN, "DPLL3 frequency divisor and/or "
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"multiplier value invalid: %d %d %d",
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multiplier, divisor, divisor2);
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ddf_msg(LVL_WARN, "CORE CLK in bypass mode, fruunig at SYS_CLK"
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" frreq of %d.%d MHz", base_freq / 1000, base_freq % 1000);
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/* Set DPLL3 to automatic to save power */
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pio_change_32(&device->cm.clocks->autoidle_pll,
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CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC,
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CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK, 5);
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/* DPLL4 provides peripheral domain clocks:
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* CAM_MCLK, EMU_PER_ALWON_CLK, DSS1_ALWON_FCLK, and 96M_ALWON_FCLK.
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* It uses SYS_CLK as reference clock and low frequency bypass.
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* 96M clock is used by McBSP[1,5], MMC[1,2,3], I2C[1,2,3], so
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* we can probably turn this off entirely (DSS is still non-functional).
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/* Set DPLL4 to automatic to save power */
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pio_change_32(&device->cm.clocks->autoidle_pll,
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CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC,
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CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK, 5);
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/* DPLL5 provide peripheral domain clocks: 120M_FCLK.
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* It uses SYS_CLK as reference clock and low frequency bypass.
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* 120M clock is used by HS USB and USB TLL.
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if ((pio_read_32(&device->cm.clocks->clken2_pll)
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& CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK)
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!= CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK) {
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/* Compute divisors and multiplier
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* See AMDM37x TRM p. 300 for the formula */
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// TODO: base_freq does not have to be rounded to Mhz
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// (that's why I used KHz as unit).
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const unsigned mult = 120;
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const unsigned div = (base_freq / 1000) - 1;
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const unsigned div2 = 1;
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if ( ((base_freq % 1000) != 0) || (div > 127)) {
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ddf_msg(LVL_ERROR, "Rounding error, or divisor to big "
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"freq: %d, div: %d", base_freq, div);
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pio_change_32(&device->cm.clocks->clksel4_pll,
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CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(mult),
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CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK, 10);
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/* Set DPLL divisor */
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pio_change_32(&device->cm.clocks->clksel4_pll,
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CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(div),
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CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK, 10);
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/* Set output clock divisor */
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pio_change_32(&device->cm.clocks->clksel5_pll,
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CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(div2),
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CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK, 10);
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pio_change_32(&device->cm.clocks->clken2_pll,
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CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK,
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CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK, 10);
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/* Set DPLL5 to automatic to save power */
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pio_change_32(&device->cm.clocks->autoidle2_pll,
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CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC,
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CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK, 5);
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/** Enable/disable function and interface clocks for USBTLL and USBHOST.
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* @param device Register map.
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* @param on True to switch clocks on.
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void amdm37x_usb_clocks_set(amdm37x_t *device, bool enabled)
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/* Enable interface and function clock for USB TLL */
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pio_set_32(&device->cm.core->fclken3,
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CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5);
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pio_set_32(&device->cm.core->iclken3,
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CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5);
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/* Enable interface and function clock for USB hosts */
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pio_set_32(&device->cm.usbhost->fclken,
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USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG |
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USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5);
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pio_set_32(&device->cm.usbhost->iclken,
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USBHOST_CM_ICLKEN_EN_USBHOST, 5);
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printf("DPLL5 (and everything else) should be on: %"
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PRIx32" %"PRIx32".\n",
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pio_read_32(&device->cm.clocks->idlest_ckgen),
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pio_read_32(&device->cm.clocks->idlest2_ckgen));
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/* Disable interface and function clock for USB hosts */
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pio_clear_32(&device->cm.usbhost->iclken,
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USBHOST_CM_ICLKEN_EN_USBHOST, 5);
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pio_clear_32(&device->cm.usbhost->fclken,
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USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG |
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USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5);
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/* Disable interface and function clock for USB TLL */
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pio_clear_32(&device->cm.core->iclken3,
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CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5);
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pio_clear_32(&device->cm.core->fclken3,
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CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5);
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/** Initialize USB TLL port connections.
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* Different modes are on page 3312 of the Manual Figure 22-34.
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* Select mode than can operate in FS/LS.
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int amdm37x_usb_tll_init(amdm37x_t *device)
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if (pio_read_32(&device->cm.core->idlest3) & CORE_CM_IDLEST3_ST_USBTLL_FLAG) {
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ddf_msg(LVL_ERROR, "USB TLL is not accessible");
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pio_set_32(&device->tll->sysconfig, TLL_SYSCONFIG_SOFTRESET_FLAG, 5);
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ddf_msg(LVL_DEBUG2, "Waiting for USB TLL reset");
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while (!(pio_read_32(&device->tll->sysstatus) & TLL_SYSSTATUS_RESET_DONE_FLAG));
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ddf_msg(LVL_DEBUG, "USB TLL Reset done.");
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/* Setup idle mode (smart idle) */
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pio_change_32(&device->tll->sysconfig,
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TLL_SYSCONFIG_CLOCKACTIVITY_FLAG | TLL_SYSCONFIG_AUTOIDLE_FLAG |
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TLL_SYSCONFIG_SIDLE_MODE_SMART, TLL_SYSCONFIG_SIDLE_MODE_MASK, 5);
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/* Smart idle for UHH */
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pio_change_32(&device->uhh->sysconfig,
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UHH_SYSCONFIG_CLOCKACTIVITY_FLAG | UHH_SYSCONFIG_AUTOIDLE_FLAG |
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UHH_SYSCONFIG_SIDLE_MODE_SMART, UHH_SYSCONFIG_SIDLE_MODE_MASK, 5);
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/* Set all ports to go through TLL(UTMI)
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* Direct connection can only work in HS mode */
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pio_set_32(&device->uhh->hostconfig,
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UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG |
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UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG |
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UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG, 5);
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pio_set_32(&device->tll->shared_conf, TLL_SHARED_CONF_FCLK_IS_ON_FLAG, 5);
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for (unsigned i = 0; i < 3; ++i) {
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/* Serial mode is the only one capable of FS/LS operation.
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* Select FS/LS mode, no idea what the difference is
395
* one of bidirectional modes might be good choice
396
* 2 = 3pin bidi phy. */
397
pio_change_32(&device->tll->channel_conf[i],
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TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE |
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TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY,
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TLL_CHANNEL_CONF_CHANMODE_MASK |
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TLL_CHANNEL_CONF_FSLSMODE_MASK, 5);
added
removed
uspace/drv/infrastructure/rootamdm37x/amdm37x.c
