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Committer: mmach
Date: 2021-03-17 18:24:35 UTC
Revision ID: netbit73@gmail.com-20210317182435-7okt04d35etrqgqp

lipiec

files added:

AUTHORS

COPYING

Makefile.am

NEWS

README

RELEASING

autogen.sh

benchmarks

benchmarks/.gitignore

benchmarks/Makefile.am

benchmarks/dri2-swap.c

benchmarks/dri3-swap.c

configure.ac

debian

debian/README.Debian

debian/README.source

debian/changelog

debian/control

debian/copyright

debian/patches

debian/patches/series

debian/rules

debian/source

debian/source/format

debian/upstream.changelog

debian/watch

debian/xorg.conf

debian/xserver-xorg-video-intel.docs

debian/xserver-xorg-video-intel.install

debian/xserver-xorg-video-intel.install.kfreebsd-amd64

debian/xserver-xorg-video-intel.install.kfreebsd-i386

debian/xserver-xorg-video-intel.links

debian/xserver-xorg-video-intel.lintian-overrides

debian/xserver-xorg-video-intel.maintscript

libobj

libobj/Makefile.am

libobj/alloca.c

libobj/getline.c

libobj/ignore.c

m4/ac_define_dir.m4

man/Makefile.am

man/intel.man

man/meson.build

meson.build

meson_options.txt

src/Makefile.am

src/backlight.c

src/backlight.h

src/compat-api.h

src/fd.c

src/fd.h

src/i915_pciids.h

src/intel_device.c

src/intel_driver.h

src/intel_list.h

src/intel_module.c

src/intel_options.c

src/intel_options.h

src/legacy

src/legacy/Makefile.am

src/legacy/README

src/legacy/i810

src/legacy/i810/Makefile.am

src/legacy/i810/i810.h

src/legacy/i810/i810_accel.c

src/legacy/i810/i810_common.h

src/legacy/i810/i810_cursor.c

src/legacy/i810/i810_dga.c

src/legacy/i810/i810_dri.c

src/legacy/i810/i810_dri.h

src/legacy/i810/i810_driver.c

src/legacy/i810/i810_hwmc.c

src/legacy/i810/i810_memory.c

src/legacy/i810/i810_reg.h

src/legacy/i810/i810_ring.h

src/legacy/i810/i810_video.c

src/legacy/i810/i810_wmark.c

src/legacy/i810/i810_xaa.c

src/legacy/i810/meson.build

src/legacy/i810/xvmc

src/legacy/i810/xvmc/I810XvMC.c

src/legacy/i810/xvmc/I810XvMC.h

src/legacy/i810/xvmc/Makefile.am

src/legacy/i810/xvmc/meson.build

src/legacy/legacy.h

src/meson.build

src/render_program

src/render_program/Makefile.am

src/render_program/exa_sf.g4a

src/render_program/exa_sf.g4b

src/render_program/exa_sf.g4b.gen5

src/render_program/exa_sf.g5a

src/render_program/exa_sf.g5b

src/render_program/exa_sf_mask.g4a

src/render_program/exa_sf_mask.g4b

src/render_program/exa_sf_mask.g4b.gen5

src/render_program/exa_sf_mask.g5a

src/render_program/exa_sf_mask.g5b

src/render_program/exa_wm.g4i

src/render_program/exa_wm_affine.g4i

src/render_program/exa_wm_affine.g6i

src/render_program/exa_wm_ca.g4a

src/render_program/exa_wm_ca.g4b

src/render_program/exa_wm_ca.g4b.gen5

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src/render_program/exa_wm_ca.g5b

src/render_program/exa_wm_ca.g6a

src/render_program/exa_wm_ca.g6b

src/render_program/exa_wm_ca_srcalpha.g4a

src/render_program/exa_wm_ca_srcalpha.g4b

src/render_program/exa_wm_ca_srcalpha.g4b.gen5

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src/render_program/exa_wm_ca_srcalpha.g5b

src/render_program/exa_wm_ca_srcalpha.g6a

src/render_program/exa_wm_ca_srcalpha.g6b

src/render_program/exa_wm_mask_affine.g4a

src/render_program/exa_wm_mask_affine.g4b

src/render_program/exa_wm_mask_affine.g4b.gen5

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src/render_program/exa_wm_mask_affine.g5b

src/render_program/exa_wm_mask_affine.g6a

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src/render_program/exa_wm_mask_affine.g7a

src/render_program/exa_wm_mask_affine.g7b

src/render_program/exa_wm_mask_projective.g4a

src/render_program/exa_wm_mask_projective.g4b

src/render_program/exa_wm_mask_projective.g4b.gen5

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src/render_program/exa_wm_mask_projective.g5b

src/render_program/exa_wm_mask_projective.g6a

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src/render_program/exa_wm_mask_projective.g7a

src/render_program/exa_wm_mask_projective.g7b

src/render_program/exa_wm_mask_sample_a.g4a

src/render_program/exa_wm_mask_sample_a.g4b

src/render_program/exa_wm_mask_sample_a.g4b.gen5

src/render_program/exa_wm_mask_sample_a.g5a

src/render_program/exa_wm_mask_sample_a.g5b

src/render_program/exa_wm_mask_sample_a.g6a

src/render_program/exa_wm_mask_sample_a.g6b

src/render_program/exa_wm_mask_sample_a.g7a

src/render_program/exa_wm_mask_sample_a.g7b

src/render_program/exa_wm_mask_sample_argb.g4a

src/render_program/exa_wm_mask_sample_argb.g4b

src/render_program/exa_wm_mask_sample_argb.g4b.gen5

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src/render_program/exa_wm_mask_sample_argb.g5b

src/render_program/exa_wm_mask_sample_argb.g6a

src/render_program/exa_wm_mask_sample_argb.g6b

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src/render_program/exa_wm_mask_sample_argb.g7b

src/render_program/exa_wm_noca.g4a

src/render_program/exa_wm_noca.g4b

src/render_program/exa_wm_noca.g4b.gen5

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src/render_program/exa_wm_noca.g5b

src/render_program/exa_wm_noca.g6a

src/render_program/exa_wm_noca.g6b

src/render_program/exa_wm_projective.g4i

src/render_program/exa_wm_sample_nv12.g4i

src/render_program/exa_wm_sample_planar.g4i

src/render_program/exa_wm_src_affine.g4a

src/render_program/exa_wm_src_affine.g4b

src/render_program/exa_wm_src_affine.g4b.gen5

src/render_program/exa_wm_src_affine.g5a

src/render_program/exa_wm_src_affine.g5b

src/render_program/exa_wm_src_affine.g6a

src/render_program/exa_wm_src_affine.g6b

src/render_program/exa_wm_src_affine.g7a

src/render_program/exa_wm_src_affine.g7b

src/render_program/exa_wm_src_affine.g8a

src/render_program/exa_wm_src_affine.g8b

src/render_program/exa_wm_src_projective.g4a

src/render_program/exa_wm_src_projective.g4b

src/render_program/exa_wm_src_projective.g4b.gen5

src/render_program/exa_wm_src_projective.g5a

src/render_program/exa_wm_src_projective.g5b

src/render_program/exa_wm_src_projective.g6a

src/render_program/exa_wm_src_projective.g6b

src/render_program/exa_wm_src_projective.g7a

src/render_program/exa_wm_src_projective.g7b

src/render_program/exa_wm_src_sample_a.g4a

src/render_program/exa_wm_src_sample_a.g4b

src/render_program/exa_wm_src_sample_a.g4b.gen5

src/render_program/exa_wm_src_sample_a.g5a

src/render_program/exa_wm_src_sample_a.g5b

src/render_program/exa_wm_src_sample_a.g6a

src/render_program/exa_wm_src_sample_a.g6b

src/render_program/exa_wm_src_sample_a.g7a

src/render_program/exa_wm_src_sample_a.g7b

src/render_program/exa_wm_src_sample_argb.g4a

src/render_program/exa_wm_src_sample_argb.g4b

src/render_program/exa_wm_src_sample_argb.g4b.gen5

src/render_program/exa_wm_src_sample_argb.g4i

src/render_program/exa_wm_src_sample_argb.g5a

src/render_program/exa_wm_src_sample_argb.g5b

src/render_program/exa_wm_src_sample_argb.g6a

src/render_program/exa_wm_src_sample_argb.g6b

src/render_program/exa_wm_src_sample_argb.g7a

src/render_program/exa_wm_src_sample_argb.g7b

src/render_program/exa_wm_src_sample_argb.g8a

src/render_program/exa_wm_src_sample_argb.g8b

src/render_program/exa_wm_src_sample_argb_ayuv.g8a

src/render_program/exa_wm_src_sample_argb_ayuv.g8b

src/render_program/exa_wm_src_sample_nv12.g4a

src/render_program/exa_wm_src_sample_nv12.g4b

src/render_program/exa_wm_src_sample_nv12.g4b.gen5

src/render_program/exa_wm_src_sample_nv12.g5a

src/render_program/exa_wm_src_sample_nv12.g5b

src/render_program/exa_wm_src_sample_nv12.g6a

src/render_program/exa_wm_src_sample_nv12.g6b

src/render_program/exa_wm_src_sample_nv12.g7a

src/render_program/exa_wm_src_sample_nv12.g7b

src/render_program/exa_wm_src_sample_nv12.g8a

src/render_program/exa_wm_src_sample_nv12.g8b

src/render_program/exa_wm_src_sample_planar.g4a

src/render_program/exa_wm_src_sample_planar.g4b

src/render_program/exa_wm_src_sample_planar.g4b.gen5

src/render_program/exa_wm_src_sample_planar.g5a

src/render_program/exa_wm_src_sample_planar.g5b

src/render_program/exa_wm_src_sample_planar.g6a

src/render_program/exa_wm_src_sample_planar.g6b

src/render_program/exa_wm_src_sample_planar.g7a

src/render_program/exa_wm_src_sample_planar.g7b

src/render_program/exa_wm_src_sample_planar.g8a

src/render_program/exa_wm_src_sample_planar.g8b

src/render_program/exa_wm_write.g4a

src/render_program/exa_wm_write.g4b

src/render_program/exa_wm_write.g4b.gen5

src/render_program/exa_wm_write.g5a

src/render_program/exa_wm_write.g5b

src/render_program/exa_wm_write.g6a

src/render_program/exa_wm_write.g6b

src/render_program/exa_wm_write.g6i

src/render_program/exa_wm_write.g7a

src/render_program/exa_wm_write.g7b

src/render_program/exa_wm_write.g8a

src/render_program/exa_wm_write.g8b

src/render_program/exa_wm_xy.g4a

src/render_program/exa_wm_xy.g4b

src/render_program/exa_wm_xy.g4b.gen5

src/render_program/exa_wm_xy.g5a

src/render_program/exa_wm_xy.g5b

src/render_program/exa_wm_yuv_rgb_bt601.g4a

src/render_program/exa_wm_yuv_rgb_bt601.g4b

src/render_program/exa_wm_yuv_rgb_bt601.g4b.gen5

src/render_program/exa_wm_yuv_rgb_bt601.g5a

src/render_program/exa_wm_yuv_rgb_bt601.g5b

src/render_program/exa_wm_yuv_rgb_bt601.g6a

src/render_program/exa_wm_yuv_rgb_bt601.g6b

src/render_program/exa_wm_yuv_rgb_bt601.g7a

src/render_program/exa_wm_yuv_rgb_bt601.g7b

src/render_program/exa_wm_yuv_rgb_bt601.g8a

src/render_program/exa_wm_yuv_rgb_bt601.g8b

src/render_program/exa_wm_yuv_rgb_bt709.g4a

src/render_program/exa_wm_yuv_rgb_bt709.g4b

src/render_program/exa_wm_yuv_rgb_bt709.g4b.gen5

src/render_program/exa_wm_yuv_rgb_bt709.g5a

src/render_program/exa_wm_yuv_rgb_bt709.g5b

src/render_program/exa_wm_yuv_rgb_bt709.g6a

src/render_program/exa_wm_yuv_rgb_bt709.g6b

src/render_program/exa_wm_yuv_rgb_bt709.g7a

src/render_program/exa_wm_yuv_rgb_bt709.g7b

src/render_program/exa_wm_yuv_rgb_bt709.g8a

src/render_program/exa_wm_yuv_rgb_bt709.g8b

src/scripts

src/scripts/clock-graph.5c

src/scripts/clock.5c

src/scripts/fix.5c

src/scripts/tv.5c

src/sna

src/sna/Makefile.am

src/sna/README

src/sna/atomic.h

src/sna/blt.c

src/sna/brw

src/sna/brw/Makefile.am

src/sna/brw/brw.h

src/sna/brw/brw_disasm.c

src/sna/brw/brw_eu.c

src/sna/brw/brw_eu.h

src/sna/brw/brw_eu_emit.c

src/sna/brw/brw_sf.c

src/sna/brw/brw_test.c

src/sna/brw/brw_test.h

src/sna/brw/brw_test_gen4.c

src/sna/brw/brw_test_gen5.c

src/sna/brw/brw_test_gen6.c

src/sna/brw/brw_test_gen7.c

src/sna/brw/brw_wm.c

src/sna/brw/meson.build

src/sna/compiler.h

src/sna/debug.h

src/sna/fb

src/sna/fb/Makefile.am

src/sna/fb/README

src/sna/fb/fb.h

src/sna/fb/fbarc.c

src/sna/fb/fbarcbits.h

src/sna/fb/fbbitmap.c

src/sna/fb/fbblt.c

src/sna/fb/fbbltone.c

src/sna/fb/fbclip.c

src/sna/fb/fbclip.h

src/sna/fb/fbcopy.c

src/sna/fb/fbfill.c

src/sna/fb/fbgc.c

src/sna/fb/fbglyph.c

src/sna/fb/fbglyphbits.h

src/sna/fb/fbimage.c

src/sna/fb/fbline.c

src/sna/fb/fblinebits.h

src/sna/fb/fbpict.c

src/sna/fb/fbpict.h

src/sna/fb/fbpoint.c

src/sna/fb/fbpointbits.h

src/sna/fb/fbpush.c

src/sna/fb/fbrop.h

src/sna/fb/fbseg.c

src/sna/fb/fbsegbits.h

src/sna/fb/fbspan.c

src/sna/fb/fbstipple.c

src/sna/fb/fbtile.c

src/sna/fb/fbutil.c

src/sna/fb/meson.build

src/sna/fb/sfb.h

src/sna/gen2_render.c

src/sna/gen2_render.h

src/sna/gen3_render.c

src/sna/gen3_render.h

src/sna/gen4_common.c

src/sna/gen4_common.h

src/sna/gen4_render.c

src/sna/gen4_render.h

src/sna/gen4_source.c

src/sna/gen4_source.h

src/sna/gen4_vertex.c

src/sna/gen4_vertex.h

src/sna/gen5_render.c

src/sna/gen5_render.h

src/sna/gen6_common.c

src/sna/gen6_common.h

src/sna/gen6_render.c

src/sna/gen6_render.h

src/sna/gen7_render.c

src/sna/gen7_render.h

src/sna/gen8_eu.c

src/sna/gen8_eu.h

src/sna/gen8_render.c

src/sna/gen8_render.h

src/sna/gen8_vertex.c

src/sna/gen8_vertex.h

src/sna/gen9_render.c

src/sna/gen9_render.h

src/sna/git_version.h.in

src/sna/kgem.c

src/sna/kgem.h

src/sna/kgem_debug.c

src/sna/kgem_debug.h

src/sna/kgem_debug_gen2.c

src/sna/kgem_debug_gen3.c

src/sna/kgem_debug_gen4.c

src/sna/kgem_debug_gen5.c

src/sna/kgem_debug_gen6.c

src/sna/kgem_debug_gen7.c

src/sna/meson.build

src/sna/rop.h

src/sna/sna.h

src/sna/sna_accel.c

src/sna/sna_acpi.c

src/sna/sna_blt.c

src/sna/sna_composite.c

src/sna/sna_cpu.c

src/sna/sna_cpuid.h

src/sna/sna_damage.c

src/sna/sna_damage.h

src/sna/sna_display.c

src/sna/sna_display_fake.c

src/sna/sna_dri2.c

src/sna/sna_dri3.c

src/sna/sna_driver.c

src/sna/sna_glyphs.c

src/sna/sna_gradient.c

src/sna/sna_io.c

src/sna/sna_module.h

src/sna/sna_present.c

src/sna/sna_reg.h

src/sna/sna_render.c

src/sna/sna_render.h

src/sna/sna_render_inline.h

src/sna/sna_stream.c

src/sna/sna_threads.c

src/sna/sna_tiling.c

src/sna/sna_transform.c

src/sna/sna_trapezoids.c

src/sna/sna_trapezoids.h

src/sna/sna_trapezoids_boxes.c

src/sna/sna_trapezoids_imprecise.c

src/sna/sna_trapezoids_mono.c

src/sna/sna_trapezoids_precise.c

src/sna/sna_vertex.c

src/sna/sna_video.c

src/sna/sna_video.h

src/sna/sna_video_hwmc.c

src/sna/sna_video_hwmc.h

src/sna/sna_video_overlay.c

src/sna/sna_video_sprite.c

src/sna/sna_video_textured.c

src/sna/xassert.h

src/uxa

src/uxa/Makefile.am

src/uxa/brw_defines.h

src/uxa/brw_structs.h

src/uxa/common.h

src/uxa/i830_3d.c

src/uxa/i830_reg.h

src/uxa/i830_render.c

src/uxa/i915_3d.c

src/uxa/i915_3d.h

src/uxa/i915_reg.h

src/uxa/i915_render.c

src/uxa/i915_video.c

src/uxa/i965_3d.c

src/uxa/i965_reg.h

src/uxa/i965_render.c

src/uxa/i965_video.c

src/uxa/intel.h

src/uxa/intel_batchbuffer.c

src/uxa/intel_batchbuffer.h

src/uxa/intel_display.c

src/uxa/intel_dri.c

src/uxa/intel_dri3.c

src/uxa/intel_driver.c

src/uxa/intel_hwmc.c

src/uxa/intel_memory.c

src/uxa/intel_present.c

src/uxa/intel_sync.c

src/uxa/intel_uxa.c

src/uxa/intel_uxa.h

src/uxa/intel_uxa_video.c

src/uxa/intel_video.c

src/uxa/intel_video.h

src/uxa/intel_video_overlay.c

src/uxa/intel_video_overlay.h

src/uxa/meson.build

src/uxa/uxa-accel.c

src/uxa/uxa-glyphs.c

src/uxa/uxa-priv.h

src/uxa/uxa-render.c

src/uxa/uxa-unaccel.c

src/uxa/uxa.c

src/uxa/uxa.h

src/uxa/uxa_module.h

test

test/.gitignore

test/DrawSegments.c

test/Makefile.am

test/README

test/basic-copyarea-size.c

test/basic-copyarea.c

test/basic-copyplane.c

test/basic-fillrect.c

test/basic-lines.c

test/basic-putimage.c

test/basic-rectangle.c

test/basic-stippledrect.c

test/basic-stress.c

test/basic-string.c

test/basic-tiledrect.c

test/cursor-test.c

test/dri2-race.c

test/dri2-speed.c

test/dri2-swap.c

test/dri2-test.c

test/dri2.c

test/dri2.h

test/dri3-test.c

test/dri3.c

test/dri3.h

test/lowlevel-blt-bench.c

test/mixed-stress.c

test/mkvsync.sh

test/present-race.c

test/present-speed.c

test/present-test.c

test/render-composite-solid-mask.c

test/render-composite-solid.c

test/render-copy-alphaless.c

test/render-copyarea-mask.c

test/render-copyarea-size.c

test/render-copyarea.c

test/render-fill-copy.c

test/render-fill.c

test/render-glyphs.c

test/render-trapezoid-image.c

test/render-trapezoid.c

test/render-triangle.c

test/shm-test.c

test/tearing.mp4

test/test.h

test/test_display.c

test/test_image.c

test/test_log.c

test/test_render.c

test/virtual.conf

test/xvidmode.c

tools

tools/.gitignore

tools/Makefile.am

tools/backlight_helper.c

tools/cursor.c

tools/dri3info.c

tools/intel-virtual-output.man

tools/meson.build

tools/org.x.xf86-video-intel.backlight-helper.policy.in

tools/virtual.c

xvmc

xvmc/Makefile.am

xvmc/brw_defines.h

xvmc/brw_structs.h

xvmc/i830_reg.h

xvmc/i915_program.h

xvmc/i915_reg.h

xvmc/i915_structs.h

xvmc/i915_xvmc.c

xvmc/i915_xvmc.h

xvmc/i965_reg.h

xvmc/i965_xvmc.c

xvmc/intel_batchbuffer.c

xvmc/intel_batchbuffer.h

xvmc/intel_xvmc.c

xvmc/intel_xvmc.h

xvmc/intel_xvmc_dump.c

xvmc/intel_xvmc_private.h

xvmc/meson.build

xvmc/shader

xvmc/shader/Makefile.am

xvmc/shader/mc

xvmc/shader/mc/Makefile.am

xvmc/shader/mc/addidct.g4i

xvmc/shader/mc/addidct_igd.g4i

xvmc/shader/mc/block_clear.g4i

xvmc/shader/mc/dual_prime.g4a

xvmc/shader/mc/dual_prime.g4b

xvmc/shader/mc/dual_prime.g4b.gen5

xvmc/shader/mc/dual_prime_igd.g4a

xvmc/shader/mc/dual_prime_igd.g4b

xvmc/shader/mc/dual_prime_igd.g4b.gen5

xvmc/shader/mc/field_backward.g4a

xvmc/shader/mc/field_backward.g4b

xvmc/shader/mc/field_backward.g4b.gen5

xvmc/shader/mc/field_backward_igd.g4a

xvmc/shader/mc/field_backward_igd.g4b

xvmc/shader/mc/field_backward_igd.g4b.gen5

xvmc/shader/mc/field_f_b.g4a

xvmc/shader/mc/field_f_b.g4b

xvmc/shader/mc/field_f_b.g4b.gen5

xvmc/shader/mc/field_f_b_igd.g4a

xvmc/shader/mc/field_f_b_igd.g4b

xvmc/shader/mc/field_f_b_igd.g4b.gen5

xvmc/shader/mc/field_forward.g4a

xvmc/shader/mc/field_forward.g4b

xvmc/shader/mc/field_forward.g4b.gen5

xvmc/shader/mc/field_forward_igd.g4a

xvmc/shader/mc/field_forward_igd.g4b

xvmc/shader/mc/field_forward_igd.g4b.gen5

xvmc/shader/mc/frame_backward.g4a

xvmc/shader/mc/frame_backward.g4b

xvmc/shader/mc/frame_backward.g4b.gen5

xvmc/shader/mc/frame_backward_igd.g4a

xvmc/shader/mc/frame_backward_igd.g4b

xvmc/shader/mc/frame_backward_igd.g4b.gen5

xvmc/shader/mc/frame_f_b.g4a

xvmc/shader/mc/frame_f_b.g4b

xvmc/shader/mc/frame_f_b.g4b.gen5

xvmc/shader/mc/frame_f_b_igd.g4a

xvmc/shader/mc/frame_f_b_igd.g4b

xvmc/shader/mc/frame_f_b_igd.g4b.gen5

xvmc/shader/mc/frame_forward.g4a

xvmc/shader/mc/frame_forward.g4b

xvmc/shader/mc/frame_forward.g4b.gen5

xvmc/shader/mc/frame_forward_igd.g4a

xvmc/shader/mc/frame_forward_igd.g4b

xvmc/shader/mc/frame_forward_igd.g4b.gen5

xvmc/shader/mc/ipicture.g4a

xvmc/shader/mc/ipicture.g4b

xvmc/shader/mc/ipicture.g4b.gen5

xvmc/shader/mc/ipicture_igd.g4a

xvmc/shader/mc/ipicture_igd.g4b

xvmc/shader/mc/ipicture_igd.g4b.gen5

xvmc/shader/mc/lib_igd.g4a

xvmc/shader/mc/lib_igd.g4b

xvmc/shader/mc/lib_igd.g4b.gen5

xvmc/shader/mc/motion_field_uv.g4i

xvmc/shader/mc/motion_field_uv_igd.g4i

xvmc/shader/mc/motion_field_y.g4i

xvmc/shader/mc/motion_field_y_igd.g4i

xvmc/shader/mc/motion_frame_uv.g4i

xvmc/shader/mc/motion_frame_uv_igd.g4i

xvmc/shader/mc/motion_frame_y.g4i

xvmc/shader/mc/motion_frame_y_igd.g4i

xvmc/shader/mc/null.g4a

xvmc/shader/mc/null.g4b

xvmc/shader/mc/null.g4b.gen5

xvmc/shader/mc/read_field_x0y0_uv.g4i

xvmc/shader/mc/read_field_x0y0_uv_igd.g4i

xvmc/shader/mc/read_field_x0y0_y.g4i

xvmc/shader/mc/read_field_x0y0_y_igd.g4i

xvmc/shader/mc/read_field_x0y1_uv.g4i

xvmc/shader/mc/read_field_x0y1_uv_igd.g4i

xvmc/shader/mc/read_field_x0y1_y.g4i

xvmc/shader/mc/read_field_x0y1_y_igd.g4i

xvmc/shader/mc/read_field_x1y0_uv.g4i

xvmc/shader/mc/read_field_x1y0_uv_igd.g4i

xvmc/shader/mc/read_field_x1y0_y.g4i

xvmc/shader/mc/read_field_x1y0_y_igd.g4i

xvmc/shader/mc/read_field_x1y1_uv.g4i

xvmc/shader/mc/read_field_x1y1_uv_igd.g4i

xvmc/shader/mc/read_field_x1y1_y.g4i

xvmc/shader/mc/read_field_x1y1_y_igd.g4i

xvmc/shader/mc/read_frame_x0y0_uv.g4i

xvmc/shader/mc/read_frame_x0y0_uv_igd.g4i

xvmc/shader/mc/read_frame_x0y0_y.g4i

xvmc/shader/mc/read_frame_x0y0_y_igd.g4i

xvmc/shader/mc/read_frame_x0y1_uv.g4i

xvmc/shader/mc/read_frame_x0y1_uv_igd.g4i

xvmc/shader/mc/read_frame_x0y1_y.g4i

xvmc/shader/mc/read_frame_x0y1_y_igd.g4i

xvmc/shader/mc/read_frame_x1y0_uv.g4i

xvmc/shader/mc/read_frame_x1y0_uv_igd.g4i

xvmc/shader/mc/read_frame_x1y0_y.g4i

xvmc/shader/mc/read_frame_x1y0_y_igd.g4i

xvmc/shader/mc/read_frame_x1y1_uv.g4i

xvmc/shader/mc/read_frame_x1y1_uv_igd.g4i

xvmc/shader/mc/read_frame_x1y1_y.g4i

xvmc/shader/mc/read_frame_x1y1_y_igd.g4i

xvmc/shader/vld

xvmc/shader/vld/Makefile.am

xvmc/shader/vld/addidct.g4i

xvmc/shader/vld/do_iq_intra.g4i

xvmc/shader/vld/do_iq_non_intra.g4i

xvmc/shader/vld/field_backward.g4a

xvmc/shader/vld/field_backward.g4b

xvmc/shader/vld/field_backward.g4b.gen5

xvmc/shader/vld/field_f_b.g4a

xvmc/shader/vld/field_f_b.g4b

xvmc/shader/vld/field_f_b.g4b.gen5

xvmc/shader/vld/field_forward.g4a

xvmc/shader/vld/field_forward.g4b

xvmc/shader/vld/field_forward.g4b.gen5

xvmc/shader/vld/frame_backward.g4a

xvmc/shader/vld/frame_backward.g4b

xvmc/shader/vld/frame_backward.g4b.gen5

xvmc/shader/vld/frame_f_b.g4a

xvmc/shader/vld/frame_f_b.g4b

xvmc/shader/vld/frame_f_b.g4b.gen5

xvmc/shader/vld/frame_forward.g4a

xvmc/shader/vld/frame_forward.g4b

xvmc/shader/vld/frame_forward.g4b.gen5

xvmc/shader/vld/idct.g4i

xvmc/shader/vld/ipicture.g4a

xvmc/shader/vld/ipicture.g4b

xvmc/shader/vld/ipicture.g4b.gen5

xvmc/shader/vld/iq_intra.g4i

xvmc/shader/vld/iq_non_intra.g4i

xvmc/shader/vld/lib.g4a

xvmc/shader/vld/lib.g4b

xvmc/shader/vld/lib.g4b.gen5

xvmc/shader/vld/motion_field_uv.g4i

xvmc/shader/vld/motion_field_y.g4i

xvmc/shader/vld/motion_frame_uv.g4i

xvmc/shader/vld/motion_frame_y.g4i

xvmc/shader/vld/read_field_x0y0_uv.g4i

xvmc/shader/vld/read_field_x0y0_y.g4i

xvmc/shader/vld/read_field_x0y1_uv.g4i

xvmc/shader/vld/read_field_x0y1_y.g4i

xvmc/shader/vld/read_field_x1y0_uv.g4i

xvmc/shader/vld/read_field_x1y0_y.g4i

xvmc/shader/vld/read_field_x1y1_uv.g4i

xvmc/shader/vld/read_field_x1y1_y.g4i

xvmc/shader/vld/read_frame_x0y0_uv.g4i

xvmc/shader/vld/read_frame_x0y0_y.g4i

xvmc/shader/vld/read_frame_x0y1_uv.g4i

xvmc/shader/vld/read_frame_x0y1_y.g4i

xvmc/shader/vld/read_frame_x1y0_uv.g4i

xvmc/shader/vld/read_frame_x1y0_y.g4i

xvmc/shader/vld/read_frame_x1y1_uv.g4i

xvmc/shader/vld/read_frame_x1y1_y.g4i

xvmc/xvmc_vld.c

Show diffs side-by-side

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removed removed

xvmc/brw_structs.h

/**************************************************************************

* Permission is hereby granted, free of charge, to any person obtaining a

* copy of this software and associated documentation files (the

* "Software"), to deal in the Software without restriction, including

* without limitation the rights to use, copy, modify, merge, publish,

* distribute, sub license, and/or sell copies of the Software, and to

* permit persons to whom the Software is furnished to do so, subject to

* the following conditions:

* The above copyright notice and this permission notice (including the

* next paragraph) shall be included in all copies or substantial portions

* of the Software.

* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.

* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR

* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

**************************************************************************/

#ifndef BRW_STRUCTS_H

#define BRW_STRUCTS_H

/* Command packets:

struct header

{

unsigned int length:16;

unsigned int opcode:16;

};

union header_union

{

struct header bits;

unsigned int dword;

};

struct brw_3d_control

{

struct

{

unsigned int length:8;

unsigned int notify_enable:1;

unsigned int pad:3;

unsigned int wc_flush_enable:1;

unsigned int depth_stall_enable:1;

unsigned int operation:2;

unsigned int opcode:16;

} header;

struct

{

unsigned int pad:2;

unsigned int dest_addr_type:1;

unsigned int dest_addr:29;

} dest;

unsigned int dword2;

unsigned int dword3;

};

struct brw_3d_primitive

{

struct

{

unsigned int length:8;

unsigned int pad:2;

unsigned int topology:5;

unsigned int indexed:1;

unsigned int opcode:16;

} header;

unsigned int verts_per_instance;

unsigned int start_vert_location;

unsigned int instance_count;

unsigned int start_instance_location;

unsigned int base_vert_location;

};

/* These seem to be passed around as function args, so it works out

* better to keep them as #defines:

#define BRW_FLUSH_READ_CACHE 0x1

#define BRW_FLUSH_STATE_CACHE 0x2

#define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4

#define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8

struct brw_mi_flush

{

unsigned int flags:4;

100

unsigned int pad:12;

101

unsigned int opcode:16;

102

};

103

104

struct brw_vf_statistics

105

{

106

unsigned int statistics_enable:1;

107

unsigned int pad:15;

108

unsigned int opcode:16;

109

};

110

111

112

113

struct brw_binding_table_pointers

114

{

115

struct header header;

116

unsigned int vs;

117

unsigned int gs;

118

unsigned int clp;

119

unsigned int sf;

120

unsigned int wm;

121

};

122

123

124

struct brw_blend_constant_color

125

{

126

struct header header;

127

float blend_constant_color[4];

128

};

129

130

131

struct brw_depthbuffer

132

{

133

union header_union header;

134

135

union {

136

struct {

137

unsigned int pitch:18;

138

unsigned int format:3;

139

unsigned int pad:4;

140

unsigned int depth_offset_disable:1;

141

unsigned int tile_walk:1;

142

unsigned int tiled_surface:1;

143

unsigned int pad2:1;

144

unsigned int surface_type:3;

145

} bits;

146

unsigned int dword;

147

} dword1;

148

149

unsigned int dword2_base_addr;

150

151

union {

152

struct {

153

unsigned int pad:1;

154

unsigned int mipmap_layout:1;

155

unsigned int lod:4;

156

unsigned int width:13;

157

unsigned int height:13;

158

} bits;

159

unsigned int dword;

160

} dword3;

161

162

union {

163

struct {

164

unsigned int pad:12;

165

unsigned int min_array_element:9;

166

unsigned int depth:11;

167

} bits;

168

unsigned int dword;

169

} dword4;

170

};

171

172

struct brw_drawrect

173

{

174

struct header header;

175

unsigned int xmin:16;

176

unsigned int ymin:16;

177

unsigned int xmax:16;

178

unsigned int ymax:16;

179

unsigned int xorg:16;

180

unsigned int yorg:16;

181

};

182

183

184

185

186

struct brw_global_depth_offset_clamp

187

{

188

struct header header;

189

float depth_offset_clamp;

190

};

191

192

struct brw_indexbuffer

193

{

194

union {

195

struct

196

{

197

unsigned int length:8;

198

unsigned int index_format:2;

199

unsigned int cut_index_enable:1;

200

unsigned int pad:5;

201

unsigned int opcode:16;

202

} bits;

203

unsigned int dword;

204

205

} header;

206

207

unsigned int buffer_start;

208

unsigned int buffer_end;

209

};

210

211

212

struct brw_line_stipple

213

{

214

struct header header;

215

216

struct

217

{

218

unsigned int pattern:16;

219

unsigned int pad:16;

220

} bits0;

221

222

struct

223

{

224

unsigned int repeat_count:9;

225

unsigned int pad:7;

226

unsigned int inverse_repeat_count:16;

227

} bits1;

228

};

229

230

231

struct brw_pipelined_state_pointers

232

{

233

struct header header;

234

235

struct {

236

unsigned int pad:5;

237

unsigned int offset:27;

238

} vs;

239

240

struct

241

{

242

unsigned int enable:1;

243

unsigned int pad:4;

244

unsigned int offset:27;

245

} gs;

246

247

struct

248

{

249

unsigned int enable:1;

250

unsigned int pad:4;

251

unsigned int offset:27;

252

} clp;

253

254

struct

255

{

256

unsigned int pad:5;

257

unsigned int offset:27;

258

} sf;

259

260

struct

261

{

262

unsigned int pad:5;

263

unsigned int offset:27;

264

} wm;

265

266

struct

267

{

268

unsigned int pad:5;

269

unsigned int offset:27; /* KW: check me! */

270

} cc;

271

};

272

273

274

struct brw_polygon_stipple_offset

275

{

276

struct header header;

277

278

struct {

279

unsigned int y_offset:5;

280

unsigned int pad:3;

281

unsigned int x_offset:5;

282

unsigned int pad0:19;

283

} bits0;

284

};

285

286

287

288

struct brw_polygon_stipple

289

{

290

struct header header;

291

unsigned int stipple[32];

292

};

293

294

295

296

struct brw_pipeline_select

297

{

298

struct

299

{

300

unsigned int pipeline_select:1;

301

unsigned int pad:15;

302

unsigned int opcode:16;

303

} header;

304

};

305

306

307

struct brw_pipe_control

308

{

309

struct

310

{

311

unsigned int length:8;

312

unsigned int notify_enable:1;

313

unsigned int pad:2;

314

unsigned int instruction_state_cache_flush_enable:1;

315

unsigned int write_cache_flush_enable:1;

316

unsigned int depth_stall_enable:1;

317

unsigned int post_sync_operation:2;

318

319

unsigned int opcode:16;

320

} header;

321

322

struct

323

{

324

unsigned int pad:2;

325

unsigned int dest_addr_type:1;

326

unsigned int dest_addr:29;

327

} bits1;

328

329

unsigned int data0;

330

unsigned int data1;

331

};

332

333

334

struct brw_urb_fence

335

{

336

struct

337

{

338

unsigned int length:8;

339

unsigned int vs_realloc:1;

340

unsigned int gs_realloc:1;

341

unsigned int clp_realloc:1;

342

unsigned int sf_realloc:1;

343

unsigned int vfe_realloc:1;

344

unsigned int cs_realloc:1;

345

unsigned int pad:2;

346

unsigned int opcode:16;

347

} header;

348

349

struct

350

{

351

unsigned int vs_fence:10;

352

unsigned int gs_fence:10;

353

unsigned int clp_fence:10;

354

unsigned int pad:2;

355

} bits0;

356

357

struct

358

{

359

unsigned int sf_fence:10;

360

unsigned int vf_fence:10;

361

unsigned int cs_fence:10;

362

unsigned int pad:2;

363

} bits1;

364

};

365

366

struct brw_constant_buffer_state /* previously brw_command_streamer */

367

{

368

struct header header;

369

370

struct

371

{

372

unsigned int nr_urb_entries:3;

373

unsigned int pad:1;

374

unsigned int urb_entry_size:5;

375

unsigned int pad0:23;

376

} bits0;

377

};

378

379

struct brw_constant_buffer

380

{

381

struct

382

{

383

unsigned int length:8;

384

unsigned int valid:1;

385

unsigned int pad:7;

386

unsigned int opcode:16;

387

} header;

388

389

struct

390

{

391

unsigned int buffer_length:6;

392

unsigned int buffer_address:26;

393

} bits0;

394

};

395

396

struct brw_state_base_address

397

{

398

struct header header;

399

400

struct

401

{

402

unsigned int modify_enable:1;

403

unsigned int pad:4;

404

unsigned int general_state_address:27;

405

} bits0;

406

407

struct

408

{

409

unsigned int modify_enable:1;

410

unsigned int pad:4;

411

unsigned int surface_state_address:27;

412

} bits1;

413

414

struct

415

{

416

unsigned int modify_enable:1;

417

unsigned int pad:4;

418

unsigned int indirect_object_state_address:27;

419

} bits2;

420

421

struct

422

{

423

unsigned int modify_enable:1;

424

unsigned int pad:11;

425

unsigned int general_state_upper_bound:20;

426

} bits3;

427

428

struct

429

{

430

unsigned int modify_enable:1;

431

unsigned int pad:11;

432

unsigned int indirect_object_state_upper_bound:20;

433

} bits4;

434

};

435

436

struct brw_state_prefetch

437

{

438

struct header header;

439

440

struct

441

{

442

unsigned int prefetch_count:3;

443

unsigned int pad:3;

444

unsigned int prefetch_pointer:26;

445

} bits0;

446

};

447

448

struct brw_system_instruction_pointer

449

{

450

struct header header;

451

452

struct

453

{

454

unsigned int pad:4;

455

unsigned int system_instruction_pointer:28;

456

} bits0;

457

};

458

459

460

461

462

/* State structs for the various fixed function units:

463

464

465

466

struct thread0

467

{

468

unsigned int pad0:1;

469

unsigned int grf_reg_count:3;

470

unsigned int pad1:2;

471

unsigned int kernel_start_pointer:26;

472

};

473

474

struct thread1

475

{

476

unsigned int ext_halt_exception_enable:1;

477

unsigned int sw_exception_enable:1;

478

unsigned int mask_stack_exception_enable:1;

479

unsigned int timeout_exception_enable:1;

480

unsigned int illegal_op_exception_enable:1;

481

unsigned int pad0:3;

482

unsigned int depth_coef_urb_read_offset:6; /* WM only */

483

unsigned int pad1:2;

484

unsigned int floating_point_mode:1;

485

unsigned int thread_priority:1;

486

unsigned int binding_table_entry_count:8;

487

unsigned int pad3:5;

488

unsigned int single_program_flow:1;

489

};

490

491

struct thread2

492

{

493

unsigned int per_thread_scratch_space:4;

494

unsigned int pad0:6;

495

unsigned int scratch_space_base_pointer:22;

496

};

497

498

499

struct thread3

500

{

501

unsigned int dispatch_grf_start_reg:4;

502

unsigned int urb_entry_read_offset:6;

503

unsigned int pad0:1;

504

unsigned int urb_entry_read_length:6;

505

unsigned int pad1:1;

506

unsigned int const_urb_entry_read_offset:6;

507

unsigned int pad2:1;

508

unsigned int const_urb_entry_read_length:6;

509

unsigned int pad3:1;

510

};

511

512

513

514

struct brw_clip_unit_state

515

{

516

struct thread0 thread0;

517

struct thread1 thread1;

518

struct thread2 thread2;

519

struct thread3 thread3;

520

521

struct

522

{

523

unsigned int pad0:9;

524

unsigned int gs_output_stats:1; /* not always */

525

unsigned int stats_enable:1;

526

unsigned int nr_urb_entries:7;

527

unsigned int pad1:1;

528

unsigned int urb_entry_allocation_size:5;

529

unsigned int pad2:1;

530

unsigned int max_threads:6; /* may be less */

531

unsigned int pad3:1;

532

} thread4;

533

534

struct

535

{

536

unsigned int pad0:13;

537

unsigned int clip_mode:3;

538

unsigned int userclip_enable_flags:8;

539

unsigned int userclip_must_clip:1;

540

unsigned int pad1:1;

541

unsigned int guard_band_enable:1;

542

unsigned int viewport_z_clip_enable:1;

543

unsigned int viewport_xy_clip_enable:1;

544

unsigned int vertex_position_space:1;

545

unsigned int api_mode:1;

546

unsigned int pad2:1;

547

} clip5;

548

549

struct

550

{

551

unsigned int pad0:5;

552

unsigned int clipper_viewport_state_ptr:27;

553

} clip6;

554

555

556

float viewport_xmin;

557

float viewport_xmax;

558

float viewport_ymin;

559

float viewport_ymax;

560

};

561

562

563

564

struct brw_cc_unit_state

565

{

566

struct

567

{

568

unsigned int pad0:3;

569

unsigned int bf_stencil_pass_depth_pass_op:3;

570

unsigned int bf_stencil_pass_depth_fail_op:3;

571

unsigned int bf_stencil_fail_op:3;

572

unsigned int bf_stencil_func:3;

573

unsigned int bf_stencil_enable:1;

574

unsigned int pad1:2;

575

unsigned int stencil_write_enable:1;

576

unsigned int stencil_pass_depth_pass_op:3;

577

unsigned int stencil_pass_depth_fail_op:3;

578

unsigned int stencil_fail_op:3;

579

unsigned int stencil_func:3;

580

unsigned int stencil_enable:1;

581

} cc0;

582

583

584

struct

585

{

586

unsigned int bf_stencil_ref:8;

587

unsigned int stencil_write_mask:8;

588

unsigned int stencil_test_mask:8;

589

unsigned int stencil_ref:8;

590

} cc1;

591

592

593

struct

594

{

595

unsigned int logicop_enable:1;

596

unsigned int pad0:10;

597

unsigned int depth_write_enable:1;

598

unsigned int depth_test_function:3;

599

unsigned int depth_test:1;

600

unsigned int bf_stencil_write_mask:8;

601

unsigned int bf_stencil_test_mask:8;

602

} cc2;

603

604

605

struct

606

{

607

unsigned int pad0:8;

608

unsigned int alpha_test_func:3;

609

unsigned int alpha_test:1;

610

unsigned int blend_enable:1;

611

unsigned int ia_blend_enable:1;

612

unsigned int pad1:1;

613

unsigned int alpha_test_format:1;

614

unsigned int pad2:16;

615

} cc3;

616

617

struct

618

{

619

unsigned int pad0:5;

620

unsigned int cc_viewport_state_offset:27;

621

} cc4;

622

623

struct

624

{

625

unsigned int pad0:2;

626

unsigned int ia_dest_blend_factor:5;

627

unsigned int ia_src_blend_factor:5;

628

unsigned int ia_blend_function:3;

629

unsigned int statistics_enable:1;

630

unsigned int logicop_func:4;

631

unsigned int pad1:11;

632

unsigned int dither_enable:1;

633

} cc5;

634

635

struct

636

{

637

unsigned int clamp_post_alpha_blend:1;

638

unsigned int clamp_pre_alpha_blend:1;

639

unsigned int clamp_range:2;

640

unsigned int pad0:11;

641

unsigned int y_dither_offset:2;

642

unsigned int x_dither_offset:2;

643

unsigned int dest_blend_factor:5;

644

unsigned int src_blend_factor:5;

645

unsigned int blend_function:3;

646

} cc6;

647

648

struct {

649

union {

650

float f;

651

unsigned char ub[4];

652

} alpha_ref;

653

} cc7;

654

};

655

656

657

658

struct brw_sf_unit_state

659

{

660

struct thread0 thread0;

661

struct {

662

unsigned int pad0:7;

663

unsigned int sw_exception_enable:1;

664

unsigned int pad1:3;

665

unsigned int mask_stack_exception_enable:1;

666

unsigned int pad2:1;

667

unsigned int illegal_op_exception_enable:1;

668

unsigned int pad3:2;

669

unsigned int floating_point_mode:1;

670

unsigned int thread_priority:1;

671

unsigned int binding_table_entry_count:8;

672

unsigned int pad4:5;

673

unsigned int single_program_flow:1;

674

} sf1;

675

676

struct thread2 thread2;

677

struct thread3 thread3;

678

679

struct

680

{

681

unsigned int pad0:10;

682

unsigned int stats_enable:1;

683

unsigned int nr_urb_entries:7;

684

unsigned int pad1:1;

685

unsigned int urb_entry_allocation_size:5;

686

unsigned int pad2:1;

687

unsigned int max_threads:6;

688

unsigned int pad3:1;

689

} thread4;

690

691

struct

692

{

693

unsigned int front_winding:1;

694

unsigned int viewport_transform:1;

695

unsigned int pad0:3;

696

unsigned int sf_viewport_state_offset:27;

697

} sf5;

698

699

struct

700

{

701

unsigned int pad0:9;

702

unsigned int dest_org_vbias:4;

703

unsigned int dest_org_hbias:4;

704

unsigned int scissor:1;

705

unsigned int disable_2x2_trifilter:1;

706

unsigned int disable_zero_pix_trifilter:1;

707

unsigned int point_rast_rule:2;

708

unsigned int line_endcap_aa_region_width:2;

709

unsigned int line_width:4;

710

unsigned int fast_scissor_disable:1;

711

unsigned int cull_mode:2;

712

unsigned int aa_enable:1;

713

} sf6;

714

715

struct

716

{

717

unsigned int point_size:11;

718

unsigned int use_point_size_state:1;

719

unsigned int subpixel_precision:1;

720

unsigned int sprite_point:1;

721

unsigned int pad0:11;

722

unsigned int trifan_pv:2;

723

unsigned int linestrip_pv:2;

724

unsigned int tristrip_pv:2;

725

unsigned int line_last_pixel_enable:1;

726

} sf7;

727

728

};

729

730

731

struct brw_gs_unit_state

732

{

733

struct thread0 thread0;

734

struct thread1 thread1;

735

struct thread2 thread2;

736

struct thread3 thread3;

737

738

struct

739

{

740

unsigned int pad0:10;

741

unsigned int stats_enable:1;

742

unsigned int nr_urb_entries:7;

743

unsigned int pad1:1;

744

unsigned int urb_entry_allocation_size:5;

745

unsigned int pad2:1;

746

unsigned int max_threads:1;

747

unsigned int pad3:6;

748

} thread4;

749

750

struct

751

{

752

unsigned int sampler_count:3;

753

unsigned int pad0:2;

754

unsigned int sampler_state_pointer:27;

755

} gs5;

756

757

758

struct

759

{

760

unsigned int max_vp_index:4;

761

unsigned int pad0:26;

762

unsigned int reorder_enable:1;

763

unsigned int pad1:1;

764

} gs6;

765

};

766

767

768

struct brw_vs_unit_state

769

{

770

struct thread0 thread0;

771

struct thread1 thread1;

772

struct thread2 thread2;

773

struct thread3 thread3;

774

775

struct

776

{

777

unsigned int pad0:10;

778

unsigned int stats_enable:1;

779

unsigned int nr_urb_entries:7;

780

unsigned int pad1:1;

781

unsigned int urb_entry_allocation_size:5;

782

unsigned int pad2:1;

783

unsigned int max_threads:4;

784

unsigned int pad3:3;

785

} thread4;

786

787

struct

788

{

789

unsigned int sampler_count:3;

790

unsigned int pad0:2;

791

unsigned int sampler_state_pointer:27;

792

} vs5;

793

794

struct

795

{

796

unsigned int vs_enable:1;

797

unsigned int vert_cache_disable:1;

798

unsigned int pad0:30;

799

} vs6;

800

};

801

802

803

struct brw_wm_unit_state

804

{

805

struct thread0 thread0;

806

struct thread1 thread1;

807

struct thread2 thread2;

808

struct thread3 thread3;

809

810

struct {

811

unsigned int stats_enable:1;

812

unsigned int pad0:1;

813

unsigned int sampler_count:3;

814

unsigned int sampler_state_pointer:27;

815

} wm4;

816

817

struct

818

{

819

unsigned int enable_8_pix:1;

820

unsigned int enable_16_pix:1;

821

unsigned int enable_32_pix:1;

822

unsigned int pad0:7;

823

unsigned int legacy_global_depth_bias:1;

824

unsigned int line_stipple:1;

825

unsigned int depth_offset:1;

826

unsigned int polygon_stipple:1;

827

unsigned int line_aa_region_width:2;

828

unsigned int line_endcap_aa_region_width:2;

829

unsigned int early_depth_test:1;

830

unsigned int thread_dispatch_enable:1;

831

unsigned int program_uses_depth:1;

832

unsigned int program_computes_depth:1;

833

unsigned int program_uses_killpixel:1;

834

unsigned int legacy_line_rast: 1;

835

unsigned int transposed_urb_read:1;

836

unsigned int max_threads:7;

837

} wm5;

838

839

float global_depth_offset_constant;

840

float global_depth_offset_scale;

841

842

struct {

843

unsigned int pad0:1;

844

unsigned int grf_reg_count_1:3;

845

unsigned int pad1:2;

846

unsigned int kernel_start_pointer_1:26;

847

} wm8;

848

849

struct {

850

unsigned int pad0:1;

851

unsigned int grf_reg_count_2:3;

852

unsigned int pad1:2;

853

unsigned int kernel_start_pointer_2:26;

854

} wm9;

855

856

struct {

857

unsigned int pad0:1;

858

unsigned int grf_reg_count_3:3;

859

unsigned int pad1:2;

860

unsigned int kernel_start_pointer_3:26;

861

} wm10;

862

};

863

864

struct brw_wm_unit_state_padded {

865

struct brw_wm_unit_state state;

866

char pad[64 - sizeof(struct brw_wm_unit_state)];

867

};

868

869

/* The hardware supports two different modes for border color. The

870

* default (OpenGL) mode uses floating-point color channels, while the

871

* legacy mode uses 4 bytes.

872

873

* More significantly, the legacy mode respects the components of the

874

* border color for channels not present in the source, (whereas the

875

* default mode will ignore the border color's alpha channel and use

876

* alpha==1 for an RGB source, for example).

877

878

* The legacy mode matches the semantics specified by the Render

879

* extension.

880

881

struct brw_sampler_default_border_color {

882

float color[4];

883

};

884

885

struct brw_sampler_legacy_border_color {

886

uint8_t color[4];

887

};

888

889

struct brw_sampler_state

890

{

891

892

struct

893

{

894

unsigned int shadow_function:3;

895

unsigned int lod_bias:11;

896

unsigned int min_filter:3;

897

unsigned int mag_filter:3;

898

unsigned int mip_filter:2;

899

unsigned int base_level:5;

900

unsigned int pad:1;

901

unsigned int lod_preclamp:1;

902

unsigned int border_color_mode:1;

903

unsigned int pad0:1;

904

unsigned int disable:1;

905

} ss0;

906

907

struct

908

{

909

unsigned int r_wrap_mode:3;

910

unsigned int t_wrap_mode:3;

911

unsigned int s_wrap_mode:3;

912

unsigned int pad:3;

913

unsigned int max_lod:10;

914

unsigned int min_lod:10;

915

} ss1;

916

917

918

struct

919

{

920

unsigned int pad:5;

921

unsigned int border_color_pointer:27;

922

} ss2;

923

924

struct

925

{

926

unsigned int pad:19;

927

unsigned int max_aniso:3;

928

unsigned int chroma_key_mode:1;

929

unsigned int chroma_key_index:2;

930

unsigned int chroma_key_enable:1;

931

unsigned int monochrome_filter_width:3;

932

unsigned int monochrome_filter_height:3;

933

} ss3;

934

};

935

936

937

struct brw_clipper_viewport

938

{

939

float xmin;

940

float xmax;

941

float ymin;

942

float ymax;

943

};

944

945

struct brw_cc_viewport

946

{

947

float min_depth;

948

float max_depth;

949

};

950

951

struct brw_sf_viewport

952

{

953

struct {

954

float m00;

955

float m11;

956

float m22;

957

float m30;

958

float m31;

959

float m32;

960

} viewport;

961

962

struct {

963

short xmin;

964

short ymin;

965

short xmax;

966

short ymax;

967

} scissor;

968

};

969

970

/* Documented in the subsystem/shared-functions/sampler chapter...

971

972

struct brw_surface_state

973

{

974

struct {

975

unsigned int cube_pos_z:1;

976

unsigned int cube_neg_z:1;

977

unsigned int cube_pos_y:1;

978

unsigned int cube_neg_y:1;

979

unsigned int cube_pos_x:1;

980

unsigned int cube_neg_x:1;

981

unsigned int pad:3;

982

unsigned int render_cache_read_mode:1;

983

unsigned int mipmap_layout_mode:1;

984

unsigned int vert_line_stride_ofs:1;

985

unsigned int vert_line_stride:1;

986

unsigned int color_blend:1;

987

unsigned int writedisable_blue:1;

988

unsigned int writedisable_green:1;

989

unsigned int writedisable_red:1;

990

unsigned int writedisable_alpha:1;

991

unsigned int surface_format:9;

992

unsigned int data_return_format:1;

993

unsigned int pad0:1;

994

unsigned int surface_type:3;

995

} ss0;

996

997

struct {

998

unsigned int base_addr;

999

} ss1;

1000

1001

struct {

1002

unsigned int render_target_rotation:2;

1003

unsigned int mip_count:4;

1004

unsigned int width:13;

1005

unsigned int height:13;

1006

} ss2;

1007

1008

struct {

1009

unsigned int tile_walk:1;

1010

unsigned int tiled_surface:1;

1011

unsigned int pad:1;

1012

unsigned int pitch:18;

1013

unsigned int depth:11;

1014

} ss3;

1015

1016

struct {

1017

unsigned int pad:19;

1018

unsigned int min_array_elt:9;

1019

unsigned int min_lod:4;

1020

} ss4;

1021

1022

struct {

1023

unsigned int pad:20;

1024

unsigned int y_offset:4;

1025

unsigned int pad2:1;

1026

unsigned int x_offset:7;

1027

} ss5;

1028

};

1029

1030

1031

1032

struct brw_vertex_buffer_state

1033

{

1034

struct {

1035

unsigned int pitch:11;

1036

unsigned int pad:15;

1037

unsigned int access_type:1;

1038

unsigned int vb_index:5;

1039

} vb0;

1040

1041

unsigned int start_addr;

1042

unsigned int max_index;

1043

#if 1

1044

unsigned int instance_data_step_rate; /* not included for sequential/random vertices? */

1045

#endif

1046

};

1047

1048

#define BRW_VBP_MAX 17

1049

1050

struct brw_vb_array_state {

1051

struct header header;

1052

struct brw_vertex_buffer_state vb[BRW_VBP_MAX];

1053

};

1054

1055

1056

struct brw_vertex_element_state

1057

{

1058

struct

1059

{

1060

unsigned int src_offset:11;

1061

unsigned int pad:5;

1062

unsigned int src_format:9;

1063

unsigned int pad0:1;

1064

unsigned int valid:1;

1065

unsigned int vertex_buffer_index:5;

1066

} ve0;

1067

1068

struct

1069

{

1070

unsigned int dst_offset:8;

1071

unsigned int pad:8;

1072

unsigned int vfcomponent3:4;

1073

unsigned int vfcomponent2:4;

1074

unsigned int vfcomponent1:4;

1075

unsigned int vfcomponent0:4;

1076

} ve1;

1077

};

1078

1079

#define BRW_VEP_MAX 18

1080

1081

struct brw_vertex_element_packet {

1082

struct header header;

1083

struct brw_vertex_element_state ve[BRW_VEP_MAX]; /* note: less than _TNL_ATTRIB_MAX */

1084

};

1085

1086

1087

struct brw_urb_immediate {

1088

unsigned int opcode:4;

1089

unsigned int offset:6;

1090

unsigned int swizzle_control:2;

1091

unsigned int pad:1;

1092

unsigned int allocate:1;

1093

unsigned int used:1;

1094

unsigned int complete:1;

1095

unsigned int response_length:4;

1096

unsigned int msg_length:4;

1097

unsigned int msg_target:4;

1098

unsigned int pad1:3;

1099

unsigned int end_of_thread:1;

1100

};

1101

1102

/* Instruction format for the execution units:

1103

1104

1105

struct brw_instruction

1106

{

1107

struct

1108

{

1109

unsigned int opcode:7;

1110

unsigned int pad:1;

1111

unsigned int access_mode:1;

1112

unsigned int mask_control:1;

1113

unsigned int dependency_control:2;

1114

unsigned int compression_control:2;

1115

unsigned int thread_control:2;

1116

unsigned int predicate_control:4;

1117

unsigned int predicate_inverse:1;

1118

unsigned int execution_size:3;

1119

unsigned int destreg__conditonalmod:4; /* destreg - send, conditionalmod - others */

1120

unsigned int pad0:2;

1121

unsigned int debug_control:1;

1122

unsigned int saturate:1;

1123

} header;

1124

1125

union {

1126

struct

1127

{

1128

unsigned int dest_reg_file:2;

1129

unsigned int dest_reg_type:3;

1130

unsigned int src0_reg_file:2;

1131

unsigned int src0_reg_type:3;

1132

unsigned int src1_reg_file:2;

1133

unsigned int src1_reg_type:3;

1134

unsigned int pad:1;

1135

unsigned int dest_subreg_nr:5;

1136

unsigned int dest_reg_nr:8;

1137

unsigned int dest_horiz_stride:2;

1138

unsigned int dest_address_mode:1;

1139

} da1;

1140

1141

struct

1142

{

1143

unsigned int dest_reg_file:2;

1144

unsigned int dest_reg_type:3;

1145

unsigned int src0_reg_file:2;

1146

unsigned int src0_reg_type:3;

1147

unsigned int pad:6;

1148

int dest_indirect_offset:10; /* offset against the deref'd address reg */

1149

unsigned int dest_subreg_nr:3; /* subnr for the address reg a0.x */

1150

unsigned int dest_horiz_stride:2;

1151

unsigned int dest_address_mode:1;

1152

} ia1;

1153

1154

struct

1155

{

1156

unsigned int dest_reg_file:2;

1157

unsigned int dest_reg_type:3;

1158

unsigned int src0_reg_file:2;

1159

unsigned int src0_reg_type:3;

1160

unsigned int src1_reg_file:2;

1161

unsigned int src1_reg_type:3;

1162

unsigned int pad0:1;

1163

unsigned int dest_writemask:4;

1164

unsigned int dest_subreg_nr:1;

1165

unsigned int dest_reg_nr:8;

1166

unsigned int pad1:2;

1167

unsigned int dest_address_mode:1;

1168

} da16;

1169

1170

struct

1171

{

1172

unsigned int dest_reg_file:2;

1173

unsigned int dest_reg_type:3;

1174

unsigned int src0_reg_file:2;

1175

unsigned int src0_reg_type:3;

1176

unsigned int pad0:6;

1177

unsigned int dest_writemask:4;

1178

int dest_indirect_offset:6;

1179

unsigned int dest_subreg_nr:3;

1180

unsigned int pad1:2;

1181

unsigned int dest_address_mode:1;

1182

} ia16;

1183

} bits1;

1184

1185

1186

union {

1187

struct

1188

{

1189

unsigned int src0_subreg_nr:5;

1190

unsigned int src0_reg_nr:8;

1191

unsigned int src0_abs:1;

1192

unsigned int src0_negate:1;

1193

unsigned int src0_address_mode:1;

1194

unsigned int src0_horiz_stride:2;

1195

unsigned int src0_width:3;

1196

unsigned int src0_vert_stride:4;

1197

unsigned int flag_reg_nr:1;

1198

unsigned int pad:6;

1199

} da1;

1200

1201

struct

1202

{

1203

int src0_indirect_offset:10;

1204

unsigned int src0_subreg_nr:3;

1205

unsigned int src0_abs:1;

1206

unsigned int src0_negate:1;

1207

unsigned int src0_address_mode:1;

1208

unsigned int src0_horiz_stride:2;

1209

unsigned int src0_width:3;

1210

unsigned int src0_vert_stride:4;

1211

unsigned int flag_reg_nr:1;

1212

unsigned int pad:6;

1213

} ia1;

1214

1215

struct

1216

{

1217

unsigned int src0_swz_x:2;

1218

unsigned int src0_swz_y:2;

1219

unsigned int src0_subreg_nr:1;

1220

unsigned int src0_reg_nr:8;

1221

unsigned int src0_abs:1;

1222

unsigned int src0_negate:1;

1223

unsigned int src0_address_mode:1;

1224

unsigned int src0_swz_z:2;

1225

unsigned int src0_swz_w:2;

1226

unsigned int pad0:1;

1227

unsigned int src0_vert_stride:4;

1228

unsigned int flag_reg_nr:1;

1229

unsigned int pad1:6;

1230

} da16;

1231

1232

struct

1233

{

1234

unsigned int src0_swz_x:2;

1235

unsigned int src0_swz_y:2;

1236

int src0_indirect_offset:6;

1237

unsigned int src0_subreg_nr:3;

1238

unsigned int src0_abs:1;

1239

unsigned int src0_negate:1;

1240

unsigned int src0_address_mode:1;

1241

unsigned int src0_swz_z:2;

1242

unsigned int src0_swz_w:2;

1243

unsigned int pad0:1;

1244

unsigned int src0_vert_stride:4;

1245

unsigned int flag_reg_nr:1;

1246

unsigned int pad1:6;

1247

} ia16;

1248

1249

} bits2;

1250

1251

union

1252

{

1253

struct

1254

{

1255

unsigned int src1_subreg_nr:5;

1256

unsigned int src1_reg_nr:8;

1257

unsigned int src1_abs:1;

1258

unsigned int src1_negate:1;

1259

unsigned int pad:1;

1260

unsigned int src1_horiz_stride:2;

1261

unsigned int src1_width:3;

1262

unsigned int src1_vert_stride:4;

1263

unsigned int pad0:7;

1264

} da1;

1265

1266

struct

1267

{

1268

unsigned int src1_swz_x:2;

1269

unsigned int src1_swz_y:2;

1270

unsigned int src1_subreg_nr:1;

1271

unsigned int src1_reg_nr:8;

1272

unsigned int src1_abs:1;

1273

unsigned int src1_negate:1;

1274

unsigned int pad0:1;

1275

unsigned int src1_swz_z:2;

1276

unsigned int src1_swz_w:2;

1277

unsigned int pad1:1;

1278

unsigned int src1_vert_stride:4;

1279

unsigned int pad2:7;

1280

} da16;

1281

1282

struct

1283

{

1284

int src1_indirect_offset:10;

1285

unsigned int src1_subreg_nr:3;

1286

unsigned int src1_abs:1;

1287

unsigned int src1_negate:1;

1288

unsigned int pad0:1;

1289

unsigned int src1_horiz_stride:2;

1290

unsigned int src1_width:3;

1291

unsigned int src1_vert_stride:4;

1292

unsigned int flag_reg_nr:1;

1293

unsigned int pad1:6;

1294

} ia1;

1295

1296

struct

1297

{

1298

unsigned int src1_swz_x:2;

1299

unsigned int src1_swz_y:2;

1300

int src1_indirect_offset:6;

1301

unsigned int src1_subreg_nr:3;

1302

unsigned int src1_abs:1;

1303

unsigned int src1_negate:1;

1304

unsigned int pad0:1;

1305

unsigned int src1_swz_z:2;

1306

unsigned int src1_swz_w:2;

1307

unsigned int pad1:1;

1308

unsigned int src1_vert_stride:4;

1309

unsigned int flag_reg_nr:1;

1310

unsigned int pad2:6;

1311

} ia16;

1312

1313

1314

struct

1315

{

1316

int jump_count:16; /* note: signed */

1317

unsigned int pop_count:4;

1318

unsigned int pad0:12;

1319

} if_else;

1320

1321

struct {

1322

unsigned int function:4;

1323

unsigned int int_type:1;

1324

unsigned int precision:1;

1325

unsigned int saturate:1;

1326

unsigned int data_type:1;

1327

unsigned int pad0:8;

1328

unsigned int response_length:4;

1329

unsigned int msg_length:4;

1330

unsigned int msg_target:4;

1331

unsigned int pad1:3;

1332

unsigned int end_of_thread:1;

1333

} math;

1334

1335

struct {

1336

unsigned int binding_table_index:8;

1337

unsigned int sampler:4;

1338

unsigned int return_format:2;

1339

unsigned int msg_type:2;

1340

unsigned int response_length:4;

1341

unsigned int msg_length:4;

1342

unsigned int msg_target:4;

1343

unsigned int pad1:3;

1344

unsigned int end_of_thread:1;

1345

} sampler;

1346

1347

struct brw_urb_immediate urb;

1348

1349

struct {

1350

unsigned int binding_table_index:8;

1351

unsigned int msg_control:4;

1352

unsigned int msg_type:2;

1353

unsigned int target_cache:2;

1354

unsigned int response_length:4;

1355

unsigned int msg_length:4;

1356

unsigned int msg_target:4;

1357

unsigned int pad1:3;

1358

unsigned int end_of_thread:1;

1359

} dp_read;

1360

1361

struct {

1362

unsigned int binding_table_index:8;

1363

unsigned int msg_control:3;

1364

unsigned int pixel_scoreboard_clear:1;

1365

unsigned int msg_type:3;

1366

unsigned int send_commit_msg:1;

1367

unsigned int response_length:4;

1368

unsigned int msg_length:4;

1369

unsigned int msg_target:4;

1370

unsigned int pad1:3;

1371

unsigned int end_of_thread:1;

1372

} dp_write;

1373

1374

struct {

1375

unsigned int pad:16;

1376

unsigned int response_length:4;

1377

unsigned int msg_length:4;

1378

unsigned int msg_target:4;

1379

unsigned int pad1:3;

1380

unsigned int end_of_thread:1;

1381

} generic;

1382

1383

unsigned int ud;

1384

} bits3;

1385

};

1386

1387

/* media pipeline */

1388

1389

struct brw_vfe_state {

1390

struct {

1391

unsigned int per_thread_scratch_space:4;

1392

unsigned int pad3:3;

1393

unsigned int extend_vfe_state_present:1;

1394

unsigned int pad2:2;

1395

unsigned int scratch_base:22;

1396

} vfe0;

1397

1398

struct {

1399

unsigned int debug_counter_control:2;

1400

unsigned int children_present:1;

1401

unsigned int vfe_mode:4;

1402

unsigned int pad2:2;

1403

unsigned int num_urb_entries:7;

1404

unsigned int urb_entry_alloc_size:9;

1405

unsigned int max_threads:7;

1406

} vfe1;

1407

1408

struct {

1409

unsigned int pad4:4;

1410

unsigned int interface_descriptor_base:28;

1411

} vfe2;

1412

};

1413

1414

struct brw_vld_state {

1415

struct {

1416

unsigned int pad6:6;

1417

unsigned int scan_order:1;

1418

unsigned int intra_vlc_format:1;

1419

unsigned int quantizer_scale_type:1;

1420

unsigned int concealment_motion_vector:1;

1421

unsigned int frame_predict_frame_dct:1;

1422

unsigned int top_field_first:1;

1423

unsigned int picture_structure:2;

1424

unsigned int intra_dc_precision:2;

1425

unsigned int f_code_0_0:4;

1426

unsigned int f_code_0_1:4;

1427

unsigned int f_code_1_0:4;

1428

unsigned int f_code_1_1:4;

1429

} vld0;

1430

1431

struct {

1432

unsigned int pad2:9;

1433

unsigned int picture_coding_type:2;

1434

unsigned int pad:21;

1435

} vld1;

1436

1437

struct {

1438

unsigned int index_0:4;

1439

unsigned int index_1:4;

1440

unsigned int index_2:4;

1441

unsigned int index_3:4;

1442

unsigned int index_4:4;

1443

unsigned int index_5:4;

1444

unsigned int index_6:4;

1445

unsigned int index_7:4;

1446

} desc_remap_table0;

1447

1448

struct {

1449

unsigned int index_8:4;

1450

unsigned int index_9:4;

1451

unsigned int index_10:4;

1452

unsigned int index_11:4;

1453

unsigned int index_12:4;

1454

unsigned int index_13:4;

1455

unsigned int index_14:4;

1456

unsigned int index_15:4;

1457

} desc_remap_table1;

1458

};

1459

1460

struct brw_interface_descriptor {

1461

struct {

1462

unsigned int grf_reg_blocks:4;

1463

unsigned int pad:2;

1464

unsigned int kernel_start_pointer:26;

1465

} desc0;

1466

1467

struct {

1468

unsigned int pad:7;

1469

unsigned int software_exception:1;

1470

unsigned int pad2:3;

1471

unsigned int maskstack_exception:1;

1472

unsigned int pad3:1;

1473

unsigned int illegal_opcode_exception:1;

1474

unsigned int pad4:2;

1475

unsigned int floating_point_mode:1;

1476

unsigned int thread_priority:1;

1477

unsigned int single_program_flow:1;

1478

unsigned int pad5:1;

1479

unsigned int const_urb_entry_read_offset:6;

1480

unsigned int const_urb_entry_read_len:6;

1481

} desc1;

1482

1483

struct {

1484

unsigned int pad:2;

1485

unsigned int sampler_count:3;

1486

unsigned int sampler_state_pointer:27;

1487

} desc2;

1488

1489

struct {

1490

unsigned int binding_table_entry_count:5;

1491

unsigned int binding_table_pointer:27;

1492

} desc3;

1493

};

1494

1495

struct gen6_blend_state

1496

{

1497

struct {

1498

unsigned int dest_blend_factor:5;

1499

unsigned int source_blend_factor:5;

1500

unsigned int pad3:1;

1501

unsigned int blend_func:3;

1502

unsigned int pad2:1;

1503

unsigned int ia_dest_blend_factor:5;

1504

unsigned int ia_source_blend_factor:5;

1505

unsigned int pad1:1;

1506

unsigned int ia_blend_func:3;

1507

unsigned int pad0:1;

1508

unsigned int ia_blend_enable:1;

1509

unsigned int blend_enable:1;

1510

} blend0;

1511

1512

struct {

1513

unsigned int post_blend_clamp_enable:1;

1514

unsigned int pre_blend_clamp_enable:1;

1515

unsigned int clamp_range:2;

1516

unsigned int pad0:4;

1517

unsigned int x_dither_offset:2;

1518

unsigned int y_dither_offset:2;

1519

unsigned int dither_enable:1;

1520

unsigned int alpha_test_func:3;

1521

unsigned int alpha_test_enable:1;

1522

unsigned int pad1:1;

1523

unsigned int logic_op_func:4;

1524

unsigned int logic_op_enable:1;

1525

unsigned int pad2:1;

1526

unsigned int write_disable_b:1;

1527

unsigned int write_disable_g:1;

1528

unsigned int write_disable_r:1;

1529

unsigned int write_disable_a:1;

1530

unsigned int pad3:1;

1531

unsigned int alpha_to_coverage_dither:1;

1532

unsigned int alpha_to_one:1;

1533

unsigned int alpha_to_coverage:1;

1534

} blend1;

1535

};

1536

1537

struct gen6_color_calc_state

1538

{

1539

struct {

1540

unsigned int alpha_test_format:1;

1541

unsigned int pad0:14;

1542

unsigned int round_disable:1;

1543

unsigned int bf_stencil_ref:8;

1544

unsigned int stencil_ref:8;

1545

} cc0;

1546

1547

union {

1548

float alpha_ref_f;

1549

struct {

1550

unsigned int ui:8;

1551

unsigned int pad0:24;

1552

} alpha_ref_fi;

1553

} cc1;

1554

1555

float constant_r;

1556

float constant_g;

1557

float constant_b;

1558

float constant_a;

1559

};

1560

1561

struct gen6_depth_stencil_state

1562

{

1563

struct {

1564

unsigned int pad0:3;

1565

unsigned int bf_stencil_pass_depth_pass_op:3;

1566

unsigned int bf_stencil_pass_depth_fail_op:3;

1567

unsigned int bf_stencil_fail_op:3;

1568

unsigned int bf_stencil_func:3;

1569

unsigned int bf_stencil_enable:1;

1570

unsigned int pad1:2;

1571

unsigned int stencil_write_enable:1;

1572

unsigned int stencil_pass_depth_pass_op:3;

1573

unsigned int stencil_pass_depth_fail_op:3;

1574

unsigned int stencil_fail_op:3;

1575

unsigned int stencil_func:3;

1576

unsigned int stencil_enable:1;

1577

} ds0;

1578

1579

struct {

1580

unsigned int bf_stencil_write_mask:8;

1581

unsigned int bf_stencil_test_mask:8;

1582

unsigned int stencil_write_mask:8;

1583

unsigned int stencil_test_mask:8;

1584

} ds1;

1585

1586

struct {

1587

unsigned int pad0:26;

1588

unsigned int depth_write_enable:1;

1589

unsigned int depth_test_func:3;

1590

unsigned int pad1:1;

1591

unsigned int depth_test_enable:1;

1592

} ds2;

1593

};

1594

1595

struct gen7_surface_state

1596

{

1597

struct {

1598

unsigned int cube_pos_z:1;

1599

unsigned int cube_neg_z:1;

1600

unsigned int cube_pos_y:1;

1601

unsigned int cube_neg_y:1;

1602

unsigned int cube_pos_x:1;

1603

unsigned int cube_neg_x:1;

1604

unsigned int pad2:2;

1605

unsigned int render_cache_read_write:1;

1606

unsigned int pad1:1;

1607

unsigned int surface_array_spacing:1;

1608

unsigned int vert_line_stride_ofs:1;

1609

unsigned int vert_line_stride:1;

1610

unsigned int tile_walk:1;

1611

unsigned int tiled_surface:1;

1612

unsigned int horizontal_alignment:1;

1613

unsigned int vertical_alignment:2;

1614

unsigned int surface_format:9; /**< BRW_SURFACEFORMAT_x */

1615

unsigned int pad0:1;

1616

unsigned int is_array:1;

1617

unsigned int surface_type:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */

1618

} ss0;

1619

1620

struct {

1621

unsigned int base_addr;

1622

} ss1;

1623

1624

struct {

1625

unsigned int width:14;

1626

unsigned int pad1:2;

1627

unsigned int height:14;

1628

unsigned int pad0:2;

1629

} ss2;

1630

1631

struct {

1632

unsigned int pitch:18;

1633

unsigned int pad:3;

1634

unsigned int depth:11;

1635

} ss3;

1636

1637

struct {

1638

unsigned int multisample_position_palette_index:3;

1639

unsigned int num_multisamples:3;

1640

unsigned int multisampled_surface_storage_format:1;

1641

unsigned int render_target_view_extent:11;

1642

unsigned int min_array_elt:11;

1643

unsigned int rotation:2;

1644

unsigned int pad0:1;

1645

} ss4;

1646

1647

struct {

1648

unsigned int mip_count:4;

1649

unsigned int min_lod:4;

1650

unsigned int pad1:12;

1651

unsigned int y_offset:4;

1652

unsigned int pad0:1;

1653

unsigned int x_offset:7;

1654

} ss5;

1655

1656

struct {

1657

unsigned int pad; /* Multisample Control Surface stuff */

1658

} ss6;

1659

1660

struct {

1661

unsigned int resource_min_lod:12;

1662

unsigned int pad0:4;

1663

unsigned int shader_chanel_select_a:3;

1664

unsigned int shader_chanel_select_b:3;

1665

unsigned int shader_chanel_select_g:3;

1666

unsigned int shader_chanel_select_r:3;

1667

unsigned int alpha_clear_color:1;

1668

unsigned int blue_clear_color:1;

1669

unsigned int green_clear_color:1;

1670

unsigned int red_clear_color:1;

1671

} ss7;

1672

};

1673

1674

struct gen7_sampler_state

1675

{

1676

struct

1677

{

1678

unsigned int aniso_algorithm:1;

1679

unsigned int lod_bias:13;

1680

unsigned int min_filter:3;

1681

unsigned int mag_filter:3;

1682

unsigned int mip_filter:2;

1683

unsigned int base_level:5;

1684

unsigned int pad1:1;

1685

unsigned int lod_preclamp:1;

1686

unsigned int default_color_mode:1;

1687

unsigned int pad0:1;

1688

unsigned int disable:1;

1689

} ss0;

1690

1691

struct

1692

{

1693

unsigned int cube_control_mode:1;

1694

unsigned int shadow_function:3;

1695

unsigned int pad:4;

1696

unsigned int max_lod:12;

1697

unsigned int min_lod:12;

1698

} ss1;

1699

1700

struct

1701

{

1702

unsigned int pad:5;

1703

unsigned int default_color_pointer:27;

1704

} ss2;

1705

1706

struct

1707

{

1708

unsigned int r_wrap_mode:3;

1709

unsigned int t_wrap_mode:3;

1710

unsigned int s_wrap_mode:3;

1711

unsigned int pad:1;

1712

unsigned int non_normalized_coord:1;

1713

unsigned int trilinear_quality:2;

1714

unsigned int address_round:6;

1715

unsigned int max_aniso:3;

1716

unsigned int chroma_key_mode:1;

1717

unsigned int chroma_key_index:2;

1718

unsigned int chroma_key_enable:1;

1719

unsigned int pad0:6;

1720

} ss3;

1721

};

1722

1723

#endif

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