122
int pit_get_out(PITState *pit, int channel, int64_t current_time)
125
int pit_get_out(ISADevice *dev, int channel, int64_t current_time)
127
PITState *pit = DO_UPCAST(PITState, dev, dev);
124
128
PITChannelState *s = &pit->channels[channel];
125
129
return pit_get_out1(s, current_time);
181
185
/* val must be 0 or 1 */
182
void pit_set_gate(PITState *pit, int channel, int val)
186
void pit_set_gate(ISADevice *dev, int channel, int val)
188
PITState *pit = DO_UPCAST(PITState, dev, dev);
184
189
PITChannelState *s = &pit->channels[channel];
186
191
switch(s->mode) {
202
207
if (s->gate < val) {
203
208
/* restart counting on rising edge */
204
s->count_load_time = qemu_get_clock(vm_clock);
209
s->count_load_time = qemu_get_clock_ns(vm_clock);
205
210
pit_irq_timer_update(s, s->count_load_time);
207
212
/* XXX: disable/enable counting */
213
int pit_get_gate(PITState *pit, int channel)
218
int pit_get_gate(ISADevice *dev, int channel)
220
PITState *pit = DO_UPCAST(PITState, dev, dev);
215
221
PITChannelState *s = &pit->channels[channel];
219
int pit_get_initial_count(PITState *pit, int channel)
225
int pit_get_initial_count(ISADevice *dev, int channel)
227
PITState *pit = DO_UPCAST(PITState, dev, dev);
221
228
PITChannelState *s = &pit->channels[channel];
225
int pit_get_mode(PITState *pit, int channel)
232
int pit_get_mode(ISADevice *dev, int channel)
234
PITState *pit = DO_UPCAST(PITState, dev, dev);
227
235
PITChannelState *s = &pit->channels[channel];
498
506
pit_load_count(s, 0);
501
PITState *pit_init(int base, qemu_irq irq)
509
static int pit_initfn(ISADevice *dev)
503
PITState *pit = &pit_state;
511
PITState *pit = DO_UPCAST(PITState, dev, dev);
504
512
PITChannelState *s;
506
514
s = &pit->channels[0];
507
515
/* the timer 0 is connected to an IRQ */
508
s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
511
vmstate_register(NULL, base, &vmstate_pit, pit);
512
qemu_register_reset(pit_reset, pit);
513
register_ioport_write(base, 4, 1, pit_ioport_write, pit);
514
register_ioport_read(base, 3, 1, pit_ioport_read, pit);
516
s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s);
517
s->irq = isa_get_irq(pit->irq);
519
register_ioport_write(pit->iobase, 4, 1, pit_ioport_write, pit);
520
register_ioport_read(pit->iobase, 3, 1, pit_ioport_read, pit);
521
isa_init_ioport(dev, pit->iobase);
523
qdev_set_legacy_instance_id(&dev->qdev, pit->iobase, 2);
528
static ISADeviceInfo pit_info = {
529
.qdev.name = "isa-pit",
530
.qdev.size = sizeof(PITState),
531
.qdev.vmsd = &vmstate_pit,
532
.qdev.reset = pit_reset,
535
.qdev.props = (Property[]) {
536
DEFINE_PROP_UINT32("irq", PITState, irq, -1),
537
DEFINE_PROP_HEX32("iobase", PITState, iobase, -1),
538
DEFINE_PROP_END_OF_LIST(),
542
static void pit_register(void)
544
isa_qdev_register(&pit_info);
546
device_init(pit_register)