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  • Committer: Package Import Robot
  • Author(s): Vagrant Cascadian
  • Date: 2011-10-03 12:29:18 UTC
  • mfrom: (1.2.13) (10.2.6 experimental)
  • Revision ID: package-import@ubuntu.com-20111003122918-zc4kv6epchrbgdta
Tags: 0.15.0+dfsg-1
* New upstream version.
* Install new qemu-system, qemu-user and qemu-user-static variants: 
  lm32, microblazeel, s390x, unicore32
* Patch from upstream to set QEMU_INCLUDES before QEMU_CFLAGS.
* Update debian/watch to check http://qemu.org/download.

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hw/mst_fpga.c
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 * This code is licensed under the GNU GPL v2.
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 */
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#include "hw.h"
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#include "pxa.h"
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#include "mainstone.h"
 
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#include "sysbus.h"
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/* Mainstone FPGA for extern irqs */
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#define FPGA_GPIO_PIN   0
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#define MST_PCMCIA0             0xe0
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#define MST_PCMCIA1             0xe4
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#define MST_PCMCIAx_READY       (1 << 10)
 
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#define MST_PCMCIAx_nCD         (1 << 5)
 
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#define MST_PCMCIA_CD0_IRQ      9
 
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#define MST_PCMCIA_CD1_IRQ      13
 
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typedef struct mst_irq_state{
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        qemu_irq *parent;
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        qemu_irq *pins;
 
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        SysBusDevice busdev;
 
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        qemu_irq parent;
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        uint32_t prev_level;
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        uint32_t leddat1;
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}mst_irq_state;
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static void
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mst_fpga_update_gpio(mst_irq_state *s)
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{
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        uint32_t level, diff;
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        int bit;
54
 
        level = s->prev_level ^ s->intsetclr;
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56
 
        for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
57
 
                bit = ffs(diff) - 1;
58
 
                qemu_set_irq(s->pins[bit], (level >> bit) & 1 );
59
 
        }
60
 
        s->prev_level = level;
61
 
}
62
 
 
63
 
static void
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mst_fpga_set_irq(void *opaque, int irq, int level)
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{
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        mst_irq_state *s = (mst_irq_state *)opaque;
 
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        uint32_t oldint = s->intsetclr & s->intmskena;
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        if (level)
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                s->prev_level |= 1u << irq;
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        else
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                s->prev_level &= ~(1u << irq);
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        if(s->intmskena & (1u << irq)) {
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                s->intsetclr = 1u << irq;
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                qemu_set_irq(s->parent[0], level);
 
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        switch(irq) {
 
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        case MST_PCMCIA_CD0_IRQ:
 
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                if (level)
 
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                        s->pcmcia0 &= ~MST_PCMCIAx_nCD;
 
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                else
 
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                        s->pcmcia0 |=  MST_PCMCIAx_nCD;
 
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                break;
 
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        case MST_PCMCIA_CD1_IRQ:
 
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                if (level)
 
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                        s->pcmcia1 &= ~MST_PCMCIAx_nCD;
 
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                else
 
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                        s->pcmcia1 |=  MST_PCMCIAx_nCD;
 
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                break;
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        }
 
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        if ((s->intmskena & (1u << irq)) && level)
 
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                s->intsetclr |= 1u << irq;
 
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        if (oldint != (s->intsetclr & s->intmskena))
 
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                qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
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}
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                return s->pcmcia1;
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        default:
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                printf("Mainstone - mst_fpga_readb: Bad register offset "
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                        REG_FMT " \n", addr);
 
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                        "0x" TARGET_FMT_plx " \n", addr);
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        }
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        return 0;
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}
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        case MST_MSCRD:
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                s->mscrd =  value;
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                break;
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        case MST_INTMSKENA:     /* Mask interupt */
 
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        case MST_INTMSKENA:     /* Mask interrupt */
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                s->intmskena = (value & 0xFEEFF);
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                mst_fpga_update_gpio(s);
 
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                qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
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                break;
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        case MST_INTSETCLR:     /* clear or set interrupt */
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                s->intsetclr = (value & 0xFEEFF);
 
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                qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
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                break;
 
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                /* For PCMCIAx allow the to change only power and reset */
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        case MST_PCMCIA0:
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                s->pcmcia0 = value;
 
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                s->pcmcia0 = (value & 0x1f) | (s->pcmcia0 & ~0x1f);
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                break;
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        case MST_PCMCIA1:
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                s->pcmcia1 = value;
 
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                s->pcmcia1 = (value & 0x1f) | (s->pcmcia1 & ~0x1f);
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                break;
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        default:
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                printf("Mainstone - mst_fpga_writeb: Bad register offset "
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                        REG_FMT " \n", addr);
 
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                        "0x" TARGET_FMT_plx " \n", addr);
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        }
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}
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        mst_fpga_writeb,
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};
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178
 
static void
179
 
mst_fpga_save(QEMUFile *f, void *opaque)
180
 
{
181
 
        struct mst_irq_state *s = (mst_irq_state *) opaque;
182
 
 
183
 
        qemu_put_be32s(f, &s->prev_level);
184
 
        qemu_put_be32s(f, &s->leddat1);
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        qemu_put_be32s(f, &s->leddat2);
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        qemu_put_be32s(f, &s->ledctrl);
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        qemu_put_be32s(f, &s->gpswr);
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        qemu_put_be32s(f, &s->mscwr1);
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        qemu_put_be32s(f, &s->mscwr2);
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        qemu_put_be32s(f, &s->mscwr3);
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        qemu_put_be32s(f, &s->mscrd);
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        qemu_put_be32s(f, &s->intmskena);
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        qemu_put_be32s(f, &s->intsetclr);
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        qemu_put_be32s(f, &s->pcmcia0);
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        qemu_put_be32s(f, &s->pcmcia1);
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}
197
 
 
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static int
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mst_fpga_load(QEMUFile *f, void *opaque, int version_id)
 
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static int mst_fpga_post_load(void *opaque, int version_id)
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{
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        mst_irq_state *s = (mst_irq_state *) opaque;
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        qemu_get_be32s(f, &s->prev_level);
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        qemu_get_be32s(f, &s->leddat1);
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        qemu_get_be32s(f, &s->leddat2);
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        qemu_get_be32s(f, &s->ledctrl);
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        qemu_get_be32s(f, &s->gpswr);
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        qemu_get_be32s(f, &s->mscwr1);
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        qemu_get_be32s(f, &s->mscwr2);
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        qemu_get_be32s(f, &s->mscwr3);
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        qemu_get_be32s(f, &s->mscrd);
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        qemu_get_be32s(f, &s->intmskena);
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        qemu_get_be32s(f, &s->intsetclr);
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        qemu_get_be32s(f, &s->pcmcia0);
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        qemu_get_be32s(f, &s->pcmcia1);
 
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        qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
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        return 0;
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}
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197
 
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qemu_irq *mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq)
 
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static int mst_fpga_init(SysBusDevice *dev)
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{
221
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        mst_irq_state *s;
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        int iomemtype;
223
 
        qemu_irq *qi;
224
 
 
225
 
        s = (mst_irq_state  *)
226
 
                qemu_mallocz(sizeof(mst_irq_state));
227
 
 
228
 
        s->parent = &cpu->pic[irq];
 
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        s = FROM_SYSBUS(mst_irq_state, dev);
 
204
 
 
205
        s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
 
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        s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
 
207
 
 
208
        sysbus_init_irq(dev, &s->parent);
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209
 
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        /* alloc the external 16 irqs */
231
 
        qi  = qemu_allocate_irqs(mst_fpga_set_irq, s, MST_NUM_IRQS);
232
 
        s->pins = qi;
 
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        qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);
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212
 
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        iomemtype = cpu_register_io_memory(mst_fpga_readfn,
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                mst_fpga_writefn, s, DEVICE_NATIVE_ENDIAN);
236
 
        cpu_register_physical_memory(base, 0x00100000, iomemtype);
237
 
        register_savevm(NULL, "mainstone_fpga", 0, 0, mst_fpga_save,
238
 
                        mst_fpga_load, s);
239
 
        return qi;
240
 
}
 
215
        sysbus_init_mmio(dev, 0x00100000, iomemtype);
 
216
        return 0;
 
217
}
 
218
 
 
219
static VMStateDescription vmstate_mst_fpga_regs = {
 
220
        .name = "mainstone_fpga",
 
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        .version_id = 0,
 
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        .minimum_version_id = 0,
 
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        .minimum_version_id_old = 0,
 
224
        .post_load = mst_fpga_post_load,
 
225
        .fields = (VMStateField []) {
 
226
                VMSTATE_UINT32(prev_level, mst_irq_state),
 
227
                VMSTATE_UINT32(leddat1, mst_irq_state),
 
228
                VMSTATE_UINT32(leddat2, mst_irq_state),
 
229
                VMSTATE_UINT32(ledctrl, mst_irq_state),
 
230
                VMSTATE_UINT32(gpswr, mst_irq_state),
 
231
                VMSTATE_UINT32(mscwr1, mst_irq_state),
 
232
                VMSTATE_UINT32(mscwr2, mst_irq_state),
 
233
                VMSTATE_UINT32(mscwr3, mst_irq_state),
 
234
                VMSTATE_UINT32(mscrd, mst_irq_state),
 
235
                VMSTATE_UINT32(intmskena, mst_irq_state),
 
236
                VMSTATE_UINT32(intsetclr, mst_irq_state),
 
237
                VMSTATE_UINT32(pcmcia0, mst_irq_state),
 
238
                VMSTATE_UINT32(pcmcia1, mst_irq_state),
 
239
                VMSTATE_END_OF_LIST(),
 
240
        },
 
241
};
 
242
 
 
243
static SysBusDeviceInfo mst_fpga_info = {
 
244
        .init = mst_fpga_init,
 
245
        .qdev.name = "mainstone-fpga",
 
246
        .qdev.desc = "Mainstone II FPGA",
 
247
        .qdev.size = sizeof(mst_irq_state),
 
248
        .qdev.vmsd = &vmstate_mst_fpga_regs,
 
249
};
 
250
 
 
251
static void mst_fpga_register(void)
 
252
{
 
253
        sysbus_register_withprop(&mst_fpga_info);
 
254
}
 
255
device_init(mst_fpga_register);