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- Committer: Bazaar Package Importer
- Author(s): Matthias Klose
- Date: 2011-06-08 14:37:01 UTC
- Revision ID: james.westby@ubuntu.com-20110608143701-ct4xkye5yzeorvcd
Tags: 4.5.3-2
* Update to SVN 20110608 (r174800) from the gcc-4_5-branch.
- Fix PR target/48774, PR tree-optimization/48809, PR middle-end/48597,
PR c/48742, PR c/48685, PR middle-end/43085, PR bootstrap/43858,
PR target/48288, PR c++/48046, PR fortran/48894, PR target/48857,
PR target/48495, PR tree-optimization/48837, PR target/48900,
PR c++/40975, PR target/48252, PR target/48708, PR c++/48936,
PR c++/48873, PR target/49238, PR target/49186,
PR tree-optimization/49038, PR target/43700, PR target/43995,
PR rtl-optimization/41619, PR tree-optimization/47714, PR fortran/45786.
* pr45979.diff: Update to the version from the trunk.
* Update the Linaro support to the 4.5-2011.05-0 release.
* Check for large file support (backport from 4.6). LP: #784705.
* Add some conditionals to build the package on older releases.
* Fix c++ biarch header installation on i386.
* Add multiarch attributes for gnat and libgnat packages.
* Add multiarch attributes for libgcj* packages.
* Adjust build dependency on multiarch glibc.
* Enable multiarch.
- Fix PR target/48774, PR tree-optimization/48809, PR middle-end/48597,
PR c/48742, PR c/48685, PR middle-end/43085, PR bootstrap/43858,
PR target/48288, PR c++/48046, PR fortran/48894, PR target/48857,
PR target/48495, PR tree-optimization/48837, PR target/48900,
PR c++/40975, PR target/48252, PR target/48708, PR c++/48936,
PR c++/48873, PR target/49238, PR target/49186,
PR tree-optimization/49038, PR target/43700, PR target/43995,
PR rtl-optimization/41619, PR tree-optimization/47714, PR fortran/45786.
* pr45979.diff: Update to the version from the trunk.
* Update the Linaro support to the 4.5-2011.05-0 release.
* Check for large file support (backport from 4.6). LP: #784705.
* Add some conditionals to build the package on older releases.
* Fix c++ biarch header installation on i386.
* Add multiarch attributes for gnat and libgnat packages.
* Add multiarch attributes for libgcj* packages.
* Adjust build dependency on multiarch glibc.
* Enable multiarch.
- files added:
- debian/patches/gcc-lfs.diff
- files modified:
- debian/changelog
added
removed
debian/patches/gcc-linaro.diff
1
# DP: Changes for the Linaro 4.5-2011.04-0 release.
1
# DP: Changes for the Linaro 4.5-2011.05-0 release.
2
2
3
--- a/src/ChangeLog
4
+++ b/src/ChangeLog
5
@@ -1,3 +1,11 @@
6
+2011-01-25 Richard Guenther <rguenther@suse.de>
7
+
8
+ Backport from mainline
9
+ 2010-05-05 Sebastian Pop <sebastian.pop@amd.com>
10
+
11
+ * configure.ac: Allow all the versions greater than 0.10 of PPL.
12
+ * configure: Regenerated.
13
+
14
2010-12-16 Release Manager
15
16
* GCC 4.5.2 released.
17
3
--- a/src/ChangeLog.linaro
18
4
+++ b/src/ChangeLog.linaro
19
@@ -0,0 +1,4553 @@
5
@@ -0,0 +1,4771 @@
6
+2011-05-16 Andrew Stubbs <ams@codesourcery.com>
7
+
8
+ GCC Linaro 4.5-2011.05-0 released.
9
+
10
+ gcc/
11
+ * LINARO-VERSION: Update.
12
+
13
+2011-05-13 Revital Eres <revital.eres@linaro.org>
14
+
15
+ gcc/
16
+ * loop-doloop.c (doloop_condition_get): Support new form of
17
+ doloop pattern and use prev_nondebug_insn instead of PREV_INSN.
18
+ * config/arm/thumb2.md (*thumb2_addsi3_compare0): Remove "*".
19
+ (doloop_end): New.
20
+ * config/arm/arm.md (*addsi3_compare0): Remove "*".
21
+ * params.def (sms-min-sc): New param flag.
22
+ * doc/invoke.texi (sms-min-sc): Document it.
23
+ * ddg.c (create_ddg_dep_from_intra_loop_link): If a true dep edge
24
+ enters the branch create an anti edge in the opposite direction
25
+ to prevent the creation of reg-moves.
26
+ (get_node_of_insn_uid, check_closing_branch_deps): Delete
27
+ functions.
28
+ (create_ddg): Restore previous definition and implementation.
29
+ * ddg.h (create_ddg): Restore previous definition.
30
+ * modulo-sched.c: Adjust comment to reflect the fact we are
31
+ scheduling closing branch.
32
+ (PS_STAGE_COUNT): Rename to CALC_STAGE_COUNT and redefine.
33
+ (stage_count): New field in struct partial_schedule.
34
+ (calculate_stage_count): New function.
35
+ (normalize_sched_times): Rename to reset_sched_times and handle
36
+ incrementing the sched time of the nodes by a constant value
37
+ passed as parameter.
38
+ (duplicate_insns_of_cycles): Skip closing branch.
39
+ (sms_schedule_by_order): Schedule closing branch.
40
+ (ps_insn_find_column): Handle closing branch.
41
+ (sms_schedule): Call reset_sched_times and adjust the code to
42
+ support scheduling of the closing branch. Use sms-min-sc.
43
+ Support new form of doloop pattern.
44
+ (ps_insert_empty_row): Update calls to normalize_sched_times
45
+ and rotate_partial_schedule functions.
46
+ (mark_doloop_insns): Remove.
47
+
48
+2011-05-13 Michael Hope <michael.hope@linaro.org>
49
+
50
+ gcc/
51
+ Backport from mainline:
52
+
53
+ 2011-05-05 Michael Hope <michael.hope@linaro.org>
54
+
55
+ PR pch/45979
56
+ * config/host-linux.c (TRY_EMPTY_VM_SPACE): Define for
57
+ __ARM_EABI__ hosts.
58
+
59
+2011-05-11 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
60
+
61
+ Backport from mainline
62
+ Julian Brown <julian@codesourcery.com>
63
+ gcc/
64
+ * config/arm/neon.md (vec_set<mode>_internal): Fix misplaced
65
+ parenthesis in D-register case.
66
+ gcc/testsuite/
67
+ * gcc.target/arm/neon-vset_lanes8.c: New test.
68
+
69
+2011-05-05 Andrew Stubbs <ams@codesourcery.com>
70
+
71
+ Merge from FSF 4.5 branch r173417 (pre 4.5.4).
72
+
73
+2011-05-03 Tom de Vries <tom@codesourcery.com>
74
+
75
+ gcc/
76
+ * stmt.c (set_jump_prob): Make robust against *inv_scale == 0.
77
+
78
+2011-05-06 Richard Sandiford <richard.sandiford@linaro.org>
79
+
80
+ gcc/
81
+ From Sergey Grechanik <mouseentity@ispras.ru>, approved for mainline
82
+
83
+ * config/arm/arm.c (coproc_secondary_reload_class): Return NO_REGS
84
+ for constant vectors.
85
+
86
+
87
+2011-04-28 Andrew Stubbs <ams@codesourcery.com>
88
+
89
+ Merge from FSF 4.5 branch r173113 (4.5.3 release).
90
+
91
+2011-04-20 Richard Sandiford <richard.sandiford@linaro.org>
92
+
93
+ gcc/
94
+ PR target/46329
95
+ * config/arm/arm.c (arm_legitimate_constant_p_1): Return false
96
+ for all Neon struct constants.
97
+
98
+2011-04-20 Richard Sandiford <richard.sandiford@linaro.org>
99
+
100
+ gcc/
101
+ * doc/tm.texi (LEGITIMATE_CONSTANT_P): Replace with...
102
+ (TARGET_LEGITIMATE_CONSTANT_P): ...this.
103
+ * target.h (gcc_target): Add legitimate_constant_p.
104
+ * target-def.h (TARGET_LEGITIMATE_CONSTANT_P): Define.
105
+ (TARGET_INITIALIZER): Include it.
106
+ * calls.c (precompute_register_parameters): Replace uses of
107
+ LEGITIMATE_CONSTANT_P with targetm.legitimate_constant_p.
108
+ (emit_library_call_value_1): Likewise.
109
+ * expr.c (move_block_to_reg, can_store_by_pieces, emit_move_insn)
110
+ (compress_float_constant, emit_push_insn, expand_expr_real_1): Likewise.
111
+ * recog.c (general_operand, immediate_operand): Likewise.
112
+ * reload.c (find_reloads_toplev, find_reloads_address_part): Likewise.
113
+ * reload1.c (init_eliminable_invariants): Likewise.
114
+ * targhooks.h (default_legitimate_constant_p); Declare.
115
+ * targhooks.c (default_legitimate_constant_p): New function.
116
+
117
+ * config/arm/arm-protos.h (arm_cannot_force_const_mem): Delete.
118
+ * config/arm/arm.h (ARM_LEGITIMATE_CONSTANT_P): Likewise.
119
+ (THUMB_LEGITIMATE_CONSTANT_P, LEGITIMATE_CONSTANT_P): Likewise.
120
+ * config/arm/arm.c (TARGET_LEGITIMATE_CONSTANT_P): Define.
121
+ (arm_legitimate_constant_p_1, thumb_legitimate_constant_p)
122
+ (arm_legitimate_constant_p): New functions.
123
+ (arm_cannot_force_const_mem): Make static.
124
+
125
+2011-04-20 Richard Sandiford <richard.sandiford@linaro.org>
126
+
127
+ gcc/
128
+ * hooks.h (hook_bool_mode_uhwi_false): Declare.
129
+ * hooks.c (hook_bool_mode_uhwi_false): New function.
130
+ * doc/tm.texi (TARGET_ARRAY_MODE_SUPPORTED_P): Document.
131
+ * target.h (array_mode_supported_p): New hook.
132
+ * target-def.h (TARGET_ARRAY_MODE_SUPPORTED_P): Define if undefined.
133
+ (TARGET_INITIALIZER): Include it.
134
+ * stor-layout.c (mode_for_array): New function.
135
+ (layout_type): Use it.
136
+ * config/arm/arm.c (arm_array_mode_supported_p): New function.
137
+ (TARGET_ARRAY_MODE_SUPPORTED_P): Define.
138
+
139
+2011-04-20 Richard Sandiford <richard.sandiford@linaro.org>
140
+
141
+ gcc/testsuite/
142
+ Backport from mainline:
143
+
144
+ 2011-04-12 Richard Sandiford <richard.sandiford@linaro.org>
145
+
146
+ * gcc.target/arm/neon-vld3-1.c: New test.
147
+ * gcc.target/arm/neon-vst3-1.c: New test.
148
+ * gcc.target/arm/neon/v*.c: Regenerate.
149
+
150
+ gcc/
151
+ Backport from mainline:
152
+
153
+ 2011-04-12 Richard Sandiford <richard.sandiford@linaro.org>
154
+
155
+ * config/arm/arm.c (arm_print_operand): Use MEM_SIZE to get the
156
+ size of a '%A' memory reference.
157
+ (T_DREG, T_QREG): New neon_builtin_type_bits.
158
+ (arm_init_neon_builtins): Assert that the load and store operands
159
+ are neon_struct_operands.
160
+ (locate_neon_builtin_icode): Provide the neon_builtin_type_bits.
161
+ (NEON_ARG_MEMORY): New builtin_arg.
162
+ (neon_dereference_pointer): New function.
163
+ (arm_expand_neon_args): Add a neon_builtin_type_bits argument.
164
+ Handle NEON_ARG_MEMORY.
165
+ (arm_expand_neon_builtin): Update after above interface changes.
166
+ Use NEON_ARG_MEMORY for loads and stores.
167
+ * config/arm/predicates.md (neon_struct_operand): New predicate.
168
+ * config/arm/neon.md (V_two_elem): Tweak formatting.
169
+ (V_three_elem): Use BLKmode for accesses that have no associated mode.
170
+ (neon_vld1<mode>, neon_vld1_dup<mode>)
171
+ (neon_vst1_lane<mode>, neon_vst1<mode>, neon_vld2<mode>)
172
+ (neon_vld2_lane<mode>, neon_vld2_dup<mode>, neon_vst2<mode>)
173
+ (neon_vst2_lane<mode>, neon_vld3<mode>, neon_vld3_lane<mode>)
174
+ (neon_vld3_dup<mode>, neon_vst3<mode>, neon_vst3_lane<mode>)
175
+ (neon_vld4<mode>, neon_vld4_lane<mode>, neon_vld4_dup<mode>)
176
+ (neon_vst4<mode>): Replace pointer operand with a memory operand.
177
+ Use %A in the output template.
178
+ (neon_vld3qa<mode>, neon_vld3qb<mode>, neon_vst3qa<mode>)
179
+ (neon_vst3qb<mode>, neon_vld4qa<mode>, neon_vld4qb<mode>)
180
+ (neon_vst4qa<mode>, neon_vst4qb<mode>): Likewise, but halve
181
+ the width of the memory access. Remove post-increment.
182
+ * config/arm/neon-testgen.ml: Allow addresses to have an alignment.
183
+
184
+2011-04-20 Richard Sandiford <richard.sandiford@linaro.org>
185
+
186
+ gcc/
187
+ Backport from mainline:
188
+
189
+ 2011-03-30 Richard Sandiford <richard.sandiford@linaro.org>
190
+ Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
191
+
192
+ PR target/43590
193
+ * config/arm/neon.md (neon_vld3qa<mode>, neon_vld4qa<mode>): Remove
194
+ operand 1 and reshuffle the operands to match.
195
+ (neon_vld3<mode>, neon_vld4<mode>): Update accordingly.
196
+
197
+2011-04-26 Chung-Lin Tang <cltang@codesourcery.com>
198
+
199
+ Backport from mainline:
200
+
201
+ 2011-03-21 Chung-Lin Tang <cltang@codesourcery.com>
202
+
203
+ gcc/
204
+ * simplify-rtx.c (simplify_binary_operation_1): Handle
205
+ (xor (and A B) C) case when B and C are both constants.
206
+
207
+ gcc/testsuite/
208
+ * gcc.target/arm/xor-and.c: New.
209
+
210
+ 2011-03-18 Chung-Lin Tang <cltang@codesourcery.com>
211
+
212
+ gcc/
213
+ * combine.c (try_combine): Do simplification only call of
214
+ subst() on i2 even when i1 is present. Update comments.
215
+
216
+ gcc/testsuite/
217
+ * gcc.target/arm/unsigned-extend-1.c: New.
218
+
219
+2011-04-19 Andrew Stubbs <ams@codesourcery.com>
220
+
221
+ gcc/
222
+ * LINARO-VERSION: Bump version.
223
+
20
224
+2011-04-19 Andrew Stubbs <ams@codesourcery.com>
21
225
+
22
226
+ GCC Linaro 4.5-2011.04-0 released.
4603
4807
| -uxpv* | -beos* | -mpeix* | -udk* \
4604
4808
| -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \
4605
4809
| -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \
4606
--- a/src/configure
4607
+++ b/src/configure
4608
@@ -5780,8 +5780,6 @@
4609
4610
4611
# Check for PPL
4612
-ppl_major_version=0
4613
-ppl_minor_version=10
4614
ppllibs=" -lppl_c -lppl -lgmpxx"
4615
pplinc=
4616
4617
@@ -5838,8 +5836,8 @@
4618
if test "x$with_ppl" != "xno" -a "${ENABLE_PPL_CHECK}" = "yes"; then
4619
saved_CFLAGS="$CFLAGS"
4620
CFLAGS="$CFLAGS $pplinc $gmpinc"
4621
- { $as_echo "$as_me:${as_lineno-$LINENO}: checking for version $ppl_major_version.$ppl_minor_version of PPL" >&5
4622
-$as_echo_n "checking for version $ppl_major_version.$ppl_minor_version of PPL... " >&6; }
4623
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking for version 0.10 (or later revision) of PPL" >&5
4624
+$as_echo_n "checking for version 0.10 (or later revision) of PPL... " >&6; }
4625
cat confdefs.h - <<_ACEOF >conftest.$ac_ext
4626
/* end confdefs.h. */
4627
#include "ppl_c.h"
4628
@@ -5847,7 +5845,7 @@
4629
main ()
4630
{
4631
4632
- #if PPL_VERSION_MAJOR != $ppl_major_version || PPL_VERSION_MINOR != $ppl_minor_version
4633
+ #if PPL_VERSION_MAJOR != 0 || PPL_VERSION_MINOR < 10
4634
choke me
4635
#endif
4636
4637
--- a/src/configure.ac
4638
+++ b/src/configure.ac
4639
@@ -1510,8 +1510,6 @@
4640
AC_SUBST(poststage1_ldflags)
4641
4642
# Check for PPL
4643
-ppl_major_version=0
4644
-ppl_minor_version=10
4645
ppllibs=" -lppl_c -lppl -lgmpxx"
4646
pplinc=
4647
4648
@@ -1552,9 +1550,9 @@
4649
if test "x$with_ppl" != "xno" -a "${ENABLE_PPL_CHECK}" = "yes"; then
4650
saved_CFLAGS="$CFLAGS"
4651
CFLAGS="$CFLAGS $pplinc $gmpinc"
4652
- AC_MSG_CHECKING([for version $ppl_major_version.$ppl_minor_version of PPL])
4653
+ AC_MSG_CHECKING([for version 0.10 (or later revision) of PPL])
4654
AC_TRY_COMPILE([#include "ppl_c.h"],[
4655
- #if PPL_VERSION_MAJOR != $ppl_major_version || PPL_VERSION_MINOR != $ppl_minor_version
4656
+ #if PPL_VERSION_MAJOR != 0 || PPL_VERSION_MINOR < 10
4657
choke me
4658
#endif
4659
], [AC_MSG_RESULT([yes])], [AC_MSG_RESULT([no]); ppllibs= ; pplinc= ; with_ppl=no ])
4660
4810
--- a/src/gcc/ChangeLog
4661
4811
+++ b/src/gcc/ChangeLog
4662
@@ -1,3 +1,902 @@
4663
+2011-03-30 H.J. Lu <hongjiu.lu@intel.com>
4664
+
4665
+ Backport from mainline
4666
+ 2011-03-30 H.J. Lu <hongjiu.lu@intel.com>
4667
+
4668
+ PR target/48349
4669
+ * config/i386/i386.h (REG_CLASS_CONTENTS): Fix a typo in
4670
+ FLOAT_SSE_REGS.
4671
+
4672
+2011-03-29 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
4673
+
4674
+ * config/s390/s390.c (s390_preferred_reload_class): Return NO_REGS
4675
+ for invalid symbolic addresses.
4676
+ (s390_secondary_reload): Don't use s390_check_symref_alignment for
4677
+ larl operands.
4678
+
4679
+2011-03-28 Richard Sandiford <richard.sandiford@linaro.org>
4680
+
4681
+ PR target/47553
4682
+ * config/arm/predicates.md (neon_lane_number): Accept 0..15.
4683
+
4684
+2011-03-23 Jonathan Wakely <jwakely.gcc@gmail.com>
4685
+
4686
+ PR other/48254
4687
+ * doc/invoke.texi (-fipa-struct-reorg): Fix typo.
4688
+
4689
+2011-03-23 Jonathan Wakely <jwakely.gcc@gmail.com>
4690
+
4691
+ PR other/48179
4692
+ PR other/48234
4693
+ * doc/extend.texi (Alignment): Move section to match order in TOC.
4694
+ * doc/invoke.texi (i386 and x86-64 Windows Options): Likewise.
4695
+
4696
+2011-03-18 H.J. Lu <hongjiu.lu@intel.com>
4697
+
4698
+ Backport from mainline
4699
+ 2011-03-17 H.J. Lu <hongjiu.lu@intel.com>
4700
+
4701
+ PR target/48171
4702
+ * config/i386/i386.opt: Add Save to -mavx and -mfma.
4703
+
4704
+2011-03-16 Pat Haugen <pthaugen@us.ibm.com>
4705
+
4706
+ PR target/47862
4707
+ * caller-save.c (insert_restore, insert_save): Use non-validate
4708
+ form of adjust_address.
4709
+
4710
+2011-03-16 Nick Clifton <nickc@redhat.com>
4711
+
4712
+ * config/rx/rx.h (JUMP_ALIGN): Define.
4713
+ (JUMP_ALIGN_MAX_SKIP, LABEL_ALIGN_AFTER_BARRIER, LOOP_ALIGN,
4714
+ (LABEL_ALIGN, LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP,
4715
+ (LOOP_ALIGN_MAX_SKIP, LABEL_ALIGN_MAX_SKIP): Define.
4716
+ * config/rx/rx-protos.h (rx_align_for_label): Prototype.
4717
+ (rx_max_skip_for_label): Prototype.
4718
+ * config/rx/rx.md (abssi3): Use CC_ZSmode.
4719
+ (andis3): Fix timings.
4720
+ (peephole): Add peephole to combine zero- and sign- extending
4721
+ loads with arithmetic instructions.
4722
+ (bset): Fix timing.
4723
+ (bclr): Fix timing.
4724
+ * config/rx/rx.c (rx_is_legitimate_address): Add checks for QImode
4725
+ and HImode reg+int address.
4726
+ (rx_print_operand): Add support for %R. Fix generation of .B and
4727
+ .W addressing modes.
4728
+ (rx_align_for_label): New function.
4729
+ (rx_max_skip_for_label): New function.
4730
+
4731
+2011-03-10 Jason Merrill <jason@redhat.com>
4732
+
4733
+ PR c++/48029
4734
+ * stor-layout.c (layout_type): Don't set structural equality
4735
+ on arrays of incomplete type.
4736
+ * tree.c (type_hash_eq): Handle comparing them properly.
4737
+
4738
+2011-03-08 Richard Guenther <rguenther@suse.de>
4739
+
4740
+ Backport from mainline
4741
+ 2011-02-10 Richard Guenther <rguenther@suse.de>
4742
+
4743
+ * tree-ssa-structalias.c (bitpos_of_field): Use BITS_PER_UNIT, not 8.
4744
+
4745
+ 2010-10-18 Richard Guenther <rguenther@suse.de>
4746
+
4747
+ PR tree-optimization/45967
4748
+ * tree-ssa-structalias.c (type_could_have_pointers): Remove.
4749
+ (could_have_pointers): Likewise.
4750
+ (handle_rhs_call, handle_const_call, handle_pure_call,
4751
+ find_func_aliases, intra_create_variable_infos): Remove calls to them.
4752
+ (struct fieldoff): Add must_have_pointers field.
4753
+ (type_must_have_pointers): New function.
4754
+ (field_must_have_pointers): Likewise.
4755
+ (push_fields_onto_fieldstack): Remove must_have_pointers_p argument.
4756
+ Adjust field merging.
4757
+ (create_function_info_for): May-have-pointers of varinfo is
4758
+ almost always true.
4759
+ (create_variable_info_for_1): Likewise.
4760
+
4761
+ 2010-10-12 Richard Guenther <rguenther@suse.de>
4762
+
4763
+ * tree-ssa-structalias.c (get_constraint_for_1): Constants
4764
+ only point to nonlocal, not anything.
4765
+
4766
+2011-03-08 Richard Guenther <rguenther@suse.de>
4767
+
4768
+ PR tree-optimization/47278
4769
+ * tree.h (DECL_REPLACEABLE_P): Remove.
4770
+ (decl_replaceable_p): Declare.
4771
+ (decl_binds_to_current_def_p): Likewise.
4772
+ * varasm.c (decl_replaceable_p): New function.
4773
+ (decl_binds_to_current_def_p): Likewise.
4774
+ * cgraph.c (cgraph_function_body_availability): Use decl_replaceable_p.
4775
+ * tree-inline.c (inlinable_function_p): Likewise.
4776
+
4777
+2011-03-07 Pat Haugen <pthaugen@us.ibm.com>
4778
+
4779
+ Backport from mainline
4780
+ 2011-03-07 Pat Haugen <pthaugen@us.ibm.com>
4781
+
4782
+ PR target/47862
4783
+ * config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
4784
+
4785
+2011-03-07 Mingjie Xing <mingjie.xing@gmail.com>
4786
+
4787
+ * doc/cfg.texi: Remove "See" before @ref.
4788
+ * doc/invoke.texi: Likewise.
4789
+
4790
+2011-03-03 Uros Bizjak <ubizjak@gmail.com>
4791
+
4792
+ * config/i386/sse.md (*avx_pmaddubsw128): Fix mode of VEC_SELECT RTX.
4793
+ (ssse3_pmaddubsw128): Ditto.
4794
+ (ssse3_pmaddubsw): Ditto.
4795
+
4796
+2011-03-03 Denis Chertykov <chertykov@gmail.com>
4797
+
4798
+ Backport from mainline
4799
+ 2011-02-22 Georg-Johann Lay <avr@gjlay.de>
4800
+
4801
+ PR target/42240
4802
+ * config/avr/avr.c (avr_cannot_modify_jumps_p): New function.
4803
+ (TARGET_CANNOT_MODIFY_JUMPS_P): Define.
4804
+
4805
+2011-03-03 Richard Guenther <rguenther@suse.de>
4806
+
4807
+ * tree-vect-stmt.c (vectorizable_operation): Remove unused vars.
4808
+
4809
+2011-03-02 Richard Guenther <rguenther@suse.de>
4810
+
4811
+ Backport from mainline
4812
+ 2011-02-07 Richard Guenther <rguenther@suse.de>
4813
+
4814
+ PR tree-optimization/47615
4815
+ * tree-ssa-sccvn.h (run_scc_vn): Take a vn-walk mode argument.
4816
+ * tree-ssa-sccvn.c (default_vn_walk_kind): New global.
4817
+ (run_scc_vn): Initialize it.
4818
+ (visit_reference_op_load): Use it.
4819
+ * tree-ssa-pre.c (execute_pre): Use VN_WALK if in PRE.
4820
+
4821
+2011-03-01 Richard Guenther <rguenther@suse.de>
4822
+
4823
+ Backport from mainline
4824
+ 2011-02-08 Richard Guenther <rguenther@suse.de>
4825
+
4826
+ PR middle-end/47639
4827
+ * tree-vect-generic.c (expand_vector_operations_1): Update
4828
+ stmts here ...
4829
+ (expand_vector_operations): ... not here. Cleanup EH info
4830
+ and the CFG if required.
4831
+
4832
+2011-03-01 Richard Guenther <rguenther@suse.de>
4833
+
4834
+ Backport from mainline
4835
+ 2011-03-01 Richard Guenther <rguenther@suse.de>
4836
+
4837
+ PR tree-optimization/47890
4838
+ * tree-vect-loop.c (get_initial_def_for_induction): Set
4839
+ related stmt properly.
4840
+
4841
+ 2010-12-01 Richard Guenther <rguenther@suse.de>
4842
+
4843
+ PR tree-optimization/46723
4844
+ * tree-vect-loop.c (get_initial_def_for_induction): Strip
4845
+ conversions from the induction evolution and apply it to
4846
+ the result instead.
4847
+ * tree-vect-stmts.c (vect_get_vec_def_for_operand): Handle
4848
+ assigns for induction defs.
4849
+
4850
+2011-02-28 Georg-Johann Lay <avr@gjlay.de>
4851
+
4852
+ PR target/45261
4853
+ * config/avr/avr.c (avr_option_override): Use error on bad options.
4854
+ (avr_help): New function.
4855
+ (TARGET_HELP): Define.
4856
+
4857
+2011-02-26 Gerald Pfeifer <gerald@pfeifer.com>
4858
+
4859
+ * doc/invoke.texi (ARC Options): Use CPU instead of cpu.
4860
+ (ARM Options): Ditto.
4861
+ (i386 and x86-64 Options): Ditto.
4862
+ (RX Options): Ditto.
4863
+ (SPARC Options): Ditto.
4864
+
4865
+2011-02-26 Tijl Coosemans <tijl@coosemans.org>
4866
+
4867
+ * config.gcc (i386-*-freebsd*): Make i486 the default arch on
4868
+ FreeBSD 6 and later. Generally use cpu generic.
4869
+
4870
+2011-02-25 Gerald Pfeifer <gerald@pfeifer.com>
4871
+
4872
+ * doc/cpp.texi (Obsolete Features): Add background on the
4873
+ origin of assertions.
4874
+ Update copyright years.
4875
+
4876
+2011-02-25 Andriy Gapon <avg@freebsd.org>
4877
+
4878
+ PR target/45808
4879
+ * config/freebsd-spec.h (FBSD_LIB_SPEC): Handle the shared case.
4880
+ Update copyright years.
4881
+
4882
+2011-02-21 Uros Bizjak <ubizjak@gmail.com>
4883
+
4884
+ PR target/47840
4885
+ * config/i386/avxintrin.h (_mm256_insert_epi32): Use _mm_insert_epi32.
4886
+ (_mm256_insert_epi64): Use _mm_insert_epi64.
4887
+
4888
+2011-02-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
4889
+
4890
+ * config.gcc (hppa[12]*-*-hpux11*): Set extra_parts.
4891
+ * config/pa/stublib.c (pthread_default_stacksize_np, pthread_mutex_lock,
4892
+ pthread_mutex_unlock, pthread_once): Reinstate pthread stubs.
4893
+ * config/pa/t-pa-hpux11: Add rules to build pthread stubs.
4894
+ * config/pa/t-pa64: Likewise.
4895
+ * config/pa/pa-hpux11.h (LINK_GCC_C_SEQUENCE_SPEC): Define.
4896
+
4897
+2011-02-17 Uros Bizjak <ubizjak@gmail.com>
4898
+
4899
+ PR target/43653
4900
+ * config/i386/i386.c (ix86_secondary_reload): Handle SSE
4901
+ input reload with PLUS RTX.
4902
+
4903
+2011-02-15 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
4904
+
4905
+ PR pch/14940
4906
+ * config/alpha/host-osf.c: New file.
4907
+ * config/alpha/x-osf: New file.
4908
+ * config.host (alpha*-dec-osf*): Use it.
4909
+
4910
+2011-02-15 Tijl Coosemans <tijl@coosemans.org>
4911
+
4912
+ * config/i386/freebsd.h (SUBTARGET32_DEFAULT_CPU): Add.
4913
+ Update copyright years.
4914
+
4915
+2011-02-11 Bernd Schmidt <bernds@codesourcery.com>
4916
+
4917
+ PR rtl-optimization/47166
4918
+ * reload1.c (emit_reload_insns): Disable the spill_reg_store
4919
+ mechanism for PRE_MODIFY and POST_MODIFY.
4920
+ (inc_for_reload): For PRE_MODIFY, return the insn that sets the
4921
+ reloadreg.
4922
+
4923
+2011-02-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
4924
+
4925
+ Backport from mainline:
4926
+ 2011-02-07 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
4927
+
4928
+ * config.gcc (hppa[12]*-*-hpux11*): Don't set extra_parts.
4929
+ * config/pa/stublib.c (pthread_default_stacksize_np, pthread_mutex_lock,
4930
+ pthread_mutex_unlock): Remove.
4931
+ * config/pa/t-pa-hpux11: Remove rules to build pthread stubs.
4932
+ * config/pa/t-pa64: Likewise.
4933
+ * config/pa/pa64-hpux.h (LIB_SPEC): In static links, link against
4934
+ shared libc if not linking against libpthread.
4935
+ * config/pa/pa-hpux11.h (LIB_SPEC): Likewise.
4936
+
4937
+2011-02-03 Michael Meissner <meissner@linux.vnet.ibm.com>
4938
+
4939
+ Backport from mainline:
4940
+ 2011-02-02 Michael Meissner <meissner@linux.vnet.ibm.com>
4941
+
4942
+ PR target/47272
4943
+ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
4944
+ Document using vector double with the load/store builtins, and
4945
+ that the load/store builtins always use Altivec instructions.
4946
+
4947
+ * config/rs6000/vector.md (vector_altivec_load_<mode>): New insns
4948
+ to use altivec memory instructions, even on VSX.
4949
+ (vector_altivec_store_<mode>): Ditto.
4950
+
4951
+ * config/rs6000/rs6000-protos.h (rs6000_address_for_altivec): New
4952
+ function.
4953
+
4954
+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
4955
+ V2DF, V2DI support to load/store overloaded builtins.
4956
+
4957
+ * config/rs6000/rs6000-builtin.def (ALTIVEC_BUILTIN_*): Add
4958
+ altivec load/store builtins for V2DF/V2DI types.
4959
+
4960
+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't
4961
+ set avoid indexed addresses on power6 if -maltivec.
4962
+ (altivec_expand_ld_builtin): Add V2DF, V2DI support, use
4963
+ vector_altivec_load/vector_altivec_store builtins.
4964
+ (altivec_expand_st_builtin): Ditto.
4965
+ (altivec_expand_builtin): Add VSX memory builtins.
4966
+ (rs6000_init_builtins): Add V2DI types to internal types.
4967
+ (altivec_init_builtins): Add support for V2DF/V2DI altivec
4968
+ load/store builtins.
4969
+ (rs6000_address_for_altivec): Insure memory address is appropriate
4970
+ for Altivec.
4971
+
4972
+ * config/rs6000/vsx.md (vsx_load_<mode>): New expanders for
4973
+ vec_vsx_ld and vec_vsx_st.
4974
+ (vsx_store_<mode>): Ditto.
4975
+
4976
+ * config/rs6000/rs6000.h (RS6000_BTI_long_long): New type
4977
+ variables to hold long long types for VSX vector memory builtins.
4978
+ (RS6000_BTI_unsigned_long_long): Ditto.
4979
+ (long_long_integer_type_internal_node): Ditti.
4980
+ (long_long_unsigned_type_internal_node): Ditti.
4981
+
4982
+ * config/rs6000/altivec.md (UNSPEC_LVX): New UNSPEC.
4983
+ (altivec_lvx_<mode>): Make altivec_lvx use a mode iterator.
4984
+ (altivec_stvx_<mode>): Make altivec_stvx use a mode iterator.
4985
+
4986
+ * config/rs6000/altivec.h (vec_vsx_ld): Define VSX memory builtin
4987
+ short cuts.
4988
+ (vec_vsx_st): Ditto.
4989
+
4990
+ Backport from mainline:
4991
+ 2011-02-01 Michael Meissner <meissner@linux.vnet.ibm.com>
4992
+
4993
+ PR target/47580
4994
+ * config/rs6000/vsx.md (vsx_float<VSi><mode>2): Use
4995
+ gpc_reg_operand instead of vsx_register_operand to match rs6000.md
4996
+ generator functions.
4997
+ (vsx_floatuns<VSi><mode>2): Ditto.
4998
+ (vsx_fix_trunc<mode><VSi>2): Ditto.
4999
+ (vsx_fixuns_trunc<mode><VSi>2): Ditto.
5000
+
5001
+2011-02-02 Nick Clifton <nickc@redhat.com>
5002
+
5003
+ Import these patches from the mainline:
5004
+ 2011-01-31 Nick Clifton <nickc@redhat.com>
5005
+
5006
+ * config/rx/rx.c (rx_get_stack_layout): Only save call clobbered
5007
+ registers inside interrupt handlers if the handler is not a leaf
5008
+ function.
5009
+
5010
+ 2011-01-25 Nick Clifton <nickc@redhat.com>
5011
+
5012
+ * config/rx/rx.h (LIBCALL_VALUE): Do not promote complex types.
5013
+ * config/rx/rx.c (rx_function_value): Likewise.
5014
+ (rx_promote_function_mode): Likewise.
5015
+ (gen_safe_add): Place an outsized immediate value inside an UNSPEC
5016
+ in order to make it legitimate.
5017
+ * config/rx/rx.md (adddi3_internal): If the second operand is a
5018
+ MEM make sure that the first operand is the same as the result
5019
+ register.
5020
+ (addsi3_unspec): Delete.
5021
+ (subdi3): Do not accept immediate operands.
5022
+ (subdi3_internal): Likewise.
5023
+
5024
+ 2011-01-24 Richard Henderson <rth@redhat.com>
5025
+
5026
+ * config/rx/predicates.md (rx_fp_comparison_operator): Don't accept
5027
+ compound unordered comparisons.
5028
+ * config/rx/rx.c (rx_split_fp_compare): Remove.
5029
+ * config/rx/rx-protos.h: Update.
5030
+ * config/rx/rx.md (gcc_conds, rx_conds): Remove.
5031
+ (cbranchsf4): Don't call rx_split_fp_compare.
5032
+ (*cbranchsf4): Use rx_split_cbranch.
5033
+ (*cmpsf): Don't accept "i" constraint.
5034
+ (*conditional_branch): Only valid after reload.
5035
+ (cstoresf4): Merge expander with insn. Don't call
5036
+ rx_split_fp_compare.
5037
+
5038
+ 2011-01-22 Nick Clifton <nickc@redhat.com>
5039
+
5040
+ * config/rx/rx.md (cstoresf4): Pass comparison operator to
5041
+ rx_split_fp_compare.
5042
+
5043
+ 2011-01-22 Nick Clifton <nickc@redhat.com>
5044
+
5045
+ * config/rx/rx.md (UNSPEC_CONST): New.
5046
+ (deallocate_and_return): Wrap the amount popped off the stack in
5047
+ an UNSPEC_CONST in order to stop it being rejected by
5048
+ -mmax-constant-size.
5049
+ (pop_and_return): Add a "(return)" rtx.
5050
+ (call): Drop the immediate operand.
5051
+ (call_internal): Likewise.
5052
+ (call_value): Likewise.
5053
+ (call_value_internal): Likewise.
5054
+ (sibcall_internal): Likewise.
5055
+ (sibcall_value_internal): Likewise.
5056
+ (sibcall): Likewise. Generate an explicit call using
5057
+ sibcall_internal.
5058
+ (sibcall_value): Likewise.
5059
+ (mov<>): FAIL if a constant operand is not legitimate.
5060
+ (addsi3_unpsec): New pattern.
5061
+
5062
+ * config/rx/rx.c (rx_print_operand_address): Handle UNPSEC
5063
+ CONSTs.
5064
+ (ok_for_max_constant): New function.
5065
+ (gen_safe_add): New function.
5066
+ (rx_expand_prologue): Use gen_safe_add.
5067
+ (rx_expand_epilogue): Likewise.
5068
+ (rx_is_legitimate_constant): Use ok_for_max_constant. Handle
5069
+ UNSPEC CONSTs.
5070
+
5071
+ 2011-01-17 Richard Henderson <rth@redhat.com>
5072
+
5073
+ * config/rx/predicates.md (rx_constshift_operand): Use match_test.
5074
+ (rx_restricted_mem_operand): New.
5075
+ (rx_shift_operand): Use register_operand.
5076
+ (rx_source_operand, rx_compare_operand): Likewise.
5077
+ * config/rx/rx.md (addsi3_flags): New expander.
5078
+ (adddi3): Rewrite as expander.
5079
+ (adc_internal, *adc_flags, adddi3_internal): New patterns.
5080
+ (subsi3_flags): New expander.
5081
+ (subdi3): Rewrite as expander.
5082
+ (sbb_internal, *sbb_flags, subdi3_internal): New patterns.
5083
+
5084
+ * config/rx/rx.c (RX_BUILTIN_SAT): Remove.
5085
+ (rx_init_builtins): Remove sat builtin.
5086
+ (rx_expand_builtin): Likewise.
5087
+ * config/rx/rx.md (ssaddsi3): New.
5088
+ (*sat): Rename from sat. Represent the CC_REG input.
5089
+
5090
+ * config/rx/predicates.md (rshift_operator): New.
5091
+ * config/rx/rx.c (rx_expand_insv): Remove.
5092
+ * config/rx/rx-protos.h: Update.
5093
+ * config/rx/rx.md (*bitset): Rename from bitset. Swap the ashift
5094
+ operand to the canonical position.
5095
+ (*bitset_in_memory, *bitinvert, *bitinvert_in_memory): Similarly.
5096
+ (*bitclr, *bitclr_in_memory): Similarly.
5097
+ (*insv_imm, rx_insv_reg, *insv_cond, *bmcc, *insv_cond_lt): New.
5098
+ (insv): Retain the zero_extract in the expansion.
5099
+
5100
+ * config/rx/rx.md (bswapsi2): Use = not + for output reload.
5101
+ (bswaphi2, bitinvert, revw): Likewise.
5102
+
5103
+ * config/rx/rx.c (gen_rx_store_vector): Use VOIDmode for gen_rtx_SET.
5104
+ (gen_rx_rtsd_vector, gen_rx_popm_vector): Likewise.
5105
+ * config/rx/rx.md (pop_and_return): Use VOIDmode for SET.
5106
+ (stack_push, stack_pushm, stack_pop, stack_popm): Likewise.
5107
+ (bitset, bitset_in_memory): Likewise.
5108
+ (bitinvert, bitinvert_in_memory): Likewise.
5109
+ (bitclr, bitclr_in_memory): Likewise.
5110
+ (insv, sync_lock_test_and_setsi, movstr, rx_movstr): Likewise.
5111
+ (rx_strend, rx_cmpstrn): Likewise.
5112
+ (rx_setmem): Likewise. Make the source BLKmode to match the dest.
5113
+ (bitop peep2 patterns): Remove.
5114
+
5115
+ * config/rx/rx.c (rx_match_ccmode): New.
5116
+ * config/rx/rx-protos.h: Update.
5117
+ * config/rx/rx.md (abssi2): Clobber, don't set flags.
5118
+ (addsi3, adddi3, andsi3, negsi2, one_cmplsi2, iorsi3): Likewise.
5119
+ (rotlsi3, rotrsi3, ashrsi3, lshrsi3, ashlsi3): Likewise.
5120
+ (subsi3, subdi3, xorsi3, addsf3, divsf3, mulsf3, subsf3): Likewise.
5121
+ (fix_truncsfsi2, floatsisf2): Likewise.
5122
+ (*abssi2_flags, *addsi3_flags, *andsi3_flags, *negsi2_flags): New.
5123
+ (*one_cmplsi2_flags, *iorsi3_flags, *rotlsi3_flags): New.
5124
+ (*rotrsi3_flags, *ashrsi3_flags, *lshrsi3_flags, *ashlsi3_flags): New.
5125
+ (*subsi3_flags, *xorsi3_flags): New.
5126
+
5127
+ * config/rx/rx.md (cstoresf4, *cstoresf4): New patterns.
5128
+
5129
+ * config/rx/rx.c (rx_print_operand): Remove workaround for
5130
+ unsplit comparison operations.
5131
+
5132
+ * config/rx/rx.md (movsicc): Split after reload.
5133
+ (*movsicc): Merge *movsieq and *movsine via match_operator.
5134
+ (*stcc): New pattern.
5135
+
5136
+ * config/rx/rx.c (rx_float_compare_mode): Remove.
5137
+ * config/rx/rx.h (rx_float_compare_mode): Remove.
5138
+ * config/rx/rx.md (cstoresi4): Split after reload.
5139
+ (*sccc): New pattern.
5140
+
5141
+ * config/rx/predicates.md (label_ref_operand): New.
5142
+ (rx_z_comparison_operator): New.
5143
+ (rx_zs_comparison_operator): New.
5144
+ (rx_fp_comparison_operator): New.
5145
+ * config/rx/rx.c (rx_print_operand) [B]: Examine comparison modes.
5146
+ Validate that the flags are set properly for the comparison.
5147
+ (rx_gen_cond_branch_template): Remove.
5148
+ (rx_cc_modes_compatible): Remove.
5149
+ (mode_from_flags): New.
5150
+ (flags_from_code): Rename from flags_needed_for_conditional.
5151
+ (rx_cc_modes_compatible): Re-write in terms of flags_from_mode.
5152
+ (rx_select_cc_mode): Likewise.
5153
+ (rx_split_fp_compare): New.
5154
+ (rx_split_cbranch): New.
5155
+ * config/rx/rx.md (most_cond, zs_cond): Remove iterators.
5156
+ (*cbranchsi4): Use match_operator and rx_split_cbranch.
5157
+ (*cbranchsf4): Similarly.
5158
+ (*cbranchsi4_tst): Rename from *tstbranchsi4_<code>. Use
5159
+ match_operator and rx_split_cbranch.
5160
+ (*cbranchsi4_tst_ext): Combine *tstbranchsi4m_eq and
5161
+ tstbranchsi4m_ne. Use match_operator and rx_split_cbranch.
5162
+ (*cmpsi): Rename from cmpsi.
5163
+ (*tstsi): Rename from tstsi.
5164
+ (*cmpsf): Rename from cmpsf; use CC_Fmode.
5165
+ (*conditional_branch): Rename from conditional_branch.
5166
+ (*reveresed_conditional_branch): Remove.
5167
+ (b<code>): Remove expander.
5168
+ * config/rx/rx-protos.h: Update.
5169
+
5170
+ * config/rx/rx.c (rx_compare_redundant): Remove.
5171
+ * config/rx/rx.md (cmpsi): Don't use it.
5172
+ * config/rx/rx-protos.h: Update.
5173
+
5174
+ * config/rx/rx-modes.def (CC_F): New mode.
5175
+ * config/rx/rx.c (rx_select_cc_mode): New.
5176
+ * config/rx/rx.h (SELECT_CC_MODE): Use it.
5177
+ * config/rx/rx-protos.h: Update.
5178
+
5179
+2011-02-01 Richard Guenther <rguenther@suse.de>
5180
+
5181
+ PR tree-optimization/47541
5182
+ * tree-ssa-structalias.c (push_fields_onto_fieldstack): Make
5183
+ sure to have a field at offset zero.
5184
+
5185
+2011-01-31 Nathan Froyd <froydnj@codesourcery.com>
5186
+
5187
+ Backport from mainline:
5188
+ 2010-12-30 Nathan Froyd <froydnj@codesourcery.com>
5189
+
5190
+ PR target/44606
5191
+ * reload1.c (choose_reload_regs): Don't look for equivalences for
5192
+ output reloads of constant loads.
5193
+
5194
+2011-01-30 Gerald Pfeifer <gerald@pfeifer.com>
5195
+
5196
+ * doc/install.texi (hppa-hp-hpux10): Remove references to HP
5197
+ support sites.
5198
+
5199
+2011-01-30 Gerald Pfeifer <gerald@pfeifer.com>
5200
+
5201
+ * doc/install.texi: Update copyright years.
5202
+
5203
+2011-01-30 Gerald Pfeifer <gerald@pfeifer.com>
5204
+
5205
+ * doc/install.texi (Binaries): Remove outdated reference for
5206
+ Motorola 68HC11/68HC12 downloads.
5207
+
5208
+2011-01-30 Gerald Pfeifer <gerald@pfeifer.com>
5209
+
5210
+ * doc/extend.texi (Thread-Local): Adjust reference to Ulrich
5211
+ Drepper's paper.
5212
+
5213
+2011-01-29 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
5214
+
5215
+ Backport from mainline:
5216
+ 2010-08-22 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
5217
+
5218
+ PR boehm-gc/34544
5219
+ * gthr-posix.h (__gthread_active_init): Delete.
5220
+ (__gthread_active_p): Do activity check here.
5221
+ Don't include errno.h on hppa-hpux. Update comment.
5222
+ * gthr-posix95.h (__gthread_active_init): Delete.
5223
+ (__gthread_active_p): Do activity check here.
5224
+ Don't include errno.h on hppa-hpux. Update comment.
5225
+ * config.gcc (hppa[12]*-*-hpux11*): Define extra_parts.
5226
+ * config/pa/pa64-hpux.h (LIB_SPEC): When -static is specified, only
5227
+ add -lpthread when -mt or -pthread is specified.
5228
+ * config/pa/pa-hpux11.h (LIB_SPEC): likewise.
5229
+ (LINK_GCC_C_SEQUENCE_SPEC): Define.
5230
+ * config/pa/t-pa-hpux11 (LIBGCCSTUB_OBJS): Define.
5231
+ (stublib.c, pthread_default_stacksize_np-stub.o,
5232
+ pthread_mutex_lock-stub.o, pthread_mutex_unlock-stub.o,
5233
+ $(T)libgcc_stub.a): Add methods.
5234
+ * config/pa/t-pa64 (LIBGCCSTUB_OBJS): Add pthread stubs.
5235
+ (stublib.c, pthread_default_stacksize_np-stub.o,
5236
+ pthread_mutex_lock-stub.o, pthread_mutex_unlock-stub.o): Add methods.
5237
+ * config/pa/stublib.c (pthread_default_stacksize_np, pthread_mutex_lock,
5238
+ pthread_mutex_unlock): New stubs.
5239
+
5240
+2011-01-26 Eric Botcazou <ebotcazou@adacore.com>
5241
+
5242
+ PR rtl-optimization/44469
5243
+ * cfgcleanup.c (try_optimize_cfg): Iterate in CFG layout mode too
5244
+ after removing trivially dead basic blocks.
5245
+
5246
+2011-01-25 Richard Guenther <rguenther@suse.de>
5247
+
5248
+ PR tree-optimization/47411
5249
+ Backport from mainline
5250
+ 2010-06-30 Michael Matz <matz@suse.de>
5251
+
5252
+ PR bootstrap/44699
5253
+ * tree-vrp.c (vrp_finalize): Deal with changing num_ssa_names.
5254
+
5255
+2011-01-21 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
5256
+
5257
+ Backport from mainline.
5258
+ 2010-09-08 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
5259
+
5260
+ PR target/44392
5261
+ * config/arm/arm.md (bswapsi2): Handle condition correctly
5262
+ for armv6 and optimize_size.
5263
+
5264
+2011-01-21 Richard Guenther <rguenther@suse.de>
5265
+
5266
+ PR tree-optimization/47365
5267
+ * tree-ssa-sccvn.h (vn_lookup_kind): Declare.
5268
+ (vn_reference_lookup_pieces): Adjust.
5269
+ (vn_reference_lookup): Likewise.
5270
+ * tree-ssa-sccvn.c (vn_walk_kind): New static global.
5271
+ (vn_reference_lookup_3): Only look through kills if in
5272
+ VN_WALKREWRITE mode.
5273
+ (vn_reference_lookup_pieces): Adjust.
5274
+ (vn_reference_lookup): Likewise.
5275
+ (visit_reference_op_load): Likewise.
5276
+ (visit_reference_op_store): Likewise.
5277
+ * tree-ssa-pre.c (phi_translate_1): Use VN_WALK mode.
5278
+ (compute_avail): Likewise.
5279
+ (eliminate): Likewise.
5280
+
5281
+2011-01-20 Richard Guenther <rguenther@suse.de>
5282
+
5283
+ PR tree-optimization/47167
5284
+ * tree-ssa-copyrename.c (copy_rename_partition_coalesce):
5285
+ Revert previous change, only avoid enumeral type changes.
5286
+
5287
+2011-01-17 H.J. Lu <hongjiu.lu@intel.com>
5288
+
5289
+ Backport from mainline
5290
+ 2011-01-17 H.J. Lu <hongjiu.lu@intel.com>
5291
+
5292
+ PR target/47318
5293
+ * config/i386/avxintrin.h (_mm_maskload_pd): Change mask to
5294
+ __m128i.
5295
+ (_mm_maskstore_pd): Likewise.
5296
+ (_mm_maskload_ps): Likewise.
5297
+ (_mm_maskstore_ps): Likewise.
5298
+ (_mm256_maskload_pd): Change mask to __m256i.
5299
+ (_mm256_maskstore_pd): Likewise.
5300
+ (_mm256_maskload_ps): Likewise.
5301
+ (_mm256_maskstore_ps): Likewise.
5302
+
5303
+ * config/i386/i386-builtin-types.def: Updated.
5304
+ (ix86_expand_special_args_builtin): Likewise.
5305
+
5306
+ * config/i386/i386.c (bdesc_special_args): Update
5307
+ __builtin_ia32_maskloadpd, __builtin_ia32_maskloadps,
5308
+ __builtin_ia32_maskloadpd256, __builtin_ia32_maskloadps256,
5309
+ __builtin_ia32_maskstorepd, __builtin_ia32_maskstoreps,
5310
+ __builtin_ia32_maskstorepd256 and __builtin_ia32_maskstoreps256.
5311
+
5312
+ * config/i386/sse.md (avx_maskload<ssemodesuffix><avxmodesuffix>):
5313
+ Use <avxpermvecmode> on mask register.
5314
+ (avx_maskstore<ssemodesuffix><avxmodesuffix>): Likewise.
5315
+
5316
+2011-01-17 Olivier Hainque <hainque@adacore.com>
5317
+ Michael Haubenwallner <michael.haubenwallner@salomon.at>
5318
+ Eric Botcazou <ebotcazou@adacore.com>
5319
+
5320
+ PR target/46655
5321
+ * xcoffout.c (ASM_OUTPUT_LINE): Output line only if positive, and only
5322
+ if <= USHRT_MAX in 32-bit mode.
5323
+
5324
+2011-01-17 Richard Guenther <rguenther@suse.de>
5325
+
5326
+ Backport from mainline
5327
+ PR tree-optimization/47286
5328
+ * tree-ssa-structalias.c (new_var_info): Register variables
5329
+ are global.
5330
+
5331
+ PR tree-optimization/44592
5332
+ * tree-ssa-ccp.c (gimplify_and_update_call_from_tree): Copy
5333
+ from trunk.
5334
+
5335
+2011-01-16 Jakub Jelinek <jakub@redhat.com>
5336
+
5337
+ Backport from mainline
5338
+ 2011-01-07 Jakub Jelinek <jakub@redhat.com>
5339
+
5340
+ PR target/47201
5341
+ * config/i386/i386.c (ix86_delegitimize_address): If
5342
+ simplify_gen_subreg fails, return orig_x.
5343
+
5344
+ 2011-01-06 Jakub Jelinek <jakub@redhat.com>
5345
+
5346
+ PR c/47150
5347
+ * c-convert.c (convert): When converting a complex expression
5348
+ other than COMPLEX_EXPR to a different complex type, ensure
5349
+ c_save_expr is called instead of save_expr, unless in_late_binary_op.
5350
+ * c-typeck.c (convert_for_assignment): Set in_late_binary_op also
5351
+ when converting COMPLEX_TYPE.
5352
+
5353
+ 2010-12-21 Jakub Jelinek <jakub@redhat.com>
5354
+
5355
+ PR target/46880
5356
+ * config/i386/sse.md (sse2_loadlpd, sse2_movsd): Fix shufpd source
5357
+ operand.
5358
+
5359
+ PR middle-end/45852
5360
+ * expr.c (store_expr): Ignore alt_rtl if equal to target,
5361
+ but has side-effects.
5362
+
5363
+ 2010-12-16 Jakub Jelinek <jakub@redhat.com>
5364
+
5365
+ PR tree-optimization/43655
5366
+ * tree-ssa-ter.c (is_replaceable_p): Don't use
5367
+ gimple_references_memory_p for -O0, instead check for load
5368
+ by looking at rhs.
5369
+
5370
+ PR debug/46893
5371
+ * cfgexpand.c (expand_debug_expr): If GET_MODE (op0) is VOIDmode,
5372
+ use TYPE_MODE (TREE_TYPE (tem)) instead of mode1.
5373
+
5374
+ 2010-12-10 Jakub Jelinek <jakub@redhat.com>
5375
+
5376
+ PR rtl-optimization/46804
5377
+ * regmove.c (optimize_reg_copy_3): Look for REG_EQUAL note
5378
+ on the setter of src_reg rather than on insn. If it is
5379
+ equal to the setter's original SET_SRC, replace it with its
5380
+ zero or sign extension instead of dropping it.
5381
+
5382
+ PR rtl-optimization/46865
5383
+ * rtl.c (rtx_equal_p_cb, rtx_equal_p): For last operand of
5384
+ ASM_OPERANDS and ASM_INPUT if integers are different,
5385
+ call locator_eq.
5386
+ * jump.c (rtx_renumbered_equal_p): Likewise.
5387
+
5388
+ PR tree-optimization/46864
5389
+ * tree-ssa-loop-im.c (loop_suitable_for_sm): Return false even
5390
+ when there are EDGE_EH exit edges.
5391
+
5392
+ 2010-12-09 Jakub Jelinek <jakub@redhat.com>
5393
+
5394
+ PR target/41082
5395
+ * config/rs6000/rs6000.c (rs6000_expand_vector_extract): Use stvx
5396
+ instead of stve*x.
5397
+ (altivec_expand_stv_builtin): For op0 use mode of operand 1 instead
5398
+ of operand 0.
5399
+ * config/rs6000/altivec.md (VI_scalar): New mode attr.
5400
+ (altivec_stve<VI_char>x, *altivec_stvesfx): Use scalar instead of
5401
+ vector mode for operand 0, put operand 1 into UNSPEC.
5402
+
5403
+2011-01-13 Nick Clifton <nickc@redhat.com>
5404
+
5405
+ Import this fix from the mainline:
5406
+ 2010-10-19 Nick Clifton <nickc@redhat.com>
5407
+
5408
+ * config/rx/rx.c (rx_function_value): Small integer types are
5409
+ promoted to SImode.
5410
+ (rx_promote_function_mode): New function.
5411
+ (TARGET_PROMOTE_FUNCTION_MODE): Define.
5412
+
5413
+2011-01-07 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
5414
+
5415
+ Backport from mainline:
5416
+ 2011-01-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
5417
+
5418
+ PR target/43309
5419
+ * config/i386/i386.c (legitimize_tls_address)
5420
+ <TLS_MODEL_INITIAL_EXEC>: Handle TARGET_64BIT && TARGET_SUN_TLS.
5421
+ * config/i386/i386.md (UNSPEC_TLS_IE_SUN): Declare.
5422
+ (tls_initial_exec_64_sun): New pattern.
5423
+
5424
+2011-01-03 Eric Botcazou <ebotcazou@adacore.com>
5425
+
5426
+ Backport from mainline
5427
+ 2010-12-30 Eric Botcazou <ebotcazou@adacore.com>
5428
+
5429
+ PR target/47038
5430
+ * config/sparc/sparc.c (sparc_file_end): Call resolve_unique_section
5431
+ on the GOT helper if USE_HIDDEN_LINKONCE.
5432
+
5433
+ 2010-12-02 Eric Botcazou <ebotcazou@adacore.com>
5434
+
5435
+ PR target/46685
5436
+ * config/sparc/sparc.c (can_use_mov_pic_label_ref): New predicate.
5437
+ (sparc_expand_move): Call it to decide whether to emit the special
5438
+ mov{si,di}_pic_label_ref patterns.
5439
+ (sparc_legitimize_pic_address): Call it to decide whether to emit
5440
+ the regular PIC sequence for labels. Fix long line.
5441
+ (sparc_file_end): Set is_thunk for the PIC helper.
5442
+
5443
+2010-12-30 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
5444
+
5445
+ * config/pa/pa.md: Add ",*" condition to 64-bit add/subtract boolean
5446
+ patterns.
5447
+
5448
+2010-12-27 Yao Qi <yao@codesourcery.com>
5449
+
5450
+ Backport from mainline:
5451
+ 2010-10-14 Yao Qi <yao@codesourcery.com>
5452
+
5453
+ PR target/45447
5454
+ * config/arm/arm.c (arm_build_builtin_va_list): Assign
5455
+ va_list_name to TYPE_STUB_DECL (va_list_type).
5456
+
5457
+2010-12-23 Sebastian Pop <sebastian.pop@amd.com>
5458
+ Richard Guenther <rguenther@suse.de>
5459
+
5460
+ PR tree-optimization/46758
5461
+ * graphite-sese-to-poly.c (scan_tree_for_params_right_scev): Use
5462
+ tree_int_to_gmp instead of int_cst_value.
5463
+ (scan_tree_for_params_int): Same.
5464
+ (scan_tree_for_params): Same.
5465
+ (pdr_add_data_dimensions): Use ppl_set_inhomogeneous_tree.
5466
+
5467
+2010-12-23 Sebastian Pop <sebastian.pop@amd.com>
5468
+
5469
+ Backport from mainline
5470
+ Fix PR45758: reset scevs before Graphite.
5471
+ 2010-09-24 Sebastian Pop <sebastian.pop@amd.com>
5472
+
5473
+ PR tree-optimization/45552
5474
+ * graphite.c (graphite_initialize): Call scev_reset.
5475
+
5476
+2010-12-23 Sebastian Pop <sebastian.pop@amd.com>
5477
+
5478
+ PR tree-optimization/43023
5479
+ * tree-data-ref.c (mem_write_stride_of_same_size_as_unit_type_p):
5480
+ Removed.
5481
+ (stores_zero_from_loop): Call stmt_stores_zero.
5482
+ (stmt_with_adjacent_zero_store_dr_p): New.
5483
+ * tree-data-ref.h (stmt_with_adjacent_zero_store_dr_p): Declared.
5484
+ (stride_of_unit_type_p): New.
5485
+ * tree-loop-distribution.c (generate_memset_zero): Do not return a
5486
+ boolean. Call gcc_assert on stride_of_unit_type_p.
5487
+ (generate_builtin): Call stmt_stores_zero.
5488
+ (rdg_flag_all_uses): Removed.
5489
+ (rdg_flag_similar_memory_accesses): Removed.
5490
+ (build_rdg_partition_for_component): Removed parameter
5491
+ other_stores. Removed call to rdg_flag_similar_memory_accesses.
5492
+ (can_generate_builtin): New.
5493
+ (similar_memory_accesses): New.
5494
+ (fuse_partitions_with_similar_memory_accesses): New.
5495
+ (rdg_build_partitions): Call
5496
+ fuse_partitions_with_similar_memory_accesses.
5497
+
5498
+2010-12-21 Martin Jambor <mjambor@suse.cz>
5499
+
5500
+ Backport from mainline:
5501
+ 2010-12-09 Martin Jambor <mjambor@suse.cz>
5502
+
5503
+ PR middle-end/46734
5504
+ * tree-sra.c (splice_param_accesses): Check that there are not
5505
+ multiple ADDRESSABLE types.
5506
+
5507
+2010-12-19 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
5508
+
5509
+ Backport from mainline:
5510
+ 2010-12-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
5511
+
5512
+ PR target/46915
5513
+ * config/pa/pa.c (branch_to_delay_slot_p): Use next_active_insn instead
5514
+ of next_real_insn. Search forward checking for both ASM_INPUT and
5515
+ ASM_OPERANDS asms until exit condition is found.
5516
+ (branch_needs_nop_p): Likewise.
5517
+ (use_skip_p): New function.
5518
+ (output_cbranch): Use use_skip_p.
5519
+ (output_bb, output_bvb): Likewise.
5520
+
5521
+2010-12-19 Eric Botcazou <ebotcazou@adacore.com>
5522
+
5523
+ PR target/46729
5524
+ * config/sparc/sparc.h (GLOBAL_OFFSET_TABLE_REGNUM): New macro.
5525
+ (PIC_OFFSET_TABLE_REGNUM): Rewrite in terms of above macro.
5526
+ * config/sparc/sparc.c (pic_helper_needed): Delete.
5527
+ (global_offset_table): Likewise.
5528
+ (pic_helper_symbol): Rename to...
5529
+ (got_helper_rtx): ...this.
5530
+ (global_offset_table_rtx): New global variable.
5531
+ (sparc_got_symbol): Likewise.
5532
+ (sparc_got): New static function.
5533
+ (check_pic): Use local variable and call sparc_got.
5534
+ (sparc_tls_symbol): Initialize to NULL_RTX.
5535
+ (sparc_tls_got): In non-PIC mode, reload the GOT register for Sun TLS
5536
+ and 32-bit ABI and copy the GOT symbol to a new register otherwise.
5537
+ (get_pc_thunk_name): Rename local variable.
5538
+ (gen_load_pcrel_sym): New wrapper around load_pcrel_sym{si,di}.
5539
+ (load_pic_register): Rename to...
5540
+ (load_got_register): ...this. Adjust and call gen_load_pcrel_sym.
5541
+ (sparc_expand_prologue): Do not test flag_pic.
5542
+ (sparc_output_mi_thunk): Use pic_offset_table_rtx directly.
5543
+ (sparc_file_end): Test got_helper_rtx instead of pic_helper_needed.
5544
+ Rename local variable and do not call get_pc_thunk_name again.
5545
+ * config/sparc/sparc.md (load_pcrel_sym): Add operand #3.
5546
+
5547
+2010-12-18 Alexandre Oliva <aoliva@redhat.com>
5548
+
5549
+ PR debug/46756
5550
+ * jump.c (mark_all_labels): Skip debug insns.
5551
+
5552
+2010-12-18 Alexandre Oliva <aoliva@redhat.com>
5553
+
5554
+ PR debug/46782
5555
+ * cfgcleanup.c (try_forward_edges): Skip debug insns.
5556
+
5557
+2010-12-16 Eric Botcazou <ebotcazou@adacore.com>
5558
+
5559
+ * tree-ssa-sccvn.c (vn_reference_lookup_3): Always punt if the call to
5560
+ get_ref_base_and_extent returns -1 as the max size.
5561
+
5562
2010-12-16 Release Manager
5563
5564
* GCC 4.5.2 released.
5565
@@ -106,7 +1010,7 @@
5566
5567
Backport from mainline:
5568
2010-09-15 Olivier Hainque <hainque@adacore.com>
5569
- Jose Ruiz <ruiz@adacore.com>
5570
+ Jose Ruiz <ruiz@adacore.com>
5571
5572
* config/alpha/osf.h (MD_UNWIND_SUPPORT): Define.
5573
* config/alpha/osf-unwind.h: New file.
4812
@@ -1,3 +1,115 @@
4813
+2010-05-05 Ira Rosen <ira.rosen@linaro.org>
4814
+
4815
+ Backport from mainline:
4816
+ 2011-04-18 Ulrich Weigand <ulrich.weigand@linaro.org>
4817
+ Ira Rosen <ira.rosen@linaro.org>
4818
+
4819
+ PR target/48252
4820
+ * config/arm/arm.c (neon_emit_pair_result_insn): Swap arguments
4821
+ to match neon_vzip/vuzp/vtrn_internal.
4822
+ * config/arm/neon.md (neon_vtrn<mode>_internal): Make both
4823
+ outputs explicitly dependent on both inputs.
4824
+ (neon_vzip<mode>_internal, neon_vuzp<mode>_internal): Likewise.
4825
+
4826
+2011-05-04 Uros Bizjak <ubizjak@gmail.com>
4827
+
4828
+ Backport from mainline
4829
+ 2011-04-21 Uros Bizjak <ubizjak@gmail.com>
4830
+
4831
+ PR target/48708
4832
+ * config/i386/i386.c (ix86_expand_vector_set) <V2DImode>: Generate
4833
+ vec_extract and vec_concat for non-SSE4_1 targets.
4834
+
4835
+2011-05-04 Uros Bizjak <ubizjak@gmail.com>
4836
+
4837
+ * config/i386/i386.md (*movdi_internal_rex64) <TYPE_SSEMOV>:
4838
+ Use %v prefix in insn mnemonic to handle TARGET_AVX.
4839
+ (*movdi_internal): Use "maybe_vex" instead of "vex" in "prefix"
4840
+ attribute calculation.
4841
+ (*movdf_internal): Output AVX mnemonics. Add "prefix" attribute.
4842
+ * config/i386/sse.md (*sse2_storeq_rex64): Do not emit %v prefix
4843
+ for mov{q} mnemonic.
4844
+ (*vec_extractv2di_1_rex64_avx): Ditto.
4845
+ (*vec_concatv2di_rex64_sse4_1): Use %vmovd for reg<->xmm moves.
4846
+ (*vec_concatv2di_rex64_sse): Use movd for reg<->xmm moves.
4847
+ * config/i386/mmx.md (*mov<mode>_internal_rex64): Ditto.
4848
+
4849
+2011-05-03 Uros Bizjak <ubizjak@gmail.com>
4850
+ Jakub Jelinek <jakub@redhat.com>
4851
+
4852
+ PR target/48774
4853
+ * config/i386/i386.c (ix86_match_ccmode): For CC{A,C,O,S}mode
4854
+ only succeed if req_mode is the same as set_mode.
4855
+
4856
+2011-05-03 Jakub Jelinek <jakub@redhat.com>
4857
+
4858
+ Backport from mainline
4859
+ 2011-04-30 Jakub Jelinek <jakub@redhat.com>
4860
+
4861
+ PR tree-optimization/48809
4862
+ * tree-switch-conversion.c (build_arrays): Compute tidx in unsigned
4863
+ type.
4864
+ (gen_inbound_check): Don't compute index_expr - range_min in utype
4865
+ again, instead reuse SSA_NAME initialized in build_arrays.
4866
+ Remove two useless gsi_for_stmt calls.
4867
+
4868
+ 2011-04-28 Jakub Jelinek <jakub@redhat.com>
4869
+
4870
+ PR middle-end/48597
4871
+ * final.c (final_scan_insn): Call dwarf2out_frame_debug even for
4872
+ inline asm.
4873
+
4874
+ 2011-04-27 Jakub Jelinek <jakub@redhat.com>
4875
+
4876
+ PR c/48742
4877
+ * c-typeck.c (build_binary_op): Don't wrap arguments if
4878
+ int_operands is true.
4879
+
4880
+ 2011-04-23 Jakub Jelinek <jakub@redhat.com>
4881
+
4882
+ PR c/48685
4883
+ * fold-const.c (fold_convert_loc): Add NOP_EXPR when casting
4884
+ to VOID_TYPE even around MODIFY_EXPR.
4885
+
4886
+2011-05-02 Ulrich Weigand <ulrich.weigand@linaro.org>
4887
+
4888
+ PR middle-end/43085
4889
+ Backport from mainline:
4890
+
4891
+ 2010-04-29 Bernd Schmidt <bernds@codesourcery.com>
4892
+
4893
+ From Dominique d'Humieres <dominiq@lps.ens.fr>
4894
+ PR bootstrap/43858
4895
+ * ifcvt.c (dead_or_predicable): Use df_simulate_find_defs to compute
4896
+ test_set.
4897
+
4898
+ 2010-04-26 Bernd Schmidt <bernds@codesourcery.com>
4899
+
4900
+ * df-problems.c (df_simulate_initialize_forwards): Set, don't clear,
4901
+ bits for artificial defs at the top of the block.
4902
+ * fwprop.c (single_def_use_enter_block): Don't call it.
4903
+
4904
+ 2010-04-22 Bernd Schmidt <bernds@codesourcery.com>
4905
+
4906
+ * ifcvt.c (dead_or_predicable): Use df_simulate_find_defs and
4907
+ df_simulate_find_noclobber_defs as appropriate. Keep track of an
4908
+ extra set merge_set_noclobber, and use it to relax the final test
4909
+ slightly.
4910
+ * df.h (df_simulate_find_noclobber_defs): Declare.
4911
+ * df-problems.c (df_simulate_find_defs): Don't ignore partial or
4912
+ conditional defs.
4913
+ (df_simulate_find_noclobber_defs): New function.
4914
+
4915
+2011-04-29 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
4916
+
4917
+ PR target/48288
4918
+ * config/pa/predicates.md (ior_operand): Delete predicate.
4919
+ (cint_ior_operand, reg_or_cint_ior_operand): New predicates.
4920
+ * config/pa/pa.md (iordi3): Use reg_or_cint_ior_operand predicate in
4921
+ expander. Use cint_ior_operand in unnamed insn.
4922
+ (iorsi3): Likewise.
4923
+ * config/pa/pa-protos.h (ior_operand): Delete declarations.
4924
+
4925
2011-04-28 Release Manager
4926
4927
* GCC 4.5.3 released.
5574
4928
--- a/src/gcc/DATESTAMP
5575
4929
+++ b/src/gcc/DATESTAMP
5576
4930
@@ -1 +1 @@
5577
-20101216
5578
+20110406
4931
-20110428
4932
+20110505
5579
4933
--- a/src/gcc/LINARO-VERSION
5580
4934
+++ b/src/gcc/LINARO-VERSION
5581
4935
@@ -0,0 +1 @@
5582
+4.5-2011.04-0
4936
+4.5-2011.05-0
5583
4937
--- a/src/gcc/Makefile.in
5584
4938
+++ b/src/gcc/Makefile.in
5585
4939
@@ -646,6 +646,7 @@
5665
5019
ira-conflicts.o: ira-conflicts.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
5666
5020
$(TARGET_H) $(RTL_H) $(REGS_H) hard-reg-set.h $(FLAGS_H) \
5667
5021
insn-config.h $(RECOG_H) $(BASIC_BLOCK_H) $(TOPLEV_H) $(TM_P_H) $(PARAMS_H) \
5668
--- a/src/gcc/ada/ChangeLog
5669
+++ b/src/gcc/ada/ChangeLog
5670
@@ -1,3 +1,18 @@
5671
+2011-02-12 Gerald Pfeifer <gerald@pfeifer.com>
5672
+
5673
+ * gnat_ugn.texi (Compiling Different Versions of Ada): Update
5674
+ link to "Ada Issues".
5675
+
5676
+2011-02-08 Eric Botcazou <ebotcazou@adacore.com>
5677
+
5678
+ * gcc-interface/Makefile.in (x86-64 darwin): Handle multilibs.
5679
+
5680
+2011-01-04 Eric Botcazou <ebotcazou@adacore.com>
5681
+
5682
+ * gcc-interface/trans.c (Subprogram_Body_to_gnu): Evaluate the
5683
+ expressions of the parameter cache within the statement group of
5684
+ the CICO mechanism.
5685
+
5686
2010-12-16 Release Manager
5687
5688
* GCC 4.5.2 released.
5689
--- a/src/gcc/ada/gcc-interface/Makefile.in
5690
+++ b/src/gcc/ada/gcc-interface/Makefile.in
5691
@@ -2143,11 +2143,17 @@
5692
s-taprop.adb<s-taprop-posix.adb \
5693
s-taspri.ads<s-taspri-posix.ads \
5694
s-tpopsp.adb<s-tpopsp-posix-foreign.adb \
5695
- a-numaux.ads<a-numaux-x86.ads \
5696
- a-numaux.adb<a-numaux-x86.adb \
5697
g-trasym.ads<g-trasym-unimplemented.ads \
5698
g-trasym.adb<g-trasym-unimplemented.adb \
5699
- system.ads<system-darwin-x86_64.ads
5700
+ a-numaux.ads<a-numaux-x86.ads \
5701
+ a-numaux.adb<a-numaux-x86.adb
5702
+ ifeq ($(strip $(MULTISUBDIR)),/i386)
5703
+ LIBGNAT_TARGET_PAIRS += \
5704
+ system.ads<system-darwin-x86.ads
5705
+ else
5706
+ LIBGNAT_TARGET_PAIRS += \
5707
+ system.ads<system-darwin-x86_64.ads
5708
+ endif
5709
endif
5710
5711
ifeq ($(strip $(filter-out powerpc%,$(arch))),)
5712
--- a/src/gcc/ada/gcc-interface/trans.c
5713
+++ b/src/gcc/ada/gcc-interface/trans.c
5714
@@ -2303,6 +2303,31 @@
5715
gnat_poplevel ();
5716
gnu_result = end_stmt_group ();
5717
5718
+ /* If we populated the parameter attributes cache, we need to make sure that
5719
+ the cached expressions are evaluated on all the possible paths leading to
5720
+ their uses. So we force their evaluation on entry of the function. */
5721
+ cache = DECL_STRUCT_FUNCTION (gnu_subprog_decl)->language->parm_attr_cache;
5722
+ if (cache)
5723
+ {
5724
+ struct parm_attr_d *pa;
5725
+ int i;
5726
+
5727
+ start_stmt_group ();
5728
+
5729
+ for (i = 0; VEC_iterate (parm_attr, cache, i, pa); i++)
5730
+ {
5731
+ if (pa->first)
5732
+ add_stmt_with_node (pa->first, gnat_node);
5733
+ if (pa->last)
5734
+ add_stmt_with_node (pa->last, gnat_node);
5735
+ if (pa->length)
5736
+ add_stmt_with_node (pa->length, gnat_node);
5737
+ }
5738
+
5739
+ add_stmt (gnu_result);
5740
+ gnu_result = end_stmt_group ();
5741
+ }
5742
+
5743
/* If we are dealing with a return from an Ada procedure with parameters
5744
passed by copy-in/copy-out, we need to return a record containing the
5745
final values of these parameters. If the list contains only one entry,
5746
@@ -2341,30 +2366,6 @@
5747
5748
pop_stack (&gnu_return_label_stack);
5749
5750
- /* If we populated the parameter attributes cache, we need to make sure
5751
- that the cached expressions are evaluated on all possible paths. */
5752
- cache = DECL_STRUCT_FUNCTION (gnu_subprog_decl)->language->parm_attr_cache;
5753
- if (cache)
5754
- {
5755
- struct parm_attr_d *pa;
5756
- int i;
5757
-
5758
- start_stmt_group ();
5759
-
5760
- for (i = 0; VEC_iterate (parm_attr, cache, i, pa); i++)
5761
- {
5762
- if (pa->first)
5763
- add_stmt_with_node (pa->first, gnat_node);
5764
- if (pa->last)
5765
- add_stmt_with_node (pa->last, gnat_node);
5766
- if (pa->length)
5767
- add_stmt_with_node (pa->length, gnat_node);
5768
- }
5769
-
5770
- add_stmt (gnu_result);
5771
- gnu_result = end_stmt_group ();
5772
- }
5773
-
5774
/* Set the end location. */
5775
Sloc_to_locus
5776
((Present (End_Label (Handled_Statement_Sequence (gnat_node)))
5777
5022
--- a/src/gcc/attribs.c
5778
5023
+++ b/src/gcc/attribs.c
5779
5024
@@ -278,6 +278,19 @@
5986
5231
+
5987
5232
--- a/src/gcc/c-common.c
5988
5233
+++ b/src/gcc/c-common.c
5989
@@ -9196,6 +9196,40 @@
5234
@@ -9197,6 +9197,40 @@
5990
5235
}
5991
5236
}
5992
5237
6038
5283
extern void set_underlying_type (tree x);
6039
5284
extern bool is_typedef_decl (tree x);
6040
5285
extern VEC(tree,gc) *make_tree_vector (void);
6041
--- a/src/gcc/c-convert.c
6042
+++ b/src/gcc/c-convert.c
6043
@@ -131,6 +131,32 @@
6044
goto maybe_fold;
6045
6046
case COMPLEX_TYPE:
6047
+ /* If converting from COMPLEX_TYPE to a different COMPLEX_TYPE
6048
+ and e is not COMPLEX_EXPR, convert_to_complex uses save_expr,
6049
+ but for the C FE c_save_expr needs to be called instead. */
6050
+ if (TREE_CODE (TREE_TYPE (e)) == COMPLEX_TYPE)
6051
+ {
6052
+ tree subtype = TREE_TYPE (type);
6053
+ tree elt_type = TREE_TYPE (TREE_TYPE (e));
6054
+
6055
+ if (TYPE_MAIN_VARIANT (elt_type) != TYPE_MAIN_VARIANT (subtype)
6056
+ && TREE_CODE (e) != COMPLEX_EXPR)
6057
+ {
6058
+ if (in_late_binary_op)
6059
+ e = save_expr (e);
6060
+ else
6061
+ e = c_save_expr (e);
6062
+ ret
6063
+ = fold_build2 (COMPLEX_EXPR, type,
6064
+ convert (subtype,
6065
+ fold_build1 (REALPART_EXPR,
6066
+ elt_type, e)),
6067
+ convert (subtype,
6068
+ fold_build1 (IMAGPART_EXPR,
6069
+ elt_type, e)));
6070
+ goto maybe_fold;
6071
+ }
6072
+ }
6073
ret = convert_to_complex (type, e);
6074
goto maybe_fold;
6075
6076
5286
--- a/src/gcc/c-typeck.c
6077
5287
+++ b/src/gcc/c-typeck.c
6078
5288
@@ -3005,8 +3005,15 @@
6104
5314
6105
5315
/* If -Wsign-compare, warn here if type1 and type2 have
6106
5316
different signedness. We'll promote the signed to unsigned
6107
@@ -5025,10 +5036,10 @@
6108
{
6109
tree ret;
6110
bool save = in_late_binary_op;
6111
- if (codel == BOOLEAN_TYPE)
6112
+ if (codel == BOOLEAN_TYPE || codel == COMPLEX_TYPE)
6113
in_late_binary_op = true;
6114
ret = convert_and_check (type, orig_rhs);
6115
- if (codel == BOOLEAN_TYPE)
6116
+ if (codel == BOOLEAN_TYPE || codel == COMPLEX_TYPE)
6117
in_late_binary_op = save;
6118
return ret;
6119
}
6120
5317
@@ -9605,6 +9616,11 @@
6121
5318
if (shorten || common || short_compare)
6122
5319
{
6129
5326
if (result_type == error_mark_node)
6130
5327
return error_mark_node;
6131
5328
}
5329
@@ -9800,7 +9816,7 @@
5330
warn_for_sign_compare (location, orig_op0_folded,
5331
orig_op1_folded, op0, op1,
5332
result_type, resultcode);
5333
- if (!in_late_binary_op)
5334
+ if (!in_late_binary_op && !int_operands)
5335
{
5336
if (!op0_maybe_const || TREE_CODE (op0) != INTEGER_CST)
5337
op0 = c_wrap_maybe_const (op0, !op0_maybe_const);
6132
5338
--- a/src/gcc/c.opt
6133
5339
+++ b/src/gcc/c.opt
6134
5340
@@ -265,6 +265,10 @@
6142
5348
Wimplicit-function-declaration
6143
5349
C ObjC Var(warn_implicit_function_declaration) Init(-1) Warning
6144
5350
Warn about implicit function declarations
6145
--- a/src/gcc/caller-save.c
6146
+++ b/src/gcc/caller-save.c
6147
@@ -1215,7 +1215,7 @@
6148
/* Check that insn to restore REGNO in save_mode[regno] is
6149
correct. */
6150
&& reg_save_code (regno, save_mode[regno]) >= 0)
6151
- mem = adjust_address (mem, save_mode[regno], 0);
6152
+ mem = adjust_address_nv (mem, save_mode[regno], 0);
6153
else
6154
mem = copy_rtx (mem);
6155
6156
@@ -1296,7 +1296,7 @@
6157
/* Check that insn to save REGNO in save_mode[regno] is
6158
correct. */
6159
&& reg_save_code (regno, save_mode[regno]) >= 0)
6160
- mem = adjust_address (mem, save_mode[regno], 0);
6161
+ mem = adjust_address_nv (mem, save_mode[regno], 0);
6162
else
6163
mem = copy_rtx (mem);
6164
6165
5351
--- a/src/gcc/calls.c
6166
5352
+++ b/src/gcc/calls.c
5353
@@ -674,7 +674,7 @@
5354
/* If the value is a non-legitimate constant, force it into a
5355
pseudo now. TLS symbols sometimes need a call to resolve. */
5356
if (CONSTANT_P (args[i].value)
5357
- && !LEGITIMATE_CONSTANT_P (args[i].value))
5358
+ && !targetm.legitimate_constant_p (args[i].mode, args[i].value))
5359
args[i].value = force_reg (args[i].mode, args[i].value);
5360
5361
/* If we are to promote the function arg to a wider mode,
6167
5362
@@ -703,7 +703,9 @@
6168
5363
6169
5364
For small register classes, also do this if this call uses
6192
5387
word_mode, word_mode);
6193
5388
6194
5389
/* There is no need to restrict this code to loading items
6195
@@ -4045,8 +4048,17 @@
5390
@@ -3410,7 +3413,8 @@
5391
5392
/* Make sure it is a reasonable operand for a move or push insn. */
5393
if (!REG_P (addr) && !MEM_P (addr)
5394
- && ! (CONSTANT_P (addr) && LEGITIMATE_CONSTANT_P (addr)))
5395
+ && !(CONSTANT_P (addr)
5396
+ && targetm.legitimate_constant_p (Pmode, addr)))
5397
addr = force_operand (addr, NULL_RTX);
5398
5399
argvec[count].value = addr;
5400
@@ -3450,7 +3454,7 @@
5401
5402
/* Make sure it is a reasonable operand for a move or push insn. */
5403
if (!REG_P (val) && !MEM_P (val)
5404
- && ! (CONSTANT_P (val) && LEGITIMATE_CONSTANT_P (val)))
5405
+ && !(CONSTANT_P (val) && targetm.legitimate_constant_p (mode, val)))
5406
val = force_operand (val, NULL_RTX);
5407
5408
if (pass_by_reference (&args_so_far, mode, NULL_TREE, 1))
5409
@@ -4045,8 +4049,17 @@
6196
5410
/* We need to make a save area. */
6197
5411
unsigned int size = arg->locate.size.constant * BITS_PER_UNIT;
6198
5412
enum machine_mode save_mode = mode_for_size (size, MODE_INT, 1);
6222
5436
static bool old_insns_match_p (int, rtx, rtx);
6223
5437
6224
5438
static void merge_blocks_move_predecessor_nojumps (basic_block, basic_block);
6225
@@ -482,15 +481,20 @@
6226
/* When not optimizing, ensure that edges or forwarder
6227
blocks with different locus are not optimized out. */
6228
int locus = single_succ_edge (target)->goto_locus;
6229
+ rtx last ;
6230
6231
if (locus && goto_locus && !locator_eq (locus, goto_locus))
6232
counter = n_basic_blocks;
6233
else if (locus)
6234
goto_locus = locus;
6235
6236
- if (INSN_P (BB_END (target)))
6237
+ last = BB_END (target);
6238
+ if (DEBUG_INSN_P (last))
6239
+ last = prev_nondebug_insn (last);
6240
+
6241
+ if (last && INSN_P (last))
6242
{
6243
- locus = INSN_LOCATOR (BB_END (target));
6244
+ locus = INSN_LOCATOR (last);
6245
6246
if (locus && goto_locus
6247
&& !locator_eq (locus, goto_locus))
6248
@@ -972,13 +976,27 @@
5439
@@ -977,13 +976,27 @@
6249
5440
be filled that clobbers a parameter expected by the subroutine.
6250
5441
6251
5442
??? We take the simple route for now and assume that if they're
6252
5443
- equal, they were constructed identically. */
6253
5444
+ equal, they were constructed identically.
6254
+
6255
+ Also check for identical exception regions. */
6256
5445
6257
5446
- if (CALL_P (i1)
6258
5447
- && (!rtx_equal_p (CALL_INSN_FUNCTION_USAGE (i1),
5448
+ Also check for identical exception regions. */
5449
+
6259
5450
+ if (CALL_P (i1))
6260
5451
+ {
6261
5452
+ /* Ensure the same EH region. */
6278
5469
6279
5470
#ifdef STACK_REGS
6280
5471
/* If cross_jump_death_matters is not 0, the insn's mode
6281
@@ -1017,6 +1035,29 @@
5472
@@ -1022,6 +1035,29 @@
6282
5473
return false;
6283
5474
}
6284
5475
6308
5499
/* Look through the insns at the end of BB1 and BB2 and find the longest
6309
5500
sequence that are equivalent. Store the first insns for that sequence
6310
5501
in *F1 and *F2 and return the sequence length.
6311
@@ -1024,9 +1065,8 @@
5502
@@ -1029,9 +1065,8 @@
6312
5503
To simplify callers of this function, if the blocks match exactly,
6313
5504
store the head of the blocks in *F1 and *F2. */
6314
5505
6320
5511
{
6321
5512
rtx i1, i2, last1, last2, afterlast1, afterlast2;
6322
5513
int ninsns = 0;
6323
@@ -1066,7 +1106,7 @@
5514
@@ -1071,7 +1106,7 @@
6324
5515
if (i1 == BB_HEAD (bb1) || i2 == BB_HEAD (bb2))
6325
5516
break;
6326
5517
6329
5520
break;
6330
5521
6331
5522
merge_memattrs (i1, i2);
6332
@@ -1074,21 +1114,7 @@
5523
@@ -1079,21 +1114,7 @@
6333
5524
/* Don't begin a cross-jump with a NOTE insn. */
6334
5525
if (INSN_P (i1))
6335
5526
{
6352
5543
6353
5544
afterlast1 = last1, afterlast2 = last2;
6354
5545
last1 = i1, last2 = i2;
6355
@@ -1130,6 +1156,97 @@
5546
@@ -1135,6 +1156,97 @@
6356
5547
return ninsns;
6357
5548
}
6358
5549
6450
5641
/* Return true iff outgoing edges of BB1 and BB2 match, together with
6451
5642
the branch instruction. This means that if we commonize the control
6452
5643
flow before end of the basic block, the semantic remains unchanged.
6453
@@ -1498,7 +1615,7 @@
5644
@@ -1503,7 +1615,7 @@
6454
5645
return false;
6455
5646
6456
5647
/* ... and part the second. */
6459
5650
6460
5651
/* Don't proceed with the crossjump unless we found a sufficient number
6461
5652
of matching instructions or the 'from' block was totally matched
6462
@@ -1923,8 +2040,7 @@
6463
}
6464
}
6465
delete_basic_block (b);
6466
- if (!(mode & CLEANUP_CFGLAYOUT))
6467
- changed = true;
6468
+ changed = true;
6469
/* Avoid trying to remove ENTRY_BLOCK_PTR. */
6470
b = (c == ENTRY_BLOCK_PTR ? c->next_bb : c);
6471
continue;
6472
5653
--- a/src/gcc/cfgexpand.c
6473
5654
+++ b/src/gcc/cfgexpand.c
6474
5655
@@ -64,7 +64,13 @@
6542
5723
goto ternary;
6543
5724
6544
5725
case TRUTH_ANDIF_EXPR:
6545
@@ -2578,7 +2593,7 @@
6546
enum machine_mode opmode = GET_MODE (op0);
6547
6548
if (opmode == VOIDmode)
6549
- opmode = mode1;
6550
+ opmode = TYPE_MODE (TREE_TYPE (tem));
6551
6552
/* This condition may hold if we're expanding the address
6553
right past the end of an array that turned out not to
6554
@@ -2599,7 +2614,8 @@
6555
? SIGN_EXTRACT
6556
: ZERO_EXTRACT, mode,
6557
GET_MODE (op0) != VOIDmode
6558
- ? GET_MODE (op0) : mode1,
6559
+ ? GET_MODE (op0)
6560
+ : TYPE_MODE (TREE_TYPE (tem)),
6561
op0, GEN_INT (bitsize), GEN_INT (bitpos));
6562
}
6563
6564
@@ -3029,18 +3045,27 @@
5726
@@ -3030,18 +3045,27 @@
6565
5727
return NULL;
6566
5728
6567
5729
case WIDEN_MULT_EXPR:
6818
5980
}
6819
5981
6820
5982
/* The given edge should potentially be a fallthru edge. If that is in
6821
--- a/src/gcc/cgraph.c
6822
+++ b/src/gcc/cgraph.c
6823
@@ -2093,7 +2093,7 @@
6824
AVAIL_AVAILABLE here? That would be good reason to preserve this
6825
bit. */
6826
6827
- else if (DECL_REPLACEABLE_P (node->decl) && !DECL_EXTERNAL (node->decl))
6828
+ else if (decl_replaceable_p (node->decl) && !DECL_EXTERNAL (node->decl))
6829
avail = AVAIL_OVERWRITABLE;
6830
else avail = AVAIL_AVAILABLE;
6831
6832
5983
--- a/src/gcc/combine.c
6833
5984
+++ b/src/gcc/combine.c
6834
5985
@@ -392,8 +392,8 @@
6860
6011
/* If the set in I2 needs to be kept around, we must make a copy of
6861
6012
PATTERN (I2), so that when we substitute I1SRC for I1DEST in
6862
6013
PATTERN (I2), we are only substituting for the original I1DEST, not into
6863
@@ -2951,12 +2962,12 @@
6014
@@ -2928,7 +2939,7 @@
6015
/* It is possible that the source of I2 or I1 may be performing
6016
an unneeded operation, such as a ZERO_EXTEND of something
6017
that is known to have the high part zero. Handle that case
6018
- by letting subst look at the innermost one of them.
6019
+ by letting subst look at the inner insns.
6020
6021
Another way to do this would be to have a function that tries
6022
to simplify a single insn instead of merging two or more
6023
@@ -2951,13 +2962,11 @@
6864
6024
if (i1)
6865
6025
{
6866
6026
subst_low_luid = DF_INSN_LUID (i1);
6867
6027
- i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
6028
- }
6029
- else
6030
- {
6031
- subst_low_luid = DF_INSN_LUID (i2);
6032
- i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
6868
6033
+ i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
6869
6034
}
6870
else
6871
{
6872
subst_low_luid = DF_INSN_LUID (i2);
6873
- i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
6874
+ i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
6875
}
6035
+
6036
+ subst_low_luid = DF_INSN_LUID (i2);
6037
+ i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
6876
6038
}
6877
6039
6878
@@ -2967,7 +2978,7 @@
6040
n_occurrences = 0; /* `subst' counts here */
6041
@@ -2967,7 +2976,7 @@
6879
6042
to avoid self-referential rtl. */
6880
6043
6881
6044
subst_low_luid = DF_INSN_LUID (i2);
6884
6047
! i1_feeds_i3 && i1dest_in_i1src);
6885
6048
substed_i2 = 1;
6886
6049
6887
@@ -2998,7 +3009,7 @@
6050
@@ -2998,7 +3007,7 @@
6888
6051
6889
6052
n_occurrences = 0;
6890
6053
subst_low_luid = DF_INSN_LUID (i1);
6893
6056
substed_i1 = 1;
6894
6057
}
6895
6058
6896
@@ -3060,7 +3071,7 @@
6059
@@ -3060,7 +3069,7 @@
6897
6060
else
6898
6061
/* See comment where i2pat is assigned. */
6899
6062
XVECEXP (newpat, 0, --total_sets)
6902
6065
}
6903
6066
}
6904
6067
6905
@@ -4612,11 +4623,13 @@
6068
@@ -4612,11 +4621,13 @@
6906
6069
6907
6070
IN_DEST is nonzero if we are processing the SET_DEST of a SET.
6908
6071
6917
6080
{
6918
6081
enum rtx_code code = GET_CODE (x);
6919
6082
enum machine_mode op0_mode = VOIDmode;
6920
@@ -4677,7 +4690,7 @@
6083
@@ -4677,7 +4688,7 @@
6921
6084
&& GET_CODE (XVECEXP (x, 0, 0)) == SET
6922
6085
&& GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
6923
6086
{
6926
6089
6927
6090
/* If this substitution failed, this whole thing fails. */
6928
6091
if (GET_CODE (new_rtx) == CLOBBER
6929
@@ -4694,7 +4707,7 @@
6092
@@ -4694,7 +4705,7 @@
6930
6093
&& GET_CODE (dest) != CC0
6931
6094
&& GET_CODE (dest) != PC)
6932
6095
{
6935
6098
6936
6099
/* If this substitution failed, this whole thing fails. */
6937
6100
if (GET_CODE (new_rtx) == CLOBBER
6938
@@ -4740,8 +4753,8 @@
6101
@@ -4740,8 +4751,8 @@
6939
6102
}
6940
6103
else
6941
6104
{
6946
6109
6947
6110
/* If this substitution failed, this whole thing
6948
6111
fails. */
6949
@@ -4818,7 +4831,9 @@
6112
@@ -4818,7 +4829,9 @@
6950
6113
&& (code == SUBREG || code == STRICT_LOW_PART
6951
6114
|| code == ZERO_EXTRACT))
6952
6115
|| code == SET)
6957
6120
6958
6121
/* If we found that we will have to reject this combination,
6959
6122
indicate that by returning the CLOBBER ourselves, rather than
6960
@@ -4875,7 +4890,7 @@
6123
@@ -4875,7 +4888,7 @@
6961
6124
/* If X is sufficiently simple, don't bother trying to do anything
6962
6125
with it. */
6963
6126
if (code != CONST_INT && code != REG && code != CLOBBER)
6966
6129
6967
6130
if (GET_CODE (x) == code)
6968
6131
break;
6969
@@ -4895,10 +4910,12 @@
6132
@@ -4895,10 +4908,12 @@
6970
6133
expression.
6971
6134
6972
6135
OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
6981
6144
{
6982
6145
enum rtx_code code = GET_CODE (x);
6983
6146
enum machine_mode mode = GET_MODE (x);
6984
@@ -4953,8 +4970,8 @@
6147
@@ -4953,8 +4968,8 @@
6985
6148
false arms to store-flag values. Be careful to use copy_rtx
6986
6149
here since true_rtx or false_rtx might share RTL with x as a
6987
6150
result of the if_then_else_cond call above. */
6992
6155
6993
6156
/* If true_rtx and false_rtx are not general_operands, an if_then_else
6994
6157
is unlikely to be simpler. */
6995
@@ -5298,7 +5315,7 @@
6158
@@ -5298,7 +5313,7 @@
6996
6159
{
6997
6160
/* Try to simplify the expression further. */
6998
6161
rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
7001
6164
7002
6165
/* If we could, great. If not, do not go ahead with the IOR
7003
6166
replacement, since PLUS appears in many special purpose
7004
@@ -5391,7 +5408,16 @@
6167
@@ -5391,7 +5406,16 @@
7005
6168
ZERO_EXTRACT is indeed appropriate, it will be placed back by
7006
6169
the call to make_compound_operation in the SET case. */
7007
6170
7019
6182
&& new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
7020
6183
&& op1 == const0_rtx
7021
6184
&& mode == GET_MODE (op0)
7022
@@ -5635,11 +5661,11 @@
6185
@@ -5635,11 +5659,11 @@
7023
6186
if (reg_mentioned_p (from, true_rtx))
7024
6187
true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
7025
6188
from, true_val),
7033
6196
7034
6197
SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
7035
6198
SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
7036
@@ -5856,11 +5882,11 @@
6199
@@ -5856,11 +5880,11 @@
7037
6200
{
7038
6201
temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
7039
6202
cond_op0, cond_op1),
7105
6268
ftree-dce
7106
6269
Common Report Var(flag_tree_dce) Optimization
7107
6270
Enable SSA dead code elimination optimization on trees
7108
--- a/src/gcc/config/alpha/host-osf.c
7109
+++ b/src/gcc/config/alpha/host-osf.c
7110
@@ -0,0 +1,147 @@
7111
+/* Tru64 UNIX host-specific hook definitions.
7112
+ Copyright (C) 2011 Free Software Foundation, Inc.
7113
+
7114
+ This file is part of GCC.
7115
+
7116
+ GCC is free software; you can redistribute it and/or modify it
7117
+ under the terms of the GNU General Public License as published
7118
+ by the Free Software Foundation; either version 3, or (at your
7119
+ option) any later version.
7120
+
7121
+ GCC is distributed in the hope that it will be useful, but WITHOUT
7122
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
7123
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
7124
+ License for more details.
7125
+
7126
+ You should have received a copy of the GNU General Public License
7127
+ along with GCC; see the file COPYING3. If not see
7128
+ <http://www.gnu.org/licenses/>. */
7129
+
7130
+#include "config.h"
7131
+#include "system.h"
7132
+#include "coretypes.h"
7133
+#include <sys/mman.h>
7134
+/* Inhibit inclusion of <sys/mount.h>, unnecessary and errors out due to
7135
+ use of poisoned bcmp, bcopy. */
7136
+#define _SYS_MOUNT_H_
7137
+#include <sys/procfs.h>
7138
+#include "hosthooks.h"
7139
+#include "hosthooks-def.h"
7140
+
7141
+
7142
+#undef HOST_HOOKS_GT_PCH_GET_ADDRESS
7143
+#define HOST_HOOKS_GT_PCH_GET_ADDRESS osf_gt_pch_get_address
7144
+#undef HOST_HOOKS_GT_PCH_USE_ADDRESS
7145
+#define HOST_HOOKS_GT_PCH_USE_ADDRESS osf_gt_pch_use_address
7146
+
7147
+/* The mmap ADDR parameter may be ignored without MAP_FIXED set. Before we
7148
+ give up, check existing mappings with ioctl(PIOCMAP) to see if the space
7149
+ is really free. */
7150
+
7151
+static void *
7152
+mmap_fixed (void *addr, size_t len, int prot, int flags, int fd, off_t off)
7153
+{
7154
+ void *base;
7155
+
7156
+ base = mmap ((caddr_t) addr, len, prot, flags, fd, off);
7157
+
7158
+ if (base != addr)
7159
+ {
7160
+ /* PID_MAX is SHRT_MAX on Tru64 UNIX V4.0, but INT_MAX on V5.1.
7161
+ Allow for both. "/proc/" + INT_MAX + '\0'. */
7162
+ char pname[6+10+1];
7163
+ int procfd, nmap;
7164
+ prmap_t *pmap;
7165
+ int i, overlap = 0;
7166
+
7167
+ if (base != (void *) MAP_FAILED)
7168
+ munmap ((caddr_t) base, len);
7169
+
7170
+ /* Check if there's any mapping overlapping [addr, addr+len). */
7171
+
7172
+ snprintf (pname, sizeof (pname), "/proc/%d", getpid ());
7173
+ procfd = open (pname, O_RDONLY);
7174
+ if (procfd == -1)
7175
+ return ((void *) MAP_FAILED);
7176
+ if (ioctl (procfd, PIOCNMAP, &nmap) == -1)
7177
+ return ((void *) MAP_FAILED);
7178
+ pmap = (prmap_t *) xmalloc (sizeof (*pmap) * (nmap+1));
7179
+ if (ioctl (procfd, PIOCMAP, pmap) == -1)
7180
+ return ((void *) MAP_FAILED);
7181
+
7182
+ /* It seems like pmap[] is sorted by address, but can we rely on
7183
+ that? */
7184
+ for (i = 0; i < nmap; i++)
7185
+ {
7186
+ uintptr_t map_start = (uintptr_t) pmap[i].pr_vaddr;
7187
+ uintptr_t map_end = map_start + pmap[i].pr_size;
7188
+
7189
+ if ((uintptr_t) addr < map_end
7190
+ && (uintptr_t) addr+len > map_start)
7191
+ {
7192
+ overlap = 1;
7193
+ break;
7194
+ }
7195
+ }
7196
+ free (pmap);
7197
+ close (procfd);
7198
+
7199
+ if (!overlap)
7200
+ base = mmap ((caddr_t) addr, len, prot, flags | MAP_FIXED, fd, off);
7201
+ else
7202
+ base = mmap ((caddr_t) addr, len, prot, flags, fd, off);
7203
+ }
7204
+
7205
+ return base;
7206
+}
7207
+
7208
+/* For various ports, try to guess a fixed spot in the vm space that's
7209
+ probably free. Take the middle between start of text segment and
7210
+ dynamic loader space. See <sys/machine/addrconf.h> and Tru64 UNIX
7211
+ Assembly Language Programmer's Guide, p.6-18, Figure 6-3: Default Layout
7212
+ of Memory (User Program View). */
7213
+#define TRY_EMPTY_VM_SPACE 0x20050000000
7214
+
7215
+/* Determine a location where we might be able to reliably allocate
7216
+ SIZE bytes. FD is the PCH file, though we should return with the
7217
+ file unmapped. */
7218
+
7219
+static void *
7220
+osf_gt_pch_get_address (size_t size, int fd)
7221
+{
7222
+ void *addr;
7223
+
7224
+ addr = mmap_fixed ((caddr_t) TRY_EMPTY_VM_SPACE, size,
7225
+ PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0);
7226
+
7227
+ /* If we failed the map, that means there's *no* free space. */
7228
+ if (addr == (void *) MAP_FAILED)
7229
+ return NULL;
7230
+ /* Unmap the area before returning. */
7231
+ munmap ((caddr_t) addr, size);
7232
+
7233
+ return addr;
7234
+}
7235
+
7236
+/* Map SIZE bytes of FD+OFFSET at BASE. Return 1 if we succeeded at
7237
+ mapping the data at BASE, -1 if we couldn't. */
7238
+
7239
+static int
7240
+osf_gt_pch_use_address (void *base, size_t size, int fd, size_t offset)
7241
+{
7242
+ void *addr;
7243
+
7244
+ /* We're called with size == 0 if we're not planning to load a PCH
7245
+ file at all. This allows the hook to free any static space that
7246
+ we might have allocated at link time. */
7247
+ if (size == 0)
7248
+ return -1;
7249
+
7250
+ addr = mmap_fixed ((caddr_t) base, size,
7251
+ PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, offset);
7252
+
7253
+ return addr == base ? 1 : -1;
7254
+}
7255
+
7256
+
7257
+const struct host_hooks host_hooks = HOST_HOOKS_INITIALIZER;
7258
6271
--- a/src/gcc/config/alpha/linux-elf.h
7259
6272
+++ b/src/gcc/config/alpha/linux-elf.h
7260
6273
@@ -29,10 +29,12 @@
7273
6286
#endif
7274
6287
#define LINUX_DYNAMIC_LINKER \
7275
6288
CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER)
7276
--- a/src/gcc/config/alpha/x-osf
7277
+++ b/src/gcc/config/alpha/x-osf
7278
@@ -0,0 +1,4 @@
7279
+host-osf.o : $(srcdir)/config/alpha/host-osf.c $(CONFIG_H) $(SYSTEM_H) \
7280
+ coretypes.h hosthooks.h hosthooks-def.h $(HOOKS_H)
7281
+ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
7282
+ $(srcdir)/config/alpha/host-osf.c
7283
6289
--- a/src/gcc/config/arm/aout.h
7284
6290
+++ b/src/gcc/config/arm/aout.h
7285
6291
@@ -163,31 +163,45 @@
7783
6789
extern int legitimate_pic_operand_p (rtx);
7784
6790
extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx);
7785
6791
extern rtx legitimize_tls_address (rtx, rtx);
7786
@@ -88,6 +88,8 @@
6792
@@ -81,13 +81,14 @@
6793
extern enum reg_class coproc_secondary_reload_class (enum machine_mode, rtx,
6794
bool);
6795
extern bool arm_tls_referenced_p (rtx);
6796
-extern bool arm_cannot_force_const_mem (rtx);
6797
6798
extern int cirrus_memory_offset (rtx);
6799
extern int arm_coproc_mem_operand (rtx, bool);
7787
6800
extern int neon_vector_mem_operand (rtx, int);
7788
6801
extern int neon_struct_mem_operand (rtx);
7789
6802
extern int arm_no_early_store_addr_dep (rtx, rtx);
7792
6805
extern int arm_no_early_alu_shift_dep (rtx, rtx);
7793
6806
extern int arm_no_early_alu_shift_value_dep (rtx, rtx);
7794
6807
extern int arm_no_early_mul_dep (rtx, rtx);
7795
@@ -98,14 +100,11 @@
6808
@@ -98,14 +99,11 @@
7796
6809
extern int label_mentioned_p (rtx);
7797
6810
extern RTX_CODE minmax_code (rtx);
7798
6811
extern int adjacent_mem_locations (rtx, rtx);
7812
6825
extern int arm_gen_movmemqi (rtx *);
7813
6826
extern enum machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx);
7814
6827
extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx,
7815
@@ -116,6 +115,7 @@
6828
@@ -116,6 +114,7 @@
7816
6829
extern void arm_reload_out_hi (rtx *);
7817
6830
extern int arm_const_double_inline_cost (rtx);
7818
6831
extern bool arm_const_double_by_parts (rtx);
7820
6833
extern const char *fp_immediate_constant (rtx);
7821
6834
extern void arm_emit_call_insn (rtx, rtx);
7822
6835
extern const char *output_call (rtx *);
7823
@@ -131,10 +131,11 @@
6836
@@ -131,10 +130,11 @@
7824
6837
extern const char *output_move_vfp (rtx *operands);
7825
6838
extern const char *output_move_neon (rtx *operands);
7826
6839
extern int arm_attr_length_move_neon (rtx);
7833
6846
extern void arm_poke_function_name (FILE *, const char *);
7834
6847
extern void arm_print_operand (FILE *, rtx, int);
7835
6848
extern void arm_print_operand_address (FILE *, rtx);
7836
@@ -148,6 +149,11 @@
6849
@@ -148,6 +148,11 @@
7837
6850
extern void arm_set_return_address (rtx, rtx);
7838
6851
extern int arm_eliminable_register (rtx);
7839
6852
extern const char *arm_output_shift(rtx *, int);
7845
6858
7846
6859
extern bool arm_output_addr_const_extra (FILE *, rtx);
7847
6860
7848
@@ -214,4 +220,17 @@
6861
@@ -214,4 +219,17 @@
7849
6862
7850
6863
extern void arm_order_regs_for_local_alloc (void);
7851
6864
7882
6895
7883
6896
/* Forward definitions of types. */
7884
6897
typedef struct minipool_node Mnode;
7885
@@ -141,6 +142,7 @@
6898
@@ -139,8 +140,11 @@
6899
static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
6900
tree);
7886
6901
static bool arm_have_conditional_execution (void);
6902
+static bool arm_cannot_force_const_mem (rtx);
6903
+static bool arm_legitimate_constant_p (enum machine_mode, rtx);
7887
6904
static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool);
7888
6905
static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);
7889
6906
+static bool thumb2_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);
7890
6907
static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
7891
6908
static bool arm_fastmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
7892
6909
static bool arm_xscale_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
7893
@@ -214,6 +216,7 @@
6910
@@ -214,16 +218,27 @@
7894
6911
static int arm_issue_rate (void);
7895
6912
static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
7896
6913
static bool arm_allocate_stack_slots_for_args (void);
7898
6915
static const char *arm_invalid_parameter_type (const_tree t);
7899
6916
static const char *arm_invalid_return_type (const_tree t);
7900
6917
static tree arm_promoted_type (const_tree t);
7901
@@ -224,6 +227,14 @@
6918
static tree arm_convert_to_type (tree type, tree expr);
6919
static bool arm_scalar_mode_supported_p (enum machine_mode);
6920
+static bool arm_array_mode_supported_p (enum machine_mode,
6921
+ unsigned HOST_WIDE_INT);
6922
static bool arm_frame_pointer_required (void);
6923
static bool arm_can_eliminate (const int, const int);
7902
6924
static void arm_asm_trampoline_template (FILE *);
7903
6925
static void arm_trampoline_init (rtx, tree, rtx);
7904
6926
static rtx arm_trampoline_adjust_address (rtx);
7913
6935
7914
6936
7915
6937
/* Table of machine attributes. */
7916
@@ -378,6 +389,9 @@
6938
@@ -344,6 +359,8 @@
6939
#define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
6940
#undef TARGET_VECTOR_MODE_SUPPORTED_P
6941
#define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
6942
+#undef TARGET_ARRAY_MODE_SUPPORTED_P
6943
+#define TARGET_ARRAY_MODE_SUPPORTED_P arm_array_mode_supported_p
6944
6945
#undef TARGET_MACHINE_DEPENDENT_REORG
6946
#define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
6947
@@ -378,6 +395,9 @@
7917
6948
#undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
7918
6949
#define TARGET_TRAMPOLINE_ADJUST_ADDRESS arm_trampoline_adjust_address
7919
6950
7923
6954
#undef TARGET_DEFAULT_SHORT_ENUMS
7924
6955
#define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
7925
6956
7926
@@ -507,6 +521,14 @@
6957
@@ -453,6 +473,9 @@
6958
#undef TARGET_HAVE_CONDITIONAL_EXECUTION
6959
#define TARGET_HAVE_CONDITIONAL_EXECUTION arm_have_conditional_execution
6960
6961
+#undef TARGET_LEGITIMATE_CONSTANT_P
6962
+#define TARGET_LEGITIMATE_CONSTANT_P arm_legitimate_constant_p
6963
+
6964
#undef TARGET_CANNOT_FORCE_CONST_MEM
6965
#define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem
6966
6967
@@ -507,6 +530,14 @@
7927
6968
#undef TARGET_CAN_ELIMINATE
7928
6969
#define TARGET_CAN_ELIMINATE arm_can_eliminate
7929
6970
7938
6979
struct gcc_target targetm = TARGET_INITIALIZER;
7939
6980
7940
6981
/* Obstack for minipool constant handling. */
7941
@@ -525,8 +547,8 @@
6982
@@ -525,8 +556,8 @@
7942
6983
/* The processor for which instructions should be scheduled. */
7943
6984
enum processor_type arm_tune = arm_none;
7944
6985
7949
6990
7950
6991
/* Which floating point hardware to schedule for. */
7951
6992
int arm_fpu_attr;
7952
@@ -580,9 +602,14 @@
6993
@@ -580,9 +611,14 @@
7953
6994
#define FL_NEON (1 << 20) /* Neon instructions. */
7954
6995
#define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M
7955
6996
architecture. */
7964
7005
#define FL_FOR_ARCH2 FL_NOTM
7965
7006
#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
7966
7007
#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
7967
@@ -600,7 +627,7 @@
7008
@@ -600,7 +636,7 @@
7968
7009
#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
7969
7010
#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
7970
7011
#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
7973
7014
#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
7974
7015
#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV)
7975
7016
#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV)
7976
@@ -638,6 +665,9 @@
7017
@@ -638,6 +674,9 @@
7977
7018
/* Nonzero if this chip supports the ARM 6K extensions. */
7978
7019
int arm_arch6k = 0;
7979
7020
7983
7024
/* Nonzero if instructions not present in the 'M' profile can be used. */
7984
7025
int arm_arch_notm = 0;
7985
7026
7986
@@ -666,6 +696,9 @@
7027
@@ -666,6 +705,9 @@
7987
7028
This typically means an ARM6 or ARM7 with MMU or MPU. */
7988
7029
int arm_tune_wbuf = 0;
7989
7030
7993
7034
/* Nonzero if tuning for Cortex-A9. */
7994
7035
int arm_tune_cortex_a9 = 0;
7995
7036
7996
@@ -697,10 +730,7 @@
7037
@@ -697,10 +739,7 @@
7997
7038
the next function. */
7998
7039
static int after_arm_reorg = 0;
7999
7040
8005
7046
8006
7047
/* For an explanation of these variables, see final_prescan_insn below. */
8007
7048
int arm_ccfsm_state;
8008
@@ -723,6 +753,12 @@
7049
@@ -723,6 +762,12 @@
8009
7050
"hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
8010
7051
};
8011
7052
8018
7059
#define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
8019
7060
#define streq(string1, string2) (strcmp (string1, string2) == 0)
8020
7061
8021
@@ -738,16 +774,52 @@
7062
@@ -738,16 +783,52 @@
8022
7063
enum processor_type core;
8023
7064
const char *arch;
8024
7065
const unsigned long flags;
8038
7079
+ arm_fastmul_rtx_costs,
8039
7080
+ NULL,
8040
7081
+ 1
8041
};
8042
7082
+};
7083
+
8043
7084
+const struct tune_params arm_xscale_tune =
8044
7085
+{
8045
7086
+ arm_xscale_rtx_costs,
8059
7100
+ arm_9e_rtx_costs,
8060
7101
+ cortex_a9_sched_adjust_cost,
8061
7102
+ 1
8062
+};
8063
+
7103
};
7104
8064
7105
+
8065
7106
/* Not all of these give usefully different compilation alternatives,
8066
7107
but there is no simple way of generalizing them. */
8073
7114
#include "arm-cores.def"
8074
7115
#undef ARM_CORE
8075
7116
{NULL, arm_none, NULL, 0, NULL}
8076
@@ -756,7 +828,7 @@
7117
@@ -756,7 +837,7 @@
8077
7118
static const struct processors all_architectures[] =
8078
7119
{
8079
7120
/* ARM Architectures */
8082
7123
from the core. */
8083
7124
8084
7125
{"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
8085
@@ -782,36 +854,19 @@
7126
@@ -782,36 +863,19 @@
8086
7127
{"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL},
8087
7128
{"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL},
8088
7129
{"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL},
8125
7166
8126
7167
/* The name of the preprocessor macro to define for this architecture. */
8127
7168
8128
@@ -905,6 +960,13 @@
7169
@@ -905,6 +969,13 @@
8129
7170
TLS_LE32
8130
7171
};
8131
7172
8139
7180
/* Emit an insn that's a simple single-set. Both the operands must be known
8140
7181
to be valid. */
8141
7182
inline static rtx
8142
@@ -1045,12 +1107,12 @@
7183
@@ -1045,12 +1116,12 @@
8143
7184
/* Conversions. */
8144
7185
set_conv_libfunc (trunc_optab, HFmode, SFmode,
8145
7186
(arm_fp16_format == ARM_FP16_FORMAT_IEEE
8156
7197
8157
7198
/* Arithmetic. */
8158
7199
set_optab_libfunc (add_optab, HFmode, NULL);
8159
@@ -1114,6 +1176,7 @@
8160
va_list_type);
8161
DECL_ARTIFICIAL (va_list_name) = 1;
8162
TYPE_NAME (va_list_type) = va_list_name;
8163
+ TYPE_STUB_DECL (va_list_type) = va_list_name;
8164
/* Create the __ap field. */
8165
ap_field = build_decl (BUILTINS_LOCATION,
8166
FIELD_DECL,
8167
@@ -1166,6 +1229,24 @@
7200
@@ -1167,6 +1238,24 @@
8168
7201
return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
8169
7202
}
8170
7203
8189
7222
/* Implement TARGET_HANDLE_OPTION. */
8190
7223
8191
7224
static bool
8192
@@ -1174,11 +1255,11 @@
7225
@@ -1175,11 +1264,11 @@
8193
7226
switch (code)
8194
7227
{
8195
7228
case OPT_march_:
8203
7236
return true;
8204
7237
8205
7238
case OPT_mhard_float:
8206
@@ -1190,7 +1271,7 @@
7239
@@ -1191,7 +1280,7 @@
8207
7240
return true;
8208
7241
8209
7242
case OPT_mtune_:
8212
7245
return true;
8213
7246
8214
7247
default:
8215
@@ -1290,88 +1371,52 @@
7248
@@ -1291,88 +1380,52 @@
8216
7249
arm_override_options (void)
8217
7250
{
8218
7251
unsigned i;
8329
7362
insn_flags = sel->flags;
8330
7363
8331
7364
/* Now check to see if the user has specified some command line
8332
@@ -1432,19 +1477,31 @@
7365
@@ -1433,19 +1486,31 @@
8333
7366
sel = best_fit;
8334
7367
}
8335
7368
8349
7382
+ /* The selected cpu may be an architecture, so lookup tuning by core ID. */
8350
7383
+ if (!arm_selected_tune)
8351
7384
+ arm_selected_tune = &all_cores[arm_selected_cpu->core];
8352
8353
- tune_flags = all_cores[(int)arm_tune].flags;
7385
+
8354
7386
+ sprintf (arm_arch_name, "__ARM_ARCH_%s__", arm_selected_cpu->arch);
8355
7387
+ insn_flags = arm_selected_cpu->flags;
8356
+
7388
7389
- tune_flags = all_cores[(int)arm_tune].flags;
8357
7390
+ arm_tune = arm_selected_tune->core;
8358
7391
+ tune_flags = arm_selected_tune->flags;
8359
7392
+ current_tune = arm_selected_tune->tune;
8370
7403
8371
7404
if (target_fp16_format_name)
8372
7405
{
8373
@@ -1555,6 +1612,7 @@
7406
@@ -1556,6 +1621,7 @@
8374
7407
arm_arch6 = (insn_flags & FL_ARCH6) != 0;
8375
7408
arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
8376
7409
arm_arch_notm = (insn_flags & FL_NOTM) != 0;
8378
7411
arm_arch7em = (insn_flags & FL_ARCH7EM) != 0;
8379
7412
arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
8380
7413
arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
8381
@@ -1567,6 +1625,7 @@
7414
@@ -1568,6 +1634,7 @@
8382
7415
arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
8383
7416
arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
8384
7417
arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
8386
7419
arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
8387
7420
8388
7421
/* If we are not using the default (ARM mode) section anchor offset
8389
@@ -1827,12 +1886,16 @@
7422
@@ -1828,12 +1895,16 @@
8390
7423
/* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */
8391
7424
if (fix_cm3_ldrd == 2)
8392
7425
{
8404
7437
if (TARGET_THUMB1 && flag_schedule_insns)
8405
7438
{
8406
7439
/* Don't warn since it's on by default in -O2. */
8407
@@ -1841,30 +1904,21 @@
7440
@@ -1842,30 +1913,21 @@
8408
7441
8409
7442
if (optimize_size)
8410
7443
{
8440
7473
}
8441
7474
8442
7475
/* Hot/Cold partitioning is not currently supported, since we can't
8443
@@ -1877,8 +1931,28 @@
7476
@@ -1878,8 +1940,28 @@
8444
7477
flag_reorder_blocks = 1;
8445
7478
}
8446
7479
8469
7502
}
8470
7503
8471
7504
static void
8472
@@ -2008,6 +2082,14 @@
7505
@@ -2009,6 +2091,14 @@
8473
7506
return !IS_NAKED (arm_current_func_type ());
8474
7507
}
8475
7508
8484
7517
8485
7518
/* Output assembler code for a block containing the constant parts
8486
7519
of a trampoline, leaving space for the variable parts.
8487
@@ -2087,6 +2169,18 @@
7520
@@ -2088,6 +2178,18 @@
8488
7521
return addr;
8489
7522
}
8490
7523
8503
7536
/* Return 1 if it is possible to return using a single instruction.
8504
7537
If SIBLING is non-null, this is a test for a return before a sibling
8505
7538
call. SIBLING is the call insn, so we can examine its register usage. */
8506
@@ -2265,11 +2359,17 @@
7539
@@ -2266,11 +2368,17 @@
8507
7540
{
8508
7541
HOST_WIDE_INT v;
8509
7542
8522
7555
}
8523
7556
8524
7557
return FALSE;
8525
@@ -2361,7 +2461,8 @@
7558
@@ -2362,7 +2470,8 @@
8526
7559
&& !cond
8527
7560
&& (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
8528
7561
1, 0)
8532
7565
{
8533
7566
if (code == SET)
8534
7567
{
8535
@@ -3190,13 +3291,82 @@
7568
@@ -3191,13 +3300,82 @@
8536
7569
immediate value easier to load. */
8537
7570
8538
7571
enum rtx_code
8619
7652
switch (code)
8620
7653
{
8621
7654
case EQ:
8622
@@ -3345,6 +3515,28 @@
7655
@@ -3346,6 +3524,28 @@
8623
7656
convert_optab_libfunc (sfix_optab, DImode, SFmode));
8624
7657
add_libcall (libcall_htab,
8625
7658
convert_optab_libfunc (ufix_optab, DImode, SFmode));
8648
7681
}
8649
7682
8650
7683
return libcall && htab_find (libcall_htab, libcall) != NULL;
8651
@@ -3838,7 +4030,18 @@
7684
@@ -3839,7 +4039,18 @@
8652
7685
use_vfp_abi (enum arm_pcs pcs_variant, bool is_double)
8653
7686
{
8654
7687
if (pcs_variant == ARM_PCS_AAPCS_VFP)
8668
7701
8669
7702
if (pcs_variant != ARM_PCS_AAPCS_LOCAL)
8670
7703
return false;
8671
@@ -4298,6 +4501,31 @@
7704
@@ -4299,6 +4510,31 @@
8672
7705
if (arm_libcall_uses_aapcs_base (libname))
8673
7706
pcum->pcs_variant = ARM_PCS_AAPCS;
8674
7707
8700
7733
pcum->aapcs_ncrn = pcum->aapcs_next_ncrn = 0;
8701
7734
pcum->aapcs_reg = NULL_RTX;
8702
7735
pcum->aapcs_partial = 0;
8703
@@ -4778,8 +5006,8 @@
7736
@@ -4779,8 +5015,8 @@
8704
7737
return false;
8705
7738
8706
7739
/* Never tailcall something for which we have no decl, or if we
8711
7744
return false;
8712
7745
8713
7746
/* The PIC register is live on entry to VxWorks PLT entries, so we
8714
@@ -4870,7 +5098,7 @@
7747
@@ -4871,7 +5107,7 @@
8715
7748
}
8716
7749
else
8717
7750
{
8720
7753
8721
7754
if (!cfun->machine->pic_reg)
8722
7755
cfun->machine->pic_reg = gen_reg_rtx (Pmode);
8723
@@ -4887,6 +5115,11 @@
7756
@@ -4888,6 +5124,11 @@
8724
7757
8725
7758
seq = get_insns ();
8726
7759
end_sequence ();
8732
7765
/* We can be called during expansion of PHI nodes, where
8733
7766
we can't yet emit instructions directly in the final
8734
7767
insn stream. Queue the insns on the entry edge, they will
8735
@@ -4903,31 +5136,14 @@
7768
@@ -4904,31 +5145,14 @@
8736
7769
if (GET_CODE (orig) == SYMBOL_REF
8737
7770
|| GET_CODE (orig) == LABEL_REF)
8738
7771
{
8764
7797
/* VxWorks does not impose a fixed gap between segments; the run-time
8765
7798
gap can be different from the object-file gap. We therefore can't
8766
7799
use GOTOFF unless we are absolutely sure that the symbol is in the
8767
@@ -4939,15 +5155,25 @@
7800
@@ -4940,15 +5164,25 @@
8768
7801
SYMBOL_REF_LOCAL_P (orig)))
8769
7802
&& NEED_GOT_RELOC
8770
7803
&& !TARGET_VXWORKS_RTP)
8783
7816
+ require_pic_register ();
8784
7817
+
8785
7818
+ pat = gen_calculate_pic_address (reg, cfun->machine->pic_reg, orig);
8786
+
7819
7820
- insn = emit_move_insn (reg, pic_ref);
8787
7821
+ /* Make the MEM as close to a constant as possible. */
8788
7822
+ mem = SET_SRC (pat);
8789
7823
+ gcc_assert (MEM_P (mem) && !MEM_VOLATILE_P (mem));
8790
7824
+ MEM_READONLY_P (mem) = 1;
8791
7825
+ MEM_NOTRAP_P (mem) = 1;
8792
8793
- insn = emit_move_insn (reg, pic_ref);
7826
+
8794
7827
+ insn = emit_insn (pat);
8795
7828
+ }
8796
7829
8797
7830
/* Put a REG_EQUAL note on this insn, so that it can be optimized
8798
7831
by loop. */
8799
@@ -5155,6 +5381,43 @@
7832
@@ -5156,6 +5390,43 @@
8800
7833
emit_use (pic_reg);
8801
7834
}
8802
7835
8840
7873
8841
7874
/* Return nonzero if X is valid as an ARM state addressing register. */
8842
7875
static int
8843
@@ -5189,6 +5452,15 @@
7876
@@ -5190,6 +5461,15 @@
8844
7877
return FALSE;
8845
7878
}
8846
7879
8856
7889
/* Return nonzero if X is a valid ARM state address operand. */
8857
7890
int
8858
7891
arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer,
8859
@@ -5246,8 +5518,9 @@
7892
@@ -5247,8 +5527,9 @@
8860
7893
rtx xop1 = XEXP (x, 1);
8861
7894
8862
7895
return ((arm_address_register_rtx_p (xop0, strict_p)
8868
7901
|| (arm_address_register_rtx_p (xop1, strict_p)
8869
7902
&& arm_legitimate_index_p (mode, xop0, outer, strict_p)));
8870
7903
}
8871
@@ -5333,7 +5606,8 @@
7904
@@ -5334,7 +5615,8 @@
8872
7905
rtx xop1 = XEXP (x, 1);
8873
7906
8874
7907
return ((arm_address_register_rtx_p (xop0, strict_p)
8878
7911
|| (arm_address_register_rtx_p (xop1, strict_p)
8879
7912
&& thumb2_legitimate_index_p (mode, xop0, strict_p)));
8880
7913
}
8881
@@ -5367,13 +5641,25 @@
7914
@@ -5368,13 +5650,25 @@
8882
7915
&& INTVAL (index) > -1024
8883
7916
&& (INTVAL (index) & 3) == 0);
8884
7917
8906
7939
if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
8907
7940
return (code == CONST_INT
8908
7941
&& INTVAL (index) < 1024
8909
@@ -5487,13 +5773,25 @@
7942
@@ -5488,13 +5782,25 @@
8910
7943
&& (INTVAL (index) & 3) == 0);
8911
7944
}
8912
7945
8934
7967
if (arm_address_register_rtx_p (index, strict_p)
8935
7968
&& (GET_MODE_SIZE (mode) <= 4))
8936
7969
return 1;
8937
@@ -5636,7 +5934,8 @@
7970
@@ -5637,7 +5943,8 @@
8938
7971
&& XEXP (x, 0) != frame_pointer_rtx
8939
7972
&& XEXP (x, 1) != frame_pointer_rtx
8940
7973
&& thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
8944
7977
return 1;
8945
7978
8946
7979
/* REG+const has 5-7 bit offset for non-SP registers. */
8947
@@ -6179,6 +6478,7 @@
7980
@@ -6149,9 +6456,47 @@
7981
return for_each_rtx (&x, arm_tls_operand_p_1, NULL);
7982
}
7983
7984
+/* Implement TARGET_LEGITIMATE_CONSTANT_P.
7985
+
7986
+ On the ARM, allow any integer (invalid ones are removed later by insn
7987
+ patterns), nice doubles and symbol_refs which refer to the function's
7988
+ constant pool XXX.
7989
+
7990
+ When generating pic allow anything. */
7991
+
7992
+static bool
7993
+arm_legitimate_constant_p_1 (enum machine_mode mode, rtx x)
7994
+{
7995
+ /* At present, we have no support for Neon structure constants, so forbid
7996
+ them here. It might be possible to handle simple cases like 0 and -1
7997
+ in future. */
7998
+ if (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))
7999
+ return false;
8000
+
8001
+ return flag_pic || !label_mentioned_p (x);
8002
+}
8003
+
8004
+static bool
8005
+thumb_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
8006
+{
8007
+ return (GET_CODE (x) == CONST_INT
8008
+ || GET_CODE (x) == CONST_DOUBLE
8009
+ || CONSTANT_ADDRESS_P (x)
8010
+ || flag_pic);
8011
+}
8012
+
8013
+static bool
8014
+arm_legitimate_constant_p (enum machine_mode mode, rtx x)
8015
+{
8016
+ return (!arm_cannot_force_const_mem (x)
8017
+ && (TARGET_32BIT
8018
+ ? arm_legitimate_constant_p_1 (mode, x)
8019
+ : thumb_legitimate_constant_p (mode, x)));
8020
+}
8021
+
8022
/* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
8023
8024
-bool
8025
+static bool
8026
arm_cannot_force_const_mem (rtx x)
8027
{
8028
rtx base, offset;
8029
@@ -6180,6 +6525,7 @@
8948
8030
thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
8949
8031
{
8950
8032
enum machine_mode mode = GET_MODE (x);
8952
8034
8953
8035
switch (code)
8954
8036
{
8955
@@ -6215,12 +6515,16 @@
8037
@@ -6216,12 +6562,16 @@
8956
8038
8957
8039
case CONST_INT:
8958
8040
if (outer == SET)
8975
8057
}
8976
8058
else if ((outer == PLUS || outer == COMPARE)
8977
8059
&& INTVAL (x) < 256 && INTVAL (x) > -256)
8978
@@ -6277,24 +6581,20 @@
8060
@@ -6278,24 +6628,20 @@
8979
8061
return 14;
8980
8062
return 2;
8981
8063
9011
8093
9012
8094
default:
9013
8095
return 99;
9014
@@ -6364,23 +6664,6 @@
8096
@@ -6365,23 +6711,6 @@
9015
8097
return true;
9016
8098
9017
8099
case MINUS:
9035
8117
if (mode == DImode)
9036
8118
{
9037
8119
*total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
9038
@@ -6474,6 +6757,19 @@
8120
@@ -6475,6 +6804,19 @@
9039
8121
return true;
9040
8122
}
9041
8123
9055
8137
/* Fall through */
9056
8138
9057
8139
case PLUS:
9058
@@ -6539,12 +6835,10 @@
8140
@@ -6540,12 +6882,10 @@
9059
8141
since then they might not be moved outside of loops. As a compromise
9060
8142
we allow integration with ops that have a constant as their second
9061
8143
operand. */
9072
8154
9073
8155
if (mode == DImode)
9074
8156
{
9075
@@ -6782,44 +7076,39 @@
8157
@@ -6783,44 +7123,39 @@
9076
8158
return false;
9077
8159
9078
8160
case SIGN_EXTEND:
9140
8222
}
9141
8223
9142
8224
return false;
9143
@@ -6878,6 +7167,17 @@
8225
@@ -6879,6 +7214,17 @@
9144
8226
*total = COSTS_N_INSNS (4);
9145
8227
return true;
9146
8228
9158
8240
default:
9159
8241
*total = COSTS_N_INSNS (4);
9160
8242
return false;
9161
@@ -6905,6 +7205,12 @@
8243
@@ -6906,6 +7252,12 @@
9162
8244
a single register, otherwise it costs one insn per word. */
9163
8245
if (REG_P (XEXP (x, 0)))
9164
8246
*total = COSTS_N_INSNS (1);
9171
8253
else
9172
8254
*total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
9173
8255
return true;
9174
@@ -7052,41 +7358,8 @@
8256
@@ -7053,41 +7405,8 @@
9175
8257
return false;
9176
8258
9177
8259
case SIGN_EXTEND:
9214
8296
9215
8297
case CONST_INT:
9216
8298
if (const_ok_for_arm (INTVAL (x)))
9217
@@ -7118,10 +7391,21 @@
8299
@@ -7119,6 +7438,17 @@
9218
8300
*total = COSTS_N_INSNS (4);
9219
8301
return true;
9220
8302
9221
- case HIGH:
9222
- case LO_SUM:
9223
- /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the
9224
- cost of these slightly. */
9225
8303
+ case CONST_VECTOR:
9226
8304
+ if (TARGET_NEON
9227
8305
+ && TARGET_HARD_FLOAT
9233
8311
+ *total = COSTS_N_INSNS (4);
9234
8312
+ return true;
9235
8313
+
9236
+ case HIGH:
9237
+ case LO_SUM:
9238
+ /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the
9239
+ cost of these slightly. */
9240
*total = COSTS_N_INSNS (1) + 1;
9241
return true;
9242
9243
@@ -7134,18 +7418,387 @@
8314
case HIGH:
8315
case LO_SUM:
8316
/* We prefer constant pool entries to MOVW/MOVT pairs, so bump the
8317
@@ -7135,18 +7465,387 @@
9244
8318
}
9245
8319
}
9246
8320
9633
8707
}
9634
8708
9635
8709
/* RTX costs for cores with a slow MUL implementation. Thumb-2 is not
9636
@@ -7290,7 +7943,8 @@
8710
@@ -7291,7 +7990,8 @@
9637
8711
so it can be ignored. */
9638
8712
9639
8713
static bool
9643
8717
{
9644
8718
enum machine_mode mode = GET_MODE (x);
9645
8719
9646
@@ -7491,15 +8145,13 @@
8720
@@ -7492,15 +8192,13 @@
9647
8721
return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
9648
8722
}
9649
8723
9663
8737
&& recog_memoized (insn) >= 0
9664
8738
&& recog_memoized (dep) >= 0)
9665
8739
{
9666
@@ -7533,10 +8185,106 @@
8740
@@ -7534,10 +8232,106 @@
9667
8741
9668
8742
if (reg_overlap_mentioned_p (recog_data.operand[opno],
9669
8743
shifted_operand))
9771
8845
9772
8846
/* XXX This is not strictly true for the FPA. */
9773
8847
if (REG_NOTE_KIND (link) == REG_DEP_ANTI
9774
@@ -7559,7 +8307,8 @@
8848
@@ -7560,7 +8354,8 @@
9775
8849
constant pool are cached, and that others will miss. This is a
9776
8850
hack. */
9777
8851
9781
8855
|| reg_mentioned_p (stack_pointer_rtx, src_mem)
9782
8856
|| reg_mentioned_p (frame_pointer_rtx, src_mem)
9783
8857
|| reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
9784
@@ -7774,11 +8523,14 @@
8858
@@ -7775,11 +8570,14 @@
9785
8859
vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd
9786
8860
eeeeeeee ffffffff gggggggg hhhhhhhh
9787
8861
vmov f32 18 aBbbbbbc defgh000 00000000 00000000
9796
8870
Variants 0-5 (inclusive) may also be used as immediates for the second
9797
8871
operand of VORR/VBIC instructions.
9798
8872
9799
@@ -7821,7 +8573,7 @@
8873
@@ -7822,7 +8620,7 @@
9800
8874
rtx el0 = CONST_VECTOR_ELT (op, 0);
9801
8875
REAL_VALUE_TYPE r0;
9802
8876
9805
8879
return -1;
9806
8880
9807
8881
REAL_VALUE_FROM_CONST_DOUBLE (r0, el0);
9808
@@ -7843,7 +8595,10 @@
8882
@@ -7844,7 +8642,10 @@
9809
8883
if (elementwidth)
9810
8884
*elementwidth = 0;
9811
8885
9817
8891
}
9818
8892
9819
8893
/* Splat vector constant out into a byte vector. */
9820
@@ -8110,8 +8865,7 @@
8894
@@ -8111,8 +8912,7 @@
9821
8895
load. */
9822
8896
9823
8897
x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0));
9827
8901
}
9828
8902
9829
8903
/* Generate code to load VALS, which is a PARALLEL containing only
9830
@@ -8207,8 +8961,7 @@
8904
@@ -8208,8 +9008,7 @@
9831
8905
{
9832
8906
x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0));
9833
8907
emit_insn (gen_rtx_SET (VOIDmode, target,
9837
8911
return;
9838
8912
}
9839
8913
9840
@@ -8217,7 +8970,7 @@
8914
@@ -8218,7 +9017,7 @@
9841
8915
if (n_var == 1)
9842
8916
{
9843
8917
rtx copy = copy_rtx (vals);
9846
8920
9847
8921
/* Load constant part of vector, substitute neighboring value for
9848
8922
varying element. */
9849
@@ -8226,9 +8979,38 @@
8923
@@ -8227,9 +9026,38 @@
9850
8924
9851
8925
/* Insert variable. */
9852
8926
x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, one_var));
9888
8962
return;
9889
8963
}
9890
8964
9891
@@ -8436,7 +9218,8 @@
8965
@@ -8437,7 +9265,8 @@
9892
8966
return arm_address_register_rtx_p (ind, 0);
9893
8967
9894
8968
/* Allow post-increment with Neon registers. */
9898
8972
return arm_address_register_rtx_p (XEXP (ind, 0), 0);
9899
8973
9900
8974
/* FIXME: vld1 allows register post-modify. */
9901
@@ -8520,11 +9303,14 @@
8975
@@ -8521,11 +9350,14 @@
9902
8976
return GENERAL_REGS;
9903
8977
}
9904
8978
9905
8979
+ /* The neon move patterns handle all legitimate vector and struct
9906
8980
+ addresses. */
9907
8981
if (TARGET_NEON
9908
+ && MEM_P (x)
8982
+ && (MEM_P (x) || GET_CODE (x) == CONST_VECTOR)
9909
8983
&& (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
9910
8984
- || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
9911
8985
- && neon_vector_mem_operand (x, 0))
9916
8990
9917
8991
if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode))
9918
8992
return NO_REGS;
9919
@@ -8903,21 +9689,155 @@
8993
@@ -8904,21 +9736,155 @@
9920
8994
return 0;
9921
8995
}
9922
8996
10044
9118
+ }
10045
9119
+ return true;
10046
9120
+}
10047
+
9121
9122
- memset (order, 0, 4 * sizeof (int));
10048
9123
+/* Used to determine in a peephole whether a sequence of load
10049
9124
+ instructions can be changed into a load-multiple instruction.
10050
9125
+ NOPS is the number of separate load instructions we are examining. The
10070
9145
+ rtx base_reg_rtx = NULL;
10071
9146
+ int base_reg = -1;
10072
9147
+ int i, ldm_case;
10073
10074
- memset (order, 0, 4 * sizeof (int));
9148
+
10075
9149
+ if (low_irq_latency)
10076
9150
+ return 0;
10077
9151
+
10083
9157
10084
9158
/* Loop over the operands and check that the memory references are
10085
9159
suitable (i.e. immediate offsets from the same base register). At
10086
@@ -8955,32 +9875,30 @@
10087
if (i == 0)
10088
{
10089
base_reg = REGNO (reg);
9160
@@ -8948,206 +9914,130 @@
9161
|| (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
9162
&& ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
9163
== REG)
9164
- || (GET_CODE (reg) == SUBREG
9165
- && GET_CODE (reg = SUBREG_REG (reg)) == REG))
9166
- && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
9167
- == CONST_INT)))
9168
- {
9169
- if (i == 0)
9170
- {
9171
- base_reg = REGNO (reg);
10090
9172
- unsorted_regs[0] = (GET_CODE (operands[i]) == REG
10091
9173
- ? REGNO (operands[i])
10092
9174
- : REGNO (SUBREG_REG (operands[i])));
10096
9178
- {
10097
9179
- if (base_reg != (int) REGNO (reg))
10098
9180
- /* Not addressed from the same base register. */
10099
+ base_reg_rtx = reg;
10100
+ if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM)
10101
return 0;
9181
- return 0;
10102
9182
-
10103
9183
- unsorted_regs[i] = (GET_CODE (operands[i]) == REG
10104
9184
- ? REGNO (operands[i])
10105
9185
- : REGNO (SUBREG_REG (operands[i])));
10106
9186
- if (unsorted_regs[i] < unsorted_regs[order[0]])
10107
9187
- order[0] = i;
10108
}
10109
+ else if (base_reg != (int) REGNO (reg))
10110
+ /* Not addressed from the same base register. */
10111
+ return 0;
10112
+
10113
+ unsorted_regs[i] = (GET_CODE (operands[i]) == REG
10114
+ ? REGNO (operands[i])
10115
+ : REGNO (SUBREG_REG (operands[i])));
10116
10117
/* If it isn't an integer register, or if it overwrites the
10118
base register but isn't the last insn in the list, then
10119
we can't do this. */
9188
- }
9189
-
9190
- /* If it isn't an integer register, or if it overwrites the
9191
- base register but isn't the last insn in the list, then
9192
- we can't do this. */
10120
9193
- if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
10121
+ if (unsorted_regs[i] < 0
10122
+ || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM)
10123
+ || unsorted_regs[i] > 14
10124
|| (i != nops - 1 && unsorted_regs[i] == base_reg))
10125
return 0;
10126
10127
unsorted_offsets[i] = INTVAL (offset);
10128
+ if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]])
10129
+ order[0] = i;
10130
}
10131
else
10132
/* Not a suitable memory address. */
10133
@@ -8989,164 +9907,90 @@
10134
10135
/* All the useful information has now been extracted from the
10136
operands into unsorted_regs and unsorted_offsets; additionally,
9194
- || (i != nops - 1 && unsorted_regs[i] == base_reg))
9195
- return 0;
9196
-
9197
- unsorted_offsets[i] = INTVAL (offset);
9198
- }
9199
- else
9200
- /* Not a suitable memory address. */
9201
- return 0;
9202
- }
9203
-
9204
- /* All the useful information has now been extracted from the
9205
- operands into unsorted_regs and unsorted_offsets; additionally,
10137
9206
- order[0] has been set to the lowest numbered register in the
10138
9207
- list. Sort the registers into order, and check that the memory
10139
9208
- offsets are ascending and adjacent. */
10153
9222
- than once. */
10154
9223
- if (order[i] == order[i - 1])
10155
9224
- return 0;
10156
+ order[0] has been set to the lowest offset in the list. Sort
10157
+ the offsets into order, verifying that they are adjacent, and
10158
+ check that the register numbers are ascending. */
10159
+ if (!compute_offset_order (nops, unsorted_offsets, order,
10160
+ check_regs ? unsorted_regs : NULL))
10161
+ return 0;
10162
9225
-
10163
9226
- /* Is the memory address adjacent and ascending? */
10164
9227
- if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
10165
9228
- return 0;
10166
9229
- }
10167
+ if (saved_order)
10168
+ memcpy (saved_order, order, sizeof order);
10169
10170
if (base)
10171
{
10172
*base = base_reg;
10173
10174
for (i = 0; i < nops; i++)
9230
-
9231
- if (base)
9232
- {
9233
- *base = base_reg;
9234
-
9235
- for (i = 0; i < nops; i++)
10175
9236
- regs[i] = unsorted_regs[order[i]];
10176
+ regs[i] = unsorted_regs[check_regs ? order[i] : i];
10177
10178
*load_offset = unsorted_offsets[order[0]];
10179
}
10180
9237
-
9238
- *load_offset = unsorted_offsets[order[0]];
9239
- }
9240
-
10181
9241
- if (unsorted_offsets[order[0]] == 0)
10182
9242
- return 1; /* ldmia */
10183
9243
-
10220
9280
- only be true for the ARM8, ARM9 and StrongARM. If this ever
10221
9281
- changes, then the test below needs to be reworked. */
10222
9282
- if (nops == 2 && arm_ld_sched)
10223
+ if (TARGET_THUMB1
10224
+ && !peep2_reg_dead_p (nops, base_reg_rtx))
10225
return 0;
9283
- return 0;
9284
+ || (GET_CODE (reg) == SUBREG
9285
+ && GET_CODE (reg = SUBREG_REG (reg)) == REG))
9286
+ && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
9287
+ == CONST_INT)))
9288
+ {
9289
+ if (i == 0)
9290
+ {
9291
+ base_reg = REGNO (reg);
9292
+ base_reg_rtx = reg;
9293
+ if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM)
9294
+ return 0;
9295
+ }
9296
+ else if (base_reg != (int) REGNO (reg))
9297
+ /* Not addressed from the same base register. */
9298
+ return 0;
10226
9299
10227
9300
- /* Can't do it without setting up the offset, only do this if it takes
10228
9301
- no more than one insn. */
10229
9302
- return (const_ok_for_arm (unsorted_offsets[order[0]])
10230
9303
- || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
10231
9304
-}
10232
-
9305
+ unsorted_regs[i] = (GET_CODE (operands[i]) == REG
9306
+ ? REGNO (operands[i])
9307
+ : REGNO (SUBREG_REG (operands[i])));
9308
10233
9309
-const char *
10234
9310
-emit_ldm_seq (rtx *operands, int nops)
10235
9311
-{
10238
9314
- HOST_WIDE_INT offset;
10239
9315
- char buf[100];
10240
9316
- int i;
10241
-
9317
+ /* If it isn't an integer register, or if it overwrites the
9318
+ base register but isn't the last insn in the list, then
9319
+ we can't do this. */
9320
+ if (unsorted_regs[i] < 0
9321
+ || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM)
9322
+ || unsorted_regs[i] > 14
9323
+ || (i != nops - 1 && unsorted_regs[i] == base_reg))
9324
+ return 0;
9325
10242
9326
- switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
10243
9327
- {
10244
9328
- case 1:
10245
9329
- strcpy (buf, "ldm%(ia%)\t");
10246
9330
- break;
10247
-
9331
+ unsorted_offsets[i] = INTVAL (offset);
9332
+ if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]])
9333
+ order[0] = i;
9334
+ }
9335
+ else
9336
+ /* Not a suitable memory address. */
9337
+ return 0;
9338
+ }
9339
10248
9340
- case 2:
10249
9341
- strcpy (buf, "ldm%(ib%)\t");
10250
9342
- break;
10251
-
9343
+ /* All the useful information has now been extracted from the
9344
+ operands into unsorted_regs and unsorted_offsets; additionally,
9345
+ order[0] has been set to the lowest offset in the list. Sort
9346
+ the offsets into order, verifying that they are adjacent, and
9347
+ check that the register numbers are ascending. */
9348
+ if (!compute_offset_order (nops, unsorted_offsets, order,
9349
+ check_regs ? unsorted_regs : NULL))
9350
+ return 0;
9351
10252
9352
- case 3:
10253
9353
- strcpy (buf, "ldm%(da%)\t");
10254
9354
- break;
10255
-
9355
+ if (saved_order)
9356
+ memcpy (saved_order, order, sizeof order);
9357
10256
9358
- case 4:
10257
9359
- strcpy (buf, "ldm%(db%)\t");
10258
9360
- break;
10259
-
9361
+ if (base)
9362
+ {
9363
+ *base = base_reg;
9364
10260
9365
- case 5:
10261
9366
- if (offset >= 0)
10262
9367
- sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
10270
9375
- base_reg = regs[0];
10271
9376
- strcpy (buf, "ldm%(ia%)\t");
10272
9377
- break;
10273
-
9378
+ for (i = 0; i < nops; i++)
9379
+ regs[i] = unsorted_regs[check_regs ? order[i] : i];
9380
10274
9381
- default:
10275
9382
- gcc_unreachable ();
10276
- }
10277
-
9383
+ *load_offset = unsorted_offsets[order[0]];
9384
}
9385
10278
9386
- sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
10279
9387
- reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
10280
-
9388
+ if (TARGET_THUMB1
9389
+ && !peep2_reg_dead_p (nops, base_reg_rtx))
9390
+ return 0;
9391
10281
9392
- for (i = 1; i < nops; i++)
10282
9393
- sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
10283
9394
- reg_names[regs[i]]);
10359
9470
10360
9471
/* Loop over the operands and check that the memory references are
10361
9472
suitable (i.e. immediate offsets from the same base register). At
10362
@@ -9181,32 +10025,32 @@
9473
@@ -9182,32 +10072,32 @@
10363
9474
&& (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
10364
9475
== CONST_INT)))
10365
9476
{
10408
9519
}
10409
9520
else
10410
9521
/* Not a suitable memory address. */
10411
@@ -9215,253 +10059,450 @@
9522
@@ -9216,159 +10106,129 @@
10412
9523
10413
9524
/* All the useful information has now been extracted from the
10414
9525
operands into unsorted_regs and unsorted_offsets; additionally,
10419
9530
- for (i = 1; i < nops; i++)
10420
9531
- {
10421
9532
- int j;
10422
+ order[0] has been set to the lowest offset in the list. Sort
10423
+ the offsets into order, verifying that they are adjacent, and
10424
+ check that the register numbers are ascending. */
10425
+ if (!compute_offset_order (nops, unsorted_offsets, order,
10426
+ check_regs ? unsorted_regs : NULL))
10427
+ return 0;
10428
9533
-
10429
9534
- order[i] = order[i - 1];
10430
9535
- for (j = 0; j < nops; j++)
10431
9536
- if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
10437
9542
- than once. */
10438
9543
- if (order[i] == order[i - 1])
10439
9544
- return 0;
10440
-
9545
+ order[0] has been set to the lowest offset in the list. Sort
9546
+ the offsets into order, verifying that they are adjacent, and
9547
+ check that the register numbers are ascending. */
9548
+ if (!compute_offset_order (nops, unsorted_offsets, order,
9549
+ check_regs ? unsorted_regs : NULL))
9550
+ return 0;
9551
10441
9552
- /* Is the memory address adjacent and ascending? */
10442
9553
- if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
10443
9554
- return 0;
10460
9571
*load_offset = unsorted_offsets[order[0]];
10461
9572
}
10462
9573
9574
- if (unsorted_offsets[order[0]] == 0)
9575
- return 1; /* stmia */
9576
-
9577
- if (unsorted_offsets[order[0]] == 4)
9578
- return 2; /* stmib */
10463
9579
+ if (TARGET_THUMB1
10464
9580
+ && !peep2_reg_dead_p (nops_total, base_reg_rtx))
10465
9581
+ return 0;
10466
+
10467
if (unsorted_offsets[order[0]] == 0)
10468
- return 1; /* stmia */
9582
9583
- if (unsorted_offsets[order[nops - 1]] == 0)
9584
- return 3; /* stmda */
9585
+ if (unsorted_offsets[order[0]] == 0)
10469
9586
+ stm_case = 1; /* stmia */
10470
9587
+ else if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
10471
9588
+ stm_case = 2; /* stmib */
10476
9593
+ else
10477
9594
+ return 0;
10478
9595
10479
- if (unsorted_offsets[order[0]] == 4)
10480
- return 2; /* stmib */
9596
- if (unsorted_offsets[order[nops - 1]] == -4)
9597
- return 4; /* stmdb */
10481
9598
+ if (!multiple_operation_profitable_p (false, nops, 0))
10482
9599
+ return 0;
10483
+
9600
9601
- return 0;
10484
9602
+ return stm_case;
10485
+}
9603
}
10486
9604
+
10487
9605
+/* Routines for use in generating RTL. */
10488
9606
10489
- if (unsorted_offsets[order[nops - 1]] == 0)
10490
- return 3; /* stmda */
9607
-const char *
9608
-emit_stm_seq (rtx *operands, int nops)
10491
9609
+/* Generate a load-multiple instruction. COUNT is the number of loads in
10492
9610
+ the instruction; REGS and MEMS are arrays containing the operands.
10493
9611
+ BASEREG is the base register to be used in addressing the memory operands.
10494
9612
+ WBACK_OFFSET is nonzero if the instruction should update the base
10495
9613
+ register. */
10496
10497
- if (unsorted_offsets[order[nops - 1]] == -4)
10498
- return 4; /* stmdb */
9614
+
10499
9615
+static rtx
10500
9616
+arm_gen_load_multiple_1 (int count, int *regs, rtx *mems, rtx basereg,
10501
9617
+ HOST_WIDE_INT wback_offset)
10502
+{
9618
{
9619
- int regs[4];
9620
- int base_reg;
9621
- HOST_WIDE_INT offset;
9622
- char buf[100];
9623
- int i;
10503
9624
+ int i = 0, j;
10504
9625
+ rtx result;
10505
9626
10506
- return 0;
9627
- switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
10507
9628
+ if (low_irq_latency || !multiple_operation_profitable_p (false, count, 0))
10508
+ {
9629
{
9630
- case 1:
9631
- strcpy (buf, "stm%(ia%)\t");
9632
- break;
10509
9633
+ rtx seq;
10510
+
9634
9635
- case 2:
9636
- strcpy (buf, "stm%(ib%)\t");
9637
- break;
10511
9638
+ start_sequence ();
10512
+
9639
9640
- case 3:
9641
- strcpy (buf, "stm%(da%)\t");
9642
- break;
10513
9643
+ for (i = 0; i < count; i++)
10514
9644
+ emit_move_insn (gen_rtx_REG (SImode, regs[i]), mems[i]);
10515
+
9645
9646
- case 4:
9647
- strcpy (buf, "stm%(db%)\t");
9648
- break;
10516
9649
+ if (wback_offset != 0)
10517
9650
+ emit_move_insn (basereg, plus_constant (basereg, wback_offset));
10518
+
9651
9652
- default:
9653
- gcc_unreachable ();
9654
- }
10519
9655
+ seq = get_insns ();
10520
9656
+ end_sequence ();
10521
+
9657
9658
- sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
9659
- reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
10522
9660
+ return seq;
10523
9661
+ }
10524
+
9662
9663
- for (i = 1; i < nops; i++)
9664
- sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
9665
- reg_names[regs[i]]);
10525
9666
+ result = gen_rtx_PARALLEL (VOIDmode,
10526
9667
+ rtvec_alloc (count + (wback_offset != 0 ? 1 : 0)));
10527
9668
+ if (wback_offset != 0)
10532
9673
+ i = 1;
10533
9674
+ count++;
10534
9675
+ }
10535
+
9676
9677
- strcat (buf, "}\t%@ phole stm");
10536
9678
+ for (j = 0; i < count; i++, j++)
10537
9679
+ XVECEXP (result, 0, i)
10538
9680
+ = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regs[j]), mems[j]);
10539
+
9681
9682
- output_asm_insn (buf, operands);
9683
- return "";
10540
9684
+ return result;
10541
9685
}
9686
-
9687
-/* Routines for use in generating RTL. */
10542
9688
10543
-const char *
10544
-emit_stm_seq (rtx *operands, int nops)
9689
-rtx
9690
-arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
9691
- int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
10545
9692
+/* Generate a store-multiple instruction. COUNT is the number of stores in
10546
9693
+ the instruction; REGS and MEMS are arrays containing the operands.
10547
9694
+ BASEREG is the base register to be used in addressing the memory operands.
10552
9699
+arm_gen_store_multiple_1 (int count, int *regs, rtx *mems, rtx basereg,
10553
9700
+ HOST_WIDE_INT wback_offset)
10554
9701
{
10555
- int regs[4];
10556
- int base_reg;
10557
- HOST_WIDE_INT offset;
10558
- char buf[100];
10559
- int i;
10560
+ int i = 0, j;
10561
+ rtx result;
9702
- HOST_WIDE_INT offset = *offsetp;
9703
int i = 0, j;
9704
rtx result;
9705
- int sign = up ? 1 : -1;
9706
- rtx mem, addr;
9707
-
9708
- /* XScale has load-store double instructions, but they have stricter
9709
- alignment requirements than load-store multiple, so we cannot
9710
- use them.
9711
-
9712
- For XScale ldm requires 2 + NREGS cycles to complete and blocks
9713
- the pipeline until completion.
10562
9714
10563
- switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
9715
- NREGS CYCLES
9716
- 1 3
9717
- 2 4
9718
- 3 5
9719
- 4 6
9720
-
9721
- An ldr instruction takes 1-3 cycles, but does not block the
9722
- pipeline.
9723
-
9724
- NREGS CYCLES
9725
- 1 1-3
9726
- 2 2-6
9727
- 3 3-9
9728
- 4 4-12
9729
-
9730
- Best case ldr will always win. However, the more ldr instructions
9731
- we issue, the less likely we are to be able to schedule them well.
9732
- Using ldr instructions also increases code size.
10564
9733
+ if (GET_CODE (basereg) == PLUS)
10565
9734
+ basereg = XEXP (basereg, 0);
10566
+
9735
9736
- As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
9737
- for counts of 3 or 4 regs. */
9738
- if (arm_tune_xscale && count <= 2 && ! optimize_size)
10567
9739
+ if (low_irq_latency || !multiple_operation_profitable_p (false, count, 0))
10568
9740
{
10569
- case 1:
10570
- strcpy (buf, "stm%(ia%)\t");
10571
- break;
10572
+ rtx seq;
10573
10574
- case 2:
10575
- strcpy (buf, "stm%(ib%)\t");
10576
- break;
10577
+ start_sequence ();
10578
10579
- case 3:
10580
- strcpy (buf, "stm%(da%)\t");
10581
- break;
10582
+ for (i = 0; i < count; i++)
9741
rtx seq;
9742
9743
start_sequence ();
9744
9745
for (i = 0; i < count; i++)
9746
- {
9747
- addr = plus_constant (from, i * 4 * sign);
9748
- mem = adjust_automodify_address (basemem, SImode, addr, offset);
9749
- emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
9750
- offset += 4 * sign;
9751
- }
10583
9752
+ emit_move_insn (mems[i], gen_rtx_REG (SImode, regs[i]));
10584
9753
10585
- case 4:
10586
- strcpy (buf, "stm%(db%)\t");
10587
- break;
9754
- if (write_back)
9755
- {
9756
- emit_move_insn (from, plus_constant (from, count * 4 * sign));
9757
- *offsetp = offset;
9758
- }
10588
9759
+ if (wback_offset != 0)
10589
9760
+ emit_move_insn (basereg, plus_constant (basereg, wback_offset));
10590
9761
10591
- default:
10592
- gcc_unreachable ();
10593
+ seq = get_insns ();
10594
+ end_sequence ();
10595
+
10596
+ return seq;
9762
seq = get_insns ();
9763
end_sequence ();
9764
@@ -9377,92 +10237,319 @@
10597
9765
}
10598
9766
10599
- sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
10600
- reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
10601
+ result = gen_rtx_PARALLEL (VOIDmode,
9767
result = gen_rtx_PARALLEL (VOIDmode,
9768
- rtvec_alloc (count + (write_back ? 1 : 0)));
9769
- if (write_back)
10602
9770
+ rtvec_alloc (count + (wback_offset != 0 ? 1 : 0)));
10603
9771
+ if (wback_offset != 0)
10604
+ {
10605
+ XVECEXP (result, 0, 0)
9772
{
9773
XVECEXP (result, 0, 0)
9774
- = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign));
10606
9775
+ = gen_rtx_SET (VOIDmode, basereg,
10607
9776
+ plus_constant (basereg, wback_offset));
10608
+ i = 1;
10609
+ count++;
10610
+ }
9777
i = 1;
9778
count++;
9779
}
10611
9780
10612
- for (i = 1; i < nops; i++)
10613
- sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
10614
- reg_names[regs[i]]);
10615
+ for (j = 0; i < count; i++, j++)
9781
for (j = 0; i < count; i++, j++)
10616
9782
+ XVECEXP (result, 0, i)
10617
9783
+ = gen_rtx_SET (VOIDmode, mems[j], gen_rtx_REG (SImode, regs[j]));
10618
10619
- strcat (buf, "}\t%@ phole stm");
9784
+
10620
9785
+ return result;
10621
9786
+}
10622
10623
- output_asm_insn (buf, operands);
10624
- return "";
9787
+
10625
9788
+/* Generate either a load-multiple or a store-multiple instruction. This
10626
9789
+ function can be used in situations where we can start with a single MEM
10627
9790
+ rtx and adjust its address upwards.
10651
9814
+ basereg = XEXP (basereg, 0);
10652
9815
+
10653
9816
+ for (i = 0; i < count; i++)
10654
+ {
9817
{
9818
- addr = plus_constant (from, j * 4 * sign);
9819
- mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
9820
- XVECEXP (result, 0, i)
9821
- = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
9822
- offset += 4 * sign;
10655
9823
+ rtx addr = plus_constant (basereg, i * 4);
10656
9824
+ mems[i] = adjust_automodify_address_nv (basemem, SImode, addr, offset);
10657
9825
+ offset += 4;
10658
+ }
10659
+
10660
+ if (write_back)
10661
+ *offsetp = offset;
10662
+
9826
}
9827
9828
if (write_back)
9829
*offsetp = offset;
9830
9831
- return result;
10663
9832
+ if (is_load)
10664
9833
+ return arm_gen_load_multiple_1 (count, regs, mems, basereg,
10665
9834
+ write_back ? 4 * count : 0);
10667
9836
+ return arm_gen_store_multiple_1 (count, regs, mems, basereg,
10668
9837
+ write_back ? 4 * count : 0);
10669
9838
}
10670
-
10671
-/* Routines for use in generating RTL. */
10672
9839
10673
9840
rtx
10674
-arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
10675
- int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
9841
-arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
9842
- int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
10676
9843
+arm_gen_load_multiple (int *regs, int count, rtx basereg, int write_back,
10677
9844
+ rtx basemem, HOST_WIDE_INT *offsetp)
10678
9845
{
10684
9851
+ return arm_gen_multiple_op (TRUE, regs, count, basereg, write_back, basemem,
10685
9852
+ offsetp);
10686
9853
+}
10687
10688
- /* XScale has load-store double instructions, but they have stricter
10689
- alignment requirements than load-store multiple, so we cannot
10690
- use them.
9854
+
10691
9855
+rtx
10692
9856
+arm_gen_store_multiple (int *regs, int count, rtx basereg, int write_back,
10693
9857
+ rtx basemem, HOST_WIDE_INT *offsetp)
10695
9859
+ return arm_gen_multiple_op (FALSE, regs, count, basereg, write_back, basemem,
10696
9860
+ offsetp);
10697
9861
+}
10698
10699
- For XScale ldm requires 2 + NREGS cycles to complete and blocks
10700
- the pipeline until completion.
9862
+
10701
9863
+/* Called from a peephole2 expander to turn a sequence of loads into an
10702
9864
+ LDM instruction. OPERANDS are the operands found by the peephole matcher;
10703
9865
+ NOPS indicates how many separate loads we are trying to combine. SORT_REGS
10704
9866
+ is true if we can reorder the registers because they are used commutatively
10705
9867
+ subsequently.
10706
9868
+ Returns true iff we could generate a new instruction. */
10707
10708
- NREGS CYCLES
10709
- 1 3
10710
- 2 4
10711
- 3 5
10712
- 4 6
9869
+
10713
9870
+bool
10714
9871
+gen_ldm_seq (rtx *operands, int nops, bool sort_regs)
10715
9872
+{
10721
9878
+ int write_back = FALSE;
10722
9879
+ int ldm_case;
10723
9880
+ rtx addr;
10724
10725
- An ldr instruction takes 1-3 cycles, but does not block the
10726
- pipeline.
9881
+
10727
9882
+ ldm_case = load_multiple_sequence (operands, nops, regs, mem_order,
10728
9883
+ &base_reg, &offset, !sort_regs);
10729
10730
- NREGS CYCLES
10731
- 1 1-3
10732
- 2 2-6
10733
- 3 3-9
10734
- 4 4-12
9884
+
10735
9885
+ if (ldm_case == 0)
10736
9886
+ return false;
10737
10738
- Best case ldr will always win. However, the more ldr instructions
10739
- we issue, the less likely we are to be able to schedule them well.
10740
- Using ldr instructions also increases code size.
9887
+
10741
9888
+ if (sort_regs)
10742
9889
+ for (i = 0; i < nops - 1; i++)
10743
9890
+ for (j = i + 1; j < nops; j++)
10748
9895
+ regs[j] = t;
10749
9896
+ }
10750
9897
+ base_reg_rtx = gen_rtx_REG (Pmode, base_reg);
10751
10752
- As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
10753
- for counts of 3 or 4 regs. */
10754
- if (arm_tune_xscale && count <= 2 && ! optimize_size)
9898
+
10755
9899
+ if (TARGET_THUMB1)
10756
{
10757
- rtx seq;
10758
-
10759
- start_sequence ();
9900
+ {
10760
9901
+ gcc_assert (peep2_reg_dead_p (nops, base_reg_rtx));
10761
9902
+ gcc_assert (ldm_case == 1 || ldm_case == 5);
10762
9903
+ write_back = TRUE;
10763
9904
+ }
10764
10765
- for (i = 0; i < count; i++)
9905
+
10766
9906
+ if (ldm_case == 5)
10767
9907
+ {
10768
9908
+ rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG (SImode, regs[0]);
10769
9909
+ emit_insn (gen_addsi3 (newbase, base_reg_rtx, GEN_INT (offset)));
10770
9910
+ offset = 0;
10771
9911
+ if (!TARGET_THUMB1)
10772
{
10773
- addr = plus_constant (from, i * 4 * sign);
10774
- mem = adjust_automodify_address (basemem, SImode, addr, offset);
10775
- emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
10776
- offset += 4 * sign;
9912
+ {
10777
9913
+ base_reg = regs[0];
10778
9914
+ base_reg_rtx = newbase;
10779
}
9915
+ }
10780
9916
+ }
10781
10782
- if (write_back)
10783
- {
10784
- emit_move_insn (from, plus_constant (from, count * 4 * sign));
10785
- *offsetp = offset;
10786
- }
9917
+
10787
9918
+ for (i = 0; i < nops; i++)
10788
9919
+ {
10789
9920
+ addr = plus_constant (base_reg_rtx, offset + i * 4);
10794
9925
+ write_back ? offset + i * 4 : 0));
10795
9926
+ return true;
10796
9927
+}
10797
10798
- seq = get_insns ();
10799
- end_sequence ();
9928
+
10800
9929
+/* Called from a peephole2 expander to turn a sequence of stores into an
10801
9930
+ STM instruction. OPERANDS are the operands found by the peephole matcher;
10802
9931
+ NOPS indicates how many separate stores we are trying to combine.
10803
9932
+ Returns true iff we could generate a new instruction. */
10804
10805
- return seq;
10806
- }
9933
+
10807
9934
+bool
10808
9935
+gen_stm_seq (rtx *operands, int nops)
10809
9936
+{
10825
9952
+ return false;
10826
9953
+
10827
9954
+ base_reg_rtx = gen_rtx_REG (Pmode, base_reg);
10828
10829
- result = gen_rtx_PARALLEL (VOIDmode,
10830
- rtvec_alloc (count + (write_back ? 1 : 0)));
10831
- if (write_back)
9955
+
10832
9956
+ base_reg_dies = peep2_reg_dead_p (nops, base_reg_rtx);
10833
9957
+ if (TARGET_THUMB1)
10834
{
10835
- XVECEXP (result, 0, 0)
10836
- = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign));
10837
- i = 1;
10838
- count++;
9958
+ {
10839
9959
+ gcc_assert (base_reg_dies);
10840
9960
+ write_back = TRUE;
10841
}
10842
10843
- for (j = 0; i < count; i++, j++)
9961
+ }
9962
+
10844
9963
+ if (stm_case == 5)
10845
{
10846
- addr = plus_constant (from, j * 4 * sign);
10847
- mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
10848
- XVECEXP (result, 0, i)
10849
- = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
10850
- offset += 4 * sign;
9964
+ {
10851
9965
+ gcc_assert (base_reg_dies);
10852
9966
+ emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset)));
10853
9967
+ offset = 0;
10854
}
10855
10856
- if (write_back)
10857
- *offsetp = offset;
9968
+ }
9969
+
10858
9970
+ addr = plus_constant (base_reg_rtx, offset);
10859
10860
- return result;
9971
+
10861
9972
+ for (i = 0; i < nops; i++)
10862
9973
+ {
10863
9974
+ addr = plus_constant (base_reg_rtx, offset + i * 4);
10867
9978
+ emit_insn (arm_gen_store_multiple_1 (nops, regs, mems, base_reg_rtx,
10868
9979
+ write_back ? offset + i * 4 : 0));
10869
9980
+ return true;
10870
}
10871
10872
-rtx
10873
-arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
10874
- int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
9981
+}
9982
+
10875
9983
+/* Called from a peephole2 expander to turn a sequence of stores that are
10876
9984
+ preceded by constant loads into an STM instruction. OPERANDS are the
10877
9985
+ operands found by the peephole matcher; NOPS indicates how many
10881
9989
+
10882
9990
+bool
10883
9991
+gen_const_stm_seq (rtx *operands, int nops)
10884
{
10885
- HOST_WIDE_INT offset = *offsetp;
10886
- int i = 0, j;
10887
- rtx result;
10888
- int sign = up ? 1 : -1;
10889
- rtx mem, addr;
9992
+{
10890
9993
+ int regs[MAX_LDM_STM_OPS], sorted_regs[MAX_LDM_STM_OPS];
10891
9994
+ int reg_order[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS];
10892
9995
+ rtx reg_rtxs[MAX_LDM_STM_OPS], orig_reg_rtxs[MAX_LDM_STM_OPS];
10900
10003
+ bool base_reg_dies;
10901
10004
+ int i, j;
10902
10005
+ HARD_REG_SET allocated;
10006
+
10007
+ stm_case = store_multiple_sequence (operands, nops, 2 * nops, regs, reg_rtxs,
10008
+ mem_order, &base_reg, &offset, false);
10009
+
10010
+ if (stm_case == 0)
10011
+ return false;
10903
10012
10904
10013
- /* See arm_gen_load_multiple for discussion of
10905
10014
- the pros/cons of ldm/stm usage for XScale. */
10906
10015
- if (arm_tune_xscale && count <= 2 && ! optimize_size)
10907
10016
- {
10908
10017
- rtx seq;
10909
+ stm_case = store_multiple_sequence (operands, nops, 2 * nops, regs, reg_rtxs,
10910
+ mem_order, &base_reg, &offset, false);
10911
10912
- start_sequence ();
10913
+ if (stm_case == 0)
10914
+ return false;
10915
10916
- for (i = 0; i < count; i++)
10917
- {
10918
- addr = plus_constant (to, i * 4 * sign);
10919
- mem = adjust_automodify_address (basemem, SImode, addr, offset);
10920
- emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
10921
- offset += 4 * sign;
10922
- }
10923
10018
+ memcpy (orig_reg_rtxs, reg_rtxs, sizeof orig_reg_rtxs);
10924
10019
10925
- if (write_back)
10926
- {
10927
- emit_move_insn (to, plus_constant (to, count * 4 * sign));
10928
- *offsetp = offset;
10929
- }
10020
- start_sequence ();
10930
10021
+ /* If the same register is used more than once, try to find a free
10931
10022
+ register. */
10932
10023
+ CLEAR_HARD_REG_SET (allocated);
10945
10036
+ }
10946
10037
+ }
10947
10038
10948
- seq = get_insns ();
10949
- end_sequence ();
10039
- for (i = 0; i < count; i++)
10040
- {
10041
- addr = plus_constant (to, i * 4 * sign);
10042
- mem = adjust_automodify_address (basemem, SImode, addr, offset);
10043
- emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
10044
- offset += 4 * sign;
10045
- }
10950
10046
+ /* Compute an ordering that maps the register numbers to an ascending
10951
10047
+ sequence. */
10952
10048
+ reg_order[0] = 0;
10954
10050
+ if (regs[i] < regs[reg_order[0]])
10955
10051
+ reg_order[0] = i;
10956
10052
10957
- return seq;
10053
- if (write_back)
10054
- {
10055
- emit_move_insn (to, plus_constant (to, count * 4 * sign));
10056
- *offsetp = offset;
10057
- }
10958
10058
+ for (i = 1; i < nops; i++)
10959
10059
+ {
10960
10060
+ int this_order = reg_order[i - 1];
10964
10064
+ || regs[j] < regs[this_order]))
10965
10065
+ this_order = j;
10966
10066
+ reg_order[i] = this_order;
10967
}
10067
+ }
10968
10068
10969
- result = gen_rtx_PARALLEL (VOIDmode,
10970
- rtvec_alloc (count + (write_back ? 1 : 0)));
10971
- if (write_back)
10069
- seq = get_insns ();
10070
- end_sequence ();
10972
10071
+ /* Ensure that registers that must be live after the instruction end
10973
10072
+ up with the correct value. */
10974
10073
+ for (i = 0; i < nops; i++)
10975
{
10976
- XVECEXP (result, 0, 0)
10977
- = gen_rtx_SET (VOIDmode, to,
10978
- plus_constant (to, count * 4 * sign));
10979
- i = 1;
10980
- count++;
10074
+ {
10981
10075
+ int this_order = reg_order[i];
10982
10076
+ if ((this_order != mem_order[i]
10983
10077
+ || orig_reg_rtxs[this_order] != reg_rtxs[this_order])
10984
10078
+ && !peep2_reg_dead_p (nops * 2, orig_reg_rtxs[this_order]))
10985
10079
+ return false;
10986
}
10080
+ }
10987
10081
10988
- for (j = 0; i < count; i++, j++)
10082
- return seq;
10989
10083
+ /* Load the constants. */
10990
10084
+ for (i = 0; i < nops; i++)
10991
{
10992
- addr = plus_constant (to, j * 4 * sign);
10993
- mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
10994
- XVECEXP (result, 0, i)
10995
- = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
10996
- offset += 4 * sign;
10085
+ {
10997
10086
+ rtx op = operands[2 * nops + mem_order[i]];
10998
10087
+ sorted_regs[i] = regs[reg_order[i]];
10999
10088
+ emit_move_insn (reg_rtxs[reg_order[i]], op);
11000
10089
}
11001
10090
10091
- result = gen_rtx_PARALLEL (VOIDmode,
10092
- rtvec_alloc (count + (write_back ? 1 : 0)));
11002
10093
- if (write_back)
11003
- *offsetp = offset;
11004
10094
+ base_reg_rtx = gen_rtx_REG (Pmode, base_reg);
11005
11006
- return result;
10095
+
11007
10096
+ base_reg_dies = peep2_reg_dead_p (nops * 2, base_reg_rtx);
11008
10097
+ if (TARGET_THUMB1)
11009
+ {
10098
{
10099
- XVECEXP (result, 0, 0)
10100
- = gen_rtx_SET (VOIDmode, to,
10101
- plus_constant (to, count * 4 * sign));
10102
- i = 1;
10103
- count++;
11010
10104
+ gcc_assert (base_reg_dies);
11011
10105
+ write_back = TRUE;
11012
+ }
11013
+
10106
}
10107
10108
- for (j = 0; i < count; i++, j++)
11014
10109
+ if (stm_case == 5)
11015
+ {
10110
{
10111
- addr = plus_constant (to, j * 4 * sign);
10112
- mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
10113
- XVECEXP (result, 0, i)
10114
- = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
10115
- offset += 4 * sign;
11016
10116
+ gcc_assert (base_reg_dies);
11017
10117
+ emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset)));
11018
10118
+ offset = 0;
11019
+ }
11020
+
10119
}
10120
10121
- if (write_back)
10122
- *offsetp = offset;
11021
10123
+ addr = plus_constant (base_reg_rtx, offset);
11022
+
10124
10125
- return result;
11023
10126
+ for (i = 0; i < nops; i++)
11024
10127
+ {
11025
10128
+ addr = plus_constant (base_reg_rtx, offset + i * 4);
11032
10135
}
11033
10136
11034
10137
int
11035
@@ -9497,20 +10538,21 @@
10138
@@ -9498,20 +10585,21 @@
11036
10139
for (i = 0; in_words_to_go >= 2; i+=4)
11037
10140
{
11038
10141
if (in_words_to_go > 4)
11062
10165
(last_bytes == 0
11063
10166
? FALSE : TRUE),
11064
10167
dstbase, &dstoffset));
11065
@@ -9838,12 +10880,14 @@
10168
@@ -9839,12 +10927,14 @@
11066
10169
11067
10170
/* Alternate canonicalizations of the above. These are somewhat cleaner. */
11068
10171
if (GET_CODE (x) == AND
11077
10180
&& COMPARISON_P (XEXP (x, 0))
11078
10181
&& COMPARISON_P (XEXP (x, 1)))
11079
10182
return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
11080
@@ -9885,6 +10929,55 @@
10183
@@ -9886,6 +10976,55 @@
11081
10184
&& (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
11082
10185
return CC_Cmode;
11083
10186
11133
10236
return CCmode;
11134
10237
}
11135
10238
11136
@@ -9894,10 +10987,39 @@
10239
@@ -9895,10 +11034,39 @@
11137
10240
rtx
11138
10241
arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
11139
10242
{
11176
10279
11177
10280
return cc_reg;
11178
10281
}
11179
@@ -10433,6 +11555,7 @@
10282
@@ -10434,6 +11602,7 @@
11180
10283
11181
10284
if (GET_CODE (insn) == JUMP_INSN
11182
10285
&& JUMP_LABEL (insn) != NULL
11184
10287
&& ((table = next_real_insn (JUMP_LABEL (insn)))
11185
10288
== next_real_insn (insn))
11186
10289
&& table != NULL
11187
@@ -11032,7 +12155,10 @@
10290
@@ -11033,7 +12202,10 @@
11188
10291
gcc_assert (GET_CODE (from) != BARRIER);
11189
10292
11190
10293
/* Count the length of this insn. */
11196
10299
11197
10300
/* If there is a jump table, add its length. */
11198
10301
tmp = is_jump_table (from);
11199
@@ -11226,6 +12352,34 @@
10302
@@ -11227,6 +12399,34 @@
11200
10303
return false;
11201
10304
}
11202
10305
11231
10334
/* Scan INSN and note any of its operands that need fixing.
11232
10335
If DO_PUSHES is false we do not actually push any of the fixups
11233
10336
needed. The function returns TRUE if any fixups were needed/pushed.
11234
@@ -11299,6 +12453,60 @@
10337
@@ -11300,6 +12500,60 @@
11235
10338
return result;
11236
10339
}
11237
10340
11292
10395
/* Gcc puts the pool in the wrong place for ARM, since we can only
11293
10396
load addresses a limited distance around the pc. We do some
11294
10397
special munging to move the constant pool values to the correct
11295
@@ -11310,6 +12518,9 @@
10398
@@ -11311,6 +12565,9 @@
11296
10399
HOST_WIDE_INT address = 0;
11297
10400
Mfix * fix;
11298
10401
11302
10405
minipool_fix_head = minipool_fix_tail = NULL;
11303
10406
11304
10407
/* The first insn must always be a note, or the code below won't
11305
@@ -11344,6 +12555,8 @@
10408
@@ -11345,6 +12602,8 @@
11306
10409
insn = table;
11307
10410
}
11308
10411
}
11311
10414
}
11312
10415
11313
10416
fix = minipool_fix_head;
11314
@@ -11549,6 +12762,21 @@
10417
@@ -11550,6 +12809,21 @@
11315
10418
vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count)
11316
10419
{
11317
10420
int i;
11333
10436
11334
10437
/* Workaround ARM10 VFPr1 bug. */
11335
10438
if (count == 2 && !arm_arch6)
11336
@@ -11619,6 +12847,56 @@
10439
@@ -11620,6 +12894,56 @@
11337
10440
rtx tmp, reg;
11338
10441
int i;
11339
10442
11390
10493
/* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
11391
10494
register pairs are stored by a store multiple insn. We avoid this
11392
10495
by pushing an extra pair. */
11393
@@ -12182,13 +13460,13 @@
10496
@@ -12183,13 +13507,13 @@
11394
10497
{
11395
10498
if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
11396
10499
{
11408
10511
}
11409
10512
}
11410
10513
else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
11411
@@ -12548,6 +13826,34 @@
10514
@@ -12549,6 +13873,34 @@
11412
10515
return 4;
11413
10516
}
11414
10517
11443
10546
/* Output an ADD r, s, #n where n may be too big for one instruction.
11444
10547
If adding zero to one register, output nothing. */
11445
10548
const char *
11446
@@ -13111,7 +14417,7 @@
10549
@@ -13112,7 +14464,7 @@
11447
10550
if (count > 0)
11448
10551
{
11449
10552
/* Workaround ARM10 VFPr1 bug. */
11452
10555
count++;
11453
10556
saved += count * 8;
11454
10557
}
11455
@@ -13134,7 +14440,7 @@
10558
@@ -13135,7 +14487,7 @@
11456
10559
/* Generate a function exit sequence. If REALLY_RETURN is false, then do
11457
10560
everything bar the final return instruction. */
11458
10561
const char *
11461
10564
{
11462
10565
char conditional[10];
11463
10566
char instr[100];
11464
@@ -13172,10 +14478,15 @@
10567
@@ -13173,10 +14525,15 @@
11465
10568
11466
10569
sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
11467
10570
11480
10583
11481
10584
if (live_regs_mask)
11482
10585
{
11483
@@ -13449,6 +14760,41 @@
10586
@@ -13450,6 +14807,41 @@
11484
10587
11485
10588
}
11486
10589
11522
10625
const char *
11523
10626
arm_output_epilogue (rtx sibling)
11524
10627
{
11525
@@ -13823,22 +15169,19 @@
10628
@@ -13824,22 +15216,19 @@
11526
10629
to load use the LDR instruction - it is faster. For Thumb-2
11527
10630
always use pop and the assembler will pick the best instruction.*/
11528
10631
if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM)
11553
10656
else
11554
10657
print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0);
11555
10658
}
11556
@@ -13959,6 +15302,32 @@
10659
@@ -13960,6 +15349,32 @@
11557
10660
11558
10661
gcc_assert (num_regs && num_regs <= 16);
11559
10662
11586
10689
/* We don't record the PC in the dwarf frame information. */
11587
10690
num_dwarf_regs = num_regs;
11588
10691
if (mask & (1 << PC_REGNUM))
11589
@@ -15122,8 +16491,18 @@
10692
@@ -15123,8 +16538,18 @@
11590
10693
the value being loaded is big-wordian or little-wordian. The
11591
10694
order of the two register loads can matter however, if the address
11592
10695
of the memory location is actually held in one of the registers
11606
10709
if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
11607
10710
{
11608
10711
output_operand_lossage ("invalid operand for code '%c'", code);
11609
@@ -15134,6 +16513,18 @@
10712
@@ -15135,6 +16560,18 @@
11610
10713
return;
11611
10714
11612
10715
case 'R':
11625
10728
if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
11626
10729
{
11627
10730
output_operand_lossage ("invalid operand for code '%c'", code);
11628
@@ -15456,6 +16847,8 @@
10731
@@ -15457,6 +16894,8 @@
11629
10732
{
11630
10733
rtx addr;
11631
10734
bool postinc = FALSE;
11632
+ unsigned align, modesize, align_bits;
10735
+ unsigned align, memsize, align_bits;
11633
10736
+
11634
10737
gcc_assert (GET_CODE (x) == MEM);
11635
10738
addr = XEXP (x, 0);
11636
10739
if (GET_CODE (addr) == POST_INC)
11637
@@ -15463,12 +16856,45 @@
10740
@@ -15464,12 +16903,45 @@
11638
10741
postinc = 1;
11639
10742
addr = XEXP (addr, 0);
11640
10743
}
11645
10748
+ instruction (for some alignments) as an aid to the memory subsystem
11646
10749
+ of the target. */
11647
10750
+ align = MEM_ALIGN (x) >> 3;
11648
+ modesize = GET_MODE_SIZE (GET_MODE (x));
10751
+ memsize = INTVAL (MEM_SIZE (x));
11649
10752
+
11650
10753
+ /* Only certain alignment specifiers are supported by the hardware. */
11651
+ if (modesize == 16 && (align % 32) == 0)
10754
+ if (memsize == 16 && (align % 32) == 0)
11652
10755
+ align_bits = 256;
11653
+ else if ((modesize == 8 || modesize == 16) && (align % 16) == 0)
10756
+ else if ((memsize == 8 || memsize == 16) && (align % 16) == 0)
11654
10757
+ align_bits = 128;
11655
10758
+ else if ((align % 8) == 0)
11656
10759
+ align_bits = 64;
11658
10761
+ align_bits = 0;
11659
10762
+
11660
10763
+ if (align_bits != 0)
11661
+ asm_fprintf (stream, ", :%d", align_bits);
10764
+ asm_fprintf (stream, ":%d", align_bits);
11662
10765
+
11663
10766
+ asm_fprintf (stream, "]");
11664
10767
+
11681
10784
/* Translate an S register number into a D register number and element index. */
11682
10785
case 'y':
11683
10786
{
11684
@@ -15818,13 +17244,35 @@
11685
default: gcc_unreachable ();
11686
}
10787
@@ -15821,11 +17293,33 @@
11687
10788
11688
- case CC_Cmode:
11689
+ case CC_Cmode:
11690
+ switch (comp_code)
10789
case CC_Cmode:
10790
switch (comp_code)
10791
- {
10792
- case LTU: return ARM_CS;
10793
- case GEU: return ARM_CC;
10794
- default: gcc_unreachable ();
10795
- }
11691
10796
+ {
11692
10797
+ case LTU: return ARM_CS;
11693
10798
+ case GEU: return ARM_CC;
11707
10812
+ }
11708
10813
+
11709
10814
+ case CC_NCVmode:
11710
switch (comp_code)
11711
- {
11712
- case LTU: return ARM_CS;
11713
- case GEU: return ARM_CC;
11714
- default: gcc_unreachable ();
11715
- }
10815
+ switch (comp_code)
11716
10816
+ {
11717
10817
+ case GE: return ARM_GE;
11718
10818
+ case LT: return ARM_LT;
11723
10823
11724
10824
case CCmode:
11725
10825
switch (comp_code)
11726
@@ -15937,6 +17385,7 @@
10826
@@ -15938,6 +17432,7 @@
11727
10827
11728
10828
/* If we start with a return insn, we only succeed if we find another one. */
11729
10829
int seeking_return = 0;
11731
10831
11732
10832
/* START_INSN will hold the insn from where we start looking. This is the
11733
10833
first insn after the following code_label if REVERSE is true. */
11734
@@ -15975,7 +17424,7 @@
10834
@@ -15976,7 +17471,7 @@
11735
10835
else
11736
10836
return;
11737
10837
}
11740
10840
{
11741
10841
start_insn = next_nonnote_insn (start_insn);
11742
10842
if (GET_CODE (start_insn) == BARRIER)
11743
@@ -15986,6 +17435,7 @@
10843
@@ -15987,6 +17482,7 @@
11744
10844
{
11745
10845
reverse = TRUE;
11746
10846
seeking_return = 1;
11748
10848
}
11749
10849
else
11750
10850
return;
11751
@@ -16026,11 +17476,15 @@
10851
@@ -16027,11 +17523,15 @@
11752
10852
label = XEXP (XEXP (SET_SRC (body), 2), 0);
11753
10853
then_not_else = FALSE;
11754
10854
}
11767
10867
then_not_else = FALSE;
11768
10868
}
11769
10869
else
11770
@@ -16131,8 +17585,7 @@
10870
@@ -16132,8 +17632,7 @@
11771
10871
&& !use_return_insn (TRUE, NULL)
11772
10872
&& !optimize_size)
11773
10873
fail = TRUE;
11777
10877
{
11778
10878
arm_ccfsm_state = 2;
11779
10879
succeed = TRUE;
11780
@@ -16299,7 +17752,7 @@
10880
@@ -16300,7 +17799,7 @@
11781
10881
return mode == SImode;
11782
10882
11783
10883
if (IS_IWMMXT_REGNUM (regno))
11786
10886
}
11787
10887
11788
10888
/* We allow almost any value to be stored in the general registers.
11789
@@ -19027,6 +20480,81 @@
10889
@@ -16946,12 +18445,14 @@
10890
T_V2SI = 0x0004,
10891
T_V2SF = 0x0008,
10892
T_DI = 0x0010,
10893
+ T_DREG = 0x001F,
10894
T_V16QI = 0x0020,
10895
T_V8HI = 0x0040,
10896
T_V4SI = 0x0080,
10897
T_V4SF = 0x0100,
10898
T_V2DI = 0x0200,
10899
T_TI = 0x0400,
10900
+ T_QREG = 0x07E0,
10901
T_EI = 0x0800,
10902
T_OI = 0x1000
10903
};
10904
@@ -17597,10 +19098,9 @@
10905
if (is_load && k == 1)
10906
{
10907
/* Neon load patterns always have the memory operand
10908
- (a SImode pointer) in the operand 1 position. We
10909
- want a const pointer to the element type in that
10910
- position. */
10911
- gcc_assert (insn_data[icode].operand[k].mode == SImode);
10912
+ in the operand 1 position. */
10913
+ gcc_assert (insn_data[icode].operand[k].predicate
10914
+ == neon_struct_operand);
10915
10916
switch (1 << j)
10917
{
10918
@@ -17635,10 +19135,9 @@
10919
else if (is_store && k == 0)
10920
{
10921
/* Similarly, Neon store patterns use operand 0 as
10922
- the memory location to store to (a SImode pointer).
10923
- Use a pointer to the element type of the store in
10924
- that position. */
10925
- gcc_assert (insn_data[icode].operand[k].mode == SImode);
10926
+ the memory location to store to. */
10927
+ gcc_assert (insn_data[icode].operand[k].predicate
10928
+ == neon_struct_operand);
10929
10930
switch (1 << j)
10931
{
10932
@@ -17958,10 +19457,11 @@
10933
}
10934
10935
static enum insn_code
10936
-locate_neon_builtin_icode (int fcode, neon_itype *itype)
10937
+locate_neon_builtin_icode (int fcode, neon_itype *itype,
10938
+ enum neon_builtin_type_bits *type_bit)
10939
{
10940
neon_builtin_datum key, *found;
10941
- int idx;
10942
+ int idx, type, ntypes;
10943
10944
key.base_fcode = fcode;
10945
found = (neon_builtin_datum *)
10946
@@ -17974,20 +19474,83 @@
10947
if (itype)
10948
*itype = found->itype;
10949
10950
+ if (type_bit)
10951
+ {
10952
+ ntypes = 0;
10953
+ for (type = 0; type < T_MAX; type++)
10954
+ if (found->bits & (1 << type))
10955
+ {
10956
+ if (ntypes == idx)
10957
+ break;
10958
+ ntypes++;
10959
+ }
10960
+ gcc_assert (type < T_MAX);
10961
+ *type_bit = (enum neon_builtin_type_bits) (1 << type);
10962
+ }
10963
return found->codes[idx];
10964
}
10965
10966
typedef enum {
10967
NEON_ARG_COPY_TO_REG,
10968
NEON_ARG_CONSTANT,
10969
+ NEON_ARG_MEMORY,
10970
NEON_ARG_STOP
10971
} builtin_arg;
10972
10973
-#define NEON_MAX_BUILTIN_ARGS 5
10974
+#define NEON_MAX_BUILTIN_ARGS 5
10975
+
10976
+/* EXP is a pointer argument to a Neon load or store intrinsic. Derive
10977
+ and return an expression for the accessed memory.
10978
+
10979
+ The intrinsic function operates on a block of registers that has
10980
+ mode REG_MODE. This block contains vectors of type TYPE_BIT.
10981
+ The function references the memory at EXP in mode MEM_MODE;
10982
+ this mode may be BLKmode if no more suitable mode is available. */
10983
+
10984
+static tree
10985
+neon_dereference_pointer (tree exp, enum machine_mode mem_mode,
10986
+ enum machine_mode reg_mode,
10987
+ enum neon_builtin_type_bits type_bit)
10988
+{
10989
+ HOST_WIDE_INT reg_size, vector_size, nvectors, nelems;
10990
+ tree elem_type, upper_bound, array_type;
10991
+
10992
+ /* Work out the size of the register block in bytes. */
10993
+ reg_size = GET_MODE_SIZE (reg_mode);
10994
+
10995
+ /* Work out the size of each vector in bytes. */
10996
+ gcc_assert (type_bit & (T_DREG | T_QREG));
10997
+ vector_size = (type_bit & T_QREG ? 16 : 8);
10998
+
10999
+ /* Work out how many vectors there are. */
11000
+ gcc_assert (reg_size % vector_size == 0);
11001
+ nvectors = reg_size / vector_size;
11002
+
11003
+ /* Work out how many elements are being loaded or stored.
11004
+ MEM_MODE == REG_MODE implies a one-to-one mapping between register
11005
+ and memory elements; anything else implies a lane load or store. */
11006
+ if (mem_mode == reg_mode)
11007
+ nelems = vector_size * nvectors;
11008
+ else
11009
+ nelems = nvectors;
11010
+
11011
+ /* Work out the type of each element. */
11012
+ gcc_assert (POINTER_TYPE_P (TREE_TYPE (exp)));
11013
+ elem_type = TREE_TYPE (TREE_TYPE (exp));
11014
+
11015
+ /* Create a type that describes the full access. */
11016
+ upper_bound = build_int_cst (size_type_node, nelems - 1);
11017
+ array_type = build_array_type (elem_type, build_index_type (upper_bound));
11018
+
11019
+ /* Dereference EXP using that type. */
11020
+ exp = convert (build_pointer_type (array_type), exp);
11021
+ return fold_build1 (INDIRECT_REF, array_type, exp);
11022
+}
11023
11024
/* Expand a Neon builtin. */
11025
static rtx
11026
arm_expand_neon_args (rtx target, int icode, int have_retval,
11027
+ enum neon_builtin_type_bits type_bit,
11028
tree exp, ...)
11029
{
11030
va_list ap;
11031
@@ -17996,7 +19559,9 @@
11032
rtx op[NEON_MAX_BUILTIN_ARGS];
11033
enum machine_mode tmode = insn_data[icode].operand[0].mode;
11034
enum machine_mode mode[NEON_MAX_BUILTIN_ARGS];
11035
+ enum machine_mode other_mode;
11036
int argc = 0;
11037
+ int opno;
11038
11039
if (have_retval
11040
&& (!target
11041
@@ -18014,26 +19579,46 @@
11042
break;
11043
else
11044
{
11045
+ opno = argc + have_retval;
11046
+ mode[argc] = insn_data[icode].operand[opno].mode;
11047
arg[argc] = CALL_EXPR_ARG (exp, argc);
11048
+ if (thisarg == NEON_ARG_MEMORY)
11049
+ {
11050
+ other_mode = insn_data[icode].operand[1 - opno].mode;
11051
+ arg[argc] = neon_dereference_pointer (arg[argc], mode[argc],
11052
+ other_mode, type_bit);
11053
+ }
11054
op[argc] = expand_normal (arg[argc]);
11055
- mode[argc] = insn_data[icode].operand[argc + have_retval].mode;
11056
11057
switch (thisarg)
11058
{
11059
case NEON_ARG_COPY_TO_REG:
11060
/*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/
11061
- if (!(*insn_data[icode].operand[argc + have_retval].predicate)
11062
+ if (!(*insn_data[icode].operand[opno].predicate)
11063
(op[argc], mode[argc]))
11064
op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
11065
break;
11066
11067
case NEON_ARG_CONSTANT:
11068
/* FIXME: This error message is somewhat unhelpful. */
11069
- if (!(*insn_data[icode].operand[argc + have_retval].predicate)
11070
+ if (!(*insn_data[icode].operand[opno].predicate)
11071
(op[argc], mode[argc]))
11072
error ("argument must be a constant");
11073
break;
11074
11075
+ case NEON_ARG_MEMORY:
11076
+ gcc_assert (MEM_P (op[argc]));
11077
+ PUT_MODE (op[argc], mode[argc]);
11078
+ /* ??? arm_neon.h uses the same built-in functions for signed
11079
+ and unsigned accesses, casting where necessary. This isn't
11080
+ alias safe. */
11081
+ set_mem_alias_set (op[argc], 0);
11082
+ if (!(*insn_data[icode].operand[opno].predicate)
11083
+ (op[argc], mode[argc]))
11084
+ op[argc] = (replace_equiv_address
11085
+ (op[argc], force_reg (Pmode, XEXP (op[argc], 0))));
11086
+ break;
11087
+
11088
case NEON_ARG_STOP:
11089
gcc_unreachable ();
11090
}
11091
@@ -18112,14 +19697,15 @@
11092
arm_expand_neon_builtin (int fcode, tree exp, rtx target)
11093
{
11094
neon_itype itype;
11095
- enum insn_code icode = locate_neon_builtin_icode (fcode, &itype);
11096
+ enum neon_builtin_type_bits type_bit;
11097
+ enum insn_code icode = locate_neon_builtin_icode (fcode, &itype, &type_bit);
11098
11099
switch (itype)
11100
{
11101
case NEON_UNOP:
11102
case NEON_CONVERT:
11103
case NEON_DUPLANE:
11104
- return arm_expand_neon_args (target, icode, 1, exp,
11105
+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
11106
NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP);
11107
11108
case NEON_BINOP:
11109
@@ -18129,90 +19715,90 @@
11110
case NEON_SCALARMULH:
11111
case NEON_SHIFTINSERT:
11112
case NEON_LOGICBINOP:
11113
- return arm_expand_neon_args (target, icode, 1, exp,
11114
+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
11115
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
11116
NEON_ARG_STOP);
11117
11118
case NEON_TERNOP:
11119
- return arm_expand_neon_args (target, icode, 1, exp,
11120
+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
11121
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
11122
NEON_ARG_CONSTANT, NEON_ARG_STOP);
11123
11124
case NEON_GETLANE:
11125
case NEON_FIXCONV:
11126
case NEON_SHIFTIMM:
11127
- return arm_expand_neon_args (target, icode, 1, exp,
11128
+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
11129
NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT,
11130
NEON_ARG_STOP);
11131
11132
case NEON_CREATE:
11133
- return arm_expand_neon_args (target, icode, 1, exp,
11134
+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
11135
NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
11136
11137
case NEON_DUP:
11138
case NEON_SPLIT:
11139
case NEON_REINTERP:
11140
- return arm_expand_neon_args (target, icode, 1, exp,
11141
+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
11142
NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
11143
11144
case NEON_COMBINE:
11145
case NEON_VTBL:
11146
- return arm_expand_neon_args (target, icode, 1, exp,
11147
+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
11148
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
11149
11150
case NEON_RESULTPAIR:
11151
- return arm_expand_neon_args (target, icode, 0, exp,
11152
+ return arm_expand_neon_args (target, icode, 0, type_bit, exp,
11153
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
11154
NEON_ARG_STOP);
11155
11156
case NEON_LANEMUL:
11157
case NEON_LANEMULL:
11158
case NEON_LANEMULH:
11159
- return arm_expand_neon_args (target, icode, 1, exp,
11160
+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
11161
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
11162
NEON_ARG_CONSTANT, NEON_ARG_STOP);
11163
11164
case NEON_LANEMAC:
11165
- return arm_expand_neon_args (target, icode, 1, exp,
11166
+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
11167
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
11168
NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP);
11169
11170
case NEON_SHIFTACC:
11171
- return arm_expand_neon_args (target, icode, 1, exp,
11172
+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
11173
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
11174
NEON_ARG_CONSTANT, NEON_ARG_STOP);
11175
11176
case NEON_SCALARMAC:
11177
- return arm_expand_neon_args (target, icode, 1, exp,
11178
+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
11179
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
11180
NEON_ARG_CONSTANT, NEON_ARG_STOP);
11181
11182
case NEON_SELECT:
11183
case NEON_VTBX:
11184
- return arm_expand_neon_args (target, icode, 1, exp,
11185
+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
11186
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
11187
NEON_ARG_STOP);
11188
11189
case NEON_LOAD1:
11190
case NEON_LOADSTRUCT:
11191
- return arm_expand_neon_args (target, icode, 1, exp,
11192
- NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
11193
+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
11194
+ NEON_ARG_MEMORY, NEON_ARG_STOP);
11195
11196
case NEON_LOAD1LANE:
11197
case NEON_LOADSTRUCTLANE:
11198
- return arm_expand_neon_args (target, icode, 1, exp,
11199
- NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
11200
+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
11201
+ NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
11202
NEON_ARG_STOP);
11203
11204
case NEON_STORE1:
11205
case NEON_STORESTRUCT:
11206
- return arm_expand_neon_args (target, icode, 0, exp,
11207
- NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
11208
+ return arm_expand_neon_args (target, icode, 0, type_bit, exp,
11209
+ NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
11210
11211
case NEON_STORE1LANE:
11212
case NEON_STORESTRUCTLANE:
11213
- return arm_expand_neon_args (target, icode, 0, exp,
11214
- NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
11215
+ return arm_expand_neon_args (target, icode, 0, type_bit, exp,
11216
+ NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
11217
NEON_ARG_STOP);
11218
}
11219
11220
@@ -18237,7 +19823,7 @@
11221
rtx tmp1 = gen_reg_rtx (mode);
11222
rtx tmp2 = gen_reg_rtx (mode);
11223
11224
- emit_insn (intfn (tmp1, op1, tmp2, op2));
11225
+ emit_insn (intfn (tmp1, op1, op2, tmp2));
11226
11227
emit_move_insn (mem, tmp1);
11228
mem = adjust_address (mem, mode, GET_MODE_SIZE (mode));
11229
@@ -19028,6 +20614,81 @@
11790
11230
#endif
11791
11231
}
11792
11232
11868
11308
/* The bits which aren't usefully expanded as rtl. */
11869
11309
const char *
11870
11310
thumb_unexpanded_epilogue (void)
11871
@@ -19035,6 +20563,7 @@
11311
@@ -19036,6 +20697,7 @@
11872
11312
int regno;
11873
11313
unsigned long live_regs_mask = 0;
11874
11314
int high_regs_pushed = 0;
11876
11316
int had_to_push_lr;
11877
11317
int size;
11878
11318
11879
@@ -19054,6 +20583,13 @@
11319
@@ -19055,6 +20717,13 @@
11880
11320
the register is used to hold a return value. */
11881
11321
size = arm_size_return_regs ();
11882
11322
11890
11330
/* The prolog may have pushed some high registers to use as
11891
11331
work registers. e.g. the testsuite file:
11892
11332
gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
11893
@@ -19137,7 +20673,9 @@
11333
@@ -19138,7 +20807,9 @@
11894
11334
live_regs_mask);
11895
11335
11896
11336
/* We have either just popped the return address into the
11901
11341
if (!had_to_push_lr)
11902
11342
thumb_exit (asm_out_file, LR_REGNUM);
11903
11343
}
11904
@@ -19319,6 +20857,7 @@
11344
@@ -19320,6 +20991,7 @@
11905
11345
stack_pointer_rtx);
11906
11346
11907
11347
amount = offsets->outgoing_args - offsets->saved_regs;
11909
11349
if (amount)
11910
11350
{
11911
11351
if (amount < 512)
11912
@@ -19403,6 +20942,7 @@
11352
@@ -19404,6 +21076,7 @@
11913
11353
emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
11914
11354
amount = offsets->locals_base - offsets->saved_regs;
11915
11355
}
11917
11357
11918
11358
gcc_assert (amount >= 0);
11919
11359
if (amount)
11920
@@ -19623,7 +21163,11 @@
11360
@@ -19624,7 +21297,11 @@
11921
11361
register. */
11922
11362
else if ((l_mask & 0xff) != 0
11923
11363
|| (high_regs_pushed == 0 && l_mask))
11930
11370
11931
11371
if (high_regs_pushed)
11932
11372
{
11933
@@ -19997,13 +21541,10 @@
11373
@@ -19998,13 +21675,10 @@
11934
11374
if (TARGET_BPABI)
11935
11375
{
11936
11376
const char *fpu_name;
11947
11387
11948
11388
if (TARGET_SOFT_FLOAT)
11949
11389
{
11950
@@ -20398,6 +21939,38 @@
11390
@@ -20399,6 +22073,38 @@
11951
11391
return !reg_overlap_mentioned_p (value, addr);
11952
11392
}
11953
11393
11986
11426
/* Return nonzero if the CONSUMER instruction (an ALU op) does not
11987
11427
have an early register shift value or amount dependency on the
11988
11428
result of PRODUCER. */
11989
@@ -21254,6 +22827,16 @@
11429
@@ -20777,6 +22483,20 @@
11430
return false;
11431
}
11432
11433
+/* Implements target hook array_mode_supported_p. */
11434
+
11435
+static bool
11436
+arm_array_mode_supported_p (enum machine_mode mode,
11437
+ unsigned HOST_WIDE_INT nelems)
11438
+{
11439
+ if (TARGET_NEON
11440
+ && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
11441
+ && (nelems >= 2 && nelems <= 4))
11442
+ return true;
11443
+
11444
+ return false;
11445
+}
11446
+
11447
/* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
11448
ARM insns and therefore guarantee that the shift count is modulo 256.
11449
DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
11450
@@ -21255,6 +22975,16 @@
11990
11451
fputc (')', fp);
11991
11452
return TRUE;
11992
11453
}
12003
11464
else if (GET_CODE (x) == CONST_VECTOR)
12004
11465
return arm_emit_vector_const (fp, x);
12005
11466
12006
@@ -21362,6 +22945,7 @@
11467
@@ -21363,6 +23093,7 @@
12007
11468
{
12008
11469
case cortexr4:
12009
11470
case cortexr4f:
12011
11472
case cortexa8:
12012
11473
case cortexa9:
12013
11474
return 2;
12014
@@ -21508,4 +23092,447 @@
11475
@@ -21509,4 +23240,447 @@
12015
11476
return !TARGET_THUMB1;
12016
11477
}
12017
11478
12715
12176
12716
12177
/* Definitions for register eliminations.
12717
12178
12718
@@ -2201,7 +2270,9 @@
12179
@@ -1927,27 +1996,6 @@
12180
#define TARGET_DEFAULT_WORD_RELOCATIONS 0
12181
#endif
12182
12183
-/* Nonzero if the constant value X is a legitimate general operand.
12184
- It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
12185
-
12186
- On the ARM, allow any integer (invalid ones are removed later by insn
12187
- patterns), nice doubles and symbol_refs which refer to the function's
12188
- constant pool XXX.
12189
-
12190
- When generating pic allow anything. */
12191
-#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
12192
-
12193
-#define THUMB_LEGITIMATE_CONSTANT_P(X) \
12194
- ( GET_CODE (X) == CONST_INT \
12195
- || GET_CODE (X) == CONST_DOUBLE \
12196
- || CONSTANT_ADDRESS_P (X) \
12197
- || flag_pic)
12198
-
12199
-#define LEGITIMATE_CONSTANT_P(X) \
12200
- (!arm_cannot_force_const_mem (X) \
12201
- && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
12202
- : THUMB_LEGITIMATE_CONSTANT_P (X)))
12203
-
12204
#ifndef SUBTARGET_NAME_ENCODING_LENGTHS
12205
#define SUBTARGET_NAME_ENCODING_LENGTHS
12206
#endif
12207
@@ -2201,7 +2249,9 @@
12719
12208
/* Try to generate sequences that don't involve branches, we can then use
12720
12209
conditional instructions */
12721
12210
#define BRANCH_COST(speed_p, predictable_p) \
12726
12215
12727
12216
/* Position Independent Code. */
12728
12217
/* We decide which register to use based on the compilation options and
12729
@@ -2253,19 +2324,7 @@
12218
@@ -2253,19 +2303,7 @@
12730
12219
: reverse_condition (code))
12731
12220
12732
12221
#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
12747
12236
12748
12237
/* The arm5 clz instruction returns 32. */
12749
12238
#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
12750
@@ -2566,6 +2625,8 @@
12239
@@ -2566,6 +2604,8 @@
12751
12240
#define RETURN_ADDR_RTX(COUNT, FRAME) \
12752
12241
arm_return_addr (COUNT, FRAME)
12753
12242
12756
12245
/* Mask of the bits in the PC that contain the real return address
12757
12246
when running in 26-bit mode. */
12758
12247
#define RETURN_ADDR_MASK26 (0x03fffffc)
12759
@@ -2765,4 +2826,8 @@
12248
@@ -2765,4 +2805,8 @@
12760
12249
#define NEED_INDICATE_EXEC_STACK 0
12761
12250
#endif
12762
12251
13662
13151
- DONE;
13663
13152
- }
13664
13153
- }
13665
+{
13666
+ if (TARGET_THUMB1)
13667
+ {
13668
+ emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1]));
13669
+ DONE;
13670
+ }
13671
+ if (MEM_P (operands[1]) && TARGET_ARM && !arm_arch4)
13672
+ {
13673
+ emit_insn (gen_extendhisi2_mem (operands[0], operands[1]));
13674
+ DONE;
13675
+ }
13676
13154
-
13677
13155
- if (TARGET_ARM && GET_CODE (operands[1]) == MEM)
13678
13156
- {
13679
13157
- emit_insn (gen_extendhisi2_mem (operands[0], operands[1]));
13680
13158
- DONE;
13681
13159
- }
13682
+ if (!arm_arch6 && !MEM_P (operands[1]))
13683
+ {
13684
+ rtx t = gen_lowpart (SImode, operands[1]);
13685
+ rtx tmp = gen_reg_rtx (SImode);
13686
+ emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (16)));
13687
+ emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (16)));
13688
+ DONE;
13689
+ }
13690
+})
13691
13160
-
13692
13161
- if (!s_register_operand (operands[1], HImode))
13693
13162
- operands[1] = copy_to_mode_reg (HImode, operands[1]);
13694
13163
-
13749
13218
- ops[1] = mem;
13750
13219
- ops[2] = const0_rtx;
13751
13220
- }
13752
-
13221
+{
13222
+ if (TARGET_THUMB1)
13223
+ {
13224
+ emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1]));
13225
+ DONE;
13226
+ }
13227
+ if (MEM_P (operands[1]) && TARGET_ARM && !arm_arch4)
13228
+ {
13229
+ emit_insn (gen_extendhisi2_mem (operands[0], operands[1]));
13230
+ DONE;
13231
+ }
13232
13753
13233
- gcc_assert (GET_CODE (ops[1]) == REG);
13754
-
13234
+ if (!arm_arch6 && !MEM_P (operands[1]))
13235
+ {
13236
+ rtx t = gen_lowpart (SImode, operands[1]);
13237
+ rtx tmp = gen_reg_rtx (SImode);
13238
+ emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (16)));
13239
+ emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (16)));
13240
+ DONE;
13241
+ }
13242
+})
13243
13755
13244
- ops[0] = operands[0];
13756
13245
- ops[3] = operands[2];
13757
13246
- output_asm_insn (\"mov\\t%3, %2\;ldrsh\\t%0, [%1, %3]\", ops);
14017
13506
+ && REG_P (XEXP (addr, 0)) && REG_P (XEXP (addr, 1)))
14018
13507
+ /* No split necessary. */
14019
13508
+ FAIL;
14020
14021
-(define_insn "*thumb1_extendqisi2_v6"
13509
+
14022
13510
+ if (GET_CODE (addr) == PLUS
14023
13511
+ && !REG_P (XEXP (addr, 0)) && !REG_P (XEXP (addr, 1)))
14024
13512
+ FAIL;
14030
13518
+ emit_insn (gen_thumb1_extendqisi2 (operands[0], t));
14031
13519
+ DONE;
14032
13520
+ }
14033
+
13521
13522
-(define_insn "*thumb1_extendqisi2_v6"
14034
13523
+ if (REG_P (addr))
14035
13524
+ {
14036
13525
+ addr = gen_rtx_PLUS (Pmode, addr, operands[0]);
14189
13678
}
14190
13679
else /* TARGET_THUMB1... */
14191
13680
{
14192
@@ -5178,9 +5146,22 @@
14193
"
14194
)
14195
13681
@@ -5175,12 +5143,25 @@
13682
arm_split_constant (SET, SImode, NULL_RTX,
13683
INTVAL (operands[1]), operands[0], NULL_RTX, 0);
13684
DONE;
13685
- "
13686
-)
13687
+ "
13688
+)
13689
+
14196
13690
+(define_split
14197
13691
+ [(set (match_operand:SI 0 "arm_general_register_operand" "")
14198
13692
+ (match_operand:SI 1 "general_operand" ""))]
14205
13699
+ arm_emit_movpair (operands[0], operands[1]);
14206
13700
+ DONE;
14207
13701
+})
14208
+
13702
14209
13703
(define_insn "*thumb1_movsi_insn"
14210
13704
- [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,l,l,l,>,l, m,*lhk")
14211
13705
- (match_operand:SI 1 "general_operand" "l, I,J,K,>,l,mi,l,*lhk"))]
15360
14854
[(set_attr "predicable" "yes")
15361
14855
(set_attr "length" "4")]
15362
14856
)
15363
@@ -11273,37 +11222,35 @@
15364
(define_expand "bswapsi2"
15365
[(set (match_operand:SI 0 "s_register_operand" "=r")
15366
(bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
15367
-"TARGET_EITHER"
15368
+"TARGET_EITHER && (arm_arch6 || !optimize_size)"
15369
"
15370
- if (!arm_arch6)
15371
- {
15372
- if (!optimize_size)
15373
- {
15374
- rtx op2 = gen_reg_rtx (SImode);
15375
- rtx op3 = gen_reg_rtx (SImode);
15376
+ if (!arm_arch6)
15377
+ {
15378
+ rtx op2 = gen_reg_rtx (SImode);
15379
+ rtx op3 = gen_reg_rtx (SImode);
15380
15381
- if (TARGET_THUMB)
15382
- {
15383
- rtx op4 = gen_reg_rtx (SImode);
15384
- rtx op5 = gen_reg_rtx (SImode);
15385
+ if (TARGET_THUMB)
15386
+ {
15387
+ rtx op4 = gen_reg_rtx (SImode);
15388
+ rtx op5 = gen_reg_rtx (SImode);
15389
15390
- emit_insn (gen_thumb_legacy_rev (operands[0], operands[1],
15391
- op2, op3, op4, op5));
15392
- }
15393
- else
15394
- {
15395
- emit_insn (gen_arm_legacy_rev (operands[0], operands[1],
15396
- op2, op3));
15397
- }
15398
+ emit_insn (gen_thumb_legacy_rev (operands[0], operands[1],
15399
+ op2, op3, op4, op5));
15400
+ }
15401
+ else
15402
+ {
15403
+ emit_insn (gen_arm_legacy_rev (operands[0], operands[1],
15404
+ op2, op3));
15405
+ }
15406
15407
- DONE;
15408
- }
15409
- else
15410
- FAIL;
15411
- }
15412
+ DONE;
15413
+ }
14857
@@ -11299,6 +11248,9 @@
15414
14858
"
15415
14859
)
15416
14860
15420
14864
;; Load the FPA co-processor patterns
15421
14865
(include "fpa.md")
15422
14866
;; Load the Maverick co-processor patterns
15423
@@ -11318,4 +11265,5 @@
14867
@@ -11313,4 +11265,5 @@
15424
14868
(include "thumb2.md")
15425
14869
;; Neon patterns
15426
14870
(include "neon.md")
21736
21180
Printf.fprintf chan "\n#include \"arm_neon.h\"\n\n";
21737
21181
Printf.fprintf chan "void test_%s (void)\n{\n" test_name
21738
21182
21183
@@ -177,7 +177,7 @@
21184
let alt2 = commas (fun x -> x) (n_things n elt_regexp) "" in
21185
"\\\\\\{((" ^ alt1 ^ ")|(" ^ alt2 ^ "))\\\\\\}"
21186
| (PtrTo elt | CstPtrTo elt) ->
21187
- "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\\\\\]"
21188
+ "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\(:\\[0-9\\]+\\)?\\\\\\]"
21189
| Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
21190
| Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
21191
| All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]"
21739
21192
@@ -257,7 +257,7 @@
21740
21193
intrinsic expands to. Watch out for any writeback character and
21741
21194
comments after the instruction. *)
21825
21278
;; (Opposite) mode to convert to/from for above conversions.
21826
21279
(define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI")
21827
21280
(V4SI "V4SF") (V4SF "V4SI")])
21828
@@ -332,6 +319,14 @@
21281
@@ -272,20 +259,18 @@
21282
21283
;; Mode of pair of elements for each vector mode, to define transfer
21284
;; size for structure lane/dup loads and stores.
21285
-(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
21286
- (V4HI "SI") (V8HI "SI")
21287
+(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
21288
+ (V4HI "SI") (V8HI "SI")
21289
(V2SI "V2SI") (V4SI "V2SI")
21290
(V2SF "V2SF") (V4SF "V2SF")
21291
(DI "V2DI") (V2DI "V2DI")])
21292
21293
;; Similar, for three elements.
21294
-;; ??? Should we define extra modes so that sizes of all three-element
21295
-;; accesses can be accurately represented?
21296
-(define_mode_attr V_three_elem [(V8QI "SI") (V16QI "SI")
21297
- (V4HI "V4HI") (V8HI "V4HI")
21298
- (V2SI "V4SI") (V4SI "V4SI")
21299
- (V2SF "V4SF") (V4SF "V4SF")
21300
- (DI "EI") (V2DI "EI")])
21301
+(define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK")
21302
+ (V4HI "BLK") (V8HI "BLK")
21303
+ (V2SI "BLK") (V4SI "BLK")
21304
+ (V2SF "BLK") (V4SF "BLK")
21305
+ (DI "EI") (V2DI "EI")])
21306
21307
;; Similar, for four elements.
21308
(define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI")
21309
@@ -332,6 +317,14 @@
21829
21310
(V4HI "V2SI") (V8HI "V4SI")
21830
21311
(V2SI "DI") (V4SI "V2DI")])
21831
21312
21840
21321
;; Mode of result of comparison operations (and bit-select operand 1).
21841
21322
(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
21842
21323
(V4HI "V4HI") (V8HI "V8HI")
21843
@@ -396,6 +391,9 @@
21324
@@ -396,6 +389,9 @@
21844
21325
;; Same, without unsigned variants (for use with *SFmode pattern).
21845
21326
(define_code_iterator vqhs_ops [plus smin smax])
21846
21327
21850
21331
;; Assembler mnemonics for above codes.
21851
21332
(define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax")
21852
21333
(umin "vmin") (umax "vmax")])
21853
@@ -451,6 +449,12 @@
21334
@@ -451,6 +447,12 @@
21854
21335
(V2SF "2") (V4SF "4")
21855
21336
(DI "1") (V2DI "2")])
21856
21337
21863
21344
(define_insn "*neon_mov<mode>"
21864
21345
[(set (match_operand:VD 0 "nonimmediate_operand"
21865
21346
"=w,Uv,w, w, ?r,?w,?r,?r, ?Us")
21866
@@ -671,6 +675,52 @@
21347
@@ -671,6 +673,52 @@
21867
21348
neon_disambiguate_copy (operands, dest, src, 4);
21868
21349
})
21869
21350
21916
21397
(define_insn "vec_set<mode>_internal"
21917
21398
[(set (match_operand:VD 0 "s_register_operand" "=w")
21918
21399
(vec_merge:VD
21919
@@ -685,7 +735,7 @@
21400
@@ -680,12 +728,12 @@
21401
(match_operand:SI 2 "immediate_operand" "i")))]
21402
"TARGET_NEON"
21403
{
21404
- int elt = ffs ((int) INTVAL (operands[2]) - 1);
21405
+ int elt = ffs ((int) INTVAL (operands[2]) - 1);
21406
if (BYTES_BIG_ENDIAN)
21920
21407
elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
21921
21408
operands[2] = GEN_INT (elt);
21922
21409
21925
21412
}
21926
21413
[(set_attr "predicable" "yes")
21927
21414
(set_attr "neon_type" "neon_mcr")])
21928
@@ -711,7 +761,7 @@
21415
@@ -711,7 +759,7 @@
21929
21416
operands[0] = gen_rtx_REG (<V_HALF>mode, regno + hi);
21930
21417
operands[2] = GEN_INT (elt);
21931
21418
21934
21421
}
21935
21422
[(set_attr "predicable" "yes")
21936
21423
(set_attr "neon_type" "neon_mcr")]
21937
@@ -731,7 +781,7 @@
21424
@@ -731,7 +779,7 @@
21938
21425
21939
21426
operands[0] = gen_rtx_REG (DImode, regno);
21940
21427
21943
21430
}
21944
21431
[(set_attr "predicable" "yes")
21945
21432
(set_attr "neon_type" "neon_mcr_2_mcrr")]
21946
@@ -799,11 +849,11 @@
21433
@@ -799,11 +847,11 @@
21947
21434
(parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
21948
21435
"TARGET_NEON"
21949
21436
{
21957
21444
}
21958
21445
[(set_attr "predicable" "yes")
21959
21446
(set_attr "neon_type" "neon_int_1")]
21960
@@ -820,17 +870,14 @@
21447
@@ -820,17 +868,14 @@
21961
21448
21962
21449
;; Doubleword and quadword arithmetic.
21963
21450
21978
21465
"vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
21979
21466
[(set (attr "neon_type")
21980
21467
(if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
21981
@@ -840,11 +887,33 @@
21468
@@ -840,11 +885,33 @@
21982
21469
(const_string "neon_int_1")))]
21983
21470
)
21984
21471
22013
21500
"vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
22014
21501
[(set (attr "neon_type")
22015
21502
(if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
22016
@@ -854,11 +923,34 @@
21503
@@ -854,11 +921,34 @@
22017
21504
(const_string "neon_int_2")))]
22018
21505
)
22019
21506
22049
21536
"vmul.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
22050
21537
[(set (attr "neon_type")
22051
21538
(if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
22052
@@ -875,12 +967,12 @@
21539
@@ -875,12 +965,12 @@
22053
21540
(const_string "neon_mul_qqq_8_16_32_ddd_32")))))]
22054
21541
)
22055
21542
22064
21551
"vmla.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
22065
21552
[(set (attr "neon_type")
22066
21553
(if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
22067
@@ -897,12 +989,12 @@
21554
@@ -897,12 +987,12 @@
22068
21555
(const_string "neon_mla_qqq_32_qqd_32_scalar")))))]
22069
21556
)
22070
21557
22079
21566
"vmls.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
22080
21567
[(set (attr "neon_type")
22081
21568
(if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
22082
@@ -937,21 +1029,26 @@
21569
@@ -937,21 +1027,26 @@
22083
21570
)
22084
21571
22085
21572
(define_insn "iordi3_neon"
22113
21600
)
22114
21601
22115
21602
;; The concrete forms of the Neon immediate-logic instructions are vbic and
22116
@@ -977,21 +1074,26 @@
21603
@@ -977,21 +1072,26 @@
22117
21604
)
22118
21605
22119
21606
(define_insn "anddi3_neon"
22147
21634
)
22148
21635
22149
21636
(define_insn "orn<mode>3_neon"
22150
@@ -1004,13 +1106,16 @@
21637
@@ -1004,13 +1104,16 @@
22151
21638
)
22152
21639
22153
21640
(define_insn "orndi3_neon"
22170
21657
)
22171
21658
22172
21659
(define_insn "bic<mode>3_neon"
22173
@@ -1022,14 +1127,18 @@
21660
@@ -1022,14 +1125,18 @@
22174
21661
[(set_attr "neon_type" "neon_int_1")]
22175
21662
)
22176
21663
22195
21682
)
22196
21683
22197
21684
(define_insn "xor<mode>3"
22198
@@ -1042,13 +1151,18 @@
21685
@@ -1042,13 +1149,18 @@
22199
21686
)
22200
21687
22201
21688
(define_insn "xordi3_neon"
22220
21707
)
22221
21708
22222
21709
(define_insn "one_cmpl<mode>2"
22223
@@ -1317,7 +1431,7 @@
21710
@@ -1317,7 +1429,7 @@
22224
21711
(parallel [(const_int 0) (const_int 1)]))
22225
21712
(vec_select:V2SF (match_dup 1)
22226
21713
(parallel [(const_int 2) (const_int 3)]))))]
22229
21716
"<VQH_mnem>.f32\t%P0, %e1, %f1"
22230
21717
[(set_attr "vqh_mnem" "<VQH_mnem>")
22231
21718
(set (attr "neon_type")
22232
@@ -1452,7 +1566,7 @@
21719
@@ -1452,7 +1564,7 @@
22233
21720
(define_expand "reduc_splus_<mode>"
22234
21721
[(match_operand:VD 0 "s_register_operand" "")
22235
21722
(match_operand:VD 1 "s_register_operand" "")]
22238
21725
{
22239
21726
neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
22240
21727
&gen_neon_vpadd_internal<mode>);
22241
@@ -1462,7 +1576,7 @@
21728
@@ -1462,7 +1574,7 @@
22242
21729
(define_expand "reduc_splus_<mode>"
22243
21730
[(match_operand:VQ 0 "s_register_operand" "")
22244
21731
(match_operand:VQ 1 "s_register_operand" "")]
22247
21734
{
22248
21735
rtx step1 = gen_reg_rtx (<V_HALF>mode);
22249
21736
rtx res_d = gen_reg_rtx (<V_HALF>mode);
22250
@@ -1497,7 +1611,7 @@
21737
@@ -1497,7 +1609,7 @@
22251
21738
(define_expand "reduc_smin_<mode>"
22252
21739
[(match_operand:VD 0 "s_register_operand" "")
22253
21740
(match_operand:VD 1 "s_register_operand" "")]
22256
21743
{
22257
21744
neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
22258
21745
&gen_neon_vpsmin<mode>);
22259
@@ -1507,7 +1621,7 @@
21746
@@ -1507,7 +1619,7 @@
22260
21747
(define_expand "reduc_smin_<mode>"
22261
21748
[(match_operand:VQ 0 "s_register_operand" "")
22262
21749
(match_operand:VQ 1 "s_register_operand" "")]
22265
21752
{
22266
21753
rtx step1 = gen_reg_rtx (<V_HALF>mode);
22267
21754
rtx res_d = gen_reg_rtx (<V_HALF>mode);
22268
@@ -1522,7 +1636,7 @@
21755
@@ -1522,7 +1634,7 @@
22269
21756
(define_expand "reduc_smax_<mode>"
22270
21757
[(match_operand:VD 0 "s_register_operand" "")
22271
21758
(match_operand:VD 1 "s_register_operand" "")]
22274
21761
{
22275
21762
neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
22276
21763
&gen_neon_vpsmax<mode>);
22277
@@ -1532,7 +1646,7 @@
21764
@@ -1532,7 +1644,7 @@
22278
21765
(define_expand "reduc_smax_<mode>"
22279
21766
[(match_operand:VQ 0 "s_register_operand" "")
22280
21767
(match_operand:VQ 1 "s_register_operand" "")]
22283
21770
{
22284
21771
rtx step1 = gen_reg_rtx (<V_HALF>mode);
22285
21772
rtx res_d = gen_reg_rtx (<V_HALF>mode);
22286
@@ -1704,15 +1818,204 @@
21773
@@ -1704,15 +1816,204 @@
22287
21774
[(set_attr "neon_type" "neon_int_5")]
22288
21775
)
22289
21776
22491
21978
UNSPEC_VADD))]
22492
21979
"TARGET_NEON"
22493
21980
"vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
22494
@@ -1785,6 +2088,8 @@
21981
@@ -1785,6 +2086,8 @@
22495
21982
[(set_attr "neon_type" "neon_int_4")]
22496
21983
)
22497
21984
22500
21987
(define_insn "neon_vmul<mode>"
22501
21988
[(set (match_operand:VDQW 0 "s_register_operand" "=w")
22502
21989
(unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w")
22503
@@ -1808,13 +2113,31 @@
21990
@@ -1808,13 +2111,31 @@
22504
21991
(const_string "neon_mul_qqq_8_16_32_ddd_32")))))]
22505
21992
)
22506
21993
22539
22026
"TARGET_NEON"
22540
22027
"vmla.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
22541
22028
[(set (attr "neon_type")
22542
@@ -1847,13 +2170,31 @@
22029
@@ -1847,13 +2168,31 @@
22543
22030
(const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
22544
22031
)
22545
22032
22578
22065
"TARGET_NEON"
22579
22066
"vmls.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
22580
22067
[(set (attr "neon_type")
22581
@@ -1963,11 +2304,27 @@
22068
@@ -1963,11 +2302,27 @@
22582
22069
(const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
22583
22070
)
22584
22071
22609
22096
UNSPEC_VSUB))]
22610
22097
"TARGET_NEON"
22611
22098
"vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
22612
@@ -2035,13 +2392,16 @@
22099
@@ -2035,13 +2390,16 @@
22613
22100
)
22614
22101
22615
22102
(define_insn "neon_vceq<mode>"
22632
22119
[(set (attr "neon_type")
22633
22120
(if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
22634
22121
(if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
22635
@@ -2051,13 +2411,16 @@
22122
@@ -2051,13 +2409,16 @@
22636
22123
)
22637
22124
22638
22125
(define_insn "neon_vcge<mode>"
22655
22142
[(set (attr "neon_type")
22656
22143
(if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
22657
22144
(if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
22658
@@ -2067,13 +2430,16 @@
22145
@@ -2067,13 +2428,16 @@
22659
22146
)
22660
22147
22661
22148
(define_insn "neon_vcgt<mode>"
22678
22165
[(set (attr "neon_type")
22679
22166
(if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
22680
22167
(if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
22681
@@ -2082,6 +2448,43 @@
22168
@@ -2082,6 +2446,43 @@
22682
22169
(const_string "neon_int_5")))]
22683
22170
)
22684
22171
22722
22209
(define_insn "neon_vcage<mode>"
22723
22210
[(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
22724
22211
(unspec:<V_cmp_result> [(match_operand:VCVTF 1 "s_register_operand" "w")
22725
@@ -2150,11 +2553,11 @@
22212
@@ -2150,11 +2551,11 @@
22726
22213
22727
22214
(define_insn "neon_vaba<mode>"
22728
22215
[(set (match_operand:VDQIW 0 "s_register_operand" "=w")
22739
22226
"TARGET_NEON"
22740
22227
"vaba.%T4%#<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
22741
22228
[(set (attr "neon_type")
22742
@@ -2164,11 +2567,11 @@
22229
@@ -2164,11 +2565,11 @@
22743
22230
22744
22231
(define_insn "neon_vabal<mode>"
22745
22232
[(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
22756
22243
"TARGET_NEON"
22757
22244
"vabal.%T4%#<V_sz_elem>\t%q0, %P2, %P3"
22758
22245
[(set_attr "neon_type" "neon_vaba")]
22759
@@ -2299,22 +2702,15 @@
22246
@@ -2299,22 +2700,15 @@
22760
22247
(const_string "neon_fp_vrecps_vrsqrts_qqq")))]
22761
22248
)
22762
22249
22787
22274
22788
22275
(define_insn "neon_vqabs<mode>"
22789
22276
[(set (match_operand:VDQIW 0 "s_register_operand" "=w")
22790
@@ -2356,26 +2752,42 @@
22277
@@ -2356,26 +2750,42 @@
22791
22278
[(set_attr "neon_type" "neon_int_1")]
22792
22279
)
22793
22280
22838
22325
(define_insn "neon_vrecpe<mode>"
22839
22326
[(set (match_operand:V32 0 "s_register_operand" "=w")
22840
22327
(unspec:V32 [(match_operand:V32 1 "s_register_operand" "w")
22841
@@ -2552,126 +2964,65 @@
22328
@@ -2552,126 +2962,65 @@
22842
22329
; Operand 3 (info word) is ignored because it does nothing useful with 64-bit
22843
22330
; elements.
22844
22331
23007
22494
23008
22495
(define_expand "neon_vcreate<mode>"
23009
22496
[(match_operand:VDX 0 "s_register_operand" "")
23010
@@ -2685,8 +3036,7 @@
22497
@@ -2685,8 +3034,7 @@
23011
22498
23012
22499
(define_insn "neon_vdup_n<mode>"
23013
22500
[(set (match_operand:VX 0 "s_register_operand" "=w")
23017
22504
"TARGET_NEON"
23018
22505
"vdup%?.<V_sz_elem>\t%<V_reg>0, %1"
23019
22506
;; Assume this schedules like vmov.
23020
@@ -2696,8 +3046,7 @@
22507
@@ -2696,8 +3044,7 @@
23021
22508
23022
22509
(define_insn "neon_vdup_n<mode>"
23023
22510
[(set (match_operand:V32 0 "s_register_operand" "=w,w")
23027
22514
"TARGET_NEON"
23028
22515
"@
23029
22516
vdup%?.<V_sz_elem>\t%<V_reg>0, %1
23030
@@ -2707,61 +3056,76 @@
22517
@@ -2707,61 +3054,76 @@
23031
22518
(set_attr "neon_type" "neon_bp_simple")]
23032
22519
)
23033
22520
23137
22624
"TARGET_NEON"
23138
22625
{
23139
22626
neon_lane_bounds (operands[2], 0, 1);
23140
@@ -2769,20 +3133,17 @@
22627
@@ -2769,20 +3131,17 @@
23141
22628
DONE;
23142
22629
})
23143
22630
23166
22653
23167
22654
;; In this insn, operand 1 should be low, and operand 2 the high part of the
23168
22655
;; dest vector.
23169
@@ -2793,9 +3154,8 @@
22656
@@ -2793,9 +3152,8 @@
23170
22657
23171
22658
(define_insn "neon_vcombine<mode>"
23172
22659
[(set (match_operand:<V_DOUBLE> 0 "s_register_operand" "=w")
23178
22665
"TARGET_NEON"
23179
22666
{
23180
22667
int dest = REGNO (operands[0]);
23181
@@ -2835,10 +3195,31 @@
22668
@@ -2835,10 +3193,82 @@
23182
22669
(set_attr "neon_type" "neon_bp_simple")]
23183
22670
)
23184
22671
23211
22698
+ (vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w")
23212
22699
+ (parallel [(const_int 4) (const_int 5)
23213
22700
+ (const_int 6) (const_int 7)])))]
23214
"TARGET_NEON"
23215
{
23216
int dest = REGNO (operands[0]);
23217
@@ -2852,10 +3233,133 @@
23218
[(set_attr "neon_type" "neon_bp_simple")]
23219
)
23220
23221
-(define_insn "neon_vget_low<mode>"
23222
- [(set (match_operand:<V_HALF> 0 "s_register_operand" "=w")
23223
- (unspec:<V_HALF> [(match_operand:VQX 1 "s_register_operand" "w")]
23224
- UNSPEC_VGET_LOW))]
22701
+ "TARGET_NEON"
22702
+{
22703
+ int dest = REGNO (operands[0]);
22704
+ int src = REGNO (operands[1]);
22705
+
22706
+ if (dest != src + 2)
22707
+ return "vmov\t%P0, %f1";
22708
+ else
22709
+ return "";
22710
+}
22711
+ [(set_attr "neon_type" "neon_bp_simple")]
22712
+)
22713
+
23225
22714
+(define_insn "neon_vget_highv4si"
23226
22715
+ [(set (match_operand:V2SI 0 "s_register_operand" "=w")
23227
22716
+ (vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w")
23260
22749
+ [(set (match_operand:DI 0 "s_register_operand" "=w")
23261
22750
+ (vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w")
23262
22751
+ (parallel [(const_int 1)])))]
23263
+ "TARGET_NEON"
23264
+{
23265
+ int dest = REGNO (operands[0]);
23266
+ int src = REGNO (operands[1]);
23267
+
23268
+ if (dest != src + 2)
23269
+ return "vmov\t%P0, %f1";
23270
+ else
23271
+ return "";
23272
+}
23273
+ [(set_attr "neon_type" "neon_bp_simple")]
23274
+)
23275
+
22752
"TARGET_NEON"
22753
{
22754
int dest = REGNO (operands[0]);
22755
@@ -2852,10 +3282,82 @@
22756
[(set_attr "neon_type" "neon_bp_simple")]
22757
)
22758
22759
-(define_insn "neon_vget_low<mode>"
22760
- [(set (match_operand:<V_HALF> 0 "s_register_operand" "=w")
22761
- (unspec:<V_HALF> [(match_operand:VQX 1 "s_register_operand" "w")]
22762
- UNSPEC_VGET_LOW))]
23276
22763
+(define_insn "neon_vget_lowv16qi"
23277
22764
+ [(set (match_operand:V8QI 0 "s_register_operand" "=w")
23278
22765
+ (vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w")
23352
22839
"TARGET_NEON"
23353
22840
{
23354
22841
int dest = REGNO (operands[0]);
23355
@@ -5048,3 +5552,205 @@
22842
@@ -3895,13 +4397,14 @@
22843
22844
(define_insn "neon_vtrn<mode>_internal"
22845
[(set (match_operand:VDQW 0 "s_register_operand" "=w")
22846
- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
22847
- UNSPEC_VTRN1))
22848
- (set (match_operand:VDQW 2 "s_register_operand" "=w")
22849
- (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
22850
- UNSPEC_VTRN2))]
22851
+ (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
22852
+ (match_operand:VDQW 2 "s_register_operand" "w")]
22853
+ UNSPEC_VTRN1))
22854
+ (set (match_operand:VDQW 3 "s_register_operand" "=2")
22855
+ (unspec:VDQW [(match_dup 1) (match_dup 2)]
22856
+ UNSPEC_VTRN2))]
22857
"TARGET_NEON"
22858
- "vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
22859
+ "vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
22860
[(set (attr "neon_type")
22861
(if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
22862
(const_string "neon_bp_simple")
22863
@@ -3921,13 +4424,14 @@
22864
22865
(define_insn "neon_vzip<mode>_internal"
22866
[(set (match_operand:VDQW 0 "s_register_operand" "=w")
22867
- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
22868
- UNSPEC_VZIP1))
22869
- (set (match_operand:VDQW 2 "s_register_operand" "=w")
22870
- (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
22871
- UNSPEC_VZIP2))]
22872
+ (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
22873
+ (match_operand:VDQW 2 "s_register_operand" "w")]
22874
+ UNSPEC_VZIP1))
22875
+ (set (match_operand:VDQW 3 "s_register_operand" "=2")
22876
+ (unspec:VDQW [(match_dup 1) (match_dup 2)]
22877
+ UNSPEC_VZIP2))]
22878
"TARGET_NEON"
22879
- "vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
22880
+ "vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
22881
[(set (attr "neon_type")
22882
(if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
22883
(const_string "neon_bp_simple")
22884
@@ -3947,13 +4451,14 @@
22885
22886
(define_insn "neon_vuzp<mode>_internal"
22887
[(set (match_operand:VDQW 0 "s_register_operand" "=w")
22888
- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
22889
+ (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
22890
+ (match_operand:VDQW 2 "s_register_operand" "w")]
22891
UNSPEC_VUZP1))
22892
- (set (match_operand:VDQW 2 "s_register_operand" "=w")
22893
- (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
22894
- UNSPEC_VUZP2))]
22895
+ (set (match_operand:VDQW 3 "s_register_operand" "=2")
22896
+ (unspec:VDQW [(match_dup 1) (match_dup 2)]
22897
+ UNSPEC_VUZP2))]
22898
"TARGET_NEON"
22899
- "vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
22900
+ "vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
22901
[(set (attr "neon_type")
22902
(if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
22903
(const_string "neon_bp_simple")
22904
@@ -4063,16 +4568,16 @@
22905
22906
(define_insn "neon_vld1<mode>"
22907
[(set (match_operand:VDQX 0 "s_register_operand" "=w")
22908
- (unspec:VDQX [(mem:VDQX (match_operand:SI 1 "s_register_operand" "r"))]
22909
+ (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_operand" "Um")]
22910
UNSPEC_VLD1))]
22911
"TARGET_NEON"
22912
- "vld1.<V_sz_elem>\t%h0, [%1]"
22913
+ "vld1.<V_sz_elem>\t%h0, %A1"
22914
[(set_attr "neon_type" "neon_vld1_1_2_regs")]
22915
)
22916
22917
(define_insn "neon_vld1_lane<mode>"
22918
[(set (match_operand:VDX 0 "s_register_operand" "=w")
22919
- (unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))
22920
+ (unspec:VDX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")
22921
(match_operand:VDX 2 "s_register_operand" "0")
22922
(match_operand:SI 3 "immediate_operand" "i")]
22923
UNSPEC_VLD1_LANE))]
22924
@@ -4083,9 +4588,9 @@
22925
if (lane < 0 || lane >= max)
22926
error ("lane out of range");
22927
if (max == 1)
22928
- return "vld1.<V_sz_elem>\t%P0, [%1]";
22929
+ return "vld1.<V_sz_elem>\t%P0, %A1";
22930
else
22931
- return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]";
22932
+ return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1";
22933
}
22934
[(set (attr "neon_type")
22935
(if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
22936
@@ -4095,7 +4600,7 @@
22937
22938
(define_insn "neon_vld1_lane<mode>"
22939
[(set (match_operand:VQX 0 "s_register_operand" "=w")
22940
- (unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))
22941
+ (unspec:VQX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")
22942
(match_operand:VQX 2 "s_register_operand" "0")
22943
(match_operand:SI 3 "immediate_operand" "i")]
22944
UNSPEC_VLD1_LANE))]
22945
@@ -4114,9 +4619,9 @@
22946
}
22947
operands[0] = gen_rtx_REG (<V_HALF>mode, regno);
22948
if (max == 2)
22949
- return "vld1.<V_sz_elem>\t%P0, [%1]";
22950
+ return "vld1.<V_sz_elem>\t%P0, %A1";
22951
else
22952
- return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]";
22953
+ return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1";
22954
}
22955
[(set (attr "neon_type")
22956
(if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
22957
@@ -4126,14 +4631,14 @@
22958
22959
(define_insn "neon_vld1_dup<mode>"
22960
[(set (match_operand:VDX 0 "s_register_operand" "=w")
22961
- (unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))]
22962
+ (unspec:VDX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")]
22963
UNSPEC_VLD1_DUP))]
22964
"TARGET_NEON"
22965
{
22966
if (GET_MODE_NUNITS (<MODE>mode) > 1)
22967
- return "vld1.<V_sz_elem>\t{%P0[]}, [%1]";
22968
+ return "vld1.<V_sz_elem>\t{%P0[]}, %A1";
22969
else
22970
- return "vld1.<V_sz_elem>\t%h0, [%1]";
22971
+ return "vld1.<V_sz_elem>\t%h0, %A1";
22972
}
22973
[(set (attr "neon_type")
22974
(if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
22975
@@ -4143,14 +4648,14 @@
22976
22977
(define_insn "neon_vld1_dup<mode>"
22978
[(set (match_operand:VQX 0 "s_register_operand" "=w")
22979
- (unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))]
22980
+ (unspec:VQX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")]
22981
UNSPEC_VLD1_DUP))]
22982
"TARGET_NEON"
22983
{
22984
if (GET_MODE_NUNITS (<MODE>mode) > 2)
22985
- return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, [%1]";
22986
+ return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, %A1";
22987
else
22988
- return "vld1.<V_sz_elem>\t%h0, [%1]";
22989
+ return "vld1.<V_sz_elem>\t%h0, %A1";
22990
}
22991
[(set (attr "neon_type")
22992
(if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
22993
@@ -4159,15 +4664,15 @@
22994
)
22995
22996
(define_insn "neon_vst1<mode>"
22997
- [(set (mem:VDQX (match_operand:SI 0 "s_register_operand" "r"))
22998
+ [(set (match_operand:VDQX 0 "neon_struct_operand" "=Um")
22999
(unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")]
23000
UNSPEC_VST1))]
23001
"TARGET_NEON"
23002
- "vst1.<V_sz_elem>\t%h1, [%0]"
23003
+ "vst1.<V_sz_elem>\t%h1, %A0"
23004
[(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")])
23005
23006
(define_insn "neon_vst1_lane<mode>"
23007
- [(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r"))
23008
+ [(set (match_operand:<V_elem> 0 "neon_struct_operand" "=Um")
23009
(vec_select:<V_elem>
23010
(match_operand:VDX 1 "s_register_operand" "w")
23011
(parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
23012
@@ -4178,9 +4683,9 @@
23013
if (lane < 0 || lane >= max)
23014
error ("lane out of range");
23015
if (max == 1)
23016
- return "vst1.<V_sz_elem>\t{%P1}, [%0]";
23017
+ return "vst1.<V_sz_elem>\t{%P1}, %A0";
23018
else
23019
- return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]";
23020
+ return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0";
23021
}
23022
[(set (attr "neon_type")
23023
(if_then_else (eq (const_string "<V_mode_nunits>") (const_int 1))
23024
@@ -4188,7 +4693,7 @@
23025
(const_string "neon_vst1_vst2_lane")))])
23026
23027
(define_insn "neon_vst1_lane<mode>"
23028
- [(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r"))
23029
+ [(set (match_operand:<V_elem> 0 "neon_struct_operand" "=Um")
23030
(vec_select:<V_elem>
23031
(match_operand:VQX 1 "s_register_operand" "w")
23032
(parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
23033
@@ -4207,24 +4712,24 @@
23034
}
23035
operands[1] = gen_rtx_REG (<V_HALF>mode, regno);
23036
if (max == 2)
23037
- return "vst1.<V_sz_elem>\t{%P1}, [%0]";
23038
+ return "vst1.<V_sz_elem>\t{%P1}, %A0";
23039
else
23040
- return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]";
23041
+ return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0";
23042
}
23043
[(set_attr "neon_type" "neon_vst1_vst2_lane")]
23044
)
23045
23046
(define_insn "neon_vld2<mode>"
23047
[(set (match_operand:TI 0 "s_register_operand" "=w")
23048
- (unspec:TI [(mem:TI (match_operand:SI 1 "s_register_operand" "r"))
23049
+ (unspec:TI [(match_operand:TI 1 "neon_struct_operand" "Um")
23050
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23051
UNSPEC_VLD2))]
23052
"TARGET_NEON"
23053
{
23054
if (<V_sz_elem> == 64)
23055
- return "vld1.64\t%h0, [%1]";
23056
+ return "vld1.64\t%h0, %A1";
23057
else
23058
- return "vld2.<V_sz_elem>\t%h0, [%1]";
23059
+ return "vld2.<V_sz_elem>\t%h0, %A1";
23060
}
23061
[(set (attr "neon_type")
23062
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
23063
@@ -4234,16 +4739,16 @@
23064
23065
(define_insn "neon_vld2<mode>"
23066
[(set (match_operand:OI 0 "s_register_operand" "=w")
23067
- (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r"))
23068
+ (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
23069
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23070
UNSPEC_VLD2))]
23071
"TARGET_NEON"
23072
- "vld2.<V_sz_elem>\t%h0, [%1]"
23073
+ "vld2.<V_sz_elem>\t%h0, %A1"
23074
[(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")])
23075
23076
(define_insn "neon_vld2_lane<mode>"
23077
[(set (match_operand:TI 0 "s_register_operand" "=w")
23078
- (unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
23079
+ (unspec:TI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
23080
(match_operand:TI 2 "s_register_operand" "0")
23081
(match_operand:SI 3 "immediate_operand" "i")
23082
(unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23083
@@ -4260,7 +4765,7 @@
23084
ops[1] = gen_rtx_REG (DImode, regno + 2);
23085
ops[2] = operands[1];
23086
ops[3] = operands[3];
23087
- output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops);
23088
+ output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
23089
return "";
23090
}
23091
[(set_attr "neon_type" "neon_vld1_vld2_lane")]
23092
@@ -4268,7 +4773,7 @@
23093
23094
(define_insn "neon_vld2_lane<mode>"
23095
[(set (match_operand:OI 0 "s_register_operand" "=w")
23096
- (unspec:OI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
23097
+ (unspec:OI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
23098
(match_operand:OI 2 "s_register_operand" "0")
23099
(match_operand:SI 3 "immediate_operand" "i")
23100
(unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23101
@@ -4290,7 +4795,7 @@
23102
ops[1] = gen_rtx_REG (DImode, regno + 4);
23103
ops[2] = operands[1];
23104
ops[3] = GEN_INT (lane);
23105
- output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops);
23106
+ output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
23107
return "";
23108
}
23109
[(set_attr "neon_type" "neon_vld1_vld2_lane")]
23110
@@ -4298,15 +4803,15 @@
23111
23112
(define_insn "neon_vld2_dup<mode>"
23113
[(set (match_operand:TI 0 "s_register_operand" "=w")
23114
- (unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
23115
+ (unspec:TI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
23116
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23117
UNSPEC_VLD2_DUP))]
23118
"TARGET_NEON"
23119
{
23120
if (GET_MODE_NUNITS (<MODE>mode) > 1)
23121
- return "vld2.<V_sz_elem>\t{%e0[], %f0[]}, [%1]";
23122
+ return "vld2.<V_sz_elem>\t{%e0[], %f0[]}, %A1";
23123
else
23124
- return "vld1.<V_sz_elem>\t%h0, [%1]";
23125
+ return "vld1.<V_sz_elem>\t%h0, %A1";
23126
}
23127
[(set (attr "neon_type")
23128
(if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
23129
@@ -4315,16 +4820,16 @@
23130
)
23131
23132
(define_insn "neon_vst2<mode>"
23133
- [(set (mem:TI (match_operand:SI 0 "s_register_operand" "r"))
23134
+ [(set (match_operand:TI 0 "neon_struct_operand" "=Um")
23135
(unspec:TI [(match_operand:TI 1 "s_register_operand" "w")
23136
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23137
UNSPEC_VST2))]
23138
"TARGET_NEON"
23139
{
23140
if (<V_sz_elem> == 64)
23141
- return "vst1.64\t%h1, [%0]";
23142
+ return "vst1.64\t%h1, %A0";
23143
else
23144
- return "vst2.<V_sz_elem>\t%h1, [%0]";
23145
+ return "vst2.<V_sz_elem>\t%h1, %A0";
23146
}
23147
[(set (attr "neon_type")
23148
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
23149
@@ -4333,17 +4838,17 @@
23150
)
23151
23152
(define_insn "neon_vst2<mode>"
23153
- [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r"))
23154
+ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
23155
(unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
23156
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23157
UNSPEC_VST2))]
23158
"TARGET_NEON"
23159
- "vst2.<V_sz_elem>\t%h1, [%0]"
23160
+ "vst2.<V_sz_elem>\t%h1, %A0"
23161
[(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]
23162
)
23163
23164
(define_insn "neon_vst2_lane<mode>"
23165
- [(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r"))
23166
+ [(set (match_operand:<V_two_elem> 0 "neon_struct_operand" "=Um")
23167
(unspec:<V_two_elem>
23168
[(match_operand:TI 1 "s_register_operand" "w")
23169
(match_operand:SI 2 "immediate_operand" "i")
23170
@@ -4361,14 +4866,14 @@
23171
ops[1] = gen_rtx_REG (DImode, regno);
23172
ops[2] = gen_rtx_REG (DImode, regno + 2);
23173
ops[3] = operands[2];
23174
- output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops);
23175
+ output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
23176
return "";
23177
}
23178
[(set_attr "neon_type" "neon_vst1_vst2_lane")]
23179
)
23180
23181
(define_insn "neon_vst2_lane<mode>"
23182
- [(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r"))
23183
+ [(set (match_operand:<V_two_elem> 0 "neon_struct_operand" "=Um")
23184
(unspec:<V_two_elem>
23185
[(match_operand:OI 1 "s_register_operand" "w")
23186
(match_operand:SI 2 "immediate_operand" "i")
23187
@@ -4391,7 +4896,7 @@
23188
ops[1] = gen_rtx_REG (DImode, regno);
23189
ops[2] = gen_rtx_REG (DImode, regno + 4);
23190
ops[3] = GEN_INT (lane);
23191
- output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops);
23192
+ output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
23193
return "";
23194
}
23195
[(set_attr "neon_type" "neon_vst1_vst2_lane")]
23196
@@ -4399,15 +4904,15 @@
23197
23198
(define_insn "neon_vld3<mode>"
23199
[(set (match_operand:EI 0 "s_register_operand" "=w")
23200
- (unspec:EI [(mem:EI (match_operand:SI 1 "s_register_operand" "r"))
23201
+ (unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um")
23202
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23203
UNSPEC_VLD3))]
23204
"TARGET_NEON"
23205
{
23206
if (<V_sz_elem> == 64)
23207
- return "vld1.64\t%h0, [%1]";
23208
+ return "vld1.64\t%h0, %A1";
23209
else
23210
- return "vld3.<V_sz_elem>\t%h0, [%1]";
23211
+ return "vld3.<V_sz_elem>\t%h0, %A1";
23212
}
23213
[(set (attr "neon_type")
23214
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
23215
@@ -4416,27 +4921,25 @@
23216
)
23217
23218
(define_expand "neon_vld3<mode>"
23219
- [(match_operand:CI 0 "s_register_operand" "=w")
23220
- (match_operand:SI 1 "s_register_operand" "+r")
23221
+ [(match_operand:CI 0 "s_register_operand")
23222
+ (match_operand:CI 1 "neon_struct_operand")
23223
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23224
"TARGET_NEON"
23225
{
23226
- emit_insn (gen_neon_vld3qa<mode> (operands[0], operands[0],
23227
- operands[1], operands[1]));
23228
- emit_insn (gen_neon_vld3qb<mode> (operands[0], operands[0],
23229
- operands[1], operands[1]));
23230
+ rtx mem;
23231
+
23232
+ mem = adjust_address (operands[1], EImode, 0);
23233
+ emit_insn (gen_neon_vld3qa<mode> (operands[0], mem));
23234
+ mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode));
23235
+ emit_insn (gen_neon_vld3qb<mode> (operands[0], mem, operands[0]));
23236
DONE;
23237
})
23238
23239
(define_insn "neon_vld3qa<mode>"
23240
[(set (match_operand:CI 0 "s_register_operand" "=w")
23241
- (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2"))
23242
- (match_operand:CI 1 "s_register_operand" "0")
23243
+ (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
23244
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23245
- UNSPEC_VLD3A))
23246
- (set (match_operand:SI 2 "s_register_operand" "=r")
23247
- (plus:SI (match_dup 3)
23248
- (const_int 24)))]
23249
+ UNSPEC_VLD3A))]
23250
"TARGET_NEON"
23251
{
23252
int regno = REGNO (operands[0]);
23253
@@ -4444,8 +4947,8 @@
23254
ops[0] = gen_rtx_REG (DImode, regno);
23255
ops[1] = gen_rtx_REG (DImode, regno + 4);
23256
ops[2] = gen_rtx_REG (DImode, regno + 8);
23257
- ops[3] = operands[2];
23258
- output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops);
23259
+ ops[3] = operands[1];
23260
+ output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops);
23261
return "";
23262
}
23263
[(set_attr "neon_type" "neon_vld3_vld4")]
23264
@@ -4453,13 +4956,10 @@
23265
23266
(define_insn "neon_vld3qb<mode>"
23267
[(set (match_operand:CI 0 "s_register_operand" "=w")
23268
- (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2"))
23269
- (match_operand:CI 1 "s_register_operand" "0")
23270
+ (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
23271
+ (match_operand:CI 2 "s_register_operand" "0")
23272
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23273
- UNSPEC_VLD3B))
23274
- (set (match_operand:SI 2 "s_register_operand" "=r")
23275
- (plus:SI (match_dup 3)
23276
- (const_int 24)))]
23277
+ UNSPEC_VLD3B))]
23278
"TARGET_NEON"
23279
{
23280
int regno = REGNO (operands[0]);
23281
@@ -4467,8 +4967,8 @@
23282
ops[0] = gen_rtx_REG (DImode, regno + 2);
23283
ops[1] = gen_rtx_REG (DImode, regno + 6);
23284
ops[2] = gen_rtx_REG (DImode, regno + 10);
23285
- ops[3] = operands[2];
23286
- output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops);
23287
+ ops[3] = operands[1];
23288
+ output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops);
23289
return "";
23290
}
23291
[(set_attr "neon_type" "neon_vld3_vld4")]
23292
@@ -4476,7 +4976,7 @@
23293
23294
(define_insn "neon_vld3_lane<mode>"
23295
[(set (match_operand:EI 0 "s_register_operand" "=w")
23296
- (unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
23297
+ (unspec:EI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
23298
(match_operand:EI 2 "s_register_operand" "0")
23299
(match_operand:SI 3 "immediate_operand" "i")
23300
(unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23301
@@ -4494,7 +4994,7 @@
23302
ops[2] = gen_rtx_REG (DImode, regno + 4);
23303
ops[3] = operands[1];
23304
ops[4] = operands[3];
23305
- output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]",
23306
+ output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
23307
ops);
23308
return "";
23309
}
23310
@@ -4503,7 +5003,7 @@
23311
23312
(define_insn "neon_vld3_lane<mode>"
23313
[(set (match_operand:CI 0 "s_register_operand" "=w")
23314
- (unspec:CI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
23315
+ (unspec:CI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
23316
(match_operand:CI 2 "s_register_operand" "0")
23317
(match_operand:SI 3 "immediate_operand" "i")
23318
(unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23319
@@ -4526,7 +5026,7 @@
23320
ops[2] = gen_rtx_REG (DImode, regno + 8);
23321
ops[3] = operands[1];
23322
ops[4] = GEN_INT (lane);
23323
- output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]",
23324
+ output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
23325
ops);
23326
return "";
23327
}
23328
@@ -4535,7 +5035,7 @@
23329
23330
(define_insn "neon_vld3_dup<mode>"
23331
[(set (match_operand:EI 0 "s_register_operand" "=w")
23332
- (unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
23333
+ (unspec:EI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
23334
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23335
UNSPEC_VLD3_DUP))]
23336
"TARGET_NEON"
23337
@@ -4548,11 +5048,11 @@
23338
ops[1] = gen_rtx_REG (DImode, regno + 2);
23339
ops[2] = gen_rtx_REG (DImode, regno + 4);
23340
ops[3] = operands[1];
23341
- output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, [%3]", ops);
23342
+ output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, %A3", ops);
23343
return "";
23344
}
23345
else
23346
- return "vld1.<V_sz_elem>\t%h0, [%1]";
23347
+ return "vld1.<V_sz_elem>\t%h0, %A1";
23348
}
23349
[(set (attr "neon_type")
23350
(if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
23351
@@ -4560,16 +5060,16 @@
23352
(const_string "neon_vld1_1_2_regs")))])
23353
23354
(define_insn "neon_vst3<mode>"
23355
- [(set (mem:EI (match_operand:SI 0 "s_register_operand" "r"))
23356
+ [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
23357
(unspec:EI [(match_operand:EI 1 "s_register_operand" "w")
23358
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23359
UNSPEC_VST3))]
23360
"TARGET_NEON"
23361
{
23362
if (<V_sz_elem> == 64)
23363
- return "vst1.64\t%h1, [%0]";
23364
+ return "vst1.64\t%h1, %A0";
23365
else
23366
- return "vst3.<V_sz_elem>\t%h1, [%0]";
23367
+ return "vst3.<V_sz_elem>\t%h1, %A0";
23368
}
23369
[(set (attr "neon_type")
23370
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
23371
@@ -4577,62 +5077,60 @@
23372
(const_string "neon_vst2_4_regs_vst3_vst4")))])
23373
23374
(define_expand "neon_vst3<mode>"
23375
- [(match_operand:SI 0 "s_register_operand" "+r")
23376
- (match_operand:CI 1 "s_register_operand" "w")
23377
+ [(match_operand:CI 0 "neon_struct_operand")
23378
+ (match_operand:CI 1 "s_register_operand")
23379
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23380
"TARGET_NEON"
23381
{
23382
- emit_insn (gen_neon_vst3qa<mode> (operands[0], operands[0], operands[1]));
23383
- emit_insn (gen_neon_vst3qb<mode> (operands[0], operands[0], operands[1]));
23384
+ rtx mem;
23385
+
23386
+ mem = adjust_address (operands[0], EImode, 0);
23387
+ emit_insn (gen_neon_vst3qa<mode> (mem, operands[1]));
23388
+ mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode));
23389
+ emit_insn (gen_neon_vst3qb<mode> (mem, operands[1]));
23390
DONE;
23391
})
23392
23393
(define_insn "neon_vst3qa<mode>"
23394
- [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0"))
23395
- (unspec:EI [(match_operand:CI 2 "s_register_operand" "w")
23396
+ [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
23397
+ (unspec:EI [(match_operand:CI 1 "s_register_operand" "w")
23398
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23399
- UNSPEC_VST3A))
23400
- (set (match_operand:SI 0 "s_register_operand" "=r")
23401
- (plus:SI (match_dup 1)
23402
- (const_int 24)))]
23403
+ UNSPEC_VST3A))]
23404
"TARGET_NEON"
23405
{
23406
- int regno = REGNO (operands[2]);
23407
+ int regno = REGNO (operands[1]);
23408
rtx ops[4];
23409
ops[0] = operands[0];
23410
ops[1] = gen_rtx_REG (DImode, regno);
23411
ops[2] = gen_rtx_REG (DImode, regno + 4);
23412
ops[3] = gen_rtx_REG (DImode, regno + 8);
23413
- output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops);
23414
+ output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops);
23415
return "";
23416
}
23417
[(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
23418
)
23419
23420
(define_insn "neon_vst3qb<mode>"
23421
- [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0"))
23422
- (unspec:EI [(match_operand:CI 2 "s_register_operand" "w")
23423
+ [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
23424
+ (unspec:EI [(match_operand:CI 1 "s_register_operand" "w")
23425
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23426
- UNSPEC_VST3B))
23427
- (set (match_operand:SI 0 "s_register_operand" "=r")
23428
- (plus:SI (match_dup 1)
23429
- (const_int 24)))]
23430
+ UNSPEC_VST3B))]
23431
"TARGET_NEON"
23432
{
23433
- int regno = REGNO (operands[2]);
23434
+ int regno = REGNO (operands[1]);
23435
rtx ops[4];
23436
ops[0] = operands[0];
23437
ops[1] = gen_rtx_REG (DImode, regno + 2);
23438
ops[2] = gen_rtx_REG (DImode, regno + 6);
23439
ops[3] = gen_rtx_REG (DImode, regno + 10);
23440
- output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops);
23441
+ output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops);
23442
return "";
23443
}
23444
[(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
23445
)
23446
23447
(define_insn "neon_vst3_lane<mode>"
23448
- [(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r"))
23449
+ [(set (match_operand:<V_three_elem> 0 "neon_struct_operand" "=Um")
23450
(unspec:<V_three_elem>
23451
[(match_operand:EI 1 "s_register_operand" "w")
23452
(match_operand:SI 2 "immediate_operand" "i")
23453
@@ -4651,7 +5149,7 @@
23454
ops[2] = gen_rtx_REG (DImode, regno + 2);
23455
ops[3] = gen_rtx_REG (DImode, regno + 4);
23456
ops[4] = operands[2];
23457
- output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]",
23458
+ output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
23459
ops);
23460
return "";
23461
}
23462
@@ -4659,7 +5157,7 @@
23463
)
23464
23465
(define_insn "neon_vst3_lane<mode>"
23466
- [(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r"))
23467
+ [(set (match_operand:<V_three_elem> 0 "neon_struct_operand" "=Um")
23468
(unspec:<V_three_elem>
23469
[(match_operand:CI 1 "s_register_operand" "w")
23470
(match_operand:SI 2 "immediate_operand" "i")
23471
@@ -4683,7 +5181,7 @@
23472
ops[2] = gen_rtx_REG (DImode, regno + 4);
23473
ops[3] = gen_rtx_REG (DImode, regno + 8);
23474
ops[4] = GEN_INT (lane);
23475
- output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]",
23476
+ output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
23477
ops);
23478
return "";
23479
}
23480
@@ -4691,15 +5189,15 @@
23481
23482
(define_insn "neon_vld4<mode>"
23483
[(set (match_operand:OI 0 "s_register_operand" "=w")
23484
- (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r"))
23485
+ (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
23486
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23487
UNSPEC_VLD4))]
23488
"TARGET_NEON"
23489
{
23490
if (<V_sz_elem> == 64)
23491
- return "vld1.64\t%h0, [%1]";
23492
+ return "vld1.64\t%h0, %A1";
23493
else
23494
- return "vld4.<V_sz_elem>\t%h0, [%1]";
23495
+ return "vld4.<V_sz_elem>\t%h0, %A1";
23496
}
23497
[(set (attr "neon_type")
23498
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
23499
@@ -4708,27 +5206,25 @@
23500
)
23501
23502
(define_expand "neon_vld4<mode>"
23503
- [(match_operand:XI 0 "s_register_operand" "=w")
23504
- (match_operand:SI 1 "s_register_operand" "+r")
23505
+ [(match_operand:XI 0 "s_register_operand")
23506
+ (match_operand:XI 1 "neon_struct_operand")
23507
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23508
"TARGET_NEON"
23509
{
23510
- emit_insn (gen_neon_vld4qa<mode> (operands[0], operands[0],
23511
- operands[1], operands[1]));
23512
- emit_insn (gen_neon_vld4qb<mode> (operands[0], operands[0],
23513
- operands[1], operands[1]));
23514
+ rtx mem;
23515
+
23516
+ mem = adjust_address (operands[1], OImode, 0);
23517
+ emit_insn (gen_neon_vld4qa<mode> (operands[0], mem));
23518
+ mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode));
23519
+ emit_insn (gen_neon_vld4qb<mode> (operands[0], mem, operands[0]));
23520
DONE;
23521
})
23522
23523
(define_insn "neon_vld4qa<mode>"
23524
[(set (match_operand:XI 0 "s_register_operand" "=w")
23525
- (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2"))
23526
- (match_operand:XI 1 "s_register_operand" "0")
23527
+ (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
23528
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23529
- UNSPEC_VLD4A))
23530
- (set (match_operand:SI 2 "s_register_operand" "=r")
23531
- (plus:SI (match_dup 3)
23532
- (const_int 32)))]
23533
+ UNSPEC_VLD4A))]
23534
"TARGET_NEON"
23535
{
23536
int regno = REGNO (operands[0]);
23537
@@ -4737,8 +5233,8 @@
23538
ops[1] = gen_rtx_REG (DImode, regno + 4);
23539
ops[2] = gen_rtx_REG (DImode, regno + 8);
23540
ops[3] = gen_rtx_REG (DImode, regno + 12);
23541
- ops[4] = operands[2];
23542
- output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops);
23543
+ ops[4] = operands[1];
23544
+ output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops);
23545
return "";
23546
}
23547
[(set_attr "neon_type" "neon_vld3_vld4")]
23548
@@ -4746,13 +5242,10 @@
23549
23550
(define_insn "neon_vld4qb<mode>"
23551
[(set (match_operand:XI 0 "s_register_operand" "=w")
23552
- (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2"))
23553
- (match_operand:XI 1 "s_register_operand" "0")
23554
+ (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
23555
+ (match_operand:XI 2 "s_register_operand" "0")
23556
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23557
- UNSPEC_VLD4B))
23558
- (set (match_operand:SI 2 "s_register_operand" "=r")
23559
- (plus:SI (match_dup 3)
23560
- (const_int 32)))]
23561
+ UNSPEC_VLD4B))]
23562
"TARGET_NEON"
23563
{
23564
int regno = REGNO (operands[0]);
23565
@@ -4761,8 +5254,8 @@
23566
ops[1] = gen_rtx_REG (DImode, regno + 6);
23567
ops[2] = gen_rtx_REG (DImode, regno + 10);
23568
ops[3] = gen_rtx_REG (DImode, regno + 14);
23569
- ops[4] = operands[2];
23570
- output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops);
23571
+ ops[4] = operands[1];
23572
+ output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops);
23573
return "";
23574
}
23575
[(set_attr "neon_type" "neon_vld3_vld4")]
23576
@@ -4770,7 +5263,7 @@
23577
23578
(define_insn "neon_vld4_lane<mode>"
23579
[(set (match_operand:OI 0 "s_register_operand" "=w")
23580
- (unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
23581
+ (unspec:OI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
23582
(match_operand:OI 2 "s_register_operand" "0")
23583
(match_operand:SI 3 "immediate_operand" "i")
23584
(unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23585
@@ -4789,7 +5282,7 @@
23586
ops[3] = gen_rtx_REG (DImode, regno + 6);
23587
ops[4] = operands[1];
23588
ops[5] = operands[3];
23589
- output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]",
23590
+ output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4",
23591
ops);
23592
return "";
23593
}
23594
@@ -4798,7 +5291,7 @@
23595
23596
(define_insn "neon_vld4_lane<mode>"
23597
[(set (match_operand:XI 0 "s_register_operand" "=w")
23598
- (unspec:XI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
23599
+ (unspec:XI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
23600
(match_operand:XI 2 "s_register_operand" "0")
23601
(match_operand:SI 3 "immediate_operand" "i")
23602
(unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23603
@@ -4822,7 +5315,7 @@
23604
ops[3] = gen_rtx_REG (DImode, regno + 12);
23605
ops[4] = operands[1];
23606
ops[5] = GEN_INT (lane);
23607
- output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]",
23608
+ output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4",
23609
ops);
23610
return "";
23611
}
23612
@@ -4831,7 +5324,7 @@
23613
23614
(define_insn "neon_vld4_dup<mode>"
23615
[(set (match_operand:OI 0 "s_register_operand" "=w")
23616
- (unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
23617
+ (unspec:OI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
23618
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23619
UNSPEC_VLD4_DUP))]
23620
"TARGET_NEON"
23621
@@ -4845,12 +5338,12 @@
23622
ops[2] = gen_rtx_REG (DImode, regno + 4);
23623
ops[3] = gen_rtx_REG (DImode, regno + 6);
23624
ops[4] = operands[1];
23625
- output_asm_insn ("vld4.<V_sz_elem>\t{%P0[], %P1[], %P2[], %P3[]}, [%4]",
23626
+ output_asm_insn ("vld4.<V_sz_elem>\t{%P0[], %P1[], %P2[], %P3[]}, %A4",
23627
ops);
23628
return "";
23629
}
23630
else
23631
- return "vld1.<V_sz_elem>\t%h0, [%1]";
23632
+ return "vld1.<V_sz_elem>\t%h0, %A1";
23633
}
23634
[(set (attr "neon_type")
23635
(if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
23636
@@ -4859,16 +5352,16 @@
23637
)
23638
23639
(define_insn "neon_vst4<mode>"
23640
- [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r"))
23641
+ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
23642
(unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
23643
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23644
UNSPEC_VST4))]
23645
"TARGET_NEON"
23646
{
23647
if (<V_sz_elem> == 64)
23648
- return "vst1.64\t%h1, [%0]";
23649
+ return "vst1.64\t%h1, %A0";
23650
else
23651
- return "vst4.<V_sz_elem>\t%h1, [%0]";
23652
+ return "vst4.<V_sz_elem>\t%h1, %A0";
23653
}
23654
[(set (attr "neon_type")
23655
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
23656
@@ -4877,64 +5370,62 @@
23657
)
23658
23659
(define_expand "neon_vst4<mode>"
23660
- [(match_operand:SI 0 "s_register_operand" "+r")
23661
- (match_operand:XI 1 "s_register_operand" "w")
23662
+ [(match_operand:XI 0 "neon_struct_operand")
23663
+ (match_operand:XI 1 "s_register_operand")
23664
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23665
"TARGET_NEON"
23666
{
23667
- emit_insn (gen_neon_vst4qa<mode> (operands[0], operands[0], operands[1]));
23668
- emit_insn (gen_neon_vst4qb<mode> (operands[0], operands[0], operands[1]));
23669
+ rtx mem;
23670
+
23671
+ mem = adjust_address (operands[0], OImode, 0);
23672
+ emit_insn (gen_neon_vst4qa<mode> (mem, operands[1]));
23673
+ mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode));
23674
+ emit_insn (gen_neon_vst4qb<mode> (mem, operands[1]));
23675
DONE;
23676
})
23677
23678
(define_insn "neon_vst4qa<mode>"
23679
- [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0"))
23680
- (unspec:OI [(match_operand:XI 2 "s_register_operand" "w")
23681
+ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
23682
+ (unspec:OI [(match_operand:XI 1 "s_register_operand" "w")
23683
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23684
- UNSPEC_VST4A))
23685
- (set (match_operand:SI 0 "s_register_operand" "=r")
23686
- (plus:SI (match_dup 1)
23687
- (const_int 32)))]
23688
+ UNSPEC_VST4A))]
23689
"TARGET_NEON"
23690
{
23691
- int regno = REGNO (operands[2]);
23692
+ int regno = REGNO (operands[1]);
23693
rtx ops[5];
23694
ops[0] = operands[0];
23695
ops[1] = gen_rtx_REG (DImode, regno);
23696
ops[2] = gen_rtx_REG (DImode, regno + 4);
23697
ops[3] = gen_rtx_REG (DImode, regno + 8);
23698
ops[4] = gen_rtx_REG (DImode, regno + 12);
23699
- output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops);
23700
+ output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
23701
return "";
23702
}
23703
[(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
23704
)
23705
23706
(define_insn "neon_vst4qb<mode>"
23707
- [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0"))
23708
- (unspec:OI [(match_operand:XI 2 "s_register_operand" "w")
23709
+ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
23710
+ (unspec:OI [(match_operand:XI 1 "s_register_operand" "w")
23711
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
23712
- UNSPEC_VST4B))
23713
- (set (match_operand:SI 0 "s_register_operand" "=r")
23714
- (plus:SI (match_dup 1)
23715
- (const_int 32)))]
23716
+ UNSPEC_VST4B))]
23717
"TARGET_NEON"
23718
{
23719
- int regno = REGNO (operands[2]);
23720
+ int regno = REGNO (operands[1]);
23721
rtx ops[5];
23722
ops[0] = operands[0];
23723
ops[1] = gen_rtx_REG (DImode, regno + 2);
23724
ops[2] = gen_rtx_REG (DImode, regno + 6);
23725
ops[3] = gen_rtx_REG (DImode, regno + 10);
23726
ops[4] = gen_rtx_REG (DImode, regno + 14);
23727
- output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops);
23728
+ output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
23729
return "";
23730
}
23731
[(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
23732
)
23733
23734
(define_insn "neon_vst4_lane<mode>"
23735
- [(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r"))
23736
+ [(set (match_operand:<V_four_elem> 0 "neon_struct_operand" "=Um")
23737
(unspec:<V_four_elem>
23738
[(match_operand:OI 1 "s_register_operand" "w")
23739
(match_operand:SI 2 "immediate_operand" "i")
23740
@@ -4954,7 +5445,7 @@
23741
ops[3] = gen_rtx_REG (DImode, regno + 4);
23742
ops[4] = gen_rtx_REG (DImode, regno + 6);
23743
ops[5] = operands[2];
23744
- output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]",
23745
+ output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0",
23746
ops);
23747
return "";
23748
}
23749
@@ -4962,7 +5453,7 @@
23750
)
23751
23752
(define_insn "neon_vst4_lane<mode>"
23753
- [(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r"))
23754
+ [(set (match_operand:<V_four_elem> 0 "neon_struct_operand" "=Um")
23755
(unspec:<V_four_elem>
23756
[(match_operand:XI 1 "s_register_operand" "w")
23757
(match_operand:SI 2 "immediate_operand" "i")
23758
@@ -4987,7 +5478,7 @@
23759
ops[3] = gen_rtx_REG (DImode, regno + 8);
23760
ops[4] = gen_rtx_REG (DImode, regno + 12);
23761
ops[5] = GEN_INT (lane);
23762
- output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]",
23763
+ output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0",
23764
ops);
23765
return "";
23766
}
23767
@@ -5048,3 +5539,205 @@
23356
23768
emit_insn (gen_orn<mode>3_neon (operands[0], operands[1], operands[2]));
23357
23769
DONE;
23358
23770
})
23912
24324
})
23913
24325
23914
24326
(define_predicate "neon_logic_op2"
23915
@@ -534,5 +607,77 @@
23916
;; TODO: We could check lane numbers more precisely based on the mode.
23917
(define_predicate "neon_lane_number"
24327
@@ -536,3 +609,79 @@
23918
24328
(and (match_code "const_int")
23919
- (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
23920
+ (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15")))
23921
+
24329
(match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15")))
24330
23922
24331
+;; Predicates for named expanders that overlap multiple ISAs.
23923
24332
+
23924
24333
+(define_predicate "cmpdi_operand"
23976
24385
+
23977
24386
+ if (!VECTOR_MODE_P (mode))
23978
24387
+ return false;
23979
24388
+
23980
24389
+ for (i = 0; i < count; i++)
23981
24390
+ {
23982
24391
+ rtx elt = XVECEXP (op, 0, i);
23991
24400
+ }
23992
24401
+ return true;
23993
24402
+})
24403
+
24404
+(define_special_predicate "neon_struct_operand"
24405
+ (and (match_code "mem")
24406
+ (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
23994
24407
--- a/src/gcc/config/arm/sfp-machine.h
23995
24408
+++ b/src/gcc/config/arm/sfp-machine.h
23996
24409
@@ -99,7 +99,7 @@
25422
25835
)
25423
25836
25424
25837
(define_insn "*cmpdf_vfp"
25425
--- a/src/gcc/config/avr/avr.c
25426
+++ b/src/gcc/config/avr/avr.c
25427
@@ -73,6 +73,7 @@
25428
static bool avr_legitimate_address_p (enum machine_mode, rtx, bool);
25429
static void avr_asm_function_end_prologue (FILE *);
25430
static void avr_asm_function_begin_epilogue (FILE *);
25431
+static bool avr_cannot_modify_jumps_p (void);
25432
static rtx avr_function_value (const_tree, const_tree, bool);
25433
static void avr_insert_attributes (tree, tree *);
25434
static void avr_asm_init_sections (void);
25435
@@ -91,6 +92,7 @@
25436
static unsigned int avr_case_values_threshold (void);
25437
static bool avr_frame_pointer_required_p (void);
25438
static bool avr_can_eliminate (const int, const int);
25439
+static void avr_help (void);
25440
25441
/* Allocate registers from r25 to r8 for parameters for function calls. */
25442
#define FIRST_CUM_REG 26
25443
@@ -192,6 +194,12 @@
25444
#undef TARGET_CAN_ELIMINATE
25445
#define TARGET_CAN_ELIMINATE avr_can_eliminate
25446
25447
+#undef TARGET_HELP
25448
+#define TARGET_HELP avr_help
25449
+
25450
+#undef TARGET_CANNOT_MODIFY_JUMPS_P
25451
+#define TARGET_CANNOT_MODIFY_JUMPS_P avr_cannot_modify_jumps_p
25452
+
25453
struct gcc_target targetm = TARGET_INITIALIZER;
25454
25455
void
25456
@@ -207,10 +215,8 @@
25457
25458
if (!t->name)
25459
{
25460
- fprintf (stderr, "unknown MCU '%s' specified\nKnown MCU names:\n",
25461
- avr_mcu_name);
25462
- for (t = avr_mcu_types; t->name; t++)
25463
- fprintf (stderr," %s\n", t->name);
25464
+ error ("unrecognized argument to -mmcu= option: %qs", avr_mcu_name);
25465
+ inform (input_location, "See --target-help for supported MCUs");
25466
}
25467
25468
avr_current_device = t;
25469
@@ -223,6 +229,42 @@
25470
init_machine_status = avr_init_machine_status;
25471
}
25472
25473
+/* Implement TARGET_HELP */
25474
+/* Report extra information for --target-help */
25475
+
25476
+static void
25477
+avr_help (void)
25478
+{
25479
+ const struct mcu_type_s *t;
25480
+ const char * const indent = " ";
25481
+ int len;
25482
+
25483
+ /* Give a list of MCUs that are accepted by -mmcu=* .
25484
+ Note that MCUs supported by the compiler might differ from
25485
+ MCUs supported by binutils. */
25486
+
25487
+ len = strlen (indent);
25488
+ printf ("Known MCU names:\n%s", indent);
25489
+
25490
+ /* Print a blank-separated list of all supported MCUs */
25491
+
25492
+ for (t = avr_mcu_types; t->name; t++)
25493
+ {
25494
+ printf ("%s ", t->name);
25495
+ len += 1 + strlen (t->name);
25496
+
25497
+ /* Break long lines */
25498
+
25499
+ if (len > 66 && (t+1)->name)
25500
+ {
25501
+ printf ("\n%s", indent);
25502
+ len = strlen (indent);
25503
+ }
25504
+ }
25505
+
25506
+ printf ("\n\n");
25507
+}
25508
+
25509
/* return register class from register number. */
25510
25511
static const enum reg_class reg_class_tab[]={
25512
@@ -953,6 +995,27 @@
25513
fprintf (file, "/* epilogue start */\n");
25514
}
25515
25516
+
25517
+/* Implement TARGET_CANNOT_MODITY_JUMPS_P */
25518
+
25519
+static bool
25520
+avr_cannot_modify_jumps_p (void)
25521
+{
25522
+
25523
+ /* Naked Functions must not have any instructions after
25524
+ their epilogue, see PR42240 */
25525
+
25526
+ if (reload_completed
25527
+ && cfun->machine
25528
+ && cfun->machine->is_naked)
25529
+ {
25530
+ return true;
25531
+ }
25532
+
25533
+ return false;
25534
+}
25535
+
25536
+
25537
/* Return nonzero if X (an RTX) is a legitimate memory address on the target
25538
machine for a memory operand of mode MODE. */
25539
25540
25838
--- a/src/gcc/config/avr/avr.h
25541
25839
+++ b/src/gcc/config/avr/avr.h
25542
25840
@@ -232,7 +232,7 @@
25570
25868
25571
25869
CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack);
25572
25870
CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack);
25573
--- a/src/gcc/config/freebsd-spec.h
25574
+++ b/src/gcc/config/freebsd-spec.h
25575
@@ -1,5 +1,6 @@
25576
/* Base configuration file for all FreeBSD targets.
25577
- Copyright (C) 1999, 2000, 2001, 2004, 2005, 2007, 2009 Free Software Foundation, Inc.
25578
+ Copyright (C) 1999, 2000, 2001, 2004, 2005, 2007, 2009, 2011
25579
+ Free Software Foundation, Inc.
25580
25581
This file is part of GCC.
25582
25583
@@ -139,6 +140,9 @@
25584
%{!shared: \
25585
%{!pg: %{pthread:-lpthread} -lc} \
25586
%{pg: %{pthread:-lpthread_p} -lc_p} \
25587
+ } \
25588
+ %{shared: \
25589
+ %{pthread:-lpthread} -lc \
25590
}"
25591
#endif
25592
#endif
25593
25871
--- a/src/gcc/config/h8300/h8300.c
25594
25872
+++ b/src/gcc/config/h8300/h8300.c
25595
25873
@@ -403,6 +403,10 @@
25621
25899
}
25622
25900
25623
25901
/* Return nonzero if the current function is an interrupt
25624
--- a/src/gcc/config/i386/avxintrin.h
25625
+++ b/src/gcc/config/i386/avxintrin.h
25626
@@ -737,7 +737,7 @@
25627
_mm256_insert_epi32 (__m256i __X, int __D, int const __N)
25628
{
25629
__m128i __Y = _mm256_extractf128_si256 (__X, __N >> 2);
25630
- __Y = _mm_insert_epi16 (__Y, __D, __N % 4);
25631
+ __Y = _mm_insert_epi32 (__Y, __D, __N % 4);
25632
return _mm256_insertf128_si256 (__X, __Y, __N >> 2);
25633
}
25634
25635
@@ -762,7 +762,7 @@
25636
_mm256_insert_epi64 (__m256i __X, int __D, int const __N)
25637
{
25638
__m128i __Y = _mm256_extractf128_si256 (__X, __N >> 1);
25639
- __Y = _mm_insert_epi16 (__Y, __D, __N % 2);
25640
+ __Y = _mm_insert_epi64 (__Y, __D, __N % 2);
25641
return _mm256_insertf128_si256 (__X, __Y, __N >> 1);
25642
}
25902
--- a/src/gcc/config/host-linux.c
25903
+++ b/src/gcc/config/host-linux.c
25904
@@ -86,6 +86,8 @@
25905
# define TRY_EMPTY_VM_SPACE 0x60000000
25906
#elif defined(__mc68000__)
25907
# define TRY_EMPTY_VM_SPACE 0x40000000
25908
+#elif defined(__ARM_EABI__)
25909
+# define TRY_EMPTY_VM_SPACE 0x60000000
25910
#else
25911
# define TRY_EMPTY_VM_SPACE 0
25643
25912
#endif
25644
@@ -890,55 +890,55 @@
25645
}
25646
25647
extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
25648
-_mm_maskload_pd (double const *__P, __m128d __M)
25649
+_mm_maskload_pd (double const *__P, __m128i __M)
25650
{
25651
return (__m128d) __builtin_ia32_maskloadpd ((const __v2df *)__P,
25652
- (__v2df)__M);
25653
+ (__v2di)__M);
25654
}
25655
25656
extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
25657
-_mm_maskstore_pd (double *__P, __m128d __M, __m128d __A)
25658
+_mm_maskstore_pd (double *__P, __m128i __M, __m128d __A)
25659
{
25660
- __builtin_ia32_maskstorepd ((__v2df *)__P, (__v2df)__M, (__v2df)__A);
25661
+ __builtin_ia32_maskstorepd ((__v2df *)__P, (__v2di)__M, (__v2df)__A);
25662
}
25663
25664
extern __inline __m256d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
25665
-_mm256_maskload_pd (double const *__P, __m256d __M)
25666
+_mm256_maskload_pd (double const *__P, __m256i __M)
25667
{
25668
return (__m256d) __builtin_ia32_maskloadpd256 ((const __v4df *)__P,
25669
- (__v4df)__M);
25670
+ (__v4di)__M);
25671
}
25672
25673
extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
25674
-_mm256_maskstore_pd (double *__P, __m256d __M, __m256d __A)
25675
+_mm256_maskstore_pd (double *__P, __m256i __M, __m256d __A)
25676
{
25677
- __builtin_ia32_maskstorepd256 ((__v4df *)__P, (__v4df)__M, (__v4df)__A);
25678
+ __builtin_ia32_maskstorepd256 ((__v4df *)__P, (__v4di)__M, (__v4df)__A);
25679
}
25680
25681
extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
25682
-_mm_maskload_ps (float const *__P, __m128 __M)
25683
+_mm_maskload_ps (float const *__P, __m128i __M)
25684
{
25685
return (__m128) __builtin_ia32_maskloadps ((const __v4sf *)__P,
25686
- (__v4sf)__M);
25687
+ (__v4si)__M);
25688
}
25689
25690
extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
25691
-_mm_maskstore_ps (float *__P, __m128 __M, __m128 __A)
25692
+_mm_maskstore_ps (float *__P, __m128i __M, __m128 __A)
25693
{
25694
- __builtin_ia32_maskstoreps ((__v4sf *)__P, (__v4sf)__M, (__v4sf)__A);
25695
+ __builtin_ia32_maskstoreps ((__v4sf *)__P, (__v4si)__M, (__v4sf)__A);
25696
}
25697
25698
extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
25699
-_mm256_maskload_ps (float const *__P, __m256 __M)
25700
+_mm256_maskload_ps (float const *__P, __m256i __M)
25701
{
25702
return (__m256) __builtin_ia32_maskloadps256 ((const __v8sf *)__P,
25703
- (__v8sf)__M);
25704
+ (__v8si)__M);
25705
}
25706
25707
extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
25708
-_mm256_maskstore_ps (float *__P, __m256 __M, __m256 __A)
25709
+_mm256_maskstore_ps (float *__P, __m256i __M, __m256 __A)
25710
{
25711
- __builtin_ia32_maskstoreps256 ((__v8sf *)__P, (__v8sf)__M, (__v8sf)__A);
25712
+ __builtin_ia32_maskstoreps256 ((__v8sf *)__P, (__v8si)__M, (__v8sf)__A);
25713
}
25714
25715
extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
25716
--- a/src/gcc/config/i386/freebsd.h
25717
+++ b/src/gcc/config/i386/freebsd.h
25718
@@ -1,5 +1,6 @@
25719
/* Definitions for Intel 386 running FreeBSD with ELF format
25720
- Copyright (C) 1996, 2000, 2002, 2004, 2007 Free Software Foundation, Inc.
25721
+ Copyright (C) 1996, 2000, 2002, 2004, 2007, 2011
25722
+ Free Software Foundation, Inc.
25723
Contributed by Eric Youngdale.
25724
Modified for stabs-in-ELF by H.J. Lu.
25725
Adapted from GNU/Linux version by John Polstra.
25726
@@ -138,3 +139,8 @@
25727
compiler get the contents of <float.h> and std::numeric_limits correct. */
25728
#undef TARGET_96_ROUND_53_LONG_DOUBLE
25729
#define TARGET_96_ROUND_53_LONG_DOUBLE (!TARGET_64BIT)
25730
+
25731
+/* Support for i386 has been removed from FreeBSD 6.0 onward. */
25732
+#if FBSD_MAJOR >= 6
25733
+#define SUBTARGET32_DEFAULT_CPU "i486"
25734
+#endif
25735
--- a/src/gcc/config/i386/i386-builtin-types.def
25736
+++ b/src/gcc/config/i386/i386-builtin-types.def
25737
@@ -229,7 +229,7 @@
25738
DEF_FUNCTION_TYPE (V1DI, V1DI, V1DI)
25739
DEF_FUNCTION_TYPE (V1DI, V2SI, V2SI)
25740
DEF_FUNCTION_TYPE (V1DI, V8QI, V8QI)
25741
-DEF_FUNCTION_TYPE (V2DF, PCV2DF, V2DF)
25742
+DEF_FUNCTION_TYPE (V2DF, PCV2DF, V2DI)
25743
DEF_FUNCTION_TYPE (V2DF, V2DF, DI)
25744
DEF_FUNCTION_TYPE (V2DF, V2DF, INT)
25745
DEF_FUNCTION_TYPE (V2DF, V2DF, PCDOUBLE)
25746
@@ -251,7 +251,7 @@
25747
DEF_FUNCTION_TYPE (V2SI, V2SI, SI)
25748
DEF_FUNCTION_TYPE (V2SI, V2SI, V2SI)
25749
DEF_FUNCTION_TYPE (V2SI, V4HI, V4HI)
25750
-DEF_FUNCTION_TYPE (V4DF, PCV4DF, V4DF)
25751
+DEF_FUNCTION_TYPE (V4DF, PCV4DF, V4DI)
25752
DEF_FUNCTION_TYPE (V4DF, V4DF, INT)
25753
DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF)
25754
DEF_FUNCTION_TYPE (V4DF, V4DF, V4DI)
25755
@@ -260,7 +260,7 @@
25756
DEF_FUNCTION_TYPE (V4HI, V4HI, SI)
25757
DEF_FUNCTION_TYPE (V4HI, V4HI, V4HI)
25758
DEF_FUNCTION_TYPE (V4HI, V8QI, V8QI)
25759
-DEF_FUNCTION_TYPE (V4SF, PCV4SF, V4SF)
25760
+DEF_FUNCTION_TYPE (V4SF, PCV4SF, V4SI)
25761
DEF_FUNCTION_TYPE (V4SF, V4SF, DI)
25762
DEF_FUNCTION_TYPE (V4SF, V4SF, INT)
25763
DEF_FUNCTION_TYPE (V4SF, V4SF, PCV2SF)
25764
@@ -284,7 +284,7 @@
25765
DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI)
25766
DEF_FUNCTION_TYPE (V8QI, V4HI, V4HI)
25767
DEF_FUNCTION_TYPE (V8QI, V8QI, V8QI)
25768
-DEF_FUNCTION_TYPE (V8SF, PCV8SF, V8SF)
25769
+DEF_FUNCTION_TYPE (V8SF, PCV8SF, V8SI)
25770
DEF_FUNCTION_TYPE (V8SF, V8SF, INT)
25771
DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF)
25772
DEF_FUNCTION_TYPE (V8SF, V8SF, V8SI)
25773
@@ -343,10 +343,10 @@
25774
DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, INT)
25775
DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, V8SI)
25776
DEF_FUNCTION_TYPE (VOID, PCVOID, UNSIGNED, UNSIGNED)
25777
-DEF_FUNCTION_TYPE (VOID, PV2DF, V2DF, V2DF)
25778
-DEF_FUNCTION_TYPE (VOID, PV4DF, V4DF, V4DF)
25779
-DEF_FUNCTION_TYPE (VOID, PV4SF, V4SF, V4SF)
25780
-DEF_FUNCTION_TYPE (VOID, PV8SF, V8SF, V8SF)
25781
+DEF_FUNCTION_TYPE (VOID, PV2DF, V2DI, V2DF)
25782
+DEF_FUNCTION_TYPE (VOID, PV4DF, V4DI, V4DF)
25783
+DEF_FUNCTION_TYPE (VOID, PV4SF, V4SI, V4SF)
25784
+DEF_FUNCTION_TYPE (VOID, PV8SF, V8SI, V8SF)
25785
DEF_FUNCTION_TYPE (VOID, UINT, UINT, UINT)
25786
DEF_FUNCTION_TYPE (VOID, UINT64, UINT, UINT)
25787
DEF_FUNCTION_TYPE (VOID, V16QI, V16QI, PCHAR)
25788
25913
--- a/src/gcc/config/i386/i386.c
25789
25914
+++ b/src/gcc/config/i386/i386.c
25790
25915
@@ -6737,12 +6737,8 @@
25936
26061
25937
26062
/* Restore the state back to the state from the prologue,
25938
26063
so that it's correct for the next epilogue. */
25939
@@ -10438,6 +10415,17 @@
25940
case TLS_MODEL_INITIAL_EXEC:
25941
if (TARGET_64BIT)
25942
{
25943
+ if (TARGET_SUN_TLS)
25944
+ {
25945
+ /* The Sun linker took the AMD64 TLS spec literally
25946
+ and can only handle %rax as destination of the
25947
+ initial executable code sequence. */
25948
+
25949
+ dest = gen_reg_rtx (Pmode);
25950
+ emit_insn (gen_tls_initial_exec_64_sun (dest, x));
25951
+ return dest;
25952
+ }
25953
+
25954
pic = NULL;
25955
type = UNSPEC_GOTNTPOFF;
25956
}
25957
@@ -11027,7 +11015,11 @@
25958
return orig_x;
25959
x = XVECEXP (XEXP (x, 0), 0, 0);
25960
if (GET_MODE (orig_x) != Pmode)
25961
- return simplify_gen_subreg (GET_MODE (orig_x), x, Pmode, 0);
25962
+ {
25963
+ x = simplify_gen_subreg (GET_MODE (orig_x), x, Pmode, 0);
25964
+ if (x == NULL_RTX)
25965
+ return orig_x;
25966
+ }
25967
return x;
25968
}
25969
25970
@@ -11096,7 +11088,11 @@
25971
return orig_x;
25972
}
25973
if (GET_MODE (orig_x) != Pmode && MEM_P (orig_x))
25974
- return simplify_gen_subreg (GET_MODE (orig_x), result, Pmode, 0);
25975
+ {
25976
+ result = simplify_gen_subreg (GET_MODE (orig_x), result, Pmode, 0);
25977
+ if (result == NULL_RTX)
25978
+ return orig_x;
25979
+ }
25980
return result;
25981
}
25982
25983
@@ -21638,14 +21634,14 @@
25984
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
25985
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
25986
25987
- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
25988
- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
25989
- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
25990
- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
25991
- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
25992
- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
25993
- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
25994
- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
25995
+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
25996
+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
25997
+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
25998
+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
25999
+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
26000
+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
26001
+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
26002
+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
26003
26004
{ OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
26005
{ OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
26006
@@ -23927,18 +23923,18 @@
26007
klass = load;
26008
memory = 1;
26009
break;
26010
- case V8SF_FTYPE_PCV8SF_V8SF:
26011
- case V4DF_FTYPE_PCV4DF_V4DF:
26012
- case V4SF_FTYPE_PCV4SF_V4SF:
26013
- case V2DF_FTYPE_PCV2DF_V2DF:
26014
+ case V8SF_FTYPE_PCV8SF_V8SI:
26015
+ case V4DF_FTYPE_PCV4DF_V4DI:
26016
+ case V4SF_FTYPE_PCV4SF_V4SI:
26017
+ case V2DF_FTYPE_PCV2DF_V2DI:
26018
nargs = 2;
26019
klass = load;
26020
memory = 0;
26021
break;
26022
- case VOID_FTYPE_PV8SF_V8SF_V8SF:
26023
- case VOID_FTYPE_PV4DF_V4DF_V4DF:
26024
- case VOID_FTYPE_PV4SF_V4SF_V4SF:
26025
- case VOID_FTYPE_PV2DF_V2DF_V2DF:
26026
+ case VOID_FTYPE_PV8SF_V8SI_V8SF:
26027
+ case VOID_FTYPE_PV4DF_V4DI_V4DF:
26028
+ case VOID_FTYPE_PV4SF_V4SI_V4SF:
26029
+ case VOID_FTYPE_PV2DF_V2DI_V2DF:
26030
nargs = 2;
26031
klass = store;
26032
/* Reserve memory operand for target. */
26033
@@ -25118,7 +25114,8 @@
26034
{
26035
/* QImode spills from non-QI registers require
26036
intermediate register on 32bit targets. */
26037
- if (!in_p && mode == QImode && !TARGET_64BIT
26038
+ if (!TARGET_64BIT
26039
+ && !in_p && mode == QImode
26040
&& (rclass == GENERAL_REGS
26041
|| rclass == LEGACY_REGS
26042
|| rclass == INDEX_REGS))
26043
@@ -25138,6 +25135,45 @@
26044
return Q_REGS;
26045
}
26046
26047
+ /* This condition handles corner case where an expression involving
26048
+ pointers gets vectorized. We're trying to use the address of a
26049
+ stack slot as a vector initializer.
26050
+
26051
+ (set (reg:V2DI 74 [ vect_cst_.2 ])
26052
+ (vec_duplicate:V2DI (reg/f:DI 20 frame)))
26053
+
26054
+ Eventually frame gets turned into sp+offset like this:
26055
+
26056
+ (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
26057
+ (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
26058
+ (const_int 392 [0x188]))))
26059
+
26060
+ That later gets turned into:
26061
+
26062
+ (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
26063
+ (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
26064
+ (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
26065
+
26066
+ We'll have the following reload recorded:
26067
+
26068
+ Reload 0: reload_in (DI) =
26069
+ (plus:DI (reg/f:DI 7 sp)
26070
+ (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
26071
+ reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
26072
+ SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
26073
+ reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
26074
+ reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
26075
+ reload_reg_rtx: (reg:V2DI 22 xmm1)
26076
+
26077
+ Which isn't going to work since SSE instructions can't handle scalar
26078
+ additions. Returning GENERAL_REGS forces the addition into integer
26079
+ register and reload can handle subsequent reloads without problems. */
26080
+
26081
+ if (in_p && GET_CODE (x) == PLUS
26082
+ && SSE_CLASS_P (rclass)
26083
+ && SCALAR_INT_MODE_P (mode))
26084
+ return GENERAL_REGS;
26085
+
26086
return NO_REGS;
26087
}
26088
26089
@@ -26619,7 +26655,7 @@
26064
@@ -14610,11 +14587,15 @@
26065
if (req_mode == CCZmode)
26066
return 0;
26067
/* FALLTHRU */
26068
+ case CCZmode:
26069
+ break;
26070
+
26071
case CCAmode:
26072
case CCCmode:
26073
case CCOmode:
26074
case CCSmode:
26075
- case CCZmode:
26076
+ if (set_mode != req_mode)
26077
+ return 0;
26078
break;
26079
26080
default:
26081
@@ -26678,7 +26659,7 @@
26090
26082
rtx prev;
26091
26083
bool replace = false;
26092
26084
26095
26087
|| optimize_bb_for_size_p (bb))
26096
26088
continue;
26097
26089
for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
26098
@@ -26649,7 +26685,10 @@
26090
@@ -26708,7 +26689,10 @@
26099
26091
}
26100
26092
if (replace)
26101
26093
{
26107
26099
delete_insn (ret);
26108
26100
}
26109
26101
}
26102
@@ -27711,10 +27695,19 @@
26103
break;
26104
26105
case V2DImode:
26106
- use_vec_merge = TARGET_SSE4_1;
26107
+ use_vec_merge = TARGET_SSE4_1 && TARGET_64BIT;
26108
if (use_vec_merge)
26109
break;
26110
26111
+ tmp = gen_reg_rtx (GET_MODE_INNER (mode));
26112
+ ix86_expand_vector_extract (false, tmp, target, 1 - elt);
26113
+ if (elt == 0)
26114
+ tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
26115
+ else
26116
+ tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
26117
+ emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
26118
+ return;
26119
+
26120
case V2DFmode:
26121
{
26122
rtx op0, op1;
26110
26123
--- a/src/gcc/config/i386/i386.h
26111
26124
+++ b/src/gcc/config/i386/i386.h
26112
26125
@@ -955,7 +955,7 @@
26132
26145
26133
26146
26134
26147
#define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
26135
@@ -1282,7 +1282,7 @@
26136
{ 0xe0000000, 0x1f }, /* MMX_REGS */ \
26137
{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
26138
{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
26139
-{ 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \
26140
+{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
26141
{ 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
26142
{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
26143
{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
26144
26148
--- a/src/gcc/config/i386/i386.md
26145
26149
+++ b/src/gcc/config/i386/i386.md
26146
26150
@@ -80,7 +80,6 @@
26151
26155
(UNSPEC_REG_SAVE 14)
26152
26156
(UNSPEC_DEF_CFA 15)
26153
26157
(UNSPEC_SET_RIP 16)
26154
@@ -92,6 +91,7 @@
26155
(UNSPEC_TLS_GD 21)
26156
(UNSPEC_TLS_LD_BASE 22)
26157
(UNSPEC_TLSDESC 23)
26158
+ (UNSPEC_TLS_IE_SUN 24)
26159
26160
; Other random patterns
26161
(UNSPEC_SCAS 30)
26162
@@ -4934,6 +4934,7 @@
26158
@@ -2430,7 +2429,7 @@
26159
[(set_attr "type" "*,*,mmx,mmxmov,mmxmov,sselog1,ssemov,ssemov,ssemov,sselog1,ssemov,ssemov,ssemov")
26160
(set (attr "prefix")
26161
(if_then_else (eq_attr "alternative" "5,6,7,8")
26162
- (const_string "vex")
26163
+ (const_string "maybe_vex")
26164
(const_string "orig")))
26165
(set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,TI,DI,V4SF,V2SF,V4SF,V2SF")])
26166
26167
@@ -2468,21 +2467,15 @@
26168
return "movdq2q\t{%1, %0|%0, %1}";
26169
26170
case TYPE_SSEMOV:
26171
- if (TARGET_AVX)
26172
- {
26173
- if (get_attr_mode (insn) == MODE_TI)
26174
- return "vmovdqa\t{%1, %0|%0, %1}";
26175
- else
26176
- return "vmovq\t{%1, %0|%0, %1}";
26177
- }
26178
-
26179
if (get_attr_mode (insn) == MODE_TI)
26180
- return "movdqa\t{%1, %0|%0, %1}";
26181
- /* FALLTHRU */
26182
+ return "%vmovdqa\t{%1, %0|%0, %1}";
26183
+ /* Handle broken assemblers that require movd instead of movq. */
26184
+ if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
26185
+ return "%vmovd\t{%1, %0|%0, %1}";
26186
+ return "%vmovq\t{%1, %0|%0, %1}";
26187
26188
case TYPE_MMXMOV:
26189
- /* Moves from and into integer register is done using movd
26190
- opcode with REX prefix. */
26191
+ /* Handle broken assemblers that require movd instead of movq. */
26192
if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
26193
return "movd\t{%1, %0|%0, %1}";
26194
return "movq\t{%1, %0|%0, %1}";
26195
@@ -2915,12 +2908,13 @@
26196
26197
case 9: case 10: case 14: case 15:
26198
return "movd\t{%1, %0|%0, %1}";
26199
- case 12: case 13:
26200
- return "%vmovd\t{%1, %0|%0, %1}";
26201
26202
case 11:
26203
return "movq\t{%1, %0|%0, %1}";
26204
26205
+ case 12: case 13:
26206
+ return "%vmovd\t{%1, %0|%0, %1}";
26207
+
26208
default:
26209
gcc_unreachable ();
26210
}
26211
@@ -3067,6 +3061,7 @@
26212
case 3:
26213
case 4:
26214
return "#";
26215
+
26216
case 5:
26217
switch (get_attr_mode (insn))
26218
{
26219
@@ -3262,7 +3257,8 @@
26220
26221
case 9:
26222
case 10:
26223
- return "%vmovd\t{%1, %0|%0, %1}";
26224
+ /* Handle broken assemblers that require movd instead of movq. */
26225
+ return "%vmovd\t{%1, %0|%0, %1}";
26226
26227
default:
26228
gcc_unreachable();
26229
@@ -3361,11 +3357,11 @@
26230
switch (get_attr_mode (insn))
26231
{
26232
case MODE_V4SF:
26233
- return "xorps\t%0, %0";
26234
+ return "%vxorps\t%0, %d0";
26235
case MODE_V2DF:
26236
- return "xorpd\t%0, %0";
26237
+ return "%vxorpd\t%0, %d0";
26238
case MODE_TI:
26239
- return "pxor\t%0, %0";
26240
+ return "%vpxor\t%0, %d0";
26241
default:
26242
gcc_unreachable ();
26243
}
26244
@@ -3375,28 +3371,56 @@
26245
switch (get_attr_mode (insn))
26246
{
26247
case MODE_V4SF:
26248
- return "movaps\t{%1, %0|%0, %1}";
26249
+ return "%vmovaps\t{%1, %0|%0, %1}";
26250
case MODE_V2DF:
26251
- return "movapd\t{%1, %0|%0, %1}";
26252
+ return "%vmovapd\t{%1, %0|%0, %1}";
26253
case MODE_TI:
26254
- return "movdqa\t{%1, %0|%0, %1}";
26255
+ return "%vmovdqa\t{%1, %0|%0, %1}";
26256
case MODE_DI:
26257
- return "movq\t{%1, %0|%0, %1}";
26258
+ return "%vmovq\t{%1, %0|%0, %1}";
26259
case MODE_DF:
26260
- return "movsd\t{%1, %0|%0, %1}";
26261
+ if (TARGET_AVX)
26262
+ {
26263
+ if (REG_P (operands[0]) && REG_P (operands[1]))
26264
+ return "vmovsd\t{%1, %0, %0|%0, %0, %1}";
26265
+ else
26266
+ return "vmovsd\t{%1, %0|%0, %1}";
26267
+ }
26268
+ else
26269
+ return "movsd\t{%1, %0|%0, %1}";
26270
case MODE_V1DF:
26271
- return "movlpd\t{%1, %0|%0, %1}";
26272
+ if (TARGET_AVX)
26273
+ {
26274
+ if (REG_P (operands[0]))
26275
+ return "vmovlpd\t{%1, %0, %0|%0, %0, %1}";
26276
+ else
26277
+ return "vmovlpd\t{%1, %0|%0, %1}";
26278
+ }
26279
+ else
26280
+ return "movlpd\t{%1, %0|%0, %1}";
26281
case MODE_V2SF:
26282
- return "movlps\t{%1, %0|%0, %1}";
26283
+ if (TARGET_AVX)
26284
+ {
26285
+ if (REG_P (operands[0]))
26286
+ return "vmovlps\t{%1, %0, %0|%0, %0, %1}";
26287
+ else
26288
+ return "vmovlps\t{%1, %0|%0, %1}";
26289
+ }
26290
+ else
26291
+ return "movlps\t{%1, %0|%0, %1}";
26292
default:
26293
gcc_unreachable ();
26294
}
26295
26296
default:
26297
- gcc_unreachable();
26298
+ gcc_unreachable ();
26299
}
26300
}
26301
[(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov")
26302
+ (set (attr "prefix")
26303
+ (if_then_else (eq_attr "alternative" "0,1,2,3,4")
26304
+ (const_string "orig")
26305
+ (const_string "maybe_vex")))
26306
(set (attr "prefix_data16")
26307
(if_then_else (eq_attr "mode" "V1DF")
26308
(const_string "1")
26309
@@ -4935,6 +4959,7 @@
26163
26310
(set (match_operand:SSEMODEI24 2 "register_operand" "")
26164
26311
(fix:SSEMODEI24 (match_dup 0)))]
26165
26312
"TARGET_SHORTEN_X87_SSE
26167
26314
&& peep2_reg_dead_p (2, operands[0])"
26168
26315
[(set (match_dup 2) (fix:SSEMODEI24 (match_dup 1)))]
26169
26316
"")
26170
@@ -13798,24 +13799,29 @@
26317
@@ -13799,24 +13824,29 @@
26171
26318
""
26172
26319
[(set_attr "length" "0")])
26173
26320
26203
26350
"reload_completed"
26204
26351
"ret"
26205
26352
[(set_attr "length" "1")
26206
@@ -13826,8 +13832,8 @@
26353
@@ -13827,8 +13857,8 @@
26207
26354
;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
26208
26355
;; instruction Athlon and K8 have.
26209
26356
26214
26361
(unspec [(const_int 0)] UNSPEC_REP)]
26215
26362
"reload_completed"
26216
26363
"rep\;ret"
26217
@@ -13837,8 +13843,8 @@
26364
@@ -13838,8 +13868,8 @@
26218
26365
(set_attr "prefix_rep" "1")
26219
26366
(set_attr "modrm" "0")])
26220
26367
26225
26372
(use (match_operand:SI 0 "const_int_operand" ""))]
26226
26373
"reload_completed"
26227
26374
"ret\t%0"
26228
@@ -13847,8 +13853,8 @@
26375
@@ -13848,8 +13878,8 @@
26229
26376
(set_attr "length_immediate" "2")
26230
26377
(set_attr "modrm" "0")])
26231
26378
26236
26383
(use (match_operand:SI 0 "register_operand" "r"))]
26237
26384
"reload_completed"
26238
26385
"jmp\t%A0"
26239
@@ -14702,6 +14708,18 @@
26240
(set_attr "memory" "load")
26241
(set_attr "imm_disp" "false")])
26242
26243
+;; The Sun linker took the AMD64 TLS spec literally and can only handle
26244
+;; %rax as destination of the initial executable code sequence.
26245
+(define_insn "tls_initial_exec_64_sun"
26246
+ [(set (match_operand:DI 0 "register_operand" "=a")
26247
+ (unspec:DI
26248
+ [(match_operand:DI 1 "tls_symbolic_operand" "")]
26249
+ UNSPEC_TLS_IE_SUN))
26250
+ (clobber (reg:CC FLAGS_REG))]
26251
+ "TARGET_64BIT && TARGET_SUN_TLS"
26252
+ "mov{q}\t{%%fs:0, %0|%0, QWORD PTR fs:0}\n\tadd{q}\t{%a1@gottpoff(%%rip), %0|%0, %a1@gottpoff[rip]}"
26253
+ [(set_attr "type" "multi")])
26254
+
26255
;; GNU2 TLS patterns can be split.
26256
26257
(define_expand "tls_dynamic_gnu2_32"
26258
@@ -20019,15 +20037,14 @@
26386
@@ -20032,15 +20062,14 @@
26259
26387
;; leal (%edx,%eax,4), %eax
26260
26388
26261
26389
(define_peephole2
26276
26404
(clobber (reg:CC FLAGS_REG))])]
26277
26405
"INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 3
26278
26406
/* Validate MODE for lea. */
26279
@@ -20036,31 +20053,27 @@
26407
@@ -20049,31 +20078,27 @@
26280
26408
|| GET_MODE (operands[0]) == HImode))
26281
26409
|| GET_MODE (operands[0]) == SImode
26282
26410
|| (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
26320
26448
operands[0] = dest;
26321
26449
})
26322
26450
26323
@@ -20252,74 +20265,6 @@
26451
@@ -20265,74 +20290,6 @@
26324
26452
{ return ASM_SHORT "0x0b0f"; }
26325
26453
[(set_attr "length" "2")])
26326
26454
26395
26523
(define_expand "prefetch"
26396
26524
[(prefetch (match_operand 0 "address_operand" "")
26397
26525
(match_operand:SI 1 "const_int_operand" "")
26398
--- a/src/gcc/config/i386/i386.opt
26399
+++ b/src/gcc/config/i386/i386.opt
26400
@@ -305,11 +305,11 @@
26401
Do not support SSE4.1 and SSE4.2 built-in functions and code generation
26402
26403
mavx
26404
-Target Report Mask(ISA_AVX) Var(ix86_isa_flags) VarExists
26405
+Target Report Mask(ISA_AVX) Var(ix86_isa_flags) VarExists Save
26406
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation
26407
26408
mfma
26409
-Target Report Mask(ISA_FMA) Var(ix86_isa_flags) VarExists
26410
+Target Report Mask(ISA_FMA) Var(ix86_isa_flags) VarExists Save
26411
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation
26412
26413
msse4a
26526
--- a/src/gcc/config/i386/mmx.md
26527
+++ b/src/gcc/config/i386/mmx.md
26528
@@ -63,6 +63,7 @@
26529
DONE;
26530
})
26531
26532
+;; movd instead of movq is required to handle broken assemblers.
26533
(define_insn "*mov<mode>_internal_rex64"
26534
[(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
26535
"=rm,r,!?y,!?y ,m ,!y,*Y2,x,x ,m,r,Yi")
26536
@@ -81,8 +82,8 @@
26537
%vpxor\t%0, %d0
26538
%vmovq\t{%1, %0|%0, %1}
26539
%vmovq\t{%1, %0|%0, %1}
26540
- %vmovq\t{%1, %0|%0, %1}
26541
- %vmovq\t{%1, %0|%0, %1}"
26542
+ %vmovd\t{%1, %0|%0, %1}
26543
+ %vmovd\t{%1, %0|%0, %1}"
26544
[(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,ssemov")
26545
(set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*")
26546
(set_attr "prefix_rep" "*,*,*,*,*,1,1,*,1,*,*,*")
26547
@@ -192,6 +193,7 @@
26548
(const_string "orig")))
26549
(set_attr "mode" "DI,DI,DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
26550
26551
+;; movd instead of movq is required to handle broken assemblers.
26552
(define_insn "*movv2sf_internal_rex64"
26553
[(set (match_operand:V2SF 0 "nonimmediate_operand"
26554
"=rm,r ,!?y,!?y ,m ,!y,*Y2,x,x,x,m,r,Yi")
26414
26555
--- a/src/gcc/config/i386/sse.md
26415
26556
+++ b/src/gcc/config/i386/sse.md
26416
@@ -5011,7 +5011,7 @@
26417
movsd\t{%2, %0|%0, %2}
26418
movlpd\t{%2, %0|%0, %2}
26419
movsd\t{%2, %0|%0, %2}
26420
- shufpd\t{$2, %2, %0|%0, %2, 2}
26421
+ shufpd\t{$2, %1, %0|%0, %1, 2}
26422
movhpd\t{%H1, %0|%0, %H1}
26423
#
26424
#
26425
@@ -5090,7 +5090,7 @@
26426
movsd\t{%2, %0|%0, %2}
26427
movlpd\t{%2, %0|%0, %2}
26428
movlpd\t{%2, %0|%0, %2}
26429
- shufpd\t{$2, %2, %0|%0, %2, 2}
26430
+ shufpd\t{$2, %1, %0|%0, %1, 2}
26431
movhps\t{%H1, %0|%0, %H1}
26432
movhps\t{%1, %H0|%H0, %1}"
26433
[(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
26434
@@ -8932,7 +8932,7 @@
26435
(ss_plus:V8HI
26436
(mult:V8HI
26437
(zero_extend:V8HI
26438
- (vec_select:V4QI
26439
+ (vec_select:V8QI
26440
(match_operand:V16QI 1 "register_operand" "x")
26441
(parallel [(const_int 0)
26442
(const_int 2)
26443
@@ -8955,7 +8955,7 @@
26444
(const_int 14)]))))
26445
(mult:V8HI
26446
(zero_extend:V8HI
26447
- (vec_select:V16QI (match_dup 1)
26448
+ (vec_select:V8QI (match_dup 1)
26449
(parallel [(const_int 1)
26450
(const_int 3)
26451
(const_int 5)
26452
@@ -8965,7 +8965,7 @@
26453
(const_int 13)
26454
(const_int 15)])))
26455
(sign_extend:V8HI
26456
- (vec_select:V16QI (match_dup 2)
26457
+ (vec_select:V8QI (match_dup 2)
26458
(parallel [(const_int 1)
26459
(const_int 3)
26460
(const_int 5)
26461
@@ -8986,7 +8986,7 @@
26462
(ss_plus:V8HI
26463
(mult:V8HI
26464
(zero_extend:V8HI
26465
- (vec_select:V4QI
26466
+ (vec_select:V8QI
26467
(match_operand:V16QI 1 "register_operand" "0")
26468
(parallel [(const_int 0)
26469
(const_int 2)
26470
@@ -9009,7 +9009,7 @@
26471
(const_int 14)]))))
26472
(mult:V8HI
26473
(zero_extend:V8HI
26474
- (vec_select:V16QI (match_dup 1)
26475
+ (vec_select:V8QI (match_dup 1)
26476
(parallel [(const_int 1)
26477
(const_int 3)
26478
(const_int 5)
26479
@@ -9019,7 +9019,7 @@
26480
(const_int 13)
26481
(const_int 15)])))
26482
(sign_extend:V8HI
26483
- (vec_select:V16QI (match_dup 2)
26484
+ (vec_select:V8QI (match_dup 2)
26485
(parallel [(const_int 1)
26486
(const_int 3)
26487
(const_int 5)
26488
@@ -9056,13 +9056,13 @@
26489
(const_int 6)]))))
26490
(mult:V4HI
26491
(zero_extend:V4HI
26492
- (vec_select:V8QI (match_dup 1)
26493
+ (vec_select:V4QI (match_dup 1)
26494
(parallel [(const_int 1)
26495
(const_int 3)
26496
(const_int 5)
26497
(const_int 7)])))
26498
(sign_extend:V4HI
26499
- (vec_select:V8QI (match_dup 2)
26500
+ (vec_select:V4QI (match_dup 2)
26501
(parallel [(const_int 1)
26502
(const_int 3)
26503
(const_int 5)
26504
@@ -12097,7 +12097,7 @@
26505
[(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
26506
(unspec:AVXMODEF2P
26507
[(match_operand:AVXMODEF2P 1 "memory_operand" "m")
26508
- (match_operand:AVXMODEF2P 2 "register_operand" "x")
26509
+ (match_operand:<avxpermvecmode> 2 "register_operand" "x")
26510
(match_dup 0)]
26511
UNSPEC_MASKLOAD))]
26512
"TARGET_AVX"
26513
@@ -12110,7 +12110,7 @@
26514
(define_insn "avx_maskstorep<avxmodesuffixf2c><avxmodesuffix>"
26515
[(set (match_operand:AVXMODEF2P 0 "memory_operand" "=m")
26516
(unspec:AVXMODEF2P
26517
- [(match_operand:AVXMODEF2P 1 "register_operand" "x")
26518
+ [(match_operand:<avxpermvecmode> 1 "register_operand" "x")
26519
(match_operand:AVXMODEF2P 2 "register_operand" "x")
26520
(match_dup 0)]
26521
UNSPEC_MASKSTORE))]
26557
@@ -7473,9 +7473,8 @@
26558
"@
26559
#
26560
#
26561
- %vmov{q}\t{%1, %0|%0, %1}"
26562
+ mov{q}\t{%1, %0|%0, %1}"
26563
[(set_attr "type" "*,*,imov")
26564
- (set_attr "prefix" "*,*,maybe_vex")
26565
(set_attr "mode" "*,*,DI")])
26566
26567
(define_insn "*sse2_storeq"
26568
@@ -7513,11 +7512,11 @@
26569
vmovhps\t{%1, %0|%0, %1}
26570
vpsrldq\t{$8, %1, %0|%0, %1, 8}
26571
vmovq\t{%H1, %0|%0, %H1}
26572
- vmov{q}\t{%H1, %0|%0, %H1}"
26573
+ mov{q}\t{%H1, %0|%0, %H1}"
26574
[(set_attr "type" "ssemov,sseishft1,ssemov,imov")
26575
(set_attr "length_immediate" "*,1,*,*")
26576
(set_attr "memory" "*,none,*,*")
26577
- (set_attr "prefix" "vex")
26578
+ (set_attr "prefix" "vex,vex,vex,orig")
26579
(set_attr "mode" "V2SF,TI,TI,DI")])
26580
26581
(define_insn "*vec_extractv2di_1_rex64"
26582
@@ -7795,6 +7794,7 @@
26583
(const_string "vex")))
26584
(set_attr "mode" "TI,TI,TI,TI,TI,V2SF")])
26585
26586
+;; movd instead of movq is required to handle broken assemblers.
26587
(define_insn "*vec_concatv2di_rex64_sse4_1"
26588
[(set (match_operand:V2DI 0 "register_operand" "=x ,x ,Yi,!x,x,x,x")
26589
(vec_concat:V2DI
26590
@@ -7804,7 +7804,7 @@
26591
"@
26592
pinsrq\t{$0x1, %2, %0|%0, %2, 0x1}
26593
movq\t{%1, %0|%0, %1}
26594
- movq\t{%1, %0|%0, %1}
26595
+ movd\t{%1, %0|%0, %1}
26596
movq2dq\t{%1, %0|%0, %1}
26597
punpcklqdq\t{%2, %0|%0, %2}
26598
movlhps\t{%2, %0|%0, %2}
26599
@@ -7815,6 +7815,7 @@
26600
(set_attr "length_immediate" "1,*,*,*,*,*,*")
26601
(set_attr "mode" "TI,TI,TI,TI,TI,V4SF,V2SF")])
26602
26603
+;; movd instead of movq is required to handle broken assemblers.
26604
(define_insn "*vec_concatv2di_rex64_sse"
26605
[(set (match_operand:V2DI 0 "register_operand" "=Y2 ,Yi,!Y2,Y2,x,x")
26606
(vec_concat:V2DI
26607
@@ -7823,7 +7824,7 @@
26608
"TARGET_64BIT && TARGET_SSE"
26609
"@
26610
movq\t{%1, %0|%0, %1}
26611
- movq\t{%1, %0|%0, %1}
26612
+ movd\t{%1, %0|%0, %1}
26613
movq2dq\t{%1, %0|%0, %1}
26614
punpcklqdq\t{%2, %0|%0, %2}
26615
movlhps\t{%2, %0|%0, %2}
26522
26616
--- a/src/gcc/config/linux-android.h
26523
26617
+++ b/src/gcc/config/linux-android.h
26524
26618
@@ -0,0 +1,53 @@
26885
26979
[(set_attr "type" "jump")
26886
26980
(set_attr "mode" "none")])
26887
26981
26888
--- a/src/gcc/config/pa/pa-hpux11.h
26889
+++ b/src/gcc/config/pa/pa-hpux11.h
26890
@@ -1,5 +1,5 @@
26891
/* Definitions of target machine for GNU compiler, for HP PA-RISC
26892
- Copyright (C) 1998, 1999, 2000, 2002, 2003, 2004, 2005, 2007, 2008
26893
+ Copyright (C) 1998, 1999, 2000, 2002, 2003, 2004, 2005, 2007, 2008, 2011
26894
Free Software Foundation, Inc.
26895
26896
This file is part of GCC.
26897
@@ -114,18 +114,24 @@
26898
-z %{mlinker-opt:-O} %{!shared:-u main -u __gcc_plt_call}\
26899
%{static:-a archive} %{shared:-b}"
26900
26901
-/* HP-UX 11 has posix threads. HP libc contains pthread stubs so that
26902
- non-threaded applications can be linked with a thread-safe libc
26903
- without a subsequent loss of performance. For more details, see
26904
- <http://docs.hp.com/en/1896/pthreads.html>. */
26905
+/* HP-UX 11 has posix threads. HP's shared libc contains pthread stubs
26906
+ so that non-threaded applications can be linked with a thread-safe
26907
+ libc without a subsequent loss of performance. For more details,
26908
+ see <http://docs.hp.com/en/1896/pthreads.html>. */
26909
#undef LIB_SPEC
26910
#define LIB_SPEC \
26911
"%{!shared:\
26912
- %{static|mt|pthread:%{fopenmp:%{static:-a archive_shared} -lrt\
26913
- %{static:-a archive}} -lpthread} -lc\
26914
- %{static:%{!nolibdld:-a archive_shared -ldld -a archive -lc}}}\
26915
+ %{fopenmp:%{static:-a archive_shared} -lrt %{static:-a archive}}\
26916
+ %{mt|pthread:-lpthread} -lc\
26917
+ %{static:%{!nolibdld:-a archive_shared -ldld -a archive -lc}\
26918
+ %{!mt:%{!pthread:-a shared -lc -a archive}}}}\
26919
%{shared:%{mt|pthread:-lpthread}}"
26920
26921
+/* The libgcc_stub.a library needs to come last. */
26922
+#undef LINK_GCC_C_SEQUENCE_SPEC
26923
+#define LINK_GCC_C_SEQUENCE_SPEC \
26924
+ "%G %L %G %{!nostdlib:%{!nodefaultlibs:%{!shared:-lgcc_stub}}}"
26925
+
26926
#undef STARTFILE_SPEC
26927
#define STARTFILE_SPEC \
26928
"%{!shared:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}} \
26929
--- a/src/gcc/config/pa/pa.c
26930
+++ b/src/gcc/config/pa/pa.c
26931
@@ -6097,35 +6097,92 @@
26932
}
26933
26934
/* Return TRUE if INSN, a jump insn, has an unfilled delay slot and
26935
- it branches to the next real instruction. Otherwise, return FALSE. */
26936
+ it branches into the delay slot. Otherwise, return FALSE. */
26937
26938
static bool
26939
branch_to_delay_slot_p (rtx insn)
26940
{
26941
+ rtx jump_insn;
26942
+
26943
if (dbr_sequence_length ())
26944
return FALSE;
26945
26946
- return next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn);
26947
+ jump_insn = next_active_insn (JUMP_LABEL (insn));
26948
+ while (insn)
26949
+ {
26950
+ insn = next_active_insn (insn);
26951
+ if (jump_insn == insn)
26952
+ return TRUE;
26953
+
26954
+ /* We can't rely on the length of asms. So, we return FALSE when
26955
+ the branch is followed by an asm. */
26956
+ if (!insn
26957
+ || GET_CODE (PATTERN (insn)) == ASM_INPUT
26958
+ || extract_asm_operands (PATTERN (insn)) != NULL_RTX
26959
+ || get_attr_length (insn) > 0)
26960
+ break;
26961
+ }
26962
+
26963
+ return FALSE;
26964
}
26965
26966
-/* Return TRUE if INSN, a jump insn, needs a nop in its delay slot.
26967
+/* Return TRUE if INSN, a forward jump insn, needs a nop in its delay slot.
26968
26969
This occurs when INSN has an unfilled delay slot and is followed
26970
- by an ASM_INPUT. Disaster can occur if the ASM_INPUT is empty and
26971
- the jump branches into the delay slot. So, we add a nop in the delay
26972
- slot just to be safe. This messes up our instruction count, but we
26973
- don't know how big the ASM_INPUT insn is anyway. */
26974
+ by an asm. Disaster can occur if the asm is empty and the jump
26975
+ branches into the delay slot. So, we add a nop in the delay slot
26976
+ when this occurs. */
26977
26978
static bool
26979
branch_needs_nop_p (rtx insn)
26980
{
26981
- rtx next_insn;
26982
+ rtx jump_insn;
26983
26984
if (dbr_sequence_length ())
26985
return FALSE;
26986
26987
- next_insn = next_real_insn (insn);
26988
- return GET_CODE (PATTERN (next_insn)) == ASM_INPUT;
26989
+ jump_insn = next_active_insn (JUMP_LABEL (insn));
26990
+ while (insn)
26991
+ {
26992
+ insn = next_active_insn (insn);
26993
+ if (!insn || jump_insn == insn)
26994
+ return TRUE;
26995
+
26996
+ if (!(GET_CODE (PATTERN (insn)) == ASM_INPUT
26997
+ || extract_asm_operands (PATTERN (insn)) != NULL_RTX)
26998
+ && get_attr_length (insn) > 0)
26999
+ break;
27000
+ }
27001
+
27002
+ return FALSE;
27003
+}
27004
+
27005
+/* Return TRUE if INSN, a forward jump insn, can use nullification
27006
+ to skip the following instruction. This avoids an extra cycle due
27007
+ to a mis-predicted branch when we fall through. */
27008
+
27009
+static bool
27010
+use_skip_p (rtx insn)
27011
+{
27012
+ rtx jump_insn = next_active_insn (JUMP_LABEL (insn));
27013
+
27014
+ while (insn)
27015
+ {
27016
+ insn = next_active_insn (insn);
27017
+
27018
+ /* We can't rely on the length of asms, so we can't skip asms. */
27019
+ if (!insn
27020
+ || GET_CODE (PATTERN (insn)) == ASM_INPUT
27021
+ || extract_asm_operands (PATTERN (insn)) != NULL_RTX)
27022
+ break;
27023
+ if (get_attr_length (insn) == 4
27024
+ && jump_insn == next_active_insn (insn))
27025
+ return TRUE;
27026
+ if (get_attr_length (insn) > 0)
27027
+ break;
27028
+ }
27029
+
27030
+ return FALSE;
27031
}
27032
27033
/* This routine handles all the normal conditional branch sequences we
27034
@@ -6139,7 +6196,7 @@
27035
output_cbranch (rtx *operands, int negated, rtx insn)
27036
{
27037
static char buf[100];
27038
- int useskip = 0;
27039
+ bool useskip;
27040
int nullify = INSN_ANNULLED_BRANCH_P (insn);
27041
int length = get_attr_length (insn);
27042
int xdelay;
27043
@@ -6177,12 +6234,7 @@
27044
/* A forward branch over a single nullified insn can be done with a
27045
comclr instruction. This avoids a single cycle penalty due to
27046
mis-predicted branch if we fall through (branch not taken). */
27047
- if (length == 4
27048
- && next_real_insn (insn) != 0
27049
- && get_attr_length (next_real_insn (insn)) == 4
27050
- && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
27051
- && nullify)
27052
- useskip = 1;
27053
+ useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE;
27054
27055
switch (length)
27056
{
27057
@@ -6470,7 +6522,7 @@
27058
output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
27059
{
27060
static char buf[100];
27061
- int useskip = 0;
27062
+ bool useskip;
27063
int nullify = INSN_ANNULLED_BRANCH_P (insn);
27064
int length = get_attr_length (insn);
27065
int xdelay;
27066
@@ -6496,13 +6548,7 @@
27067
/* A forward branch over a single nullified insn can be done with a
27068
extrs instruction. This avoids a single cycle penalty due to
27069
mis-predicted branch if we fall through (branch not taken). */
27070
-
27071
- if (length == 4
27072
- && next_real_insn (insn) != 0
27073
- && get_attr_length (next_real_insn (insn)) == 4
27074
- && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
27075
- && nullify)
27076
- useskip = 1;
27077
+ useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE;
27078
27079
switch (length)
27080
{
27081
@@ -6661,7 +6707,7 @@
27082
output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
27083
{
27084
static char buf[100];
27085
- int useskip = 0;
27086
+ bool useskip;
27087
int nullify = INSN_ANNULLED_BRANCH_P (insn);
27088
int length = get_attr_length (insn);
27089
int xdelay;
27090
@@ -6687,13 +6733,7 @@
27091
/* A forward branch over a single nullified insn can be done with a
27092
extrs instruction. This avoids a single cycle penalty due to
27093
mis-predicted branch if we fall through (branch not taken). */
27094
-
27095
- if (length == 4
27096
- && next_real_insn (insn) != 0
27097
- && get_attr_length (next_real_insn (insn)) == 4
27098
- && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
27099
- && nullify)
27100
- useskip = 1;
27101
+ useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE;
27102
27103
switch (length)
27104
{
26982
--- a/src/gcc/config/pa/pa-protos.h
26983
+++ b/src/gcc/config/pa/pa-protos.h
26984
@@ -79,7 +79,6 @@
26985
extern int prefetch_cc_operand (rtx, enum machine_mode);
26986
extern int prefetch_nocc_operand (rtx, enum machine_mode);
26987
extern int and_operand (rtx, enum machine_mode);
26988
-extern int ior_operand (rtx, enum machine_mode);
26989
extern int arith32_operand (rtx, enum machine_mode);
26990
extern int uint32_operand (rtx, enum machine_mode);
26991
extern int reg_before_reload_operand (rtx, enum machine_mode);
26992
@@ -94,7 +93,6 @@
26993
extern int fmpyaddoperands (rtx *);
26994
extern int fmpysuboperands (rtx *);
26995
extern int call_operand_address (rtx, enum machine_mode);
26996
-extern int ior_operand (rtx, enum machine_mode);
26997
extern void emit_bcond_fp (rtx[]);
26998
extern int emit_move_sequence (rtx *, enum machine_mode, rtx);
26999
extern int emit_hpdiv_const (rtx *, int);
27105
27000
--- a/src/gcc/config/pa/pa.md
27106
27001
+++ b/src/gcc/config/pa/pa.md
27107
@@ -811,7 +811,7 @@
27108
(match_operand:DI 3 "arith11_operand" "rI"))
27109
(match_operand:DI 1 "register_operand" "r")))]
27110
"TARGET_64BIT"
27111
- "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
27112
+ "sub%I3,* %3,%2,%%r0\;add,dc %%r0,%1,%0"
27113
[(set_attr "type" "binary")
27114
(set_attr "length" "8")])
27115
27116
@@ -833,7 +833,7 @@
27117
(match_operand:DI 3 "register_operand" "r"))
27118
(match_operand:DI 1 "register_operand" "r")))]
27119
"TARGET_64BIT"
27120
- "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
27121
+ "sub,* %2,%3,%%r0\;add,dc %%r0,%1,%0"
27122
[(set_attr "type" "binary")
27123
(set_attr "length" "8")])
27124
27125
@@ -856,7 +856,7 @@
27126
(match_operand:DI 3 "int11_operand" "I"))
27127
(match_operand:DI 1 "register_operand" "r")))]
27128
"TARGET_64BIT"
27129
- "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
27130
+ "addi,* %k3,%2,%%r0\;add,dc %%r0,%1,%0"
27131
[(set_attr "type" "binary")
27132
(set_attr "length" "8")])
27133
27134
@@ -902,7 +902,7 @@
27135
(gtu:DI (match_operand:DI 2 "register_operand" "r")
27136
(match_operand:DI 3 "arith11_operand" "rI"))))]
27137
"TARGET_64BIT"
27138
- "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
27139
+ "sub%I3,* %3,%2,%%r0\;sub,db %1,%%r0,%0"
27140
[(set_attr "type" "binary")
27141
(set_attr "length" "8")])
27142
27143
@@ -924,7 +924,7 @@
27144
(match_operand:DI 3 "arith11_operand" "rI")))
27145
(match_operand:DI 4 "register_operand" "r")))]
27146
"TARGET_64BIT"
27147
- "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
27148
+ "sub%I3,* %3,%2,%%r0\;sub,db %1,%4,%0"
27149
[(set_attr "type" "binary")
27150
(set_attr "length" "8")])
27151
27152
@@ -946,7 +946,7 @@
27153
(ltu:DI (match_operand:DI 2 "register_operand" "r")
27154
(match_operand:DI 3 "register_operand" "r"))))]
27155
"TARGET_64BIT"
27156
- "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
27157
+ "sub,* %2,%3,%%r0\;sub,db %1,%%r0,%0"
27158
[(set_attr "type" "binary")
27159
(set_attr "length" "8")])
27160
27161
@@ -968,7 +968,7 @@
27162
(match_operand:DI 3 "register_operand" "r")))
27163
(match_operand:DI 4 "register_operand" "r")))]
27164
"TARGET_64BIT"
27165
- "sub %2,%3,%%r0\;sub,db %1,%4,%0"
27166
+ "sub,* %2,%3,%%r0\;sub,db %1,%4,%0"
27167
[(set_attr "type" "binary")
27168
(set_attr "length" "8")])
27169
27170
@@ -991,7 +991,7 @@
27171
(leu:DI (match_operand:DI 2 "register_operand" "r")
27172
(match_operand:DI 3 "int11_operand" "I"))))]
27173
"TARGET_64BIT"
27174
- "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
27175
+ "addi,* %k3,%2,%%r0\;sub,db %1,%%r0,%0"
27176
[(set_attr "type" "binary")
27177
(set_attr "length" "8")])
27178
27179
@@ -1013,7 +1013,7 @@
27180
(match_operand:DI 3 "int11_operand" "I")))
27181
(match_operand:DI 4 "register_operand" "r")))]
27182
"TARGET_64BIT"
27183
- "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
27184
+ "addi,* %k3,%2,%%r0\;sub,db %1,%4,%0"
27185
[(set_attr "type" "binary")
27186
(set_attr "length" "8")])
27187
27188
--- a/src/gcc/config/pa/pa64-hpux.h
27189
+++ b/src/gcc/config/pa/pa64-hpux.h
27190
@@ -1,6 +1,6 @@
27191
/* Definitions of target machine for GNU compiler, for HPs running
27192
HPUX using the 64bit runtime model.
27193
- Copyright (C) 1999, 2000, 2001, 2002, 2004, 2005, 2007, 2008
27194
+ Copyright (C) 1999, 2000, 2001, 2002, 2004, 2005, 2007, 2008, 2011
27195
Free Software Foundation, Inc.
27196
27197
This file is part of GCC.
27198
@@ -59,36 +59,42 @@
27199
#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_GNU_LD)
27200
#define LIB_SPEC \
27201
"%{!shared:\
27202
- %{!p:%{!pg:%{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\
27203
- %{static:-a archive}} -lpthread} -lc\
27204
- %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\
27205
+ %{!p:%{!pg:%{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\
27206
+ %{mt|pthread:-lpthread} -lc\
27207
+ %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\
27208
+ %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\
27209
%{p:%{!pg:%{static:%{!mhp-ld:-a shared}%{mhp-ld:-a archive_shared}}\
27210
-lprof %{static:-a archive}\
27211
- %{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\
27212
- %{static:-a archive}} -lpthread} -lc\
27213
- %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\
27214
+ %{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\
27215
+ %{mt|pthread:-lpthread} -lc\
27216
+ %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\
27217
+ %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\
27218
%{pg:%{static:%{!mhp-ld:-a shared}%{mhp-ld:-a archive_shared}}\
27219
-lgprof %{static:-a archive}\
27220
- %{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\
27221
- %{static:-a archive}} -lpthread} -lc\
27222
- %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\
27223
+ %{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\
27224
+ %{mt|pthread:-lpthread} -lc\
27225
+ %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\
27226
+ %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\
27227
%{shared:%{mt|pthread:-lpthread}}"
27228
#else
27229
#define LIB_SPEC \
27230
"%{!shared:\
27231
- %{!p:%{!pg:%{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\
27232
- %{static:-a archive}} -lpthread} -lc\
27233
- %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\
27234
+ %{!p:%{!pg:%{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\
27235
+ %{mt|pthread:-lpthread} -lc\
27236
+ %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\
27237
+ %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\
27238
%{p:%{!pg:%{static:%{mgnu-ld:-a shared}%{!mgnu-ld:-a archive_shared}}\
27239
-lprof %{static:-a archive}\
27240
- %{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\
27241
- %{static:-a archive}} -lpthread} -lc\
27242
- %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\
27243
+ %{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\
27244
+ %{mt|pthread:-lpthread} -lc\
27245
+ %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\
27246
+ %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\
27247
%{pg:%{static:%{mgnu-ld:-a shared}%{!mgnu-ld:-a archive_shared}}\
27248
-lgprof %{static:-a archive}\
27249
- %{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\
27250
- %{static:-a archive}} -lpthread} -lc\
27251
- %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\
27252
+ %{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\
27253
+ %{mt|pthread:-lpthread} -lc\
27254
+ %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\
27255
+ %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\
27256
%{shared:%{mt|pthread:-lpthread}}"
27257
#endif
27258
27259
--- a/src/gcc/config/pa/stublib.c
27260
+++ b/src/gcc/config/pa/stublib.c
27261
@@ -1,5 +1,5 @@
27262
/* Stub functions.
27263
- Copyright (C) 2006, 2009 Free Software Foundation, Inc.
27264
+ Copyright (C) 2006, 2009, 2011 Free Software Foundation, Inc.
27265
27266
This file is part of GCC.
27267
27268
@@ -56,3 +56,42 @@
27002
@@ -5686,7 +5686,7 @@
27003
(define_expand "iordi3"
27004
[(set (match_operand:DI 0 "register_operand" "")
27005
(ior:DI (match_operand:DI 1 "register_operand" "")
27006
- (match_operand:DI 2 "ior_operand" "")))]
27007
+ (match_operand:DI 2 "reg_or_cint_ior_operand" "")))]
27008
""
27009
"
27269
27010
{
27270
}
27271
#endif
27272
+
27273
+#ifdef L_pthread_default_stacksize_np
27274
+int pthread_default_stacksize_np (unsigned long __attribute__((unused)),
27275
+ unsigned long *);
27276
+int
27277
+pthread_default_stacksize_np (unsigned long new, unsigned long *old)
27278
+{
27279
+ if (old)
27280
+ *old = 0;
27281
+ return 0;
27282
+}
27283
+#endif
27284
+
27285
+#ifdef L_pthread_mutex_lock
27286
+int pthread_mutex_lock (void);
27287
+int
27288
+pthread_mutex_lock (void)
27289
+{
27290
+ return 0;
27291
+}
27292
+#endif
27293
+
27294
+#ifdef L_pthread_mutex_unlock
27295
+int pthread_mutex_unlock (void);
27296
+int
27297
+pthread_mutex_unlock (void)
27298
+{
27299
+ return 0;
27300
+}
27301
+#endif
27302
+
27303
+#ifdef L_pthread_once
27304
+int pthread_once (void);
27305
+int
27306
+pthread_once (void)
27307
+{
27308
+ return 0;
27309
+}
27310
+#endif
27311
--- a/src/gcc/config/pa/t-pa-hpux11
27312
+++ b/src/gcc/config/pa/t-pa-hpux11
27313
@@ -1,2 +1,31 @@
27314
TARGET_LIBGCC2_CFLAGS = -fPIC -frandom-seed=fixed-seed
27315
LIB2FUNCS_EXTRA=lib2funcs.asm quadlib.c
27316
+LIBGCCSTUB_OBJS = pthread_default_stacksize_np-stub.o \
27317
+ pthread_mutex_lock-stub.o \
27318
+ pthread_mutex_unlock-stub.o \
27319
+ pthread_once-stub.o
27320
+
27321
+stublib.c: $(srcdir)/config/pa/stublib.c
27322
+ rm -f stublib.c
27323
+ cp $(srcdir)/config/pa/stublib.c .
27324
+
27325
+pthread_default_stacksize_np-stub.o: stublib.c $(GCC_PASSES)
27326
+ $(GCC_FOR_TARGET) -c -O2 -DL_pthread_default_stacksize_np stublib.c \
27327
+ -o pthread_default_stacksize_np-stub.o
27328
+
27329
+pthread_mutex_lock-stub.o: stublib.c $(GCC_PASSES)
27330
+ $(GCC_FOR_TARGET) -c -O2 -DL_pthread_mutex_lock stublib.c \
27331
+ -o pthread_mutex_lock-stub.o
27332
+
27333
+pthread_mutex_unlock-stub.o: stublib.c $(GCC_PASSES)
27334
+ $(GCC_FOR_TARGET) -c -O2 -DL_pthread_mutex_unlock stublib.c \
27335
+ -o pthread_mutex_unlock-stub.o
27336
+
27337
+pthread_once-stub.o: stublib.c $(GCC_PASSES)
27338
+ $(GCC_FOR_TARGET) -c -O2 -DL_pthread_once stublib.c \
27339
+ -o pthread_once-stub.o
27340
+
27341
+$(T)libgcc_stub.a: $(LIBGCCSTUB_OBJS)
27342
+ -rm -rf $(T)libgcc_stub.a
27343
+ $(AR) rc $(T)libgcc_stub.a $(LIBGCCSTUB_OBJS)
27344
+ $(RANLIB) $(T)libgcc_stub.a
27345
--- a/src/gcc/config/pa/t-pa64
27346
+++ b/src/gcc/config/pa/t-pa64
27347
@@ -1,5 +1,5 @@
27348
# Copyright (C) 2000, 2001, 2002, 2004, 2006,
27349
-# 2007 Free Software Foundation, Inc.
27350
+# 2007, 2011 Free Software Foundation, Inc.
27351
#
27352
# This file is part of GCC.
27353
#
27354
@@ -19,7 +19,11 @@
27355
27356
TARGET_LIBGCC2_CFLAGS = -fPIC -Dpa64=1 -DELF=1 -mlong-calls
27357
LIB2FUNCS_EXTRA = quadlib.c
27358
-LIBGCCSTUB_OBJS = rfi-stub.o dfi-stub.o jvrc-stub.o cxaf-stub.o
27359
+LIBGCCSTUB_OBJS = rfi-stub.o dfi-stub.o jvrc-stub.o cxaf-stub.o \
27360
+ pthread_default_stacksize_np-stub.o \
27361
+ pthread_mutex_lock-stub.o \
27362
+ pthread_mutex_unlock-stub.o \
27363
+ pthread_once-stub.o
27364
27365
stublib.c: $(srcdir)/config/pa/stublib.c
27366
rm -f stublib.c
27367
@@ -41,6 +45,22 @@
27368
$(GCC_FOR_TARGET) -c -O2 -DL_Jv_RegisterClasses stublib.c \
27369
-o jvrc-stub.o
27370
27371
+pthread_default_stacksize_np-stub.o: stublib.c $(GCC_PASSES)
27372
+ $(GCC_FOR_TARGET) -c -O2 -DL_pthread_default_stacksize_np stublib.c \
27373
+ -o pthread_default_stacksize_np-stub.o
27374
+
27375
+pthread_mutex_lock-stub.o: stublib.c $(GCC_PASSES)
27376
+ $(GCC_FOR_TARGET) -c -O2 -DL_pthread_mutex_lock stublib.c \
27377
+ -o pthread_mutex_lock-stub.o
27378
+
27379
+pthread_mutex_unlock-stub.o: stublib.c $(GCC_PASSES)
27380
+ $(GCC_FOR_TARGET) -c -O2 -DL_pthread_mutex_unlock stublib.c \
27381
+ -o pthread_mutex_unlock-stub.o
27382
+
27383
+pthread_once-stub.o: stublib.c $(GCC_PASSES)
27384
+ $(GCC_FOR_TARGET) -c -O2 -DL_pthread_once stublib.c \
27385
+ -o pthread_once-stub.o
27386
+
27387
$(T)libgcc_stub.a: $(LIBGCCSTUB_OBJS)
27388
-rm -rf $(T)libgcc_stub.a
27389
$(AR) rc $(T)libgcc_stub.a $(LIBGCCSTUB_OBJS)
27011
@@ -5707,7 +5707,7 @@
27012
(define_insn ""
27013
[(set (match_operand:DI 0 "register_operand" "=r,r")
27014
(ior:DI (match_operand:DI 1 "register_operand" "0,0")
27015
- (match_operand:DI 2 "ior_operand" "M,i")))]
27016
+ (match_operand:DI 2 "cint_ior_operand" "M,i")))]
27017
"TARGET_64BIT"
27018
"* return output_64bit_ior (operands); "
27019
[(set_attr "type" "binary,shift")
27020
@@ -5726,19 +5726,14 @@
27021
(define_expand "iorsi3"
27022
[(set (match_operand:SI 0 "register_operand" "")
27023
(ior:SI (match_operand:SI 1 "register_operand" "")
27024
- (match_operand:SI 2 "arith32_operand" "")))]
27025
+ (match_operand:SI 2 "reg_or_cint_ior_operand" "")))]
27026
""
27027
- "
27028
-{
27029
- if (! (ior_operand (operands[2], SImode)
27030
- || register_operand (operands[2], SImode)))
27031
- operands[2] = force_reg (SImode, operands[2]);
27032
-}")
27033
+ "")
27034
27035
(define_insn ""
27036
[(set (match_operand:SI 0 "register_operand" "=r,r")
27037
(ior:SI (match_operand:SI 1 "register_operand" "0,0")
27038
- (match_operand:SI 2 "ior_operand" "M,i")))]
27039
+ (match_operand:SI 2 "cint_ior_operand" "M,i")))]
27040
""
27041
"* return output_ior (operands); "
27042
[(set_attr "type" "binary,shift")
27043
--- a/src/gcc/config/pa/predicates.md
27044
+++ b/src/gcc/config/pa/predicates.md
27045
@@ -411,11 +411,15 @@
27046
27047
;; True iff depi can be used to compute (reg | OP).
27048
27049
-(define_predicate "ior_operand"
27050
- (match_code "const_int")
27051
-{
27052
- return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
27053
-})
27054
+(define_predicate "cint_ior_operand"
27055
+ (and (match_code "const_int")
27056
+ (match_test "ior_mask_p (INTVAL (op))")))
27057
+
27058
+;; True iff OP can be used to compute (reg | OP).
27059
+
27060
+(define_predicate "reg_or_cint_ior_operand"
27061
+ (ior (match_operand 0 "register_operand")
27062
+ (match_operand 0 "cint_ior_operand")))
27063
27064
;; True iff OP is a CONST_INT of the forms 0...0xxxx or
27065
;; 0...01...1xxxx. Such values can be the left hand side x in (x <<
27390
27066
--- a/src/gcc/config/picochip/picochip.c
27391
27067
+++ b/src/gcc/config/picochip/picochip.c
27392
27068
@@ -1996,7 +1996,7 @@
27409
27085
27410
27086
/* How Values Fit in Registers */
27411
27087
27412
--- a/src/gcc/config/rs6000/altivec.h
27413
+++ b/src/gcc/config/rs6000/altivec.h
27414
@@ -1,5 +1,6 @@
27415
/* PowerPC AltiVec include file.
27416
- Copyright (C) 2002, 2003, 2004, 2005, 2008, 2009 Free Software Foundation, Inc.
27417
+ Copyright (C) 2002, 2003, 2004, 2005, 2008, 2009, 2010, 2011
27418
+ Free Software Foundation, Inc.
27419
Contributed by Aldy Hernandez (aldyh@redhat.com).
27420
Rewritten by Paolo Bonzini (bonzini@gnu.org).
27421
27422
@@ -315,6 +316,8 @@
27423
#define vec_nearbyint __builtin_vec_nearbyint
27424
#define vec_rint __builtin_vec_rint
27425
#define vec_sqrt __builtin_vec_sqrt
27426
+#define vec_vsx_ld __builtin_vec_vsx_ld
27427
+#define vec_vsx_st __builtin_vec_vsx_st
27428
#endif
27429
27430
/* Predicates.
27431
--- a/src/gcc/config/rs6000/altivec.md
27432
+++ b/src/gcc/config/rs6000/altivec.md
27433
@@ -1,5 +1,5 @@
27434
;; AltiVec patterns.
27435
-;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
27436
+;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
27437
;; Free Software Foundation, Inc.
27438
;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
27439
27440
@@ -98,7 +98,7 @@
27441
(UNSPEC_STVE 203)
27442
(UNSPEC_SET_VSCR 213)
27443
(UNSPEC_GET_VRSAVE 214)
27444
- ;; 215 deleted
27445
+ (UNSPEC_LVX 215)
27446
(UNSPEC_REDUC_PLUS 217)
27447
(UNSPEC_VECSH 219)
27448
(UNSPEC_EXTEVEN_V4SI 220)
27449
@@ -171,6 +171,7 @@
27450
(define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI])
27451
27452
(define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
27453
+(define_mode_attr VI_scalar [(V4SI "SI") (V8HI "HI") (V16QI "QI")])
27454
27455
;; Vector move instructions.
27456
(define_insn "*altivec_mov<mode>"
27457
@@ -1751,17 +1752,19 @@
27458
"lvxl %0,%y1"
27459
[(set_attr "type" "vecload")])
27460
27461
-(define_insn "altivec_lvx"
27462
- [(set (match_operand:V4SI 0 "register_operand" "=v")
27463
- (match_operand:V4SI 1 "memory_operand" "Z"))]
27464
+(define_insn "altivec_lvx_<mode>"
27465
+ [(parallel
27466
+ [(set (match_operand:VM2 0 "register_operand" "=v")
27467
+ (match_operand:VM2 1 "memory_operand" "Z"))
27468
+ (unspec [(const_int 0)] UNSPEC_LVX)])]
27469
"TARGET_ALTIVEC"
27470
"lvx %0,%y1"
27471
[(set_attr "type" "vecload")])
27472
27473
-(define_insn "altivec_stvx"
27474
+(define_insn "altivec_stvx_<mode>"
27475
[(parallel
27476
- [(set (match_operand:V4SI 0 "memory_operand" "=Z")
27477
- (match_operand:V4SI 1 "register_operand" "v"))
27478
+ [(set (match_operand:VM2 0 "memory_operand" "=Z")
27479
+ (match_operand:VM2 1 "register_operand" "v"))
27480
(unspec [(const_int 0)] UNSPEC_STVX)])]
27481
"TARGET_ALTIVEC"
27482
"stvx %1,%y0"
27483
@@ -1777,19 +1780,15 @@
27484
[(set_attr "type" "vecstore")])
27485
27486
(define_insn "altivec_stve<VI_char>x"
27487
- [(parallel
27488
- [(set (match_operand:VI 0 "memory_operand" "=Z")
27489
- (match_operand:VI 1 "register_operand" "v"))
27490
- (unspec [(const_int 0)] UNSPEC_STVE)])]
27491
+ [(set (match_operand:<VI_scalar> 0 "memory_operand" "=Z")
27492
+ (unspec:<VI_scalar> [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))]
27493
"TARGET_ALTIVEC"
27494
"stve<VI_char>x %1,%y0"
27495
[(set_attr "type" "vecstore")])
27496
27497
(define_insn "*altivec_stvesfx"
27498
- [(parallel
27499
- [(set (match_operand:V4SF 0 "memory_operand" "=Z")
27500
- (match_operand:V4SF 1 "register_operand" "v"))
27501
- (unspec [(const_int 0)] UNSPEC_STVE)])]
27502
+ [(set (match_operand:SF 0 "memory_operand" "=Z")
27503
+ (unspec:SF [(match_operand:V4SF 1 "register_operand" "v")] UNSPEC_STVE))]
27504
"TARGET_ALTIVEC"
27505
"stvewx %1,%y0"
27506
[(set_attr "type" "vecstore")])
27507
27088
--- a/src/gcc/config/rs6000/linux64.h
27508
27089
+++ b/src/gcc/config/rs6000/linux64.h
27509
27090
@@ -344,10 +344,12 @@
27522
27103
#endif
27523
27104
#define LINUX_DYNAMIC_LINKER32 \
27524
27105
CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32)
27525
--- a/src/gcc/config/rs6000/rs6000-builtin.def
27526
+++ b/src/gcc/config/rs6000/rs6000-builtin.def
27527
@@ -1,5 +1,5 @@
27528
/* Builtin functions for rs6000/powerpc.
27529
- Copyright (C) 2009, 2010
27530
+ Copyright (C) 2009, 2010, 2011
27531
Free Software Foundation, Inc.
27532
Contributed by Michael Meissner (meissner@linux.vnet.ibm.com)
27533
27534
@@ -37,6 +37,10 @@
27535
RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_16qi, RS6000_BTC_MEM)
27536
RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_4sf, RS6000_BTC_MEM)
27537
RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_4sf, RS6000_BTC_MEM)
27538
+RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_2df, RS6000_BTC_MEM)
27539
+RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_2df, RS6000_BTC_MEM)
27540
+RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_2di, RS6000_BTC_MEM)
27541
+RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_2di, RS6000_BTC_MEM)
27542
RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUBM, RS6000_BTC_CONST)
27543
RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUHM, RS6000_BTC_CONST)
27544
RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUWM, RS6000_BTC_CONST)
27545
@@ -774,12 +778,20 @@
27546
27547
/* VSX builtins. */
27548
RS6000_BUILTIN(VSX_BUILTIN_LXSDX, RS6000_BTC_MEM)
27549
-RS6000_BUILTIN(VSX_BUILTIN_LXVD2X, RS6000_BTC_MEM)
27550
+RS6000_BUILTIN(VSX_BUILTIN_LXVD2X_V2DF, RS6000_BTC_MEM)
27551
+RS6000_BUILTIN(VSX_BUILTIN_LXVD2X_V2DI, RS6000_BTC_MEM)
27552
RS6000_BUILTIN(VSX_BUILTIN_LXVDSX, RS6000_BTC_MEM)
27553
-RS6000_BUILTIN(VSX_BUILTIN_LXVW4X, RS6000_BTC_MEM)
27554
+RS6000_BUILTIN(VSX_BUILTIN_LXVW4X_V4SF, RS6000_BTC_MEM)
27555
+RS6000_BUILTIN(VSX_BUILTIN_LXVW4X_V4SI, RS6000_BTC_MEM)
27556
+RS6000_BUILTIN(VSX_BUILTIN_LXVW4X_V8HI, RS6000_BTC_MEM)
27557
+RS6000_BUILTIN(VSX_BUILTIN_LXVW4X_V16QI, RS6000_BTC_MEM)
27558
RS6000_BUILTIN(VSX_BUILTIN_STXSDX, RS6000_BTC_MEM)
27559
-RS6000_BUILTIN(VSX_BUILTIN_STXVD2X, RS6000_BTC_MEM)
27560
-RS6000_BUILTIN(VSX_BUILTIN_STXVW4X, RS6000_BTC_MEM)
27561
+RS6000_BUILTIN(VSX_BUILTIN_STXVD2X_V2DF, RS6000_BTC_MEM)
27562
+RS6000_BUILTIN(VSX_BUILTIN_STXVD2X_V2DI, RS6000_BTC_MEM)
27563
+RS6000_BUILTIN(VSX_BUILTIN_STXVW4X_V4SF, RS6000_BTC_MEM)
27564
+RS6000_BUILTIN(VSX_BUILTIN_STXVW4X_V4SI, RS6000_BTC_MEM)
27565
+RS6000_BUILTIN(VSX_BUILTIN_STXVW4X_V8HI, RS6000_BTC_MEM)
27566
+RS6000_BUILTIN(VSX_BUILTIN_STXVW4X_V16QI, RS6000_BTC_MEM)
27567
RS6000_BUILTIN(VSX_BUILTIN_XSABSDP, RS6000_BTC_CONST)
27568
RS6000_BUILTIN(VSX_BUILTIN_XSADDDP, RS6000_BTC_FP_PURE)
27569
RS6000_BUILTIN(VSX_BUILTIN_XSCMPODP, RS6000_BTC_FP_PURE)
27570
@@ -975,8 +987,10 @@
27571
RS6000_BUILTIN(VSX_BUILTIN_VEC_XXSLDWI, RS6000_BTC_MISC)
27572
RS6000_BUILTIN(VSX_BUILTIN_VEC_XXSPLTD, RS6000_BTC_MISC)
27573
RS6000_BUILTIN(VSX_BUILTIN_VEC_XXSPLTW, RS6000_BTC_MISC)
27574
+RS6000_BUILTIN(VSX_BUILTIN_VEC_LD, RS6000_BTC_MISC)
27575
+RS6000_BUILTIN(VSX_BUILTIN_VEC_ST, RS6000_BTC_MISC)
27576
RS6000_BUILTIN_EQUATE(VSX_BUILTIN_OVERLOADED_LAST,
27577
- VSX_BUILTIN_VEC_XXSPLTW)
27578
+ VSX_BUILTIN_VEC_ST)
27579
27580
/* Combined VSX/Altivec builtins. */
27581
RS6000_BUILTIN(VECTOR_BUILTIN_FLOAT_V4SI_V4SF, RS6000_BTC_FP_PURE)
27582
--- a/src/gcc/config/rs6000/rs6000-c.c
27583
+++ b/src/gcc/config/rs6000/rs6000-c.c
27584
@@ -965,6 +965,15 @@
27585
{ VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,
27586
RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
27587
{ ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
27588
+ RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
27589
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
27590
+ RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
27591
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
27592
+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
27593
+ ~RS6000_BTI_unsigned_V2DI, 0 },
27594
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
27595
+ RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
27596
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
27597
RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
27598
{ ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
27599
RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
27600
@@ -1077,9 +1086,19 @@
27601
{ ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
27602
RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
27603
{ ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
27604
- RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
27605
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
27606
+ ~RS6000_BTI_unsigned_V16QI, 0 },
27607
{ ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
27608
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
27609
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
27610
+ RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
27611
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
27612
+ RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
27613
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
27614
+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
27615
+ ~RS6000_BTI_unsigned_V2DI, 0 },
27616
+ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
27617
+ RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
27618
{ ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
27619
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
27620
{ ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
27621
@@ -1098,6 +1117,17 @@
27622
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
27623
{ ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
27624
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
27625
+ { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
27626
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
27627
+ { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
27628
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
27629
+ { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
27630
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
27631
+ { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
27632
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
27633
+ { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
27634
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
27635
+ ~RS6000_BTI_unsigned_long_long, 0 },
27636
{ ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
27637
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
27638
{ ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
27639
@@ -1116,6 +1146,17 @@
27640
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
27641
{ ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
27642
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
27643
+ { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
27644
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
27645
+ { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
27646
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
27647
+ { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
27648
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
27649
+ { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
27650
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
27651
+ { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
27652
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
27653
+ ~RS6000_BTI_unsigned_long_long, 0 },
27654
{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
27655
RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
27656
{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
27657
@@ -2609,6 +2650,16 @@
27658
{ ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
27659
RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE },
27660
{ ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
27661
+ RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
27662
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
27663
+ RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
27664
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
27665
+ RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
27666
+ ~RS6000_BTI_unsigned_V2DI },
27667
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
27668
+ RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
27669
+ ~RS6000_BTI_bool_V2DI },
27670
+ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
27671
RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
27672
{ ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
27673
RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
27674
@@ -2774,6 +2825,18 @@
27675
RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
27676
{ ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
27677
RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
27678
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
27679
+ RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
27680
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
27681
+ RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
27682
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
27683
+ RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
27684
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
27685
+ RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
27686
+ ~RS6000_BTI_unsigned_V2DI },
27687
+ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
27688
+ RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
27689
+ ~RS6000_BTI_bool_V2DI },
27690
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
27691
RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
27692
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
27693
@@ -2967,6 +3030,135 @@
27694
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
27695
RS6000_BTI_NOT_OPAQUE },
27696
27697
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
27698
+ RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
27699
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
27700
+ RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
27701
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
27702
+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
27703
+ ~RS6000_BTI_unsigned_V2DI, 0 },
27704
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
27705
+ RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
27706
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
27707
+ RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
27708
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
27709
+ RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
27710
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
27711
+ RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
27712
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
27713
+ RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
27714
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
27715
+ RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
27716
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
27717
+ RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
27718
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
27719
+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
27720
+ ~RS6000_BTI_unsigned_V4SI, 0 },
27721
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
27722
+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
27723
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
27724
+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
27725
+ ~RS6000_BTI_unsigned_long, 0 },
27726
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
27727
+ RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
27728
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
27729
+ RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
27730
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
27731
+ RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
27732
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
27733
+ RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
27734
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
27735
+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
27736
+ ~RS6000_BTI_unsigned_V8HI, 0 },
27737
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
27738
+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
27739
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
27740
+ RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
27741
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
27742
+ RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
27743
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
27744
+ RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
27745
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
27746
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
27747
+ ~RS6000_BTI_unsigned_V16QI, 0 },
27748
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
27749
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
27750
+
27751
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
27752
+ RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
27753
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
27754
+ RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
27755
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
27756
+ RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
27757
+ ~RS6000_BTI_unsigned_V2DI },
27758
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
27759
+ RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
27760
+ ~RS6000_BTI_bool_V2DI },
27761
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
27762
+ RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
27763
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
27764
+ RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
27765
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
27766
+ RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
27767
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
27768
+ RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
27769
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
27770
+ RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
27771
+ ~RS6000_BTI_unsigned_V4SI },
27772
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
27773
+ RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
27774
+ ~RS6000_BTI_UINTSI },
27775
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
27776
+ RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
27777
+ ~RS6000_BTI_bool_V4SI },
27778
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
27779
+ RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
27780
+ ~RS6000_BTI_UINTSI },
27781
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
27782
+ RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
27783
+ ~RS6000_BTI_INTSI },
27784
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
27785
+ RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
27786
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
27787
+ RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
27788
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
27789
+ RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
27790
+ ~RS6000_BTI_unsigned_V8HI },
27791
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
27792
+ RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
27793
+ ~RS6000_BTI_UINTHI },
27794
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
27795
+ RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
27796
+ ~RS6000_BTI_bool_V8HI },
27797
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
27798
+ RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
27799
+ ~RS6000_BTI_UINTHI },
27800
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
27801
+ RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
27802
+ ~RS6000_BTI_INTHI },
27803
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
27804
+ RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
27805
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
27806
+ RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
27807
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
27808
+ RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
27809
+ ~RS6000_BTI_unsigned_V16QI },
27810
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
27811
+ RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
27812
+ ~RS6000_BTI_UINTQI },
27813
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
27814
+ RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
27815
+ ~RS6000_BTI_bool_V16QI },
27816
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
27817
+ RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
27818
+ ~RS6000_BTI_UINTQI },
27819
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
27820
+ RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
27821
+ ~RS6000_BTI_INTQI },
27822
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
27823
+ RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI,
27824
+ ~RS6000_BTI_pixel_V8HI },
27825
+
27826
/* Predicates. */
27827
{ ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
27828
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
27829
--- a/src/gcc/config/rs6000/rs6000-protos.h
27830
+++ b/src/gcc/config/rs6000/rs6000-protos.h
27831
@@ -1,5 +1,6 @@
27832
/* Definitions of target machine for GNU compiler, for IBM RS/6000.
27833
- Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
27834
+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
27835
+ 2010, 2011
27836
Free Software Foundation, Inc.
27837
Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
27838
27839
@@ -130,6 +131,7 @@
27840
27841
extern rtx rs6000_machopic_legitimize_pic_address (rtx, enum machine_mode,
27842
rtx);
27843
+extern rtx rs6000_address_for_altivec (rtx);
27844
#endif /* RTX_CODE */
27845
27846
#ifdef TREE_CODE
27847
27106
--- a/src/gcc/config/rs6000/rs6000.c
27848
27107
+++ b/src/gcc/config/rs6000/rs6000.c
27849
@@ -2865,9 +2865,12 @@
27850
/* If not explicitly specified via option, decide whether to generate indexed
27851
load/store instructions. */
27852
if (TARGET_AVOID_XFORM == -1)
27853
- /* Avoid indexed addressing when targeting Power6 in order to avoid
27854
- the DERAT mispredict penalty. */
27855
- TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB);
27856
+ /* Avoid indexed addressing when targeting Power6 in order to avoid the
27857
+ DERAT mispredict penalty. However the LVE and STVE altivec instructions
27858
+ need indexed accesses and the type used is the scalar type of the element
27859
+ being loaded or stored. */
27860
+ TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB
27861
+ && !TARGET_ALTIVEC);
27862
27863
rs6000_init_hard_regno_mode_ok ();
27864
}
27865
@@ -4472,7 +4475,7 @@
27866
{
27867
enum machine_mode mode = GET_MODE (vec);
27868
enum machine_mode inner_mode = GET_MODE_INNER (mode);
27869
- rtx mem, x;
27870
+ rtx mem;
27871
27872
if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
27873
{
27874
@@ -4485,17 +4488,11 @@
27875
/* Allocate mode-sized buffer. */
27876
mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
27877
27878
+ emit_move_insn (mem, vec);
27879
+
27880
/* Add offset to field within buffer matching vector element. */
27881
- mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
27882
+ mem = adjust_address_nv (mem, inner_mode, elt * GET_MODE_SIZE (inner_mode));
27883
27884
- /* Store single field into mode-sized buffer. */
27885
- x = gen_rtx_UNSPEC (VOIDmode,
27886
- gen_rtvec (1, const0_rtx), UNSPEC_STVE);
27887
- emit_insn (gen_rtx_PARALLEL (VOIDmode,
27888
- gen_rtvec (2,
27889
- gen_rtx_SET (VOIDmode,
27890
- mem, vec),
27891
- x)));
27892
emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
27893
}
27894
27895
@@ -9897,6 +9894,7 @@
27896
rtx op2 = expand_normal (arg2);
27897
rtx pat, addr;
27898
enum machine_mode tmode = insn_data[icode].operand[0].mode;
27899
+ enum machine_mode smode = insn_data[icode].operand[1].mode;
27900
enum machine_mode mode1 = Pmode;
27901
enum machine_mode mode2 = Pmode;
27902
27903
@@ -9906,8 +9904,8 @@
27904
|| arg2 == error_mark_node)
27905
return const0_rtx;
27906
27907
- if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
27908
- op0 = copy_to_mode_reg (tmode, op0);
27909
+ if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
27910
+ op0 = copy_to_mode_reg (smode, op0);
27911
27912
op2 = copy_to_mode_reg (mode2, op2);
27913
27914
@@ -10041,16 +10039,22 @@
27915
switch (fcode)
27916
{
27917
case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
27918
- icode = CODE_FOR_vector_load_v16qi;
27919
+ icode = CODE_FOR_vector_altivec_load_v16qi;
27920
break;
27921
case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
27922
- icode = CODE_FOR_vector_load_v8hi;
27923
+ icode = CODE_FOR_vector_altivec_load_v8hi;
27924
break;
27925
case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
27926
- icode = CODE_FOR_vector_load_v4si;
27927
+ icode = CODE_FOR_vector_altivec_load_v4si;
27928
break;
27929
case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
27930
- icode = CODE_FOR_vector_load_v4sf;
27931
+ icode = CODE_FOR_vector_altivec_load_v4sf;
27932
+ break;
27933
+ case ALTIVEC_BUILTIN_LD_INTERNAL_2df:
27934
+ icode = CODE_FOR_vector_altivec_load_v2df;
27935
+ break;
27936
+ case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
27937
+ icode = CODE_FOR_vector_altivec_load_v2di;
27938
break;
27939
default:
27940
*expandedp = false;
27941
@@ -10094,16 +10098,22 @@
27942
switch (fcode)
27943
{
27944
case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
27945
- icode = CODE_FOR_vector_store_v16qi;
27946
+ icode = CODE_FOR_vector_altivec_store_v16qi;
27947
break;
27948
case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
27949
- icode = CODE_FOR_vector_store_v8hi;
27950
+ icode = CODE_FOR_vector_altivec_store_v8hi;
27951
break;
27952
case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
27953
- icode = CODE_FOR_vector_store_v4si;
27954
+ icode = CODE_FOR_vector_altivec_store_v4si;
27955
break;
27956
case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
27957
- icode = CODE_FOR_vector_store_v4sf;
27958
+ icode = CODE_FOR_vector_altivec_store_v4sf;
27959
+ break;
27960
+ case ALTIVEC_BUILTIN_ST_INTERNAL_2df:
27961
+ icode = CODE_FOR_vector_altivec_store_v2df;
27962
+ break;
27963
+ case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
27964
+ icode = CODE_FOR_vector_altivec_store_v2di;
27965
break;
27966
default:
27967
*expandedp = false;
27968
@@ -10336,7 +10346,7 @@
27969
switch (fcode)
27970
{
27971
case ALTIVEC_BUILTIN_STVX:
27972
- return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp);
27973
+ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
27974
case ALTIVEC_BUILTIN_STVEBX:
27975
return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
27976
case ALTIVEC_BUILTIN_STVEHX:
27977
@@ -10355,6 +10365,19 @@
27978
case ALTIVEC_BUILTIN_STVRXL:
27979
return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
27980
27981
+ case VSX_BUILTIN_STXVD2X_V2DF:
27982
+ return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
27983
+ case VSX_BUILTIN_STXVD2X_V2DI:
27984
+ return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
27985
+ case VSX_BUILTIN_STXVW4X_V4SF:
27986
+ return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
27987
+ case VSX_BUILTIN_STXVW4X_V4SI:
27988
+ return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
27989
+ case VSX_BUILTIN_STXVW4X_V8HI:
27990
+ return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
27991
+ case VSX_BUILTIN_STXVW4X_V16QI:
27992
+ return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
27993
+
27994
case ALTIVEC_BUILTIN_MFVSCR:
27995
icode = CODE_FOR_altivec_mfvscr;
27996
tmode = insn_data[icode].operand[0].mode;
27997
@@ -10479,7 +10502,7 @@
27998
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
27999
exp, target, false);
28000
case ALTIVEC_BUILTIN_LVX:
28001
- return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
28002
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
28003
exp, target, false);
28004
case ALTIVEC_BUILTIN_LVLX:
28005
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
28006
@@ -10493,6 +10516,25 @@
28007
case ALTIVEC_BUILTIN_LVRXL:
28008
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
28009
exp, target, true);
28010
+ case VSX_BUILTIN_LXVD2X_V2DF:
28011
+ return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
28012
+ exp, target, false);
28013
+ case VSX_BUILTIN_LXVD2X_V2DI:
28014
+ return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
28015
+ exp, target, false);
28016
+ case VSX_BUILTIN_LXVW4X_V4SF:
28017
+ return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
28018
+ exp, target, false);
28019
+ case VSX_BUILTIN_LXVW4X_V4SI:
28020
+ return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
28021
+ exp, target, false);
28022
+ case VSX_BUILTIN_LXVW4X_V8HI:
28023
+ return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
28024
+ exp, target, false);
28025
+ case VSX_BUILTIN_LXVW4X_V16QI:
28026
+ return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
28027
+ exp, target, false);
28028
+ break;
28029
default:
28030
break;
28031
/* Fall through. */
28032
@@ -11099,6 +11141,8 @@
28033
28034
long_integer_type_internal_node = long_integer_type_node;
28035
long_unsigned_type_internal_node = long_unsigned_type_node;
28036
+ long_long_integer_type_internal_node = long_long_integer_type_node;
28037
+ long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
28038
intQI_type_internal_node = intQI_type_node;
28039
uintQI_type_internal_node = unsigned_intQI_type_node;
28040
intHI_type_internal_node = intHI_type_node;
28041
@@ -11108,7 +11152,7 @@
28042
intDI_type_internal_node = intDI_type_node;
28043
uintDI_type_internal_node = unsigned_intDI_type_node;
28044
float_type_internal_node = float_type_node;
28045
- double_type_internal_node = float_type_node;
28046
+ double_type_internal_node = double_type_node;
28047
void_type_internal_node = void_type_node;
28048
28049
/* Initialize the modes for builtin_function_type, mapping a machine mode to
28050
@@ -11631,19 +11675,11 @@
28051
size_t i;
28052
tree ftype;
28053
28054
- tree pfloat_type_node = build_pointer_type (float_type_node);
28055
- tree pint_type_node = build_pointer_type (integer_type_node);
28056
- tree pshort_type_node = build_pointer_type (short_integer_type_node);
28057
- tree pchar_type_node = build_pointer_type (char_type_node);
28058
-
28059
tree pvoid_type_node = build_pointer_type (void_type_node);
28060
28061
- tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
28062
- tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
28063
- tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
28064
- tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
28065
-
28066
- tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
28067
+ tree pcvoid_type_node
28068
+ = build_pointer_type (build_qualified_type (void_type_node,
28069
+ TYPE_QUAL_CONST));
28070
28071
tree int_ftype_opaque
28072
= build_function_type_list (integer_type_node,
28073
@@ -11666,26 +11702,6 @@
28074
= build_function_type_list (integer_type_node,
28075
integer_type_node, V4SI_type_node,
28076
V4SI_type_node, NULL_TREE);
28077
- tree v4sf_ftype_pcfloat
28078
- = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
28079
- tree void_ftype_pfloat_v4sf
28080
- = build_function_type_list (void_type_node,
28081
- pfloat_type_node, V4SF_type_node, NULL_TREE);
28082
- tree v4si_ftype_pcint
28083
- = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
28084
- tree void_ftype_pint_v4si
28085
- = build_function_type_list (void_type_node,
28086
- pint_type_node, V4SI_type_node, NULL_TREE);
28087
- tree v8hi_ftype_pcshort
28088
- = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
28089
- tree void_ftype_pshort_v8hi
28090
- = build_function_type_list (void_type_node,
28091
- pshort_type_node, V8HI_type_node, NULL_TREE);
28092
- tree v16qi_ftype_pcchar
28093
- = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
28094
- tree void_ftype_pchar_v16qi
28095
- = build_function_type_list (void_type_node,
28096
- pchar_type_node, V16QI_type_node, NULL_TREE);
28097
tree void_ftype_v4si
28098
= build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
28099
tree v8hi_ftype_void
28100
@@ -11697,16 +11713,32 @@
28101
28102
tree opaque_ftype_long_pcvoid
28103
= build_function_type_list (opaque_V4SI_type_node,
28104
- long_integer_type_node, pcvoid_type_node, NULL_TREE);
28105
+ long_integer_type_node, pcvoid_type_node,
28106
+ NULL_TREE);
28107
tree v16qi_ftype_long_pcvoid
28108
= build_function_type_list (V16QI_type_node,
28109
- long_integer_type_node, pcvoid_type_node, NULL_TREE);
28110
+ long_integer_type_node, pcvoid_type_node,
28111
+ NULL_TREE);
28112
tree v8hi_ftype_long_pcvoid
28113
= build_function_type_list (V8HI_type_node,
28114
- long_integer_type_node, pcvoid_type_node, NULL_TREE);
28115
+ long_integer_type_node, pcvoid_type_node,
28116
+ NULL_TREE);
28117
tree v4si_ftype_long_pcvoid
28118
= build_function_type_list (V4SI_type_node,
28119
- long_integer_type_node, pcvoid_type_node, NULL_TREE);
28120
+ long_integer_type_node, pcvoid_type_node,
28121
+ NULL_TREE);
28122
+ tree v4sf_ftype_long_pcvoid
28123
+ = build_function_type_list (V4SF_type_node,
28124
+ long_integer_type_node, pcvoid_type_node,
28125
+ NULL_TREE);
28126
+ tree v2df_ftype_long_pcvoid
28127
+ = build_function_type_list (V2DF_type_node,
28128
+ long_integer_type_node, pcvoid_type_node,
28129
+ NULL_TREE);
28130
+ tree v2di_ftype_long_pcvoid
28131
+ = build_function_type_list (V2DI_type_node,
28132
+ long_integer_type_node, pcvoid_type_node,
28133
+ NULL_TREE);
28134
28135
tree void_ftype_opaque_long_pvoid
28136
= build_function_type_list (void_type_node,
28137
@@ -11724,6 +11756,18 @@
28138
= build_function_type_list (void_type_node,
28139
V8HI_type_node, long_integer_type_node,
28140
pvoid_type_node, NULL_TREE);
28141
+ tree void_ftype_v4sf_long_pvoid
28142
+ = build_function_type_list (void_type_node,
28143
+ V4SF_type_node, long_integer_type_node,
28144
+ pvoid_type_node, NULL_TREE);
28145
+ tree void_ftype_v2df_long_pvoid
28146
+ = build_function_type_list (void_type_node,
28147
+ V2DF_type_node, long_integer_type_node,
28148
+ pvoid_type_node, NULL_TREE);
28149
+ tree void_ftype_v2di_long_pvoid
28150
+ = build_function_type_list (void_type_node,
28151
+ V2DI_type_node, long_integer_type_node,
28152
+ pvoid_type_node, NULL_TREE);
28153
tree int_ftype_int_v8hi_v8hi
28154
= build_function_type_list (integer_type_node,
28155
integer_type_node, V8HI_type_node,
28156
@@ -11755,22 +11799,6 @@
28157
pcvoid_type_node, integer_type_node,
28158
integer_type_node, NULL_TREE);
28159
28160
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
28161
- ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
28162
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
28163
- ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
28164
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
28165
- ALTIVEC_BUILTIN_LD_INTERNAL_4si);
28166
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
28167
- ALTIVEC_BUILTIN_ST_INTERNAL_4si);
28168
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
28169
- ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
28170
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
28171
- ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
28172
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
28173
- ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
28174
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
28175
- ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
28176
def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
28177
def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
28178
def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
28179
@@ -11802,6 +11830,35 @@
28180
def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
28181
def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
28182
28183
+ def_builtin (MASK_VSX, "__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
28184
+ VSX_BUILTIN_LXVD2X_V2DF);
28185
+ def_builtin (MASK_VSX, "__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
28186
+ VSX_BUILTIN_LXVD2X_V2DI);
28187
+ def_builtin (MASK_VSX, "__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
28188
+ VSX_BUILTIN_LXVW4X_V4SF);
28189
+ def_builtin (MASK_VSX, "__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
28190
+ VSX_BUILTIN_LXVW4X_V4SI);
28191
+ def_builtin (MASK_VSX, "__builtin_vsx_lxvw4x_v8hi",
28192
+ v8hi_ftype_long_pcvoid, VSX_BUILTIN_LXVW4X_V8HI);
28193
+ def_builtin (MASK_VSX, "__builtin_vsx_lxvw4x_v16qi",
28194
+ v16qi_ftype_long_pcvoid, VSX_BUILTIN_LXVW4X_V16QI);
28195
+ def_builtin (MASK_VSX, "__builtin_vsx_stxvd2x_v2df",
28196
+ void_ftype_v2df_long_pvoid, VSX_BUILTIN_STXVD2X_V2DF);
28197
+ def_builtin (MASK_VSX, "__builtin_vsx_stxvd2x_v2di",
28198
+ void_ftype_v2di_long_pvoid, VSX_BUILTIN_STXVD2X_V2DI);
28199
+ def_builtin (MASK_VSX, "__builtin_vsx_stxvw4x_v4sf",
28200
+ void_ftype_v4sf_long_pvoid, VSX_BUILTIN_STXVW4X_V4SF);
28201
+ def_builtin (MASK_VSX, "__builtin_vsx_stxvw4x_v4si",
28202
+ void_ftype_v4si_long_pvoid, VSX_BUILTIN_STXVW4X_V4SI);
28203
+ def_builtin (MASK_VSX, "__builtin_vsx_stxvw4x_v8hi",
28204
+ void_ftype_v8hi_long_pvoid, VSX_BUILTIN_STXVW4X_V8HI);
28205
+ def_builtin (MASK_VSX, "__builtin_vsx_stxvw4x_v16qi",
28206
+ void_ftype_v16qi_long_pvoid, VSX_BUILTIN_STXVW4X_V16QI);
28207
+ def_builtin (MASK_VSX, "__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
28208
+ VSX_BUILTIN_VEC_LD);
28209
+ def_builtin (MASK_VSX, "__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
28210
+ VSX_BUILTIN_VEC_ST);
28211
+
28212
if (rs6000_cpu == PROCESSOR_CELL)
28213
{
28214
def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
28215
@@ -18506,7 +18563,7 @@
27108
@@ -18563,7 +18563,7 @@
28216
27109
p = rtvec_alloc ((lr ? 4 : 3) + n_regs);
28217
27110
28218
27111
if (!savep && lr)
28221
27114
28222
27115
RTVEC_ELT (p, offset++)
28223
27116
= gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 65));
28224
@@ -19581,7 +19638,7 @@
27117
@@ -19638,7 +19638,7 @@
28225
27118
alloc_rname = ggc_strdup (rname);
28226
27119
28227
27120
j = 0;
28230
27123
RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
28231
27124
gen_rtx_REG (Pmode,
28232
27125
LR_REGNO));
28233
@@ -20197,7 +20254,7 @@
27126
@@ -20254,7 +20254,7 @@
28234
27127
else
28235
27128
p = rtvec_alloc (2);
28236
27129
28239
27132
RTVEC_ELT (p, 1) = ((restoring_FPRs_inline || !lr)
28240
27133
? gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 65))
28241
27134
: gen_rtx_CLOBBER (VOIDmode,
28242
@@ -20638,7 +20695,7 @@
27135
@@ -20695,7 +20695,7 @@
28243
27136
gen_rtx_USE (VOIDmode,
28244
27137
gen_rtx_REG (SImode,
28245
27138
LR_REGNO)),
28248
27141
SIBLING_CALL_P (insn) = 1;
28249
27142
emit_barrier ();
28250
27143
28251
@@ -25811,4 +25868,29 @@
28252
}
28253
}
28254
28255
+/* Given a memory reference, if it is not in the form for altivec memory
28256
+ reference instructions (i.e. reg or reg+reg addressing with AND of -16),
28257
+ convert to the altivec format. */
28258
+
28259
+rtx
28260
+rs6000_address_for_altivec (rtx x)
28261
+{
28262
+ gcc_assert (MEM_P (x));
28263
+ if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x)))
28264
+ {
28265
+ rtx addr = XEXP (x, 0);
28266
+ int strict_p = (reload_in_progress || reload_completed);
28267
+
28268
+ if (!legitimate_indexed_address_p (addr, strict_p)
28269
+ && !legitimate_indirect_address_p (addr, strict_p))
28270
+ addr = copy_to_mode_reg (Pmode, addr);
28271
+
28272
+ addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16));
28273
+ x = change_address (x, GET_MODE (x), addr);
28274
+ }
28275
+
28276
+ return x;
28277
+}
28278
+
28279
+
28280
#include "gt-rs6000.h"
28281
--- a/src/gcc/config/rs6000/rs6000.h
28282
+++ b/src/gcc/config/rs6000/rs6000.h
28283
@@ -1,6 +1,7 @@
28284
/* Definitions of target machine for GNU compiler, for IBM RS/6000.
28285
Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
28286
- 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
28287
+ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
28288
+ 2010, 2011
28289
Free Software Foundation, Inc.
28290
Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
28291
28292
@@ -1035,6 +1036,16 @@
28293
28294
#define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)]
28295
28296
+/* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
28297
+ enough space to account for vectors in FP regs. */
28298
+#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
28299
+ (TARGET_VSX \
28300
+ && ((MODE) == VOIDmode || VSX_VECTOR_MODE (MODE) \
28301
+ || ALTIVEC_VECTOR_MODE (MODE)) \
28302
+ && FP_REGNO_P (REGNO) \
28303
+ ? V2DFmode \
28304
+ : choose_hard_reg_mode ((REGNO), (NREGS), false))
28305
+
28306
#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
28307
(((TARGET_32BIT && TARGET_POWERPC64 \
28308
&& (GET_MODE_SIZE (MODE) > 4) \
28309
@@ -2489,6 +2500,8 @@
28310
RS6000_BTI_pixel_V8HI, /* __vector __pixel */
28311
RS6000_BTI_long, /* long_integer_type_node */
28312
RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
28313
+ RS6000_BTI_long_long, /* long_long_integer_type_node */
28314
+ RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */
28315
RS6000_BTI_INTQI, /* intQI_type_node */
28316
RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
28317
RS6000_BTI_INTHI, /* intHI_type_node */
28318
@@ -2532,6 +2545,8 @@
28319
#define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
28320
#define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
28321
28322
+#define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long])
28323
+#define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long])
28324
#define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
28325
#define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
28326
#define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
28327
27144
--- a/src/gcc/config/rs6000/sysv4.h
28328
27145
+++ b/src/gcc/config/rs6000/sysv4.h
28329
27146
@@ -901,10 +901,12 @@
28342
27159
#endif
28343
27160
#define LINUX_DYNAMIC_LINKER \
28344
27161
CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER)
28345
--- a/src/gcc/config/rs6000/vector.md
28346
+++ b/src/gcc/config/rs6000/vector.md
28347
@@ -3,7 +3,7 @@
28348
;; expander, and the actual vector instructions will be in altivec.md and
28349
;; vsx.md
28350
28351
-;; Copyright (C) 2009, 2010
28352
+;; Copyright (C) 2009, 2010, 2011
28353
;; Free Software Foundation, Inc.
28354
;; Contributed by Michael Meissner <meissner@linux.vnet.ibm.com>
28355
28356
@@ -123,6 +123,43 @@
28357
DONE;
28358
})
28359
28360
+;; Vector floating point load/store instructions that uses the Altivec
28361
+;; instructions even if we are compiling for VSX, since the Altivec
28362
+;; instructions silently ignore the bottom 3 bits of the address, and VSX does
28363
+;; not.
28364
+(define_expand "vector_altivec_load_<mode>"
28365
+ [(set (match_operand:VEC_M 0 "vfloat_operand" "")
28366
+ (match_operand:VEC_M 1 "memory_operand" ""))]
28367
+ "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
28368
+ "
28369
+{
28370
+ gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
28371
+
28372
+ if (VECTOR_MEM_VSX_P (<MODE>mode))
28373
+ {
28374
+ operands[1] = rs6000_address_for_altivec (operands[1]);
28375
+ emit_insn (gen_altivec_lvx_<mode> (operands[0], operands[1]));
28376
+ DONE;
28377
+ }
28378
+}")
28379
+
28380
+(define_expand "vector_altivec_store_<mode>"
28381
+ [(set (match_operand:VEC_M 0 "memory_operand" "")
28382
+ (match_operand:VEC_M 1 "vfloat_operand" ""))]
28383
+ "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
28384
+ "
28385
+{
28386
+ gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
28387
+
28388
+ if (VECTOR_MEM_VSX_P (<MODE>mode))
28389
+ {
28390
+ operands[0] = rs6000_address_for_altivec (operands[0]);
28391
+ emit_insn (gen_altivec_stvx_<mode> (operands[0], operands[1]));
28392
+ DONE;
28393
+ }
28394
+}")
28395
+
28396
+
28397
28398
;; Reload patterns for vector operations. We may need an addtional base
28399
;; register to convert the reg+offset addressing to reg+reg for vector
28400
--- a/src/gcc/config/rs6000/vsx.md
28401
+++ b/src/gcc/config/rs6000/vsx.md
28402
@@ -1,5 +1,5 @@
28403
;; VSX patterns.
28404
-;; Copyright (C) 2009
28405
+;; Copyright (C) 2009, 2010, 2011
28406
;; Free Software Foundation, Inc.
28407
;; Contributed by Michael Meissner <meissner@linux.vnet.ibm.com>
28408
28409
@@ -309,6 +309,19 @@
28410
}
28411
[(set_attr "type" "vecstore,vecload,vecsimple,*,*,*,vecsimple,*,vecstore,vecload")])
28412
28413
+;; Explicit load/store expanders for the builtin functions
28414
+(define_expand "vsx_load_<mode>"
28415
+ [(set (match_operand:VSX_M 0 "vsx_register_operand" "")
28416
+ (match_operand:VSX_M 1 "memory_operand" ""))]
28417
+ "VECTOR_MEM_VSX_P (<MODE>mode)"
28418
+ "")
28419
+
28420
+(define_expand "vsx_store_<mode>"
28421
+ [(set (match_operand:VEC_M 0 "memory_operand" "")
28422
+ (match_operand:VEC_M 1 "vsx_register_operand" ""))]
28423
+ "VECTOR_MEM_VSX_P (<MODE>mode)"
28424
+ "")
28425
+
28426
28427
;; VSX scalar and vector floating point arithmetic instructions
28428
(define_insn "*vsx_add<mode>3"
28429
@@ -866,33 +879,34 @@
28430
;; the fprs because we don't want to add the altivec registers to movdi/movsi.
28431
;; For the unsigned tests, there isn't a generic double -> unsigned conversion
28432
;; in rs6000.md so don't test VECTOR_UNIT_VSX_P, just test against VSX.
28433
+;; Don't use vsx_register_operand here, use gpc_reg_operand to match rs6000.md.
28434
(define_insn "vsx_float<VSi><mode>2"
28435
- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
28436
- (float:VSX_B (match_operand:<VSI> 1 "vsx_register_operand" "<VSr2>,<VSr3>")))]
28437
+ [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?wa")
28438
+ (float:VSX_B (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))]
28439
"VECTOR_UNIT_VSX_P (<MODE>mode)"
28440
"x<VSv>cvsx<VSc><VSs> %x0,%x1"
28441
[(set_attr "type" "<VStype_simple>")
28442
(set_attr "fp_type" "<VSfptype_simple>")])
28443
28444
(define_insn "vsx_floatuns<VSi><mode>2"
28445
- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
28446
- (unsigned_float:VSX_B (match_operand:<VSI> 1 "vsx_register_operand" "<VSr2>,<VSr3>")))]
28447
+ [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?wa")
28448
+ (unsigned_float:VSX_B (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))]
28449
"VECTOR_UNIT_VSX_P (<MODE>mode)"
28450
"x<VSv>cvux<VSc><VSs> %x0,%x1"
28451
[(set_attr "type" "<VStype_simple>")
28452
(set_attr "fp_type" "<VSfptype_simple>")])
28453
28454
(define_insn "vsx_fix_trunc<mode><VSi>2"
28455
- [(set (match_operand:<VSI> 0 "vsx_register_operand" "=<VSr2>,?<VSr3>")
28456
- (fix:<VSI> (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]
28457
+ [(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>")
28458
+ (fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,wa")))]
28459
"VECTOR_UNIT_VSX_P (<MODE>mode)"
28460
"x<VSv>cv<VSs>sx<VSc>s %x0,%x1"
28461
[(set_attr "type" "<VStype_simple>")
28462
(set_attr "fp_type" "<VSfptype_simple>")])
28463
28464
(define_insn "vsx_fixuns_trunc<mode><VSi>2"
28465
- [(set (match_operand:<VSI> 0 "vsx_register_operand" "=<VSr2>,?<VSr3>")
28466
- (unsigned_fix:<VSI> (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]
28467
+ [(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>")
28468
+ (unsigned_fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,wa")))]
28469
"VECTOR_UNIT_VSX_P (<MODE>mode)"
28470
"x<VSv>cv<VSs>ux<VSc>s %x0,%x1"
28471
[(set_attr "type" "<VStype_simple>")
28472
--- a/src/gcc/config/rx/predicates.md
28473
+++ b/src/gcc/config/rx/predicates.md
28474
@@ -1,5 +1,5 @@
28475
;; Predicate definitions for Renesas RX.
28476
-;; Copyright (C) 2008, 2009 Free Software Foundation, Inc.
28477
+;; Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.
28478
;; Contributed by Red Hat.
28479
;;
28480
;; This file is part of GCC.
28481
@@ -37,19 +37,19 @@
28482
;; Only small integers or a value in a register are permitted.
28483
28484
(define_predicate "rx_shift_operand"
28485
- (match_code "const_int,reg")
28486
- {
28487
- if (CONST_INT_P (op))
28488
- return IN_RANGE (INTVAL (op), 0, 31);
28489
- return true;
28490
- }
28491
+ (ior (match_operand 0 "register_operand")
28492
+ (and (match_code "const_int")
28493
+ (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
28494
)
28495
28496
(define_predicate "rx_constshift_operand"
28497
- (match_code "const_int")
28498
- {
28499
- return IN_RANGE (INTVAL (op), 0, 31);
28500
- }
28501
+ (and (match_code "const_int")
28502
+ (match_test "IN_RANGE (INTVAL (op), 0, 31)"))
28503
+)
28504
+
28505
+(define_predicate "rx_restricted_mem_operand"
28506
+ (and (match_code "mem")
28507
+ (match_test "rx_is_restricted_memory_address (XEXP (op, 0), mode)"))
28508
)
28509
28510
;; Check that the operand is suitable as the source operand
28511
@@ -57,20 +57,9 @@
28512
;; and a restricted subset of memory addresses are allowed.
28513
28514
(define_predicate "rx_source_operand"
28515
- (match_code "const_int,const_double,const,symbol_ref,label_ref,reg,mem")
28516
- {
28517
- if (CONSTANT_P (op))
28518
- return rx_is_legitimate_constant (op);
28519
-
28520
- if (! MEM_P (op))
28521
- return true;
28522
-
28523
- /* Do not allow size conversions whilst accessing memory. */
28524
- if (GET_MODE (op) != mode)
28525
- return false;
28526
-
28527
- return rx_is_restricted_memory_address (XEXP (op, 0), mode);
28528
- }
28529
+ (ior (match_operand 0 "register_operand")
28530
+ (match_operand 0 "immediate_operand")
28531
+ (match_operand 0 "rx_restricted_mem_operand"))
28532
)
28533
28534
;; Check that the operand is suitable as the source operand
28535
@@ -79,16 +68,8 @@
28536
;; CONST_INTs are not.
28537
28538
(define_predicate "rx_compare_operand"
28539
- (match_code "subreg,reg,mem")
28540
- {
28541
- if (GET_CODE (op) == SUBREG)
28542
- return REG_P (XEXP (op, 0));
28543
-
28544
- if (! MEM_P (op))
28545
- return true;
28546
-
28547
- return rx_is_restricted_memory_address (XEXP (op, 0), mode);
28548
- }
28549
+ (ior (match_operand 0 "register_operand")
28550
+ (match_operand 0 "rx_restricted_mem_operand"))
28551
)
28552
28553
;; Return true if OP is a store multiple operation. This looks like:
28554
@@ -293,3 +274,24 @@
28555
element = XVECEXP (op, 0, count - 1);
28556
return GET_CODE (element) == RETURN;
28557
})
28558
+
28559
+(define_predicate "label_ref_operand"
28560
+ (match_code "label_ref")
28561
+)
28562
+
28563
+(define_predicate "rx_z_comparison_operator"
28564
+ (match_code "eq,ne")
28565
+)
28566
+
28567
+(define_predicate "rx_zs_comparison_operator"
28568
+ (match_code "eq,ne")
28569
+)
28570
+
28571
+;; GT and LE omitted due to operand swap required.
28572
+(define_predicate "rx_fp_comparison_operator"
28573
+ (match_code "eq,ne,lt,ge,ordered,unordered")
28574
+)
28575
+
28576
+(define_predicate "rshift_operator"
28577
+ (match_code "ashiftrt,lshiftrt")
28578
+)
28579
--- a/src/gcc/config/rx/rx-modes.def
28580
+++ b/src/gcc/config/rx/rx-modes.def
28581
@@ -1,5 +1,6 @@
28582
-/* Definitions of target machine for GNU compiler, for RX.
28583
- Copyright (C) 2010 by Nick Clifton (nickc@redhat.com).
28584
+/* Definitions of target specific machine modes for the RX.
28585
+ Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
28586
+ Contributed by Red Hat.
28587
28588
This file is part of GCC.
28589
28590
@@ -20,3 +21,5 @@
28591
CC_MODE (CC_ZS);
28592
CC_MODE (CC_ZSO);
28593
CC_MODE (CC_ZSC);
28594
+
28595
+CC_MODE (CC_F); /* fcmp */
28596
--- a/src/gcc/config/rx/rx-protos.h
28597
+++ b/src/gcc/config/rx/rx-protos.h
28598
@@ -1,5 +1,5 @@
28599
/* Exported function prototypes from the Renesas RX backend.
28600
- Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
28601
+ Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
28602
Contributed by Red Hat.
28603
28604
This file is part of GCC.
28605
@@ -31,19 +31,23 @@
28606
extern void rx_set_optimization_options (void);
28607
28608
#ifdef RTX_CODE
28609
+extern int rx_align_for_label (rtx);
28610
extern bool rx_compare_redundant (rtx);
28611
extern void rx_emit_stack_popm (rtx *, bool);
28612
extern void rx_emit_stack_pushm (rtx *);
28613
extern void rx_expand_epilogue (bool);
28614
-extern bool rx_expand_insv (rtx *);
28615
extern const char * rx_gen_cond_branch_template (rtx, bool);
28616
extern char * rx_gen_move_template (rtx *, bool);
28617
extern bool rx_is_legitimate_constant (rtx);
28618
extern bool rx_is_mode_dependent_addr (rtx);
28619
extern bool rx_is_restricted_memory_address (rtx, Mmode);
28620
+extern bool rx_match_ccmode (rtx, Mmode);
28621
+extern int rx_max_skip_for_label (rtx);
28622
extern void rx_notice_update_cc (rtx body, rtx insn);
28623
extern void rx_print_operand (FILE *, rtx, int);
28624
extern void rx_print_operand_address (FILE *, rtx);
28625
+extern Mmode rx_select_cc_mode (enum rtx_code, rtx, rtx);
28626
+extern void rx_split_cbranch (Mmode, enum rtx_code, rtx, rtx, rtx);
28627
#endif
28628
28629
#ifdef TREE_CODE
28630
27162
--- a/src/gcc/config/rx/rx.c
28631
27163
+++ b/src/gcc/config/rx/rx.c
28632
@@ -1,5 +1,5 @@
28633
/* Subroutines used for code generation on Renesas RX processors.
28634
- Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
28635
+ Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
28636
Contributed by Red Hat.
28637
28638
This file is part of GCC.
28639
@@ -51,6 +51,12 @@
28640
#include "target-def.h"
28641
#include "langhooks.h"
28642
28643
+#define CC_FLAG_S (1 << 0)
28644
+#define CC_FLAG_Z (1 << 1)
28645
+#define CC_FLAG_O (1 << 2)
28646
+#define CC_FLAG_C (1 << 3)
28647
+#define CC_FLAG_FP (1 << 4) /* Fake, to differentiate CC_Fmode. */
28648
+
28649
enum rx_cpu_types rx_cpu_type = RX600;
28650
28651
/* Return true if OP is a reference to an object in a small data area. */
28652
@@ -74,7 +80,9 @@
28653
/* Register Indirect. */
28654
return true;
28655
28656
- if (GET_MODE_SIZE (mode) == 4
28657
+ if ((GET_MODE_SIZE (mode) == 4
28658
+ || GET_MODE_SIZE (mode) == 2
28659
+ || GET_MODE_SIZE (mode) == 1)
28660
&& (GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC))
28661
/* Pre-decrement Register Indirect or
28662
Post-increment Register Indirect. */
28663
@@ -176,7 +184,10 @@
28664
base = XEXP (mem, 0);
28665
index = XEXP (mem, 1);
28666
28667
- return RX_REG_P (base) && CONST_INT_P (index);
28668
+ if (! RX_REG_P (base) || ! CONST_INT_P (index))
28669
+ return false;
28670
+
28671
+ return IN_RANGE (INTVAL (index), 0, (0x10000 * GET_MODE_SIZE (mode)) - 1);
28672
28673
case SYMBOL_REF:
28674
/* Can happen when small data is being supported.
28675
@@ -312,9 +323,18 @@
28676
break;
28677
}
28678
28679
+ case CONST:
28680
+ if (GET_CODE (XEXP (addr, 0)) == UNSPEC)
28681
+ {
28682
+ addr = XEXP (addr, 0);
28683
+ gcc_assert (XINT (addr, 1) == UNSPEC_CONST);
28684
+
28685
+ addr = XVECEXP (addr, 0, 0);
28686
+ gcc_assert (CONST_INT_P (addr));
28687
+ }
28688
+ /* Fall through. */
28689
case LABEL_REF:
28690
case SYMBOL_REF:
28691
- case CONST:
28692
fprintf (file, "#");
28693
default:
28694
output_addr_const (file, addr);
28695
@@ -351,8 +371,75 @@
28696
return true;
28697
}
28698
28699
+/* Convert a CC_MODE to the set of flags that it represents. */
28700
28701
-int rx_float_compare_mode;
28702
+static unsigned int
28703
+flags_from_mode (enum machine_mode mode)
28704
+{
28705
+ switch (mode)
28706
+ {
28707
+ case CC_ZSmode:
28708
+ return CC_FLAG_S | CC_FLAG_Z;
28709
+ case CC_ZSOmode:
28710
+ return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O;
28711
+ case CC_ZSCmode:
28712
+ return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_C;
28713
+ case CCmode:
28714
+ return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O | CC_FLAG_C;
28715
+ case CC_Fmode:
28716
+ return CC_FLAG_FP;
28717
+ default:
28718
+ gcc_unreachable ();
28719
+ }
28720
+}
28721
+
28722
+/* Convert a set of flags to a CC_MODE that can implement it. */
28723
+
28724
+static enum machine_mode
28725
+mode_from_flags (unsigned int f)
28726
+{
28727
+ if (f & CC_FLAG_FP)
28728
+ return CC_Fmode;
28729
+ if (f & CC_FLAG_O)
28730
+ {
28731
+ if (f & CC_FLAG_C)
28732
+ return CCmode;
28733
+ else
28734
+ return CC_ZSOmode;
28735
+ }
28736
+ else if (f & CC_FLAG_C)
28737
+ return CC_ZSCmode;
28738
+ else
28739
+ return CC_ZSmode;
28740
+}
28741
+
28742
+/* Convert an RTX_CODE to the set of flags needed to implement it.
28743
+ This assumes an integer comparison. */
28744
+
28745
+static unsigned int
28746
+flags_from_code (enum rtx_code code)
28747
+{
28748
+ switch (code)
28749
+ {
28750
+ case LT:
28751
+ case GE:
28752
+ return CC_FLAG_S | CC_FLAG_O;
28753
+ case GT:
28754
+ case LE:
28755
+ return CC_FLAG_S | CC_FLAG_O | CC_FLAG_Z;
28756
+ case GEU:
28757
+ case LTU:
28758
+ return CC_FLAG_C;
28759
+ case GTU:
28760
+ case LEU:
28761
+ return CC_FLAG_C | CC_FLAG_Z;
28762
+ case EQ:
28763
+ case NE:
28764
+ return CC_FLAG_Z;
28765
+ default:
28766
+ gcc_unreachable ();
28767
+ }
28768
+}
28769
28770
/* Handles the insertion of a single operand into the assembler output.
28771
The %<letter> directives supported are:
28772
@@ -365,11 +452,14 @@
28773
%L Print low part of a DImode register, integer or address.
28774
%N Print the negation of the immediate value.
28775
%Q If the operand is a MEM, then correctly generate
28776
- register indirect or register relative addressing. */
28777
+ register indirect or register relative addressing.
28778
+ %R Like %Q but for zero-extending loads. */
28779
28780
void
28781
rx_print_operand (FILE * file, rtx op, int letter)
28782
{
28783
+ bool unsigned_load = false;
28784
+
28785
switch (letter)
28786
{
28787
case 'A':
28788
@@ -393,21 +483,48 @@
28789
break;
28790
28791
case 'B':
28792
- switch (GET_CODE (op))
28793
- {
28794
- case LT: fprintf (file, "lt"); break;
28795
- case GE: fprintf (file, "ge"); break;
28796
- case GT: fprintf (file, "gt"); break;
28797
- case LE: fprintf (file, "le"); break;
28798
- case GEU: fprintf (file, "geu"); break;
28799
- case LTU: fprintf (file, "ltu"); break;
28800
- case GTU: fprintf (file, "gtu"); break;
28801
- case LEU: fprintf (file, "leu"); break;
28802
- case EQ: fprintf (file, "eq"); break;
28803
- case NE: fprintf (file, "ne"); break;
28804
- default: debug_rtx (op); gcc_unreachable ();
28805
- }
28806
- break;
28807
+ {
28808
+ enum rtx_code code = GET_CODE (op);
28809
+ enum machine_mode mode = GET_MODE (XEXP (op, 0));
28810
+ const char * ret;
28811
+
28812
+ if (mode == CC_Fmode)
28813
+ {
28814
+ /* C flag is undefined, and O flag carries unordered. None of the
28815
+ branch combinations that include O use it helpfully. */
28816
+ switch (code)
28817
+ {
28818
+ case ORDERED: ret = "no"; break;
28819
+ case UNORDERED: ret = "o"; break;
28820
+ case LT: ret = "n"; break;
28821
+ case GE: ret = "pz"; break;
28822
+ case EQ: ret = "eq"; break;
28823
+ case NE: ret = "ne"; break;
28824
+ default: gcc_unreachable ();
28825
+ }
28826
+ }
28827
+ else
28828
+ {
28829
+ switch (code)
28830
+ {
28831
+ case LT: ret = "lt"; break;
28832
+ case GE: ret = "ge"; break;
28833
+ case GT: ret = "gt"; break;
28834
+ case LE: ret = "le"; break;
28835
+ case GEU: ret = "geu"; break;
28836
+ case LTU: ret = "ltu"; break;
28837
+ case GTU: ret = "gtu"; break;
28838
+ case LEU: ret = "leu"; break;
28839
+ case EQ: ret = "eq"; break;
28840
+ case NE: ret = "ne"; break;
28841
+ default: gcc_unreachable ();
28842
+ }
28843
+ gcc_assert ((flags_from_code (code)
28844
+ & ~flags_from_mode (mode)) == 0);
28845
+ }
28846
+ fputs (ret, file);
28847
+ break;
28848
+ }
28849
28850
case 'C':
28851
gcc_assert (CONST_INT_P (op));
28852
@@ -506,10 +623,15 @@
28853
rx_print_integer (file, - INTVAL (op));
28854
break;
28855
28856
+ case 'R':
28857
+ gcc_assert (GET_MODE_SIZE (GET_MODE (op)) < 4);
28858
+ unsigned_load = true;
28859
+ /* Fall through. */
28860
case 'Q':
28861
if (MEM_P (op))
28862
{
28863
HOST_WIDE_INT offset;
28864
+ rtx mem = op;
28865
28866
op = XEXP (op, 0);
28867
28868
@@ -544,22 +666,24 @@
28869
rx_print_operand (file, op, 0);
28870
fprintf (file, "].");
28871
28872
- switch (GET_MODE_SIZE (GET_MODE (op)))
28873
+ switch (GET_MODE_SIZE (GET_MODE (mem)))
28874
{
28875
case 1:
28876
- gcc_assert (offset < 65535 * 1);
28877
- fprintf (file, "B");
28878
+ gcc_assert (offset <= 65535 * 1);
28879
+ fprintf (file, unsigned_load ? "UB" : "B");
28880
break;
28881
case 2:
28882
gcc_assert (offset % 2 == 0);
28883
- gcc_assert (offset < 65535 * 2);
28884
- fprintf (file, "W");
28885
+ gcc_assert (offset <= 65535 * 2);
28886
+ fprintf (file, unsigned_load ? "UW" : "W");
28887
break;
28888
- default:
28889
+ case 4:
28890
gcc_assert (offset % 4 == 0);
28891
- gcc_assert (offset < 65535 * 4);
28892
+ gcc_assert (offset <= 65535 * 4);
28893
fprintf (file, "L");
28894
break;
28895
+ default:
28896
+ gcc_unreachable ();
28897
}
28898
break;
28899
}
28900
@@ -698,51 +822,6 @@
28901
extension, src_template, dst_template);
28902
return out_template;
28903
}
28904
-
28905
-/* Returns an assembler template for a conditional branch instruction. */
28906
-
28907
-const char *
28908
-rx_gen_cond_branch_template (rtx condition, bool reversed)
28909
-{
28910
- enum rtx_code code = GET_CODE (condition);
28911
-
28912
- if (reversed)
28913
- {
28914
- if (rx_float_compare_mode)
28915
- code = reverse_condition_maybe_unordered (code);
28916
- else
28917
- code = reverse_condition (code);
28918
- }
28919
-
28920
- /* We do not worry about encoding the branch length here as GAS knows
28921
- how to choose the smallest version, and how to expand a branch that
28922
- is to a destination that is out of range. */
28923
-
28924
- switch (code)
28925
- {
28926
- case UNEQ: return "bo\t1f\n\tbeq\t%0\n1:";
28927
- case LTGT: return "bo\t1f\n\tbne\t%0\n1:";
28928
- case UNLT: return "bo\t1f\n\tbn\t%0\n1:";
28929
- case UNGE: return "bo\t1f\n\tbpz\t%0\n1:";
28930
- case UNLE: return "bo\t1f\n\tbgt\t1f\n\tbra\t%0\n1:";
28931
- case UNGT: return "bo\t1f\n\tble\t1f\n\tbra\t%0\n1:";
28932
- case UNORDERED: return "bo\t%0";
28933
- case ORDERED: return "bno\t%0";
28934
-
28935
- case LT: return rx_float_compare_mode ? "bn\t%0" : "blt\t%0";
28936
- case GE: return rx_float_compare_mode ? "bpz\t%0" : "bge\t%0";
28937
- case GT: return "bgt\t%0";
28938
- case LE: return "ble\t%0";
28939
- case GEU: return "bgeu\t%0";
28940
- case LTU: return "bltu\t%0";
28941
- case GTU: return "bgtu\t%0";
28942
- case LEU: return "bleu\t%0";
28943
- case EQ: return "beq\t%0";
28944
- case NE: return "bne\t%0";
28945
- default:
28946
- gcc_unreachable ();
28947
- }
28948
-}
28949
28950
/* Return VALUE rounded up to the next ALIGNMENT boundary. */
28951
28952
@@ -821,7 +900,35 @@
28953
const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
28954
bool outgoing ATTRIBUTE_UNUSED)
28955
{
28956
- return gen_rtx_REG (TYPE_MODE (ret_type), FUNC_RETURN_REGNUM);
28957
+ enum machine_mode mode = TYPE_MODE (ret_type);
28958
+
28959
+ /* RX ABI specifies that small integer types are
28960
+ promoted to int when returned by a function. */
28961
+ if (GET_MODE_SIZE (mode) > 0
28962
+ && GET_MODE_SIZE (mode) < 4
28963
+ && ! COMPLEX_MODE_P (mode))
28964
+ return gen_rtx_REG (SImode, FUNC_RETURN_REGNUM);
28965
+
28966
+ return gen_rtx_REG (mode, FUNC_RETURN_REGNUM);
28967
+}
28968
+
28969
+/* TARGET_PROMOTE_FUNCTION_MODE must behave in the same way with
28970
+ regard to function returns as does TARGET_FUNCTION_VALUE. */
28971
+
28972
+static enum machine_mode
28973
+rx_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
28974
+ enum machine_mode mode,
28975
+ int * punsignedp ATTRIBUTE_UNUSED,
28976
+ const_tree funtype ATTRIBUTE_UNUSED,
28977
+ int for_return)
28978
+{
28979
+ if (for_return != 1
28980
+ || GET_MODE_SIZE (mode) >= 4
28981
+ || COMPLEX_MODE_P (mode)
28982
+ || GET_MODE_SIZE (mode) < 1)
28983
+ return mode;
28984
+
28985
+ return SImode;
28986
}
28987
28988
static bool
28989
@@ -1058,7 +1165,13 @@
28990
28991
for (save_mask = high = low = 0, reg = 1; reg < CC_REGNUM; reg++)
28992
{
28993
- if (df_regs_ever_live_p (reg)
28994
+ if ((df_regs_ever_live_p (reg)
28995
+ /* Always save all call clobbered registers inside non-leaf
28996
+ interrupt handlers, even if they are not live - they may
28997
+ be used in (non-interrupt aware) routines called from this one. */
28998
+ || (call_used_regs[reg]
28999
+ && is_interrupt_func (NULL_TREE)
29000
+ && ! current_function_is_leaf))
29001
&& (! call_used_regs[reg]
29002
/* Even call clobbered registered must
29003
be pushed inside interrupt handlers. */
29004
@@ -1213,6 +1326,59 @@
29005
}
29006
}
29007
29008
+static bool
29009
+ok_for_max_constant (HOST_WIDE_INT val)
29010
+{
29011
+ if (rx_max_constant_size == 0 || rx_max_constant_size == 4)
29012
+ /* If there is no constraint on the size of constants
29013
+ used as operands, then any value is legitimate. */
29014
+ return true;
29015
+
29016
+ /* rx_max_constant_size specifies the maximum number
29017
+ of bytes that can be used to hold a signed value. */
29018
+ return IN_RANGE (val, (-1 << (rx_max_constant_size * 8)),
29019
+ ( 1 << (rx_max_constant_size * 8)));
29020
+}
29021
+
29022
+/* Generate an ADD of SRC plus VAL into DEST.
29023
+ Handles the case where VAL is too big for max_constant_value.
29024
+ Sets FRAME_RELATED_P on the insn if IS_FRAME_RELATED is true. */
29025
+
29026
+static void
29027
+gen_safe_add (rtx dest, rtx src, rtx val, bool is_frame_related)
29028
+{
29029
+ rtx insn;
29030
+
29031
+ if (val == NULL_RTX || INTVAL (val) == 0)
29032
+ {
29033
+ gcc_assert (dest != src);
29034
+
29035
+ insn = emit_move_insn (dest, src);
29036
+ }
29037
+ else if (ok_for_max_constant (INTVAL (val)))
29038
+ insn = emit_insn (gen_addsi3 (dest, src, val));
29039
+ else
29040
+ {
29041
+ /* Wrap VAL in an UNSPEC so that rx_is_legitimate_constant
29042
+ will not reject it. */
29043
+ val = gen_rtx_CONST (SImode, gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_CONST));
29044
+ insn = emit_insn (gen_addsi3 (dest, src, val));
29045
+
29046
+ if (is_frame_related)
29047
+ /* We have to provide our own frame related note here
29048
+ as the dwarf2out code cannot be expected to grok
29049
+ our unspec. */
29050
+ add_reg_note (insn, REG_FRAME_RELATED_EXPR,
29051
+ gen_rtx_SET (SImode, dest,
29052
+ gen_rtx_PLUS (SImode, src, val)));
29053
+ return;
29054
+ }
29055
+
29056
+ if (is_frame_related)
29057
+ RTX_FRAME_RELATED_P (insn) = 1;
29058
+ return;
29059
+}
29060
+
29061
void
29062
rx_expand_prologue (void)
29063
{
29064
@@ -1298,23 +1464,12 @@
29065
emit_insn (gen_stack_pushm (GEN_INT (2 * UNITS_PER_WORD),
29066
gen_rx_store_vector (acc_low, acc_high)));
29067
}
29068
-
29069
- frame_size += 2 * UNITS_PER_WORD;
29070
}
29071
29072
/* If needed, set up the frame pointer. */
29073
if (frame_pointer_needed)
29074
- {
29075
- if (frame_size)
29076
- insn = emit_insn (gen_addsi3 (frame_pointer_rtx, stack_pointer_rtx,
29077
- GEN_INT (- (HOST_WIDE_INT) frame_size)));
29078
- else
29079
- insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
29080
-
29081
- RTX_FRAME_RELATED_P (insn) = 1;
29082
- }
29083
-
29084
- insn = NULL_RTX;
29085
+ gen_safe_add (frame_pointer_rtx, stack_pointer_rtx,
29086
+ GEN_INT (- (HOST_WIDE_INT) frame_size), true);
29087
29088
/* Allocate space for the outgoing args.
29089
If the stack frame has not already been set up then handle this as well. */
29090
@@ -1323,29 +1478,26 @@
29091
if (frame_size)
29092
{
29093
if (frame_pointer_needed)
29094
- insn = emit_insn (gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx,
29095
- GEN_INT (- (HOST_WIDE_INT)
29096
- stack_size)));
29097
+ gen_safe_add (stack_pointer_rtx, frame_pointer_rtx,
29098
+ GEN_INT (- (HOST_WIDE_INT) stack_size), true);
29099
else
29100
- insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
29101
- GEN_INT (- (HOST_WIDE_INT)
29102
- (frame_size + stack_size))));
29103
+ gen_safe_add (stack_pointer_rtx, stack_pointer_rtx,
29104
+ GEN_INT (- (HOST_WIDE_INT) (frame_size + stack_size)),
29105
+ true);
29106
}
29107
else
29108
- insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
29109
- GEN_INT (- (HOST_WIDE_INT) stack_size)));
29110
+ gen_safe_add (stack_pointer_rtx, stack_pointer_rtx,
29111
+ GEN_INT (- (HOST_WIDE_INT) stack_size), true);
29112
}
29113
else if (frame_size)
29114
{
29115
if (! frame_pointer_needed)
29116
- insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
29117
- GEN_INT (- (HOST_WIDE_INT) frame_size)));
29118
+ gen_safe_add (stack_pointer_rtx, stack_pointer_rtx,
29119
+ GEN_INT (- (HOST_WIDE_INT) frame_size), true);
29120
else
29121
- insn = emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
29122
+ gen_safe_add (stack_pointer_rtx, frame_pointer_rtx, NULL_RTX,
29123
+ true);
29124
}
29125
-
29126
- if (insn != NULL_RTX)
29127
- RTX_FRAME_RELATED_P (insn) = 1;
29128
}
29129
29130
static void
29131
@@ -1425,7 +1577,7 @@
27164
@@ -1577,7 +1577,7 @@
29132
27165
: plus_constant (stack_pointer_rtx,
29133
27166
i * UNITS_PER_WORD)));
29134
27167
29137
27170
29138
27171
return vector;
29139
27172
}
29140
@@ -1523,8 +1675,8 @@
29141
{
29142
/* Cannot use the special instructions - deconstruct by hand. */
29143
if (total_size)
29144
- emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
29145
- GEN_INT (total_size)));
29146
+ gen_safe_add (stack_pointer_rtx, stack_pointer_rtx,
29147
+ GEN_INT (total_size), false);
29148
29149
if (MUST_SAVE_ACC_REGISTER)
29150
{
29151
@@ -1615,8 +1767,8 @@
29152
return;
29153
}
29154
29155
- emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
29156
- GEN_INT (total_size)));
29157
+ gen_safe_add (stack_pointer_rtx, stack_pointer_rtx,
29158
+ GEN_INT (total_size), false);
29159
}
29160
29161
if (low)
29162
@@ -1893,7 +2045,7 @@
29163
if (rx_cpu_type == RX610)
29164
return NULL_RTX;
29165
29166
- if (! CONST_INT_P (arg) || ! IN_RANGE (arg, 0, (1 << 4) - 1))
29167
+ if (! CONST_INT_P (arg) || ! IN_RANGE (INTVAL (arg), 0, (1 << 4) - 1))
29168
return NULL_RTX;
29169
29170
emit_insn (gen_mvtipl (arg));
29171
@@ -1962,6 +2114,31 @@
29172
return target;
29173
}
29174
29175
+static int
29176
+valid_psw_flag (rtx op, const char *which)
29177
+{
29178
+ static int mvtc_inform_done = 0;
29179
+
29180
+ if (GET_CODE (op) == CONST_INT)
29181
+ switch (INTVAL (op))
29182
+ {
29183
+ case 0: case 'c': case 'C':
29184
+ case 1: case 'z': case 'Z':
29185
+ case 2: case 's': case 'S':
29186
+ case 3: case 'o': case 'O':
29187
+ case 8: case 'i': case 'I':
29188
+ case 9: case 'u': case 'U':
29189
+ return 1;
29190
+ }
29191
+
29192
+ error ("__builtin_rx_%s takes 'C', 'Z', 'S', 'O', 'I', or 'U'", which);
29193
+ if (!mvtc_inform_done)
29194
+ error ("use __builtin_rx_mvtc (0, ... ) to write arbitrary values to PSW");
29195
+ mvtc_inform_done = 1;
29196
+
29197
+ return 0;
29198
+}
29199
+
29200
static rtx
29201
rx_expand_builtin (tree exp,
29202
rtx target,
29203
@@ -1977,10 +2154,14 @@
29204
switch (fcode)
29205
{
29206
case RX_BUILTIN_BRK: emit_insn (gen_brk ()); return NULL_RTX;
29207
- case RX_BUILTIN_CLRPSW: return rx_expand_void_builtin_1_arg
29208
- (op, gen_clrpsw, false);
29209
- case RX_BUILTIN_SETPSW: return rx_expand_void_builtin_1_arg
29210
- (op, gen_setpsw, false);
29211
+ case RX_BUILTIN_CLRPSW:
29212
+ if (! valid_psw_flag (op, "clrpsw"))
29213
+ return NULL_RTX;
29214
+ return rx_expand_void_builtin_1_arg (op, gen_clrpsw, false);
29215
+ if (! valid_psw_flag (op, "setpsw"))
29216
+ return NULL_RTX;
29217
+ return rx_expand_void_builtin_1_arg (op, gen_setpsw, false);
29218
+ case RX_BUILTIN_SETPSW:
29219
case RX_BUILTIN_INT: return rx_expand_void_builtin_1_arg
29220
(op, gen_int, false);
29221
case RX_BUILTIN_MACHI: return rx_expand_builtin_mac (exp, gen_machi);
29222
@@ -2187,6 +2368,13 @@
29223
}
29224
}
29225
27173
@@ -2367,6 +2367,14 @@
27174
error ("Changing the FPU insns/math optimizations pairing is not supported");
27175
}
27176
}
27177
+
29226
27178
+static void
29227
27179
+rx_option_override (void)
29228
27180
+{
29233
27185
29234
27186
static bool
29235
27187
rx_allocate_stack_slots_for_args (void)
29236
@@ -2233,50 +2421,10 @@
29237
static bool
29238
rx_is_ms_bitfield_layout (const_tree record_type ATTRIBUTE_UNUSED)
29239
{
29240
- return TRUE;
29241
+ /* The packed attribute overrides the MS behaviour. */
29242
+ return ! TYPE_PACKED (record_type);
29243
}
29244
29245
-/* Try to generate code for the "isnv" pattern which inserts bits
29246
- into a word.
29247
- operands[0] => Location to be altered.
29248
- operands[1] => Number of bits to change.
29249
- operands[2] => Starting bit.
29250
- operands[3] => Value to insert.
29251
- Returns TRUE if successful, FALSE otherwise. */
29252
-
29253
-bool
29254
-rx_expand_insv (rtx * operands)
29255
-{
29256
- if (INTVAL (operands[1]) != 1
29257
- || ! CONST_INT_P (operands[3]))
29258
- return false;
29259
-
29260
- if (MEM_P (operands[0])
29261
- && INTVAL (operands[2]) > 7)
29262
- return false;
29263
-
29264
- switch (INTVAL (operands[3]))
29265
- {
29266
- case 0:
29267
- if (MEM_P (operands[0]))
29268
- emit_insn (gen_bitclr_in_memory (operands[0], operands[0],
29269
- operands[2]));
29270
- else
29271
- emit_insn (gen_bitclr (operands[0], operands[0], operands[2]));
29272
- break;
29273
- case 1:
29274
- case -1:
29275
- if (MEM_P (operands[0]))
29276
- emit_insn (gen_bitset_in_memory (operands[0], operands[0],
29277
- operands[2]));
29278
- else
29279
- emit_insn (gen_bitset (operands[0], operands[0], operands[2]));
29280
- break;
29281
- default:
29282
- return false;
29283
- }
29284
- return true;
29285
-}
29286
29287
/* Returns true if X a legitimate constant for an immediate
29288
operand on the RX. X is already known to satisfy CONSTANT_P. */
29289
@@ -2284,8 +2432,6 @@
29290
bool
29291
rx_is_legitimate_constant (rtx x)
29292
{
29293
- HOST_WIDE_INT val;
29294
-
29295
switch (GET_CODE (x))
29296
{
29297
case CONST:
29298
@@ -2308,7 +2454,9 @@
29299
case SYMBOL_REF:
29300
return true;
29301
29302
- /* One day we may have to handle UNSPEC constants here. */
29303
+ case UNSPEC:
29304
+ return XINT (x, 1) == UNSPEC_CONST;
29305
+
29306
default:
29307
/* FIXME: Can this ever happen ? */
29308
abort ();
29309
@@ -2328,17 +2476,7 @@
29310
break;
29311
}
29312
29313
- if (rx_max_constant_size == 0 || rx_max_constant_size == 4)
29314
- /* If there is no constraint on the size of constants
29315
- used as operands, then any value is legitimate. */
29316
- return true;
29317
-
29318
- val = INTVAL (x);
29319
-
29320
- /* rx_max_constant_size specifies the maximum number
29321
- of bytes that can be used to hold a signed value. */
29322
- return IN_RANGE (val, (-1 << (rx_max_constant_size * 8)),
29323
- ( 1 << (rx_max_constant_size * 8)));
29324
+ return ok_for_max_constant (INTVAL (x));
29325
}
29326
29327
static int
29328
@@ -2462,211 +2600,113 @@
29329
}
29330
}
29331
29332
+/* Return a CC_MODE of which both M1 and M2 are subsets. */
29333
+
29334
static enum machine_mode
29335
rx_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
29336
{
29337
- if (m1 == CCmode)
29338
- return m2;
29339
- if (m2 == CCmode)
29340
- return m1;
29341
+ unsigned f;
29342
+
29343
+ /* Early out for identical modes. */
29344
if (m1 == m2)
29345
return m1;
29346
- if (m1 == CC_ZSmode)
29347
- return m1;
29348
- if (m2 == CC_ZSmode)
29349
- return m2;
29350
- return VOIDmode;
29351
+
29352
+ /* There's no valid combination for FP vs non-FP. */
29353
+ f = flags_from_mode (m1) | flags_from_mode (m2);
29354
+ if (f & CC_FLAG_FP)
29355
+ return VOIDmode;
29356
+
29357
+ /* Otherwise, see what mode can implement all the flags. */
29358
+ return mode_from_flags (f);
29359
}
29360
29361
-#define CC_FLAG_S (1 << 0)
29362
-#define CC_FLAG_Z (1 << 1)
29363
-#define CC_FLAG_O (1 << 2)
29364
-#define CC_FLAG_C (1 << 3)
29365
+/* Return the minimal CC mode needed to implement (CMP_CODE X Y). */
29366
29367
-static unsigned int
29368
-flags_needed_for_conditional (rtx conditional)
29369
+enum machine_mode
29370
+rx_select_cc_mode (enum rtx_code cmp_code, rtx x, rtx y ATTRIBUTE_UNUSED)
29371
{
29372
- switch (GET_CODE (conditional))
29373
- {
29374
- case LE:
29375
- case GT: return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O;
29376
+ if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
29377
+ return CC_Fmode;
29378
29379
- case LEU:
29380
- case GTU: return CC_FLAG_Z | CC_FLAG_C;
29381
+ return mode_from_flags (flags_from_code (cmp_code));
29382
+}
29383
29384
- case LT:
29385
- case GE: return CC_FLAG_S | CC_FLAG_O;
29386
+/* Split the conditional branch. Emit (COMPARE C1 C2) into CC_REG with
29387
+ CC_MODE, and use that in branches based on that compare. */
29388
29389
- case LTU:
29390
- case GEU: return CC_FLAG_C;
29391
+void
29392
+rx_split_cbranch (enum machine_mode cc_mode, enum rtx_code cmp1,
29393
+ rtx c1, rtx c2, rtx label)
29394
+{
29395
+ rtx flags, x;
29396
29397
- case EQ:
29398
- case NE: return CC_FLAG_Z;
29399
+ flags = gen_rtx_REG (cc_mode, CC_REG);
29400
+ x = gen_rtx_COMPARE (cc_mode, c1, c2);
29401
+ x = gen_rtx_SET (VOIDmode, flags, x);
29402
+ emit_insn (x);
29403
29404
- default: gcc_unreachable ();
29405
- }
29406
+ x = gen_rtx_fmt_ee (cmp1, VOIDmode, flags, const0_rtx);
29407
+ x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, label, pc_rtx);
29408
+ x = gen_rtx_SET (VOIDmode, pc_rtx, x);
29409
+ emit_jump_insn (x);
29410
}
29411
29412
-static unsigned int
29413
-flags_from_mode (enum machine_mode mode)
29414
-{
29415
- switch (mode)
29416
- {
29417
- case CCmode: return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O | CC_FLAG_C;
29418
- case CC_ZSmode: return CC_FLAG_S | CC_FLAG_Z;
29419
- case CC_ZSOmode: return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O;
29420
- case CC_ZSCmode: return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_C;
29421
- default: gcc_unreachable ();
29422
- }
29423
-}
29424
-
29425
-/* Returns true if a compare insn is redundant because it
29426
- would only set flags that are already set correctly. */
29427
+/* A helper function for matching parallels that set the flags. */
29428
29429
bool
29430
-rx_compare_redundant (rtx cmp)
29431
+rx_match_ccmode (rtx insn, enum machine_mode cc_mode)
29432
{
29433
- unsigned int flags_needed;
29434
- unsigned int flags_set;
29435
- rtx next;
29436
- rtx prev;
29437
- rtx source;
29438
- rtx dest;
29439
- static rtx cc_reg = NULL_RTX;
29440
-
29441
- if (cc_reg == NULL_RTX)
29442
- cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
29443
-
29444
- /* We can only eliminate compares against 0. */
29445
- if (GET_CODE (XEXP (SET_SRC (PATTERN (cmp)), 1)) != CONST_INT
29446
- || INTVAL (XEXP (SET_SRC (PATTERN (cmp)), 1)) != 0)
29447
- return false;
29448
-
29449
- /* Locate the branch insn that follows the
29450
- compare and which tests the bits in the PSW. */
29451
- next = cmp;
29452
- do
29453
- {
29454
- /* If we have found an insn that sets or clobbers the CC
29455
- register and it was not the IF_THEN_ELSE insn that we
29456
- are looking for, then the comparison is redundant. */
29457
- if (next != cmp && reg_mentioned_p (cc_reg, PATTERN (next)))
29458
- return true;
29459
+ rtx op1, flags;
29460
+ enum machine_mode flags_mode;
29461
29462
- next = next_nonnote_insn (next);
29463
+ gcc_assert (XVECLEN (PATTERN (insn), 0) == 2);
29464
29465
- /* If we run out of insns without finding the
29466
- user then the comparison is unnecessary. */
29467
- if (next == NULL_RTX)
29468
- return true;
29469
+ op1 = XVECEXP (PATTERN (insn), 0, 1);
29470
+ gcc_assert (GET_CODE (SET_SRC (op1)) == COMPARE);
29471
29472
- /* If we have found another comparison
29473
- insn then the first one is redundant. */
29474
- if (INSN_P (next)
29475
- && GET_CODE (PATTERN (next)) == SET
29476
- && REG_P (SET_DEST (PATTERN (next)))
29477
- && REGNO (SET_DEST (PATTERN (next))) == CC_REGNUM)
29478
- return true;
29479
+ flags = SET_DEST (op1);
29480
+ flags_mode = GET_MODE (flags);
29481
29482
- /* If we have found another arithmetic/logic insn that
29483
- sets the PSW flags then the comparison is redundant. */
29484
- if (INSN_P (next)
29485
- && GET_CODE (PATTERN (next)) == PARALLEL
29486
- && GET_CODE (XVECEXP (PATTERN (next), 0, 1)) == SET
29487
- && REG_P (SET_DEST (XVECEXP (PATTERN (next), 0, 1)))
29488
- && REGNO (SET_DEST (XVECEXP (PATTERN (next), 0, 1))) == CC_REGNUM)
29489
- return true;
29490
-
29491
- /* If we have found an unconditional branch then the
29492
- PSW flags might be carried along with the jump, so
29493
- the comparison is necessary. */
29494
- if (INSN_P (next) && JUMP_P (next))
29495
- {
29496
- if (GET_CODE (PATTERN (next)) != SET)
29497
- /* If the jump does not involve setting the PC
29498
- then it is a return of some kind, and we know
29499
- that the comparison is not used. */
29500
- return true;
29501
-
29502
- if (GET_CODE (SET_SRC (PATTERN (next))) != IF_THEN_ELSE)
29503
- return false;
29504
- }
29505
- }
29506
- while (! INSN_P (next)
29507
- || DEBUG_INSN_P (next)
29508
- || GET_CODE (PATTERN (next)) != SET
29509
- || GET_CODE (SET_SRC (PATTERN (next))) != IF_THEN_ELSE);
29510
-
29511
- flags_needed = flags_needed_for_conditional (XEXP (SET_SRC (PATTERN (next)), 0));
29512
-
29513
- /* Now look to see if there was a previous
29514
- instruction which set the PSW bits. */
29515
- source = XEXP (SET_SRC (PATTERN (cmp)), 0);
29516
- prev = cmp;
29517
- do
29518
- {
29519
- /* If this insn uses/sets/clobbers the CC register
29520
- and it is not the insn that we are looking for
29521
- below, then we must need the comparison. */
29522
- if (prev != cmp && reg_mentioned_p (cc_reg, PATTERN (prev)))
29523
- return false;
29524
+ if (GET_MODE (SET_SRC (op1)) != flags_mode)
29525
+ return false;
29526
+ if (GET_MODE_CLASS (flags_mode) != MODE_CC)
29527
+ return false;
29528
29529
- prev = prev_nonnote_insn (prev);
29530
+ /* Ensure that the mode of FLAGS is compatible with CC_MODE. */
29531
+ if (flags_from_mode (flags_mode) & ~flags_from_mode (cc_mode))
29532
+ return false;
29533
29534
- if (prev == NULL_RTX)
29535
- return false;
29536
+ return true;
29537
+}
29538
+
29539
+int
29540
+rx_align_for_label (rtx lab ATTRIBUTE_UNUSED)
29541
+{
29542
+ return optimize_size ? 1 : 3;
29543
+}
29544
29545
- /* If we encounter an insn which changes the contents of
29546
- the register which is the source of the comparison then
29547
- we will definitely need the comparison. */
29548
- if (INSN_P (prev)
29549
- && GET_CODE (PATTERN (prev)) == SET
29550
- && rtx_equal_p (SET_DEST (PATTERN (prev)), source))
29551
- {
29552
- /* Unless this instruction is a simple register move
29553
- instruction. In which case we can continue our
29554
- scan backwards, but now using the *source* of this
29555
- set instruction. */
29556
- if (REG_P (SET_SRC (PATTERN (prev))))
29557
- source = SET_SRC (PATTERN (prev));
29558
- /* We can also survive a sign-extension if the test is
29559
- for EQ/NE. Note the same does not apply to zero-
29560
- extension as this can turn a non-zero bit-pattern
29561
- into zero. */
29562
- else if (flags_needed == CC_FLAG_Z
29563
- && GET_CODE (SET_SRC (PATTERN (prev))) == SIGN_EXTEND)
29564
- source = XEXP (SET_SRC (PATTERN (prev)), 0);
29565
- else
29566
- return false;
29567
- }
29568
+int
29569
+rx_max_skip_for_label (rtx lab)
29570
+{
29571
+ int opsize;
29572
+ rtx op;
29573
29574
- /* A label means a possible branch into the
29575
- code here, so we have to stop scanning. */
29576
- if (LABEL_P (prev))
29577
- return false;
29578
- }
29579
- while (! INSN_P (prev)
29580
- || DEBUG_INSN_P (prev)
29581
- || GET_CODE (PATTERN (prev)) != PARALLEL
29582
- || GET_CODE (XVECEXP (PATTERN (prev), 0, 1)) != SET
29583
- || ! REG_P (SET_DEST (XVECEXP (PATTERN (prev), 0, 1)))
29584
- || REGNO (SET_DEST (XVECEXP (PATTERN (prev), 0, 1))) != CC_REGNUM);
29585
-
29586
- flags_set = flags_from_mode (GET_MODE (SET_DEST (XVECEXP (PATTERN (prev), 0, 1))));
29587
-
29588
- dest = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
29589
- /* The destination of the previous arithmetic/logic instruction
29590
- must match the source in the comparison operation. For registers
29591
- we ignore the mode as there may have been a sign-extension involved. */
29592
- if (! rtx_equal_p (source, dest))
29593
+ if (lab == NULL_RTX)
29594
+ return 0;
29595
+ op = lab;
29596
+ do
29597
{
29598
- if (REG_P (source) && REG_P (dest) && REGNO (dest) == REGNO (source))
29599
- ;
29600
- else
29601
- return false;
29602
+ op = next_nonnote_insn (op);
29603
}
29604
-
29605
- return ((flags_set & flags_needed) == flags_needed);
29606
+ while (op && (LABEL_P (op)
29607
+ || (INSN_P (op) && GET_CODE (PATTERN (op)) == USE)));
29608
+ if (!op)
29609
+ return 0;
29610
+
29611
+ opsize = get_attr_length (op);
29612
+ if (opsize >= 0 && opsize < 8)
29613
+ return opsize - 1;
29614
+ return 0;
29615
}
29616
29617
#undef TARGET_FUNCTION_VALUE
29618
@@ -2759,6 +2799,12 @@
29619
#undef TARGET_CC_MODES_COMPATIBLE
29620
#define TARGET_CC_MODES_COMPATIBLE rx_cc_modes_compatible
29621
29622
+#undef TARGET_PROMOTE_FUNCTION_MODE
29623
+#define TARGET_PROMOTE_FUNCTION_MODE rx_promote_function_mode
29624
+
27188
@@ -2794,6 +2802,9 @@
27189
#undef TARGET_PROMOTE_FUNCTION_MODE
27190
#define TARGET_PROMOTE_FUNCTION_MODE rx_promote_function_mode
27191
29625
27192
+#undef TARGET_OPTION_OVERRIDE
29626
27193
+#define TARGET_OPTION_OVERRIDE rx_option_override
29627
27194
+
29628
27195
struct gcc_target targetm = TARGET_INITIALIZER;
29629
27196
29630
27197
/* #include "gt-rx.h" */
29631
--- a/src/gcc/config/rx/rx.h
29632
+++ b/src/gcc/config/rx/rx.h
29633
@@ -1,5 +1,5 @@
29634
/* GCC backend definitions for the Renesas RX processor.
29635
- Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
29636
+ Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
29637
Contributed by Red Hat.
29638
29639
This file is part of GCC.
29640
@@ -25,7 +25,10 @@
29641
builtin_define ("__RX__"); \
29642
builtin_assert ("cpu=RX"); \
29643
if (rx_cpu_type == RX610) \
29644
- builtin_assert ("machine=RX610"); \
29645
+ { \
29646
+ builtin_define ("__RX610__"); \
29647
+ builtin_assert ("machine=RX610"); \
29648
+ } \
29649
else \
29650
builtin_assert ("machine=RX600"); \
29651
\
29652
@@ -144,6 +147,10 @@
29653
#define SIZE_TYPE "long unsigned int"
29654
#undef PTRDIFF_TYPE
29655
#define PTRDIFF_TYPE "long int"
29656
+#undef WCHAR_TYPE
29657
+#define WCHAR_TYPE "long int"
29658
+#undef WCHAR_TYPE_SIZE
29659
+#define WCHAR_TYPE_SIZE BITS_PER_WORD
29660
#define POINTERS_EXTEND_UNSIGNED 1
29661
#define FUNCTION_MODE QImode
29662
#define CASE_VECTOR_MODE Pmode
29663
@@ -260,6 +267,7 @@
29664
29665
#define LIBCALL_VALUE(MODE) \
29666
gen_rtx_REG (((GET_MODE_CLASS (MODE) != MODE_INT \
29667
+ || COMPLEX_MODE_P (MODE) \
29668
|| GET_MODE_SIZE (MODE) >= 4) \
29669
? (MODE) \
29670
: SImode), \
29671
@@ -354,7 +362,7 @@
29672
{ \
29673
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
29674
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "cc" \
29675
- };
29676
+ }
29677
29678
#define ADDITIONAL_REGISTER_NAMES \
29679
{ \
29680
@@ -616,8 +624,6 @@
29681
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
29682
rx_print_operand_address (FILE, ADDR)
29683
29684
-extern int rx_float_compare_mode;
29685
-
29686
/* This is a version of REG_P that also returns TRUE for SUBREGs. */
29687
#define RX_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
29688
29689
@@ -653,14 +659,33 @@
29690
29691
#define BRANCH_COST(SPEED, PREDICT) 1
29692
#define REGISTER_MOVE_COST(MODE, FROM, TO) 2
29693
-#define MEMORY_MOVE_COST(MODE, REGCLASS, IN) (2 + memory_move_secondary_cost (MODE, REGCLASS, IN))
29694
+#define MEMORY_MOVE_COST(MODE, REGCLASS, IN) \
29695
+ (((IN) ? 2 : 0) + memory_move_secondary_cost (MODE, REGCLASS, IN))
29696
29697
-#define SELECT_CC_MODE(OP,X,Y) \
29698
- (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CC_ZSmode : \
29699
- (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS ? CC_ZSCmode : \
29700
- (GET_CODE (X) == ABS ? CC_ZSOmode : \
29701
- (GET_CODE (X) == AND || GET_CODE (X) == NOT || GET_CODE (X) == IOR \
29702
- || GET_CODE (X) == XOR || GET_CODE (X) == ROTATE \
29703
- || GET_CODE (X) == ROTATERT || GET_CODE (X) == ASHIFTRT \
29704
- || GET_CODE (X) == LSHIFTRT || GET_CODE (X) == ASHIFT ? CC_ZSmode : \
29705
- CCmode))))
29706
+#define SELECT_CC_MODE(OP,X,Y) rx_select_cc_mode ((OP), (X), (Y))
29707
+
29708
+#define JUMP_ALIGN(x) rx_align_for_label (x)
29709
+#define JUMP_ALIGN_MAX_SKIP rx_max_skip_for_label (label)
29710
+#define LABEL_ALIGN_AFTER_BARRIER(x) rx_align_for_label (x)
29711
+#define LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP rx_max_skip_for_label (label)
29712
+#define LOOP_ALIGN(x) rx_align_for_label (x)
29713
+#define LOOP_ALIGN_MAX_SKIP rx_max_skip_for_label (label)
29714
+#define LABEL_ALIGN(x) rx_align_for_label (x)
29715
+#define LABEL_ALIGN_MAX_SKIP rx_max_skip_for_label (NULL_RTX)
29716
+
29717
+#define ASM_OUTPUT_MAX_SKIP_ALIGN(STREAM, LOG, MAX_SKIP) \
29718
+ do \
29719
+ { \
29720
+ if ((LOG) == 0 || (MAX_SKIP) == 0) \
29721
+ break; \
29722
+ if (TARGET_AS100_SYNTAX) \
29723
+ { \
29724
+ if ((LOG) >= 2) \
29725
+ fprintf (STREAM, "\t.ALIGN 4\t; %d alignment actually requested\n", 1 << (LOG)); \
29726
+ else \
29727
+ fprintf (STREAM, "\t.ALIGN 2\n"); \
29728
+ } \
29729
+ else \
29730
+ fprintf (STREAM, "\t.balign %d,3,%d\n", 1 << (LOG), (MAX_SKIP)); \
29731
+ } \
29732
+ while (0)
29733
--- a/src/gcc/config/rx/rx.md
29734
+++ b/src/gcc/config/rx/rx.md
29735
@@ -1,5 +1,5 @@
29736
;; Machine Description for Renesas RX processors
29737
-;; Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
29738
+;; Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
29739
;; Contributed by Red Hat.
29740
29741
;; This file is part of GCC.
29742
@@ -19,14 +19,6 @@
29743
;; <http://www.gnu.org/licenses/>.
29744
29745
29746
-;; This code iterator allows all branch instructions to
29747
-;; be generated from a single define_expand template.
29748
-(define_code_iterator most_cond [eq ne gt ge lt le gtu geu ltu leu
29749
- unordered ordered ])
29750
-
29751
-;; Likewise, but only the ones that use Z or S.
29752
-(define_code_iterator zs_cond [eq ne gtu geu ltu leu ])
29753
-
29754
;; This code iterator is used for sign- and zero- extensions.
29755
(define_mode_iterator small_int_modes [(HI "") (QI "")])
29756
29757
@@ -38,15 +30,6 @@
29758
[(SF "ALLOW_RX_FPU_INSNS") (SI "") (HI "") (QI "")])
29759
29760
29761
-;; Used to map RX condition names to GCC
29762
-;; condition names for builtin instructions.
29763
-(define_code_iterator gcc_conds [eq ne gt ge lt le gtu geu ltu leu
29764
- unge unlt uneq ltgt])
29765
-(define_code_attr rx_conds [(eq "eq") (ne "ne") (gt "gt") (ge "ge") (lt "lt")
29766
- (le "le") (gtu "gtu") (geu "geu") (ltu "ltu")
29767
- (leu "leu") (unge "pz") (unlt "n") (uneq "o")
29768
- (ltgt "no")])
29769
-
29770
(define_constants
29771
[
29772
(SP_REG 0)
29773
@@ -58,6 +41,7 @@
29774
(UNSPEC_RTE 10)
29775
(UNSPEC_RTFI 11)
29776
(UNSPEC_NAKED 12)
29777
+ (UNSPEC_CONST 13)
29778
29779
(UNSPEC_MOVSTR 20)
29780
(UNSPEC_MOVMEM 21)
29781
@@ -150,6 +134,8 @@
29782
(define_insn_reservation "throughput_18_latency_18" 1
29783
(eq_attr "timings" "1818") "throughput*18")
29784
29785
+;; ----------------------------------------------------------------------------
29786
+
29787
;; Comparisons
29788
29789
;; Note - we do not specify the two instructions necessary to perform
29790
@@ -160,254 +146,164 @@
29791
29792
(define_expand "cbranchsi4"
29793
[(set (pc)
29794
- (if_then_else (match_operator 0 "comparison_operator"
29795
- [(match_operand:SI 1 "register_operand")
29796
- (match_operand:SI 2 "rx_source_operand")])
29797
- (label_ref (match_operand 3 ""))
29798
- (pc)))
29799
- ]
29800
- ""
29801
+ (if_then_else
29802
+ (match_operator 0 "comparison_operator"
29803
+ [(match_operand:SI 1 "register_operand")
29804
+ (match_operand:SI 2 "rx_source_operand")])
29805
+ (label_ref (match_operand 3 ""))
29806
+ (pc)))]
29807
""
29808
)
29809
29810
-(define_insn_and_split "*cbranchsi4_<code>"
29811
+(define_insn_and_split "*cbranchsi4"
29812
[(set (pc)
29813
- (if_then_else (most_cond (match_operand:SI 0 "register_operand" "r")
29814
- (match_operand:SI 1 "rx_source_operand" "riQ"))
29815
- (label_ref (match_operand 2 "" ""))
29816
- (pc)))
29817
- ]
29818
+ (if_then_else
29819
+ (match_operator 3 "comparison_operator"
29820
+ [(match_operand:SI 0 "register_operand" "r")
29821
+ (match_operand:SI 1 "rx_source_operand" "riQ")])
29822
+ (match_operand 2 "label_ref_operand" "")
29823
+ (pc)))]
29824
""
29825
"#"
29826
"reload_completed"
29827
[(const_int 0)]
29828
- "
29829
- /* We contstruct the split by hand as otherwise the JUMP_LABEL
29830
- attribute is not set correctly on the jump insn. */
29831
- emit_insn (gen_cmpsi (operands[0], operands[1]));
29832
-
29833
- emit_jump_insn (gen_conditional_branch (operands[2],
29834
- gen_rtx_fmt_ee (<most_cond:CODE>, CCmode,
29835
- gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
29836
- "
29837
-)
29838
+{
29839
+ rx_split_cbranch (CCmode, GET_CODE (operands[3]),
29840
+ operands[0], operands[1], operands[2]);
29841
+ DONE;
29842
+})
29843
29844
-;; -----------------------------------------------------------------------------
29845
-;; These two are the canonical TST/branch insns. However, GCC
29846
-;; generates a wide variety of tst-like patterns, we catch those
29847
-;; below.
29848
-(define_insn_and_split "*tstbranchsi4_<code>"
29849
- [(set (pc)
29850
- (if_then_else (zs_cond (and:SI (match_operand:SI 0 "register_operand" "r")
29851
- (match_operand:SI 1 "rx_source_operand" "riQ"))
29852
- (const_int 0))
29853
- (label_ref (match_operand 2 "" ""))
29854
- (pc)))
29855
- ]
29856
- ""
29857
- "#"
29858
+(define_insn "*cmpsi"
29859
+ [(set (reg:CC CC_REG)
29860
+ (compare:CC (match_operand:SI 0 "register_operand" "r,r,r,r,r,r,r")
29861
+ (match_operand:SI 1 "rx_source_operand" "r,Uint04,Int08,Sint16,Sint24,i,Q")))]
29862
"reload_completed"
29863
- [(const_int 0)]
29864
- "
29865
- emit_insn (gen_tstsi (operands[0], operands[1]));
29866
-
29867
- emit_jump_insn (gen_conditional_branch (operands[2],
29868
- gen_rtx_fmt_ee (<zs_cond:CODE>, CCmode,
29869
- gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
29870
- "
29871
+ "cmp\t%Q1, %0"
29872
+ [(set_attr "timings" "11,11,11,11,11,11,33")
29873
+ (set_attr "length" "2,2,3,4,5,6,5")]
29874
)
29875
29876
-;; Inverse of above
29877
-(define_insn_and_split "*tstbranchsi4_<code>"
29878
+;; Canonical method for representing TST.
29879
+(define_insn_and_split "*cbranchsi4_tst"
29880
[(set (pc)
29881
- (if_then_else (zs_cond (and:SI (match_operand:SI 0 "register_operand" "r")
29882
- (match_operand:SI 1 "rx_source_operand" "riQ"))
29883
- (const_int 0))
29884
- (pc)
29885
- (label_ref (match_operand 2 "" ""))))
29886
- ]
29887
+ (if_then_else
29888
+ (match_operator 3 "rx_zs_comparison_operator"
29889
+ [(and:SI (match_operand:SI 0 "register_operand" "r")
29890
+ (match_operand:SI 1 "rx_source_operand" "riQ"))
29891
+ (const_int 0)])
29892
+ (match_operand 2 "label_ref_operand" "")
29893
+ (pc)))]
29894
""
29895
"#"
29896
"reload_completed"
29897
[(const_int 0)]
29898
- "
29899
- emit_insn (gen_tstsi (operands[0], operands[1]));
29900
-
29901
- emit_jump_insn (gen_conditional_branch (operands[2],
29902
- gen_rtx_fmt_ee (reverse_condition (<zs_cond:CODE>), CCmode,
29903
- gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
29904
- "
29905
-)
29906
+{
29907
+ rx_split_cbranch (CC_ZSmode, GET_CODE (operands[3]),
29908
+ XEXP (operands[3], 0), XEXP (operands[3], 1),
29909
+ operands[2]);
29910
+ DONE;
29911
+})
29912
29913
;; Various other ways that GCC codes "var & const"
29914
-
29915
-(define_insn_and_split "*tstbranchsi4m_eq"
29916
+(define_insn_and_split "*cbranchsi4_tst_ext"
29917
[(set (pc)
29918
- (if_then_else (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
29919
- (match_operand 1 "rx_constshift_operand" "i")
29920
- (match_operand 2 "rx_constshift_operand" "i"))
29921
- (const_int 0))
29922
- (label_ref (match_operand 3 "" ""))
29923
- (pc)))
29924
- ]
29925
+ (if_then_else
29926
+ (match_operator 4 "rx_z_comparison_operator"
29927
+ [(zero_extract:SI
29928
+ (match_operand:SI 0 "register_operand" "r")
29929
+ (match_operand:SI 1 "rx_constshift_operand" "")
29930
+ (match_operand:SI 2 "rx_constshift_operand" ""))
29931
+ (const_int 0)])
29932
+ (match_operand 3 "label_ref_operand" "")
29933
+ (pc)))]
29934
""
29935
"#"
29936
- ""
29937
- [(set (pc)
29938
- (if_then_else (eq (and:SI (match_dup 0)
29939
- (match_dup 4))
29940
- (const_int 0))
29941
- (label_ref (match_dup 3))
29942
- (pc)))
29943
- ]
29944
- "operands[4] = GEN_INT (((1 << INTVAL (operands[1]))-1) << INTVAL (operands[2]));"
29945
-)
29946
+ "reload_completed"
29947
+ [(const_int 0)]
29948
+{
29949
+ HOST_WIDE_INT mask;
29950
+ rtx x;
29951
+
29952
+ mask = 1;
29953
+ mask <<= INTVAL (operands[1]);
29954
+ mask -= 1;
29955
+ mask <<= INTVAL (operands[2]);
29956
+ x = gen_rtx_AND (SImode, operands[0], gen_int_mode (mask, SImode));
29957
+
29958
+ rx_split_cbranch (CC_ZSmode, GET_CODE (operands[4]),
29959
+ x, const0_rtx, operands[3]);
29960
+ DONE;
29961
+})
29962
29963
-(define_insn_and_split "*tstbranchsi4m_ne"
29964
- [(set (pc)
29965
- (if_then_else (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
29966
- (match_operand 1 "rx_constshift_operand" "i")
29967
- (match_operand 2 "rx_constshift_operand" "i"))
29968
- (const_int 0))
29969
- (label_ref (match_operand 3 "" ""))
29970
- (pc)))
29971
- ]
29972
- ""
29973
- "#"
29974
- ""
29975
- [(set (pc)
29976
- (if_then_else (ne (and:SI (match_dup 0)
29977
- (match_dup 4))
29978
- (const_int 0))
29979
- (label_ref (match_dup 3))
29980
- (pc)))
29981
- ]
29982
- "operands[4] = GEN_INT (((1 << INTVAL (operands[1]))-1) << INTVAL (operands[2]));"
29983
+(define_insn "*tstsi"
29984
+ [(set (reg:CC_ZS CC_REG)
29985
+ (compare:CC_ZS
29986
+ (and:SI (match_operand:SI 0 "register_operand" "r,r,r")
29987
+ (match_operand:SI 1 "rx_source_operand" "r,i,Q"))
29988
+ (const_int 0)))]
29989
+ "reload_completed"
29990
+ "tst\t%Q1, %0"
29991
+ [(set_attr "timings" "11,11,33")
29992
+ (set_attr "length" "3,7,6")]
29993
)
29994
29995
-;; -----------------------------------------------------------------------------
29996
-
29997
(define_expand "cbranchsf4"
29998
[(set (pc)
29999
- (if_then_else (match_operator 0 "comparison_operator"
30000
- [(match_operand:SF 1 "register_operand")
30001
- (match_operand:SF 2 "rx_source_operand")])
30002
- (label_ref (match_operand 3 ""))
30003
- (pc)))
30004
- ]
30005
+ (if_then_else
30006
+ (match_operator 0 "rx_fp_comparison_operator"
30007
+ [(match_operand:SF 1 "register_operand")
30008
+ (match_operand:SF 2 "rx_source_operand")])
30009
+ (label_ref (match_operand 3 ""))
30010
+ (pc)))]
30011
"ALLOW_RX_FPU_INSNS"
30012
- ""
30013
)
30014
30015
-(define_insn_and_split "*cbranchsf4_<code>"
30016
+(define_insn_and_split "*cbranchsf4"
30017
[(set (pc)
30018
- (if_then_else (most_cond (match_operand:SF 0 "register_operand" "r")
30019
- (match_operand:SF 1 "rx_source_operand" "rFiQ"))
30020
- (label_ref (match_operand 2 "" ""))
30021
- (pc)))
30022
- ]
30023
+ (if_then_else
30024
+ (match_operator 3 "rx_fp_comparison_operator"
30025
+ [(match_operand:SF 0 "register_operand" "r")
30026
+ (match_operand:SF 1 "rx_source_operand" "rFQ")])
30027
+ (match_operand 2 "label_ref_operand" "")
30028
+ (pc)))]
30029
"ALLOW_RX_FPU_INSNS"
30030
"#"
30031
"&& reload_completed"
30032
[(const_int 0)]
30033
- "
30034
- /* We contstruct the split by hand as otherwise the JUMP_LABEL
30035
- attribute is not set correctly on the jump insn. */
30036
- emit_insn (gen_cmpsf (operands[0], operands[1]));
30037
-
30038
- emit_jump_insn (gen_conditional_branch (operands[2],
30039
- gen_rtx_fmt_ee (<most_cond:CODE>, CCmode,
30040
- gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
30041
- "
30042
-)
30043
-
30044
-(define_insn "tstsi"
30045
- [(set (reg:CC_ZS CC_REG)
30046
- (compare:CC_ZS (and:SI (match_operand:SI 0 "register_operand" "r,r,r")
30047
- (match_operand:SI 1 "rx_source_operand" "r,i,Q"))
30048
- (const_int 0)))]
30049
- ""
30050
- {
30051
- rx_float_compare_mode = false;
30052
- return "tst\t%Q1, %0";
30053
- }
30054
- [(set_attr "timings" "11,11,33")
30055
- (set_attr "length" "3,7,6")]
30056
-)
30057
-
30058
-(define_insn "cmpsi"
30059
- [(set (reg:CC CC_REG)
30060
- (compare:CC (match_operand:SI 0 "register_operand" "r,r,r,r,r,r,r")
30061
- (match_operand:SI 1 "rx_source_operand" "r,Uint04,Int08,Sint16,Sint24,i,Q")))]
30062
- ""
30063
- {
30064
- rx_float_compare_mode = false;
30065
- if (rx_compare_redundant (insn))
30066
- return "; Compare Eliminated: cmp %Q1, %0";
30067
- return "cmp\t%Q1, %0";
30068
- }
30069
- [(set_attr "timings" "11,11,11,11,11,11,33")
30070
- (set_attr "length" "2,2,3,4,5,6,5")]
30071
-)
30072
-
30073
-;; This pattern is disabled when -fnon-call-exceptions is active because
30074
-;; it could generate a floating point exception, which would introduce an
30075
-;; edge into the flow graph between this insn and the conditional branch
30076
-;; insn to follow, thus breaking the cc0 relationship. Run the g++ test
30077
-;; g++.dg/eh/080514-1.C to see this happen.
30078
-(define_insn "cmpsf"
30079
- [(set (reg:CC_ZSO CC_REG)
30080
- (compare:CC_ZSO (match_operand:SF 0 "register_operand" "r,r,r")
30081
- (match_operand:SF 1 "rx_source_operand" "r,iF,Q")))]
30082
- "ALLOW_RX_FPU_INSNS"
30083
- {
30084
- rx_float_compare_mode = true;
30085
- return "fcmp\t%1, %0";
30086
- }
30087
+{
30088
+ rx_split_cbranch (CC_Fmode, GET_CODE (operands[3]),
30089
+ operands[0], operands[1], operands[2]);
30090
+ DONE;
30091
+})
30092
+
30093
+(define_insn "*cmpsf"
30094
+ [(set (reg:CC_F CC_REG)
30095
+ (compare:CC_F
30096
+ (match_operand:SF 0 "register_operand" "r,r,r")
30097
+ (match_operand:SF 1 "rx_source_operand" "r,F,Q")))]
30098
+ "ALLOW_RX_FPU_INSNS && reload_completed"
30099
+ "fcmp\t%1, %0"
30100
[(set_attr "timings" "11,11,33")
30101
(set_attr "length" "3,7,5")]
30102
)
30103
30104
;; Flow Control Instructions:
30105
30106
-(define_expand "b<code>"
30107
+(define_insn "*conditional_branch"
30108
[(set (pc)
30109
- (if_then_else (most_cond (reg:CC CC_REG) (const_int 0))
30110
- (label_ref (match_operand 0))
30111
- (pc)))]
30112
- ""
30113
- ""
30114
-)
30115
-
30116
-(define_insn "conditional_branch"
30117
- [(set (pc)
30118
- (if_then_else (match_operator 1 "comparison_operator"
30119
- [(reg:CC CC_REG) (const_int 0)])
30120
- (label_ref (match_operand 0 "" ""))
30121
- (pc)))]
30122
- ""
30123
- {
30124
- return rx_gen_cond_branch_template (operands[1], false);
30125
- }
30126
+ (if_then_else
30127
+ (match_operator 1 "comparison_operator"
30128
+ [(reg CC_REG) (const_int 0)])
30129
+ (label_ref (match_operand 0 "" ""))
30130
+ (pc)))]
30131
+ "reload_completed"
30132
+ "b%B1\t%0"
30133
[(set_attr "length" "8") ;; This length is wrong, but it is
30134
;; too hard to compute statically.
30135
(set_attr "timings" "33")] ;; The timing assumes that the branch is taken.
30136
)
30137
30138
-(define_insn "*reveresed_conditional_branch"
30139
- [(set (pc)
30140
- (if_then_else (match_operator 1 "comparison_operator"
30141
- [(reg:CC CC_REG) (const_int 0)])
30142
- (pc)
30143
- (label_ref (match_operand 0 "" ""))))]
30144
- ""
30145
- {
30146
- return rx_gen_cond_branch_template (operands[1], true);
30147
- }
30148
- [(set_attr "length" "8") ;; This length is wrong, but it is
30149
- ;; too hard to compute statically.
30150
- (set_attr "timings" "33")] ;; The timing assumes that the branch is taken.
30151
-)
30152
+;; ----------------------------------------------------------------------------
30153
30154
(define_insn "jump"
30155
[(set (pc)
30156
@@ -448,10 +344,12 @@
30157
(set_attr "timings" "55")]
30158
)
30159
30160
+;; Unspec used so that the constant will not be invalid
30161
+;; if -mmax-constant-size has been specified.
30162
(define_insn "deallocate_and_return"
30163
[(set (reg:SI SP_REG)
30164
(plus:SI (reg:SI SP_REG)
30165
- (match_operand:SI 0 "immediate_operand" "i")))
30166
+ (const:SI (unspec:SI [(match_operand 0 "const_int_operand" "n")] UNSPEC_CONST))))
30167
(return)]
30168
""
30169
"rtsd\t%0"
30170
@@ -461,9 +359,10 @@
30171
30172
(define_insn "pop_and_return"
30173
[(match_parallel 1 "rx_rtsd_vector"
30174
- [(set:SI (reg:SI SP_REG)
30175
- (plus:SI (reg:SI SP_REG)
30176
- (match_operand:SI 0 "const_int_operand" "n")))])]
30177
+ [(set (reg:SI SP_REG)
30178
+ (plus:SI (reg:SI SP_REG)
30179
+ (match_operand:SI 0 "const_int_operand" "n")))])
30180
+ (return)]
30181
"reload_completed"
30182
{
30183
rx_emit_stack_popm (operands, false);
30184
@@ -513,14 +412,14 @@
30185
30186
if (! rx_call_operand (dest, Pmode))
30187
dest = force_reg (Pmode, dest);
30188
- emit_call_insn (gen_call_internal (dest, operands[1]));
30189
+ emit_call_insn (gen_call_internal (dest));
30190
DONE;
30191
}
30192
)
30193
30194
(define_insn "call_internal"
30195
[(call (mem:QI (match_operand:SI 0 "rx_call_operand" "r,Symbol"))
30196
- (match_operand:SI 1 "general_operand" "g,g"))
30197
+ (const_int 0))
30198
(clobber (reg:CC CC_REG))]
30199
""
30200
"@
30201
@@ -540,7 +439,7 @@
30202
30203
if (! rx_call_operand (dest, Pmode))
30204
dest = force_reg (Pmode, dest);
30205
- emit_call_insn (gen_call_value_internal (operands[0], dest, operands[2]));
30206
+ emit_call_insn (gen_call_value_internal (operands[0], dest));
30207
DONE;
30208
}
30209
)
30210
@@ -548,7 +447,7 @@
30211
(define_insn "call_value_internal"
30212
[(set (match_operand 0 "register_operand" "=r,r")
30213
(call (mem:QI (match_operand:SI 1 "rx_call_operand" "r,Symbol"))
30214
- (match_operand:SI 2 "general_operand" "g,g")))
30215
+ (const_int 0)))
30216
(clobber (reg:CC CC_REG))]
30217
""
30218
"@
30219
@@ -572,12 +471,14 @@
30220
{
30221
if (MEM_P (operands[0]))
30222
operands[0] = XEXP (operands[0], 0);
30223
+ emit_call_insn (gen_sibcall_internal (operands[0]));
30224
+ DONE;
30225
}
30226
)
30227
30228
(define_insn "sibcall_internal"
30229
[(call (mem:QI (match_operand:SI 0 "rx_symbolic_call_operand" "Symbol"))
30230
- (match_operand:SI 1 "general_operand" "g"))
30231
+ (const_int 0))
30232
(return)]
30233
""
30234
"bra\t%A0"
30235
@@ -595,13 +496,15 @@
30236
{
30237
if (MEM_P (operands[1]))
30238
operands[1] = XEXP (operands[1], 0);
30239
+ emit_call_insn (gen_sibcall_value_internal (operands[0], operands[1]));
30240
+ DONE;
30241
}
30242
)
30243
30244
(define_insn "sibcall_value_internal"
30245
[(set (match_operand 0 "register_operand" "=r")
30246
(call (mem:QI (match_operand:SI 1 "rx_symbolic_call_operand" "Symbol"))
30247
- (match_operand:SI 2 "general_operand" "g")))
30248
+ (const_int 0)))
30249
(return)]
30250
""
30251
"bra\t%A1"
30252
@@ -653,6 +556,9 @@
30253
{
30254
if (MEM_P (operand0) && MEM_P (operand1))
30255
operands[1] = copy_to_mode_reg (<register_modes:MODE>mode, operand1);
30256
+ if (CONST_INT_P (operand1)
30257
+ && ! rx_is_legitimate_constant (operand1))
30258
+ FAIL;
30259
}
30260
)
30261
30262
@@ -688,11 +594,11 @@
30263
)
30264
30265
(define_insn "stack_push"
30266
- [(set:SI (reg:SI SP_REG)
30267
- (minus:SI (reg:SI SP_REG)
30268
- (const_int 4)))
30269
- (set:SI (mem:SI (reg:SI SP_REG))
30270
- (match_operand:SI 0 "register_operand" "r"))]
30271
+ [(set (reg:SI SP_REG)
30272
+ (minus:SI (reg:SI SP_REG)
30273
+ (const_int 4)))
30274
+ (set (mem:SI (reg:SI SP_REG))
30275
+ (match_operand:SI 0 "register_operand" "r"))]
30276
""
30277
"push.l\t%0"
30278
[(set_attr "length" "2")]
30279
@@ -700,9 +606,9 @@
30280
30281
(define_insn "stack_pushm"
30282
[(match_parallel 1 "rx_store_multiple_vector"
30283
- [(set:SI (reg:SI SP_REG)
30284
- (minus:SI (reg:SI SP_REG)
30285
- (match_operand:SI 0 "const_int_operand" "n")))])]
30286
+ [(set (reg:SI SP_REG)
30287
+ (minus:SI (reg:SI SP_REG)
30288
+ (match_operand:SI 0 "const_int_operand" "n")))])]
30289
"reload_completed"
30290
{
30291
rx_emit_stack_pushm (operands);
30292
@@ -713,11 +619,11 @@
30293
)
30294
30295
(define_insn "stack_pop"
30296
- [(set:SI (match_operand:SI 0 "register_operand" "=r")
30297
- (mem:SI (reg:SI SP_REG)))
30298
- (set:SI (reg:SI SP_REG)
30299
- (plus:SI (reg:SI SP_REG)
30300
- (const_int 4)))]
30301
+ [(set (match_operand:SI 0 "register_operand" "=r")
30302
+ (mem:SI (reg:SI SP_REG)))
30303
+ (set (reg:SI SP_REG)
30304
+ (plus:SI (reg:SI SP_REG)
30305
+ (const_int 4)))]
30306
""
30307
"pop\t%0"
30308
[(set_attr "length" "2")
30309
@@ -726,9 +632,9 @@
30310
30311
(define_insn "stack_popm"
30312
[(match_parallel 1 "rx_load_multiple_vector"
30313
- [(set:SI (reg:SI SP_REG)
30314
- (plus:SI (reg:SI SP_REG)
30315
- (match_operand:SI 0 "const_int_operand" "n")))])]
30316
+ [(set (reg:SI SP_REG)
30317
+ (plus:SI (reg:SI SP_REG)
30318
+ (match_operand:SI 0 "const_int_operand" "n")))])]
30319
"reload_completed"
30320
{
30321
rx_emit_stack_popm (operands, true);
30322
@@ -738,68 +644,139 @@
30323
(set_attr "timings" "45")] ;; The timing is a guesstimate average timing.
30324
)
30325
30326
-;; FIXME: Add memory destination options ?
30327
-(define_insn "cstoresi4"
30328
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
30329
+(define_insn_and_split "cstoresi4"
30330
+ [(set (match_operand:SI 0 "register_operand" "=r")
30331
(match_operator:SI 1 "comparison_operator"
30332
- [(match_operand:SI 2 "register_operand" "r,r,r,r,r,r,r")
30333
- (match_operand:SI 3 "rx_source_operand" "r,Uint04,Int08,Sint16,Sint24,i,Q")]))
30334
- (clobber (reg:CC CC_REG))] ;; Because the cc flags are set based on comparing ops 2 & 3 not the value in op 0.
30335
+ [(match_operand:SI 2 "register_operand" "r")
30336
+ (match_operand:SI 3 "rx_source_operand" "riQ")]))
30337
+ (clobber (reg:CC CC_REG))]
30338
""
30339
- {
30340
- rx_float_compare_mode = false;
30341
- return "cmp\t%Q3, %Q2\n\tsc%B1.L\t%0";
30342
- }
30343
- [(set_attr "timings" "22,22,22,22,22,22,44")
30344
- (set_attr "length" "5,5,6,7,8,9,8")]
30345
+ "#"
30346
+ "reload_completed"
30347
+ [(const_int 0)]
30348
+{
30349
+ rtx flags, x;
30350
+
30351
+ flags = gen_rtx_REG (CCmode, CC_REG);
30352
+ x = gen_rtx_COMPARE (CCmode, operands[2], operands[3]);
30353
+ x = gen_rtx_SET (VOIDmode, flags, x);
30354
+ emit_insn (x);
30355
+
30356
+ x = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, flags, const0_rtx);
30357
+ x = gen_rtx_SET (VOIDmode, operands[0], x);
30358
+ emit_insn (x);
30359
+ DONE;
30360
+})
30361
+
30362
+(define_insn "*sccc"
30363
+ [(set (match_operand:SI 0 "register_operand" "=r")
30364
+ (match_operator:SI 1 "comparison_operator"
30365
+ [(reg CC_REG) (const_int 0)]))]
30366
+ "reload_completed"
30367
+ "sc%B1.L\t%0"
30368
+ [(set_attr "length" "3")]
30369
)
30370
30371
+(define_insn_and_split "cstoresf4"
30372
+ [(set (match_operand:SI 0 "register_operand" "=r")
30373
+ (match_operator:SI 1 "rx_fp_comparison_operator"
30374
+ [(match_operand:SF 2 "register_operand" "r")
30375
+ (match_operand:SF 3 "rx_source_operand" "rFQ")]))]
30376
+ "ALLOW_RX_FPU_INSNS"
30377
+ "#"
30378
+ "reload_completed"
30379
+ [(const_int 0)]
30380
+{
30381
+ rtx flags, x;
30382
+
30383
+ flags = gen_rtx_REG (CC_Fmode, CC_REG);
30384
+ x = gen_rtx_COMPARE (CC_Fmode, operands[2], operands[3]);
30385
+ x = gen_rtx_SET (VOIDmode, flags, x);
30386
+ emit_insn (x);
30387
+
30388
+ x = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, flags, const0_rtx);
30389
+ x = gen_rtx_SET (VOIDmode, operands[0], x);
30390
+ emit_insn (x);
30391
+ DONE;
30392
+})
30393
+
30394
(define_expand "movsicc"
30395
[(parallel
30396
[(set (match_operand:SI 0 "register_operand")
30397
(if_then_else:SI (match_operand:SI 1 "comparison_operator")
30398
(match_operand:SI 2 "nonmemory_operand")
30399
- (match_operand:SI 3 "immediate_operand")))
30400
- (clobber (reg:CC CC_REG))])] ;; See cstoresi4
30401
+ (match_operand:SI 3 "nonmemory_operand")))
30402
+ (clobber (reg:CC CC_REG))])]
30403
""
30404
- {
30405
- if (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE)
30406
- FAIL;
30407
- if (! CONST_INT_P (operands[3]))
30408
- FAIL;
30409
- }
30410
-)
30411
+{
30412
+ /* ??? Support other conditions via cstore into a temporary? */
30413
+ if (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE)
30414
+ FAIL;
30415
+ /* One operand must be a constant. */
30416
+ if (!CONSTANT_P (operands[2]) && !CONSTANT_P (operands[3]))
30417
+ FAIL;
30418
+})
30419
30420
-(define_insn "*movsieq"
30421
- [(set (match_operand:SI 0 "register_operand" "=r,r,r")
30422
- (if_then_else:SI (eq (match_operand:SI 3 "register_operand" "r,r,r")
30423
- (match_operand:SI 4 "rx_source_operand" "riQ,riQ,riQ"))
30424
- (match_operand:SI 1 "nonmemory_operand" "0,i,r")
30425
- (match_operand:SI 2 "immediate_operand" "i,i,i")))
30426
- (clobber (reg:CC CC_REG))] ;; See cstoresi4
30427
- ""
30428
- "@
30429
- cmp\t%Q4, %Q3\n\tstnz\t%2, %0
30430
- cmp\t%Q4, %Q3\n\tmov.l\t%2, %0\n\tstz\t%1, %0
30431
- cmp\t%Q4, %Q3\n\tmov.l\t%1, %0\n\tstnz\t%2, %0"
30432
- [(set_attr "length" "13,19,15")
30433
- (set_attr "timings" "22,33,33")]
30434
-)
30435
-
30436
-(define_insn "*movsine"
30437
- [(set (match_operand:SI 0 "register_operand" "=r,r,r")
30438
- (if_then_else:SI (ne (match_operand:SI 3 "register_operand" "r,r,r")
30439
- (match_operand:SI 4 "rx_source_operand" "riQ,riQ,riQ"))
30440
- (match_operand:SI 1 "nonmemory_operand" "0,i,r")
30441
- (match_operand:SI 2 "immediate_operand" "i,i,i")))
30442
- (clobber (reg:CC CC_REG))] ;; See cstoresi4
30443
- ""
30444
- "@
30445
- cmp\t%Q4, %Q3\n\tstz\t%2, %0
30446
- cmp\t%Q4, %Q3\n\tmov.l\t%2, %0\n\tstnz\t%1, %0
30447
- cmp\t%Q4, %Q3\n\tmov.l\t%1, %0\n\tstz\t%2, %0"
30448
- [(set_attr "length" "13,19,15")
30449
- (set_attr "timings" "22,33,33")]
30450
+(define_insn_and_split "*movsicc"
30451
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
30452
+ (if_then_else:SI
30453
+ (match_operator 5 "rx_z_comparison_operator"
30454
+ [(match_operand:SI 3 "register_operand" "r,r")
30455
+ (match_operand:SI 4 "rx_source_operand" "riQ,riQ")])
30456
+ (match_operand:SI 1 "nonmemory_operand" "i,ri")
30457
+ (match_operand:SI 2 "nonmemory_operand" "ri,i")))
30458
+ (clobber (reg:CC CC_REG))]
30459
+ "CONSTANT_P (operands[1]) || CONSTANT_P (operands[2])"
30460
+ "#"
30461
+ "&& reload_completed"
30462
+ [(const_int 0)]
30463
+{
30464
+ rtx x, flags, op0, op1, op2;
30465
+ enum rtx_code cmp_code;
30466
+
30467
+ flags = gen_rtx_REG (CCmode, CC_REG);
30468
+ x = gen_rtx_COMPARE (CCmode, operands[3], operands[4]);
30469
+ emit_insn (gen_rtx_SET (VOIDmode, flags, x));
30470
+
30471
+ cmp_code = GET_CODE (operands[5]);
30472
+ op0 = operands[0];
30473
+ op1 = operands[1];
30474
+ op2 = operands[2];
30475
+
30476
+ /* If OP2 is the constant, reverse the sense of the move. */
30477
+ if (!CONSTANT_P (operands[1]))
30478
+ {
30479
+ x = op1, op1 = op2, op2 = x;
30480
+ cmp_code = reverse_condition (cmp_code);
30481
+ }
30482
+
30483
+ /* If OP2 does not match the output, copy it into place. We have allowed
30484
+ these alternatives so that the destination can legitimately be one of
30485
+ the comparison operands without increasing register pressure. */
30486
+ if (!rtx_equal_p (op0, op2))
30487
+ emit_move_insn (op0, op2);
30488
+
30489
+ x = gen_rtx_fmt_ee (cmp_code, VOIDmode, flags, const0_rtx);
30490
+ x = gen_rtx_IF_THEN_ELSE (SImode, x, op1, op0);
30491
+ emit_insn (gen_rtx_SET (VOIDmode, op0, x));
30492
+ DONE;
30493
+})
30494
+
30495
+(define_insn "*stcc"
30496
+ [(set (match_operand:SI 0 "register_operand" "+r,r,r,r")
30497
+ (if_then_else:SI
30498
+ (match_operator 2 "rx_z_comparison_operator"
30499
+ [(reg CC_REG) (const_int 0)])
30500
+ (match_operand:SI 1 "immediate_operand" "Sint08,Sint16,Sint24,i")
30501
+ (match_dup 0)))]
30502
+ "reload_completed"
30503
+{
30504
+ if (GET_CODE (operands[2]) == EQ)
30505
+ return "stz\t%1, %0";
30506
+ else
30507
+ return "stnz\t%1, %0";
30508
+}
30509
+ [(set_attr "length" "4,5,6,7")]
30510
)
30511
30512
;; Arithmetic Instructions
30513
@@ -807,9 +784,7 @@
30514
(define_insn "abssi2"
30515
[(set (match_operand:SI 0 "register_operand" "=r,r")
30516
(abs:SI (match_operand:SI 1 "register_operand" "0,r")))
30517
- (set (reg:CC_ZSO CC_REG)
30518
- (compare:CC_ZSO (abs:SI (match_dup 1))
30519
- (const_int 0)))]
30520
+ (clobber (reg:CC CC_REG))]
30521
""
30522
"@
30523
abs\t%0
30524
@@ -817,13 +792,27 @@
30525
[(set_attr "length" "2,3")]
30526
)
30527
30528
+(define_insn "*abssi2_flags"
30529
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
30530
+ (abs:SI (match_operand:SI 1 "register_operand" "0,r")))
30531
+ (set (reg CC_REG)
30532
+ (compare (abs:SI (match_dup 1))
30533
+ (const_int 0)))]
30534
+ ;; Note - although the ABS instruction does set the O bit in the processor
30535
+ ;; status word, it does not do so in a way that is comparable with the CMP
30536
+ ;; instruction. Hence we use CC_ZSmode rather than CC_ZSOmode.
30537
+ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
30538
+ "@
30539
+ abs\t%0
30540
+ abs\t%1, %0"
30541
+ [(set_attr "length" "2,3")]
30542
+)
30543
+
30544
(define_insn "addsi3"
30545
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r")
30546
(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0")
30547
(match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q")))
30548
- (set (reg:CC_ZSC CC_REG) ;; See subsi3
30549
- (compare:CC_ZSC (plus:SI (match_dup 1) (match_dup 2))
30550
- (const_int 0)))]
30551
+ (clobber (reg:CC CC_REG))]
30552
""
30553
"@
30554
add\t%2, %0
30555
@@ -844,27 +833,170 @@
30556
(set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")]
30557
)
30558
30559
-(define_insn "adddi3"
30560
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r")
30561
- (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,0,0")
30562
- (match_operand:DI 2 "rx_source_operand"
30563
- "r,Sint08,Sint16,Sint24,i,Q")))
30564
- (set (reg:CC_ZSC CC_REG) ;; See subsi3
30565
- (compare:CC_ZSC (plus:DI (match_dup 1) (match_dup 2))
30566
- (const_int 0)))]
30567
- ""
30568
- "add\t%L2, %L0\n\tadc\t%H2, %H0"
30569
- [(set_attr "timings" "22,22,22,22,22,44")
30570
- (set_attr "length" "5,7,9,11,13,11")]
30571
+(define_insn "*addsi3_flags"
30572
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r")
30573
+ (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0")
30574
+ (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q")))
30575
+ (set (reg CC_REG)
30576
+ (compare (plus:SI (match_dup 1) (match_dup 2))
30577
+ (const_int 0)))]
30578
+ "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
30579
+ "@
30580
+ add\t%2, %0
30581
+ add\t%2, %0
30582
+ sub\t%N2, %0
30583
+ add\t%2, %0
30584
+ add\t%2, %0
30585
+ add\t%2, %0
30586
+ add\t%2, %0
30587
+ add\t%1, %0
30588
+ add\t%2, %1, %0
30589
+ add\t%2, %1, %0
30590
+ add\t%2, %1, %0
30591
+ add\t%2, %1, %0
30592
+ add\t%2, %1, %0
30593
+ add\t%Q2, %0"
30594
+ [(set_attr "timings" "11,11,11,11,11,11,11,11,11,11,11,11,11,33")
30595
+ (set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")]
30596
+)
30597
+
30598
+;; A helper to expand the above with the CC_MODE filled in.
30599
+(define_expand "addsi3_flags"
30600
+ [(parallel [(set (match_operand:SI 0 "register_operand")
30601
+ (plus:SI (match_operand:SI 1 "register_operand")
30602
+ (match_operand:SI 2 "rx_source_operand")))
30603
+ (set (reg:CC_ZSC CC_REG)
30604
+ (compare:CC_ZSC (plus:SI (match_dup 1) (match_dup 2))
30605
+ (const_int 0)))])]
30606
+)
30607
+
30608
+(define_insn "adc_internal"
30609
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
30610
+ (plus:SI
30611
+ (plus:SI
30612
+ (ltu:SI (reg:CC CC_REG) (const_int 0))
30613
+ (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0"))
30614
+ (match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q")))
30615
+ (clobber (reg:CC CC_REG))]
30616
+ "reload_completed"
30617
+ "adc %2,%0"
30618
+ [(set_attr "timings" "11,11,11,11,11,33")
30619
+ (set_attr "length" "3,4,5,6,7,6")]
30620
)
30621
30622
+(define_insn "*adc_flags"
30623
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
30624
+ (plus:SI
30625
+ (plus:SI
30626
+ (ltu:SI (reg:CC CC_REG) (const_int 0))
30627
+ (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0"))
30628
+ (match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q")))
30629
+ (set (reg CC_REG)
30630
+ (compare
30631
+ (plus:SI
30632
+ (plus:SI
30633
+ (ltu:SI (reg:CC CC_REG) (const_int 0))
30634
+ (match_dup 1))
30635
+ (match_dup 2))
30636
+ (const_int 0)))]
30637
+ "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
30638
+ "adc %2,%0"
30639
+ [(set_attr "timings" "11,11,11,11,11,33")
30640
+ (set_attr "length" "3,4,5,6,7,6")]
30641
+)
30642
+
30643
+(define_expand "adddi3"
30644
+ [(set (match_operand:DI 0 "register_operand")
30645
+ (plus:DI (match_operand:DI 1 "register_operand")
30646
+ (match_operand:DI 2 "rx_source_operand")))]
30647
+ ""
30648
+{
30649
+ rtx op0l, op0h, op1l, op1h, op2l, op2h;
30650
+
30651
+ op0l = gen_lowpart (SImode, operands[0]);
30652
+ op1l = gen_lowpart (SImode, operands[1]);
30653
+ op2l = gen_lowpart (SImode, operands[2]);
30654
+ op0h = gen_highpart (SImode, operands[0]);
30655
+ op1h = gen_highpart (SImode, operands[1]);
30656
+ op2h = gen_highpart_mode (SImode, DImode, operands[2]);
30657
+
30658
+ emit_insn (gen_adddi3_internal (op0l, op0h, op1l, op2l, op1h, op2h));
30659
+ DONE;
30660
+})
30661
+
30662
+(define_insn_and_split "adddi3_internal"
30663
+ [(set (match_operand:SI 0 "register_operand" "=r")
30664
+ (plus:SI (match_operand:SI 2 "register_operand" "r")
30665
+ (match_operand:SI 3 "rx_source_operand" "riQ")))
30666
+ (set (match_operand:SI 1 "register_operand" "=r")
30667
+ (plus:SI
30668
+ (plus:SI
30669
+ (ltu:SI (plus:SI (match_dup 2) (match_dup 3)) (match_dup 2))
30670
+ (match_operand:SI 4 "register_operand" "%1"))
30671
+ (match_operand:SI 5 "rx_source_operand" "riQ")))
30672
+ (clobber (match_scratch:SI 6 "=&r"))
30673
+ (clobber (reg:CC CC_REG))]
30674
+ ""
30675
+ "#"
30676
+ "reload_completed"
30677
+ [(const_int 0)]
30678
+{
30679
+ rtx op0l = operands[0];
30680
+ rtx op0h = operands[1];
30681
+ rtx op1l = operands[2];
30682
+ rtx op2l = operands[3];
30683
+ rtx op1h = operands[4];
30684
+ rtx op2h = operands[5];
30685
+ rtx scratch = operands[6];
30686
+ rtx x;
30687
+
30688
+ if (reg_overlap_mentioned_p (op0l, op1h))
30689
+ {
30690
+ emit_move_insn (scratch, op0l);
30691
+ op1h = scratch;
30692
+ if (reg_overlap_mentioned_p (op0l, op2h))
30693
+ op2h = scratch;
30694
+ }
30695
+ else if (reg_overlap_mentioned_p (op0l, op2h))
30696
+ {
30697
+ emit_move_insn (scratch, op0l);
30698
+ op2h = scratch;
30699
+ }
30700
+
30701
+ if (rtx_equal_p (op0l, op1l))
30702
+ ;
30703
+ /* It is preferable that op0l == op1l... */
30704
+ else if (rtx_equal_p (op0l, op2l))
30705
+ x = op1l, op1l = op2l, op2l = x;
30706
+ /* ... but it is only a requirement if op2l == MEM. */
30707
+ else if (MEM_P (op2l))
30708
+ {
30709
+ /* Let's hope that we still have a scratch register free. */
30710
+ gcc_assert (op1h != scratch);
30711
+ emit_move_insn (scratch, op2l);
30712
+ op2l = scratch;
30713
+ }
30714
+
30715
+ emit_insn (gen_addsi3_flags (op0l, op1l, op2l));
30716
+
30717
+ if (rtx_equal_p (op0h, op1h))
30718
+ ;
30719
+ else if (rtx_equal_p (op0h, op2h))
30720
+ x = op1h, op1h = op2h, op2h = x;
30721
+ else
30722
+ {
30723
+ emit_move_insn (op0h, op1h);
30724
+ op1h = op0h;
30725
+ }
30726
+ emit_insn (gen_adc_internal (op0h, op1h, op2h));
30727
+ DONE;
30728
+})
30729
+
30730
(define_insn "andsi3"
30731
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
30732
(and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
30733
(match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
30734
- (set (reg:CC_ZS CC_REG)
30735
- (compare:CC_ZS (and:SI (match_dup 1) (match_dup 2))
30736
- (const_int 0)))]
30737
+ (clobber (reg:CC CC_REG))]
30738
""
30739
"@
30740
and\t%2, %0
30741
@@ -876,13 +1008,35 @@
30742
and\t%1, %0
30743
and\t%2, %1, %0
30744
and\t%Q2, %0"
30745
- [(set_attr "timings" "11,11,11,11,11,11,11,33,33")
30746
+ [(set_attr "timings" "11,11,11,11,11,11,11,11,33")
30747
+ (set_attr "length" "2,2,3,4,5,6,2,5,5")]
30748
+)
30749
+
30750
+(define_insn "*andsi3_flags"
30751
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
30752
+ (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
30753
+ (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
30754
+ (set (reg CC_REG)
30755
+ (compare (and:SI (match_dup 1) (match_dup 2))
30756
+ (const_int 0)))]
30757
+ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
30758
+ "@
30759
+ and\t%2, %0
30760
+ and\t%2, %0
30761
+ and\t%2, %0
30762
+ and\t%2, %0
30763
+ and\t%2, %0
30764
+ and\t%2, %0
30765
+ and\t%1, %0
30766
+ and\t%2, %1, %0
30767
+ and\t%Q2, %0"
30768
+ [(set_attr "timings" "11,11,11,11,11,11,11,11,33")
30769
(set_attr "length" "2,2,3,4,5,6,2,5,5")]
30770
)
30771
30772
;; Byte swap (single 32-bit value).
30773
(define_insn "bswapsi2"
30774
- [(set (match_operand:SI 0 "register_operand" "+r")
30775
+ [(set (match_operand:SI 0 "register_operand" "=r")
30776
(bswap:SI (match_operand:SI 1 "register_operand" "r")))]
30777
""
30778
"revl\t%1, %0"
30779
@@ -891,7 +1045,7 @@
30780
30781
;; Byte swap (single 16-bit value). Note - we ignore the swapping of the high 16-bits.
30782
(define_insn "bswaphi2"
30783
- [(set (match_operand:HI 0 "register_operand" "+r")
30784
+ [(set (match_operand:HI 0 "register_operand" "=r")
30785
(bswap:HI (match_operand:HI 1 "register_operand" "r")))]
30786
""
30787
"revw\t%1, %0"
30788
@@ -999,12 +1153,23 @@
30789
(define_insn "negsi2"
30790
[(set (match_operand:SI 0 "register_operand" "=r,r")
30791
(neg:SI (match_operand:SI 1 "register_operand" "0,r")))
30792
- (set (reg:CC CC_REG)
30793
- (compare:CC (neg:SI (match_dup 1))
30794
- (const_int 0)))]
30795
- ;; The NEG instruction does not comply with -fwrapv semantics.
30796
- ;; See gcc.c-torture/execute/pr22493-1.c for an example of this.
30797
- "! flag_wrapv"
30798
+ (clobber (reg:CC CC_REG))]
30799
+ ""
30800
+ "@
30801
+ neg\t%0
30802
+ neg\t%1, %0"
30803
+ [(set_attr "length" "2,3")]
30804
+)
30805
+
30806
+;; Note that the O and C flags are not set as per a normal compare,
30807
+;; and thus are unusable in that context.
30808
+(define_insn "*negsi2_flags"
30809
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
30810
+ (neg:SI (match_operand:SI 1 "register_operand" "0,r")))
30811
+ (set (reg CC_REG)
30812
+ (compare (neg:SI (match_dup 1))
30813
+ (const_int 0)))]
30814
+ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
30815
"@
30816
neg\t%0
30817
neg\t%1, %0"
30818
@@ -1014,9 +1179,7 @@
30819
(define_insn "one_cmplsi2"
30820
[(set (match_operand:SI 0 "register_operand" "=r,r")
30821
(not:SI (match_operand:SI 1 "register_operand" "0,r")))
30822
- (set (reg:CC_ZS CC_REG)
30823
- (compare:CC_ZS (not:SI (match_dup 1))
30824
- (const_int 0)))]
30825
+ (clobber (reg:CC CC_REG))]
30826
""
30827
"@
30828
not\t%0
30829
@@ -1024,13 +1187,24 @@
30830
[(set_attr "length" "2,3")]
30831
)
30832
30833
+(define_insn "*one_cmplsi2_flags"
30834
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
30835
+ (not:SI (match_operand:SI 1 "register_operand" "0,r")))
30836
+ (set (reg CC_REG)
30837
+ (compare (not:SI (match_dup 1))
30838
+ (const_int 0)))]
30839
+ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
30840
+ "@
30841
+ not\t%0
30842
+ not\t%1, %0"
30843
+ [(set_attr "length" "2,3")]
30844
+)
30845
+
30846
(define_insn "iorsi3"
30847
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
30848
(ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
30849
(match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
30850
- (set (reg:CC_ZS CC_REG)
30851
- (compare:CC_ZS (ior:SI (match_dup 1) (match_dup 2))
30852
- (const_int 0)))]
30853
+ (clobber (reg:CC CC_REG))]
30854
""
30855
"@
30856
or\t%2, %0
30857
@@ -1046,37 +1220,77 @@
30858
(set_attr "length" "2,2,3,4,5,6,2,3,5")]
30859
)
30860
30861
+(define_insn "*iorsi3_flags"
30862
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
30863
+ (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
30864
+ (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
30865
+ (set (reg CC_REG)
30866
+ (compare (ior:SI (match_dup 1) (match_dup 2))
30867
+ (const_int 0)))]
30868
+ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
30869
+ "@
30870
+ or\t%2, %0
30871
+ or\t%2, %0
30872
+ or\t%2, %0
30873
+ or\t%2, %0
30874
+ or\t%2, %0
30875
+ or\t%Q2, %0
30876
+ or\t%1, %0
30877
+ or\t%2, %1, %0
30878
+ or\t%Q2, %0"
30879
+ [(set_attr "timings" "11,11,11,11,11,11,11,11,33")
30880
+ (set_attr "length" "2,2,3,4,5,6,2,3,5")]
30881
+)
30882
+
30883
(define_insn "rotlsi3"
30884
[(set (match_operand:SI 0 "register_operand" "=r")
30885
(rotate:SI (match_operand:SI 1 "register_operand" "0")
30886
(match_operand:SI 2 "rx_shift_operand" "rn")))
30887
- (set (reg:CC_ZS CC_REG)
30888
- (compare:CC_ZS (rotate:SI (match_dup 1) (match_dup 2))
30889
- (const_int 0)))]
30890
+ (clobber (reg:CC CC_REG))]
30891
""
30892
"rotl\t%2, %0"
30893
[(set_attr "length" "3")]
30894
)
30895
30896
+(define_insn "*rotlsi3_flags"
30897
+ [(set (match_operand:SI 0 "register_operand" "=r")
30898
+ (rotate:SI (match_operand:SI 1 "register_operand" "0")
30899
+ (match_operand:SI 2 "rx_shift_operand" "rn")))
30900
+ (set (reg CC_REG)
30901
+ (compare (rotate:SI (match_dup 1) (match_dup 2))
30902
+ (const_int 0)))]
30903
+ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
30904
+ "rotl\t%2, %0"
30905
+ [(set_attr "length" "3")]
30906
+)
30907
+
30908
(define_insn "rotrsi3"
30909
[(set (match_operand:SI 0 "register_operand" "=r")
30910
(rotatert:SI (match_operand:SI 1 "register_operand" "0")
30911
(match_operand:SI 2 "rx_shift_operand" "rn")))
30912
- (set (reg:CC_ZS CC_REG)
30913
- (compare:CC_ZS (rotatert:SI (match_dup 1) (match_dup 2))
30914
- (const_int 0)))]
30915
+ (clobber (reg:CC CC_REG))]
30916
""
30917
"rotr\t%2, %0"
30918
[(set_attr "length" "3")]
30919
)
30920
30921
+(define_insn "*rotrsi3_flags"
30922
+ [(set (match_operand:SI 0 "register_operand" "=r")
30923
+ (rotatert:SI (match_operand:SI 1 "register_operand" "0")
30924
+ (match_operand:SI 2 "rx_shift_operand" "rn")))
30925
+ (set (reg CC_REG)
30926
+ (compare (rotatert:SI (match_dup 1) (match_dup 2))
30927
+ (const_int 0)))]
30928
+ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
30929
+ "rotr\t%2, %0"
30930
+ [(set_attr "length" "3")]
30931
+)
30932
+
30933
(define_insn "ashrsi3"
30934
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
30935
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
30936
(match_operand:SI 2 "rx_shift_operand" "r,n,n")))
30937
- (set (reg:CC_ZS CC_REG)
30938
- (compare:CC_ZS (ashiftrt:SI (match_dup 1) (match_dup 2))
30939
- (const_int 0)))]
30940
+ (clobber (reg:CC CC_REG))]
30941
""
30942
"@
30943
shar\t%2, %0
30944
@@ -1085,13 +1299,26 @@
30945
[(set_attr "length" "3,2,3")]
30946
)
30947
30948
+(define_insn "*ashrsi3_flags"
30949
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r")
30950
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
30951
+ (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
30952
+ (set (reg CC_REG)
30953
+ (compare (ashiftrt:SI (match_dup 1) (match_dup 2))
30954
+ (const_int 0)))]
30955
+ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
30956
+ "@
30957
+ shar\t%2, %0
30958
+ shar\t%2, %0
30959
+ shar\t%2, %1, %0"
30960
+ [(set_attr "length" "3,2,3")]
30961
+)
30962
+
30963
(define_insn "lshrsi3"
30964
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
30965
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
30966
(match_operand:SI 2 "rx_shift_operand" "r,n,n")))
30967
- (set (reg:CC_ZS CC_REG)
30968
- (compare:CC_ZS (lshiftrt:SI (match_dup 1) (match_dup 2))
30969
- (const_int 0)))]
30970
+ (clobber (reg:CC CC_REG))]
30971
""
30972
"@
30973
shlr\t%2, %0
30974
@@ -1100,13 +1327,26 @@
30975
[(set_attr "length" "3,2,3")]
30976
)
30977
30978
+(define_insn "*lshrsi3_flags"
30979
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r")
30980
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
30981
+ (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
30982
+ (set (reg CC_REG)
30983
+ (compare (lshiftrt:SI (match_dup 1) (match_dup 2))
30984
+ (const_int 0)))]
30985
+ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
30986
+ "@
30987
+ shlr\t%2, %0
30988
+ shlr\t%2, %0
30989
+ shlr\t%2, %1, %0"
30990
+ [(set_attr "length" "3,2,3")]
30991
+)
30992
+
30993
(define_insn "ashlsi3"
30994
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
30995
(ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
30996
(match_operand:SI 2 "rx_shift_operand" "r,n,n")))
30997
- (set (reg:CC_ZS CC_REG)
30998
- (compare:CC_ZS (ashift:SI (match_dup 1) (match_dup 2))
30999
- (const_int 0)))]
31000
+ (clobber (reg:CC CC_REG))]
31001
""
31002
"@
31003
shll\t%2, %0
31004
@@ -1115,16 +1355,57 @@
31005
[(set_attr "length" "3,2,3")]
31006
)
31007
31008
+(define_insn "*ashlsi3_flags"
31009
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r")
31010
+ (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
31011
+ (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
31012
+ (set (reg CC_REG)
31013
+ (compare (ashift:SI (match_dup 1) (match_dup 2))
31014
+ (const_int 0)))]
31015
+ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
31016
+ "@
31017
+ shll\t%2, %0
31018
+ shll\t%2, %0
31019
+ shll\t%2, %1, %0"
31020
+ [(set_attr "length" "3,2,3")]
31021
+)
31022
+
31023
+;; Saturate to 32-bits
31024
+(define_insn_and_split "ssaddsi3"
31025
+ [(set (match_operand:SI 0 "register_operand" "=r")
31026
+ (ss_plus:SI (match_operand:SI 1 "register_operand" "r")
31027
+ (match_operand:SI 2 "rx_source_operand" "riQ")))
31028
+ (clobber (reg:CC CC_REG))]
31029
+ ""
31030
+ "#"
31031
+ "reload_completed"
31032
+ [(parallel [(set (match_dup 0)
31033
+ (plus:SI (match_dup 1) (match_dup 2)))
31034
+ (set (reg:CC_ZSC CC_REG)
31035
+ (compare:CC_ZSC
31036
+ (plus:SI (match_dup 1) (match_dup 2))
31037
+ (const_int 0)))])
31038
+ (set (match_dup 0)
31039
+ (unspec:SI [(match_dup 0) (reg:CC CC_REG)]
31040
+ UNSPEC_BUILTIN_SAT))]
31041
+ ""
31042
+)
31043
+
31044
+(define_insn "*sat"
31045
+ [(set (match_operand:SI 0 "register_operand" "=r")
31046
+ (unspec:SI [(match_operand:SI 1 "register_operand" "0")
31047
+ (reg:CC CC_REG)]
31048
+ UNSPEC_BUILTIN_SAT))]
31049
+ "reload_completed"
31050
+ "sat\t%0"
31051
+ [(set_attr "length" "2")]
31052
+)
31053
+
31054
(define_insn "subsi3"
31055
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
31056
(minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0")
31057
(match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q")))
31058
- (set (reg:CC_ZSC CC_REG)
31059
- ;; Note - we do not acknowledge that the SUB instruction sets the Overflow
31060
- ;; flag because its interpretation is different from comparing the result
31061
- ;; against zero. Compile and run gcc.c-torture/execute/cmpsi-1.c to see this.
31062
- (compare:CC_ZSC (minus:SI (match_dup 1) (match_dup 2))
31063
- (const_int 0)))]
31064
+ (clobber (reg:CC CC_REG))]
31065
""
31066
"@
31067
sub\t%2, %0
31068
@@ -1136,32 +1417,267 @@
31069
(set_attr "length" "2,2,6,3,5")]
31070
)
31071
31072
-(define_insn "subdi3"
31073
- [(set (match_operand:DI 0 "register_operand" "=r,r")
31074
- (minus:DI (match_operand:DI 1 "register_operand" "0,0")
31075
- (match_operand:DI 2 "rx_source_operand" "r,Q")))
31076
- (set (reg:CC_ZSC CC_REG) ;; See subsi3
31077
- (compare:CC_ZSC (minus:DI (match_dup 1) (match_dup 2))
31078
- (const_int 0)))]
31079
- ""
31080
- "sub\t%L2, %L0\n\tsbb\t%H2, %H0"
31081
- [(set_attr "timings" "22,44")
31082
- (set_attr "length" "5,11")]
31083
+;; Note that the O flag is set as if (compare op1 op2) not for
31084
+;; what is described here, (compare op0 0).
31085
+(define_insn "*subsi3_flags"
31086
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
31087
+ (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0")
31088
+ (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q")))
31089
+ (set (reg CC_REG)
31090
+ (compare (minus:SI (match_dup 1) (match_dup 2))
31091
+ (const_int 0)))]
31092
+ "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
31093
+ "@
31094
+ sub\t%2, %0
31095
+ sub\t%2, %0
31096
+ add\t%N2, %0
31097
+ sub\t%2, %1, %0
31098
+ sub\t%Q2, %0"
31099
+ [(set_attr "timings" "11,11,11,11,33")
31100
+ (set_attr "length" "2,2,6,3,5")]
31101
)
31102
31103
+;; A helper to expand the above with the CC_MODE filled in.
31104
+(define_expand "subsi3_flags"
31105
+ [(parallel [(set (match_operand:SI 0 "register_operand")
31106
+ (minus:SI (match_operand:SI 1 "register_operand")
31107
+ (match_operand:SI 2 "rx_source_operand")))
31108
+ (set (reg:CC_ZSC CC_REG)
31109
+ (compare:CC_ZSC (minus:SI (match_dup 1) (match_dup 2))
31110
+ (const_int 0)))])]
31111
+)
31112
+
31113
+(define_insn "sbb_internal"
31114
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
31115
+ (minus:SI
31116
+ (minus:SI
31117
+ (match_operand:SI 1 "register_operand" " 0,0")
31118
+ (match_operand:SI 2 "rx_compare_operand" " r,Q"))
31119
+ (geu:SI (reg:CC CC_REG) (const_int 0))))
31120
+ (clobber (reg:CC CC_REG))]
31121
+ "reload_completed"
31122
+ "sbb\t%2, %0"
31123
+ [(set_attr "timings" "11,33")
31124
+ (set_attr "length" "3,6")]
31125
+)
31126
+
31127
+(define_insn "*sbb_flags"
31128
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
31129
+ (minus:SI
31130
+ (minus:SI
31131
+ (match_operand:SI 1 "register_operand" " 0,0")
31132
+ (match_operand:SI 2 "rx_compare_operand" " r,Q"))
31133
+ (geu:SI (reg:CC CC_REG) (const_int 0))))
31134
+ (set (reg CC_REG)
31135
+ (compare
31136
+ (minus:SI
31137
+ (minus:SI (match_dup 1) (match_dup 2))
31138
+ (geu:SI (reg:CC CC_REG) (const_int 0)))
31139
+ (const_int 0)))]
31140
+ "reload_completed"
31141
+ "sbb\t%2, %0"
31142
+ [(set_attr "timings" "11,33")
31143
+ (set_attr "length" "3,6")]
31144
+)
31145
+
31146
+(define_expand "subdi3"
31147
+ [(set (match_operand:DI 0 "register_operand")
31148
+ (minus:DI (match_operand:DI 1 "register_operand")
31149
+ (match_operand:DI 2 "rx_compare_operand")))]
31150
+ ""
31151
+{
31152
+ rtx op0l, op0h, op1l, op1h, op2l, op2h;
31153
+
31154
+ op0l = gen_lowpart (SImode, operands[0]);
31155
+ op1l = gen_lowpart (SImode, operands[1]);
31156
+ op2l = gen_lowpart (SImode, operands[2]);
31157
+ op0h = gen_highpart (SImode, operands[0]);
31158
+ op1h = gen_highpart (SImode, operands[1]);
31159
+ op2h = gen_highpart_mode (SImode, DImode, operands[2]);
31160
+
31161
+ emit_insn (gen_subdi3_internal (op0l, op0h, op1l, op2l, op1h, op2h));
31162
+ DONE;
31163
+})
31164
+
31165
+(define_insn_and_split "subdi3_internal"
31166
+ [(set (match_operand:SI 0 "register_operand" "=&r,&r")
31167
+ (minus:SI (match_operand:SI 2 "register_operand" " 0, r")
31168
+ (match_operand:SI 3 "rx_compare_operand" "rQ, r")))
31169
+ (set (match_operand:SI 1 "register_operand" "= r, r")
31170
+ (minus:SI
31171
+ (minus:SI
31172
+ (match_operand:SI 4 "register_operand" " 1, 1")
31173
+ (match_operand:SI 5 "rx_compare_operand" " rQ,rQ"))
31174
+ (geu:SI (match_dup 2) (match_dup 3))))
31175
+ (clobber (reg:CC CC_REG))]
31176
+ ""
31177
+ "#"
31178
+ "reload_completed"
31179
+ [(const_int 0)]
31180
+{
31181
+ emit_insn (gen_subsi3_flags (operands[0], operands[2], operands[3]));
31182
+ emit_insn (gen_sbb_internal (operands[1], operands[4], operands[5]));
31183
+ DONE;
31184
+})
31185
+
31186
(define_insn "xorsi3"
31187
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
31188
(xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
31189
(match_operand:SI 2 "rx_source_operand"
31190
"r,Sint08,Sint16,Sint24,i,Q")))
31191
- (set (reg:CC_ZS CC_REG)
31192
- (compare:CC_ZS (xor:SI (match_dup 1) (match_dup 2))
31193
- (const_int 0)))]
31194
+ (clobber (reg:CC CC_REG))]
31195
""
31196
"xor\t%Q2, %0"
31197
[(set_attr "timings" "11,11,11,11,11,33")
31198
(set_attr "length" "3,4,5,6,7,6")]
31199
)
31200
+
31201
+(define_insn "*xorsi3_flags"
31202
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
31203
+ (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
31204
+ (match_operand:SI 2 "rx_source_operand"
31205
+ "r,Sint08,Sint16,Sint24,i,Q")))
31206
+ (set (reg CC_REG)
31207
+ (compare (xor:SI (match_dup 1) (match_dup 2))
31208
+ (const_int 0)))]
31209
+ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
31210
+ "xor\t%Q2, %0"
31211
+ [(set_attr "timings" "11,11,11,11,11,33")
31212
+ (set_attr "length" "3,4,5,6,7,6")]
31213
+)
31214
+
31215
+;; A set of peepholes to catch extending loads followed by arithmetic operations.
31216
+;; We use iterators where possible to reduce the amount of typing and hence the
31217
+;; possibilities for typos.
31218
+
31219
+(define_code_iterator extend_types [(zero_extend "") (sign_extend "")])
31220
+(define_code_attr letter [(zero_extend "R") (sign_extend "Q")])
31221
+
31222
+(define_code_iterator memex_commutative [(plus "") (and "") (ior "") (xor "")])
31223
+(define_code_iterator memex_noncomm [(div "") (udiv "") (minus "")])
31224
+(define_code_iterator memex_nocc [(smax "") (smin "") (mult "")])
31225
+
31226
+(define_code_attr op [(plus "add") (and "and") (div "div") (udiv "divu") (smax "max") (smin "min") (mult "mul") (ior "or") (minus "sub") (xor "xor")])
31227
+
31228
+(define_peephole2
31229
+ [(set (match_operand:SI 0 "register_operand")
31230
+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
31231
+ (parallel [(set (match_operand:SI 2 "register_operand")
31232
+ (memex_commutative:SI (match_dup 0)
31233
+ (match_dup 2)))
31234
+ (clobber (reg:CC CC_REG))])]
31235
+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
31236
+ [(parallel [(set:SI (match_dup 2)
31237
+ (memex_commutative:SI (match_dup 2)
31238
+ (extend_types:SI (match_dup 1))))
31239
+ (clobber (reg:CC CC_REG))])]
31240
+)
31241
+
31242
+(define_peephole2
31243
+ [(set (match_operand:SI 0 "register_operand")
31244
+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
31245
+ (parallel [(set (match_operand:SI 2 "register_operand")
31246
+ (memex_commutative:SI (match_dup 2)
31247
+ (match_dup 0)))
31248
+ (clobber (reg:CC CC_REG))])]
31249
+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
31250
+ [(parallel [(set:SI (match_dup 2)
31251
+ (memex_commutative:SI (match_dup 2)
31252
+ (extend_types:SI (match_dup 1))))
31253
+ (clobber (reg:CC CC_REG))])]
31254
+)
31255
+
31256
+(define_peephole2
31257
+ [(set (match_operand:SI 0 "register_operand")
31258
+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
31259
+ (parallel [(set (match_operand:SI 2 "register_operand")
31260
+ (memex_noncomm:SI (match_dup 2)
31261
+ (match_dup 0)))
31262
+ (clobber (reg:CC CC_REG))])]
31263
+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
31264
+ [(parallel [(set:SI (match_dup 2)
31265
+ (memex_noncomm:SI (match_dup 2)
31266
+ (extend_types:SI (match_dup 1))))
31267
+ (clobber (reg:CC CC_REG))])]
31268
+)
31269
+
31270
+(define_peephole2
31271
+ [(set (match_operand:SI 0 "register_operand")
31272
+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
31273
+ (set (match_operand:SI 2 "register_operand")
31274
+ (memex_nocc:SI (match_dup 0)
31275
+ (match_dup 2)))]
31276
+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
31277
+ [(set:SI (match_dup 2)
31278
+ (memex_nocc:SI (match_dup 2)
31279
+ (extend_types:SI (match_dup 1))))]
31280
+)
31281
+
31282
+(define_peephole2
31283
+ [(set (match_operand:SI 0 "register_operand")
31284
+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
31285
+ (set (match_operand:SI 2 "register_operand")
31286
+ (memex_nocc:SI (match_dup 2)
31287
+ (match_dup 0)))]
31288
+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
31289
+ [(set:SI (match_dup 2)
31290
+ (memex_nocc:SI (match_dup 2)
31291
+ (extend_types:SI (match_dup 1))))]
31292
+)
31293
+
31294
+(define_insn "*<memex_commutative:code>si3_<extend_types:code><small_int_modes:mode>"
31295
+ [(set (match_operand:SI 0 "register_operand" "=r")
31296
+ (memex_commutative:SI (match_operand:SI 1 "register_operand" "%0")
31297
+ (extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))
31298
+ (clobber (reg:CC CC_REG))]
31299
+ ""
31300
+ "<memex_commutative:op>\t%<extend_types:letter>2, %0"
31301
+ [(set_attr "timings" "33")
31302
+ (set_attr "length" "5")] ;; Worst case sceanario. FIXME: If we defined separate patterns
31303
+) ;; rather than using iterators we could specify exact sizes.
31304
+
31305
+(define_insn "*<memex_noncomm:code>si3_<extend_types:code><small_int_modes:mode>"
31306
+ [(set (match_operand:SI 0 "register_operand" "=r")
31307
+ (memex_noncomm:SI (match_operand:SI 1 "register_operand" "0")
31308
+ (extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))
31309
+ (clobber (reg:CC CC_REG))]
31310
+ ""
31311
+ "<memex_noncomm:op>\t%<extend_types:letter>2, %0"
31312
+ [(set_attr "timings" "33")
31313
+ (set_attr "length" "5")] ;; Worst case sceanario. FIXME: If we defined separate patterns
31314
+) ;; rather than using iterators we could specify exact sizes.
31315
+
31316
+(define_insn "*<memex_nocc:code>si3_<extend_types:code><small_int_modes:mode>"
31317
+ [(set (match_operand:SI 0 "register_operand" "=r")
31318
+ (memex_nocc:SI (match_operand:SI 1 "register_operand" "%0")
31319
+ (extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))]
31320
+ ""
31321
+ "<memex_nocc:op>\t%<extend_types:letter>2, %0"
31322
+ [(set_attr "timings" "33")
31323
+ (set_attr "length" "5")] ;; Worst case sceanario. FIXME: If we defined separate patterns
31324
+) ;; rather than using iterators we could specify exact sizes.
31325
+
31326
+(define_peephole2
31327
+ [(set (match_operand:SI 0 "register_operand")
31328
+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
31329
+ (set (reg:CC CC_REG)
31330
+ (compare:CC (match_operand:SI 2 "register_operand")
31331
+ (match_dup 0)))]
31332
+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
31333
+ [(set (reg:CC CC_REG)
31334
+ (compare:CC (match_dup 2)
31335
+ (extend_types:SI (match_dup 1))))]
31336
+)
31337
+
31338
+(define_insn "*comparesi3_<extend_types:code><small_int_modes:mode>"
31339
+ [(set (reg:CC CC_REG)
31340
+ (compare:CC (match_operand:SI 0 "register_operand" "=r")
31341
+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand" "Q"))))]
31342
+ ""
31343
+ "cmp\t%<extend_types:letter>1, %0"
31344
+ [(set_attr "timings" "33")
31345
+ (set_attr "length" "5")] ;; Worst case sceanario. FIXME: If we defined separate patterns
31346
+) ;; rather than using iterators we could specify exact sizes.
31347
31348
;; Floating Point Instructions
31349
31350
@@ -1169,9 +1685,7 @@
31351
[(set (match_operand:SF 0 "register_operand" "=r,r,r")
31352
(plus:SF (match_operand:SF 1 "register_operand" "%0,0,0")
31353
(match_operand:SF 2 "rx_source_operand" "r,F,Q")))
31354
- (set (reg:CC_ZS CC_REG)
31355
- (compare:CC_ZS (plus:SF (match_dup 1) (match_dup 2))
31356
- (const_int 0)))]
31357
+ (clobber (reg:CC CC_REG))]
31358
"ALLOW_RX_FPU_INSNS"
31359
"fadd\t%2, %0"
31360
[(set_attr "timings" "44,44,66")
31361
@@ -1182,9 +1696,7 @@
31362
[(set (match_operand:SF 0 "register_operand" "=r,r,r")
31363
(div:SF (match_operand:SF 1 "register_operand" "0,0,0")
31364
(match_operand:SF 2 "rx_source_operand" "r,F,Q")))
31365
- (set (reg:CC_ZS CC_REG)
31366
- (compare:CC_ZS (div:SF (match_dup 1) (match_dup 2))
31367
- (const_int 0)))]
31368
+ (clobber (reg:CC CC_REG))]
31369
"ALLOW_RX_FPU_INSNS"
31370
"fdiv\t%2, %0"
31371
[(set_attr "timings" "1616,1616,1818")
31372
@@ -1195,9 +1707,7 @@
31373
[(set (match_operand:SF 0 "register_operand" "=r,r,r")
31374
(mult:SF (match_operand:SF 1 "register_operand" "%0,0,0")
31375
(match_operand:SF 2 "rx_source_operand" "r,F,Q")))
31376
- (set (reg:CC_ZS CC_REG)
31377
- (compare:CC_ZS (mult:SF (match_dup 1) (match_dup 2))
31378
- (const_int 0)))]
31379
+ (clobber (reg:CC CC_REG))]
31380
"ALLOW_RX_FPU_INSNS"
31381
"fmul\t%2, %0"
31382
[(set_attr "timings" "33,33,55")
31383
@@ -1208,9 +1718,7 @@
31384
[(set (match_operand:SF 0 "register_operand" "=r,r,r")
31385
(minus:SF (match_operand:SF 1 "register_operand" "0,0,0")
31386
(match_operand:SF 2 "rx_source_operand" "r,F,Q")))
31387
- (set (reg:CC_ZS CC_REG)
31388
- (compare:CC_ZS (minus:SF (match_dup 1) (match_dup 2))
31389
- (const_int 0)))]
31390
+ (clobber (reg:CC CC_REG))]
31391
"ALLOW_RX_FPU_INSNS"
31392
"fsub\t%Q2, %0"
31393
[(set_attr "timings" "44,44,66")
31394
@@ -1220,9 +1728,7 @@
31395
(define_insn "fix_truncsfsi2"
31396
[(set (match_operand:SI 0 "register_operand" "=r,r")
31397
(fix:SI (match_operand:SF 1 "rx_compare_operand" "r,Q")))
31398
- (set (reg:CC_ZS CC_REG)
31399
- (compare:CC_ZS (fix:SI (match_dup 1))
31400
- (const_int 0)))]
31401
+ (clobber (reg:CC CC_REG))]
31402
"ALLOW_RX_FPU_INSNS"
31403
"ftoi\t%Q1, %0"
31404
[(set_attr "timings" "22,44")
31405
@@ -1232,9 +1738,7 @@
31406
(define_insn "floatsisf2"
31407
[(set (match_operand:SF 0 "register_operand" "=r,r")
31408
(float:SF (match_operand:SI 1 "rx_compare_operand" "r,Q")))
31409
- (set (reg:CC_ZS CC_REG)
31410
- (compare:CC_ZS (float:SF (match_dup 1))
31411
- (const_int 0)))]
31412
+ (clobber (reg:CC CC_REG))]
31413
"ALLOW_RX_FPU_INSNS"
31414
"itof\t%Q1, %0"
31415
[(set_attr "timings" "22,44")
31416
@@ -1242,217 +1746,216 @@
31417
)
31418
31419
;; Bit manipulation instructions.
31420
-;; Note - there are two versions of each pattern because the memory
31421
-;; accessing versions use QImode whilst the register accessing
31422
-;; versions use SImode.
31423
-;; The peephole are here because the combiner only looks at a maximum
31424
-;; of three instructions at a time.
31425
31426
-(define_insn "bitset"
31427
- [(set:SI (match_operand:SI 0 "register_operand" "=r")
31428
- (ior:SI (match_operand:SI 1 "register_operand" "0")
31429
- (ashift:SI (const_int 1)
31430
- (match_operand:SI 2 "nonmemory_operand" "ri"))))]
31431
+;; ??? The *_in_memory patterns will not be matched without further help.
31432
+;; At one time we had the insv expander generate them, but I suspect that
31433
+;; in general we get better performance by exposing the register load to
31434
+;; the optimizers.
31435
+;;
31436
+;; An alternate solution would be to re-organize these patterns such
31437
+;; that allow both register and memory operands. This would allow the
31438
+;; register allocator to spill and not load the register operand. This
31439
+;; would be possible only for operations for which we have a constant
31440
+;; bit offset, so that we can adjust the address by ofs/8 and replace
31441
+;; the offset in the insn by ofs%8.
31442
+
31443
+(define_insn "*bitset"
31444
+ [(set (match_operand:SI 0 "register_operand" "=r")
31445
+ (ior:SI (ashift:SI (const_int 1)
31446
+ (match_operand:SI 1 "rx_shift_operand" "ri"))
31447
+ (match_operand:SI 2 "register_operand" "0")))]
31448
""
31449
- "bset\t%2, %0"
31450
+ "bset\t%1, %0"
31451
[(set_attr "length" "3")]
31452
)
31453
31454
-(define_insn "bitset_in_memory"
31455
- [(set:QI (match_operand:QI 0 "memory_operand" "=m")
31456
- (ior:QI (match_operand:QI 1 "memory_operand" "0")
31457
- (ashift:QI (const_int 1)
31458
- (match_operand:QI 2 "nonmemory_operand" "ri"))))]
31459
+(define_insn "*bitset_in_memory"
31460
+ [(set (match_operand:QI 0 "memory_operand" "+Q")
31461
+ (ior:QI (ashift:QI (const_int 1)
31462
+ (match_operand:QI 1 "nonmemory_operand" "ri"))
31463
+ (match_dup 0)))]
31464
""
31465
- "bset\t%2, %0.B"
31466
+ "bset\t%1, %0.B"
31467
[(set_attr "length" "3")
31468
- (set_attr "timings" "34")]
31469
+ (set_attr "timings" "33")]
31470
)
31471
31472
-;; (set (reg A) (const_int 1))
31473
-;; (set (reg A) (ashift (reg A) (reg B)))
31474
-;; (set (reg C) (ior (reg A) (reg C)))
31475
-(define_peephole2
31476
- [(set:SI (match_operand:SI 0 "register_operand" "")
31477
- (const_int 1))
31478
- (set:SI (match_dup 0)
31479
- (ashift:SI (match_dup 0)
31480
- (match_operand:SI 1 "register_operand" "")))
31481
- (set:SI (match_operand:SI 2 "register_operand" "")
31482
- (ior:SI (match_dup 0)
31483
- (match_dup 2)))]
31484
- "dead_or_set_p (insn, operands[0])"
31485
- [(set:SI (match_dup 2)
31486
- (ior:SI (match_dup 2)
31487
- (ashift:SI (const_int 1)
31488
- (match_dup 1))))]
31489
-)
31490
-
31491
-;; (set (reg A) (const_int 1))
31492
-;; (set (reg A) (ashift (reg A) (reg B)))
31493
-;; (set (reg A) (ior (reg A) (reg C)))
31494
-;; (set (reg C) (reg A)
31495
-(define_peephole2
31496
- [(set:SI (match_operand:SI 0 "register_operand" "")
31497
- (const_int 1))
31498
- (set:SI (match_dup 0)
31499
- (ashift:SI (match_dup 0)
31500
- (match_operand:SI 1 "register_operand" "")))
31501
- (set:SI (match_dup 0)
31502
- (ior:SI (match_dup 0)
31503
- (match_operand:SI 2 "register_operand" "")))
31504
- (set:SI (match_dup 2) (match_dup 0))]
31505
- "dead_or_set_p (insn, operands[0])"
31506
- [(set:SI (match_dup 2)
31507
- (ior:SI (match_dup 2)
31508
- (ashift:SI (const_int 1)
31509
- (match_dup 1))))]
31510
-)
31511
-
31512
-(define_insn "bitinvert"
31513
- [(set:SI (match_operand:SI 0 "register_operand" "+r")
31514
- (xor:SI (match_operand:SI 1 "register_operand" "0")
31515
- (ashift:SI (const_int 1)
31516
- (match_operand:SI 2 "nonmemory_operand" "ri"))))]
31517
+(define_insn "*bitinvert"
31518
+ [(set (match_operand:SI 0 "register_operand" "=r")
31519
+ (xor:SI (ashift:SI (const_int 1)
31520
+ (match_operand:SI 1 "rx_shift_operand" "ri"))
31521
+ (match_operand:SI 2 "register_operand" "0")))]
31522
""
31523
- "bnot\t%2, %0"
31524
+ "bnot\t%1, %0"
31525
[(set_attr "length" "3")]
31526
)
31527
31528
-(define_insn "bitinvert_in_memory"
31529
- [(set:QI (match_operand:QI 0 "memory_operand" "+m")
31530
- (xor:QI (match_operand:QI 1 "register_operand" "0")
31531
- (ashift:QI (const_int 1)
31532
- (match_operand:QI 2 "nonmemory_operand" "ri"))))]
31533
+(define_insn "*bitinvert_in_memory"
31534
+ [(set (match_operand:QI 0 "memory_operand" "+Q")
31535
+ (xor:QI (ashift:QI (const_int 1)
31536
+ (match_operand:QI 1 "nonmemory_operand" "ri"))
31537
+ (match_dup 0)))]
31538
""
31539
- "bnot\t%2, %0.B"
31540
+ "bnot\t%1, %0.B"
31541
[(set_attr "length" "5")
31542
(set_attr "timings" "33")]
31543
)
31544
31545
-;; (set (reg A) (const_int 1))
31546
-;; (set (reg A) (ashift (reg A) (reg B)))
31547
-;; (set (reg C) (xor (reg A) (reg C)))
31548
-(define_peephole2
31549
- [(set:SI (match_operand:SI 0 "register_operand" "")
31550
- (const_int 1))
31551
- (set:SI (match_dup 0)
31552
- (ashift:SI (match_dup 0)
31553
- (match_operand:SI 1 "register_operand" "")))
31554
- (set:SI (match_operand:SI 2 "register_operand" "")
31555
- (xor:SI (match_dup 0)
31556
- (match_dup 2)))]
31557
- "dead_or_set_p (insn, operands[0])"
31558
- [(set:SI (match_dup 2)
31559
- (xor:SI (match_dup 2)
31560
- (ashift:SI (const_int 1)
31561
- (match_dup 1))))]
31562
+(define_insn "*bitclr"
31563
+ [(set (match_operand:SI 0 "register_operand" "=r")
31564
+ (and:SI (not:SI
31565
+ (ashift:SI
31566
+ (const_int 1)
31567
+ (match_operand:SI 1 "rx_shift_operand" "ri")))
31568
+ (match_operand:SI 2 "register_operand" "0")))]
31569
""
31570
+ "bclr\t%1, %0"
31571
+ [(set_attr "length" "3")]
31572
)
31573
-
31574
-;; (set (reg A) (const_int 1))
31575
-;; (set (reg A) (ashift (reg A) (reg B)))
31576
-;; (set (reg A) (xor (reg A) (reg C)))
31577
-;; (set (reg C) (reg A))
31578
-(define_peephole2
31579
- [(set:SI (match_operand:SI 0 "register_operand" "")
31580
- (const_int 1))
31581
- (set:SI (match_dup 0)
31582
- (ashift:SI (match_dup 0)
31583
- (match_operand:SI 1 "register_operand" "")))
31584
- (set:SI (match_dup 0)
31585
- (xor:SI (match_dup 0)
31586
- (match_operand:SI 2 "register_operand" "")))
31587
- (set:SI (match_dup 2) (match_dup 0))]
31588
- "dead_or_set_p (insn, operands[0])"
31589
- [(set:SI (match_dup 2)
31590
- (xor:SI (match_dup 2)
31591
- (ashift:SI (const_int 1)
31592
- (match_dup 1))))]
31593
+
31594
+(define_insn "*bitclr_in_memory"
31595
+ [(set (match_operand:QI 0 "memory_operand" "+Q")
31596
+ (and:QI (not:QI
31597
+ (ashift:QI
31598
+ (const_int 1)
31599
+ (match_operand:QI 1 "nonmemory_operand" "ri")))
31600
+ (match_dup 0)))]
31601
""
31602
+ "bclr\t%1, %0.B"
31603
+ [(set_attr "length" "3")
31604
+ (set_attr "timings" "33")]
31605
)
31606
31607
-(define_insn "bitclr"
31608
- [(set:SI (match_operand:SI 0 "register_operand" "+r")
31609
- (and:SI (match_operand:SI 1 "register_operand" "0")
31610
- (not:SI (ashift:SI (const_int 1)
31611
- (match_operand:SI 2 "nonmemory_operand" "ri")))))]
31612
- ""
31613
- "bclr\t%2, %0"
31614
+(define_insn "*insv_imm"
31615
+ [(set (zero_extract:SI
31616
+ (match_operand:SI 0 "register_operand" "+r")
31617
+ (const_int 1)
31618
+ (match_operand:SI 1 "rx_shift_operand" "ri"))
31619
+ (match_operand:SI 2 "const_int_operand" ""))]
31620
+ ""
31621
+{
31622
+ if (INTVAL (operands[2]) & 1)
31623
+ return "bset\t%1, %0";
31624
+ else
31625
+ return "bclr\t%1, %0";
31626
+}
31627
[(set_attr "length" "3")]
31628
)
31629
31630
-(define_insn "bitclr_in_memory"
31631
- [(set:QI (match_operand:QI 0 "memory_operand" "+m")
31632
- (and:QI (match_operand:QI 1 "memory_operand" "0")
31633
- (not:QI (ashift:QI (const_int 1)
31634
- (match_operand:QI 2 "nonmemory_operand" "ri")))))]
31635
+(define_insn_and_split "rx_insv_reg"
31636
+ [(set (zero_extract:SI
31637
+ (match_operand:SI 0 "register_operand" "+r")
31638
+ (const_int 1)
31639
+ (match_operand:SI 1 "const_int_operand" ""))
31640
+ (match_operand:SI 2 "register_operand" "r"))
31641
+ (clobber (reg:CC CC_REG))]
31642
""
31643
- "bclr\t%2, %0.B"
31644
- [(set_attr "length" "3")
31645
- (set_attr "timings" "34")]
31646
+ "#"
31647
+ "reload_completed"
31648
+ [(set (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1))
31649
+ (match_dup 3))]
31650
+{
31651
+ rtx flags, x;
31652
+
31653
+ /* Emit tst #1, op2. */
31654
+ flags = gen_rtx_REG (CC_ZSmode, CC_REG);
31655
+ x = gen_rtx_AND (SImode, operands[2], const1_rtx);
31656
+ x = gen_rtx_COMPARE (CC_ZSmode, x, const0_rtx);
31657
+ x = gen_rtx_SET (VOIDmode, flags, x);
31658
+ emit_insn (x);
31659
+
31660
+ /* Emit bmne. */
31661
+ operands[3] = gen_rtx_NE (SImode, flags, const0_rtx);
31662
+})
31663
+
31664
+(define_insn_and_split "*insv_cond"
31665
+ [(set (zero_extract:SI
31666
+ (match_operand:SI 0 "register_operand" "+r")
31667
+ (const_int 1)
31668
+ (match_operand:SI 1 "const_int_operand" ""))
31669
+ (match_operator:SI 4 "comparison_operator"
31670
+ [(match_operand:SI 2 "register_operand" "r")
31671
+ (match_operand:SI 3 "rx_source_operand" "riQ")]))
31672
+ (clobber (reg:CC CC_REG))]
31673
+ ""
31674
+ "#"
31675
+ "reload_completed"
31676
+ [(set (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1))
31677
+ (match_dup 4))]
31678
+{
31679
+ rtx flags, x;
31680
+
31681
+ flags = gen_rtx_REG (CCmode, CC_REG);
31682
+ x = gen_rtx_COMPARE (CCmode, operands[2], operands[3]);
31683
+ x = gen_rtx_SET (VOIDmode, flags, x);
31684
+ emit_insn (x);
31685
+
31686
+ operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
31687
+ flags, const0_rtx);
31688
+})
31689
+
31690
+(define_insn "*bmcc"
31691
+ [(set (zero_extract:SI
31692
+ (match_operand:SI 0 "register_operand" "+r")
31693
+ (const_int 1)
31694
+ (match_operand:SI 1 "const_int_operand" ""))
31695
+ (match_operator:SI 2 "comparison_operator"
31696
+ [(reg CC_REG) (const_int 0)]))]
31697
+ "reload_completed"
31698
+ "bm%B2\t%1, %0"
31699
+ [(set_attr "length" "3")]
31700
)
31701
31702
-;; (set (reg A) (const_int -2))
31703
-;; (set (reg A) (rotate (reg A) (reg B)))
31704
-;; (set (reg C) (and (reg A) (reg C)))
31705
-(define_peephole2
31706
- [(set:SI (match_operand:SI 0 "register_operand" "")
31707
- (const_int -2))
31708
- (set:SI (match_dup 0)
31709
- (rotate:SI (match_dup 0)
31710
- (match_operand:SI 1 "register_operand" "")))
31711
- (set:SI (match_operand:SI 2 "register_operand" "")
31712
- (and:SI (match_dup 0)
31713
- (match_dup 2)))]
31714
- "dead_or_set_p (insn, operands[0])"
31715
- [(set:SI (match_dup 2)
31716
- (and:SI (match_dup 2)
31717
- (not:SI (ashift:SI (const_int 1)
31718
- (match_dup 1)))))]
31719
-)
31720
-
31721
-;; (set (reg A) (const_int -2))
31722
-;; (set (reg A) (rotate (reg A) (reg B)))
31723
-;; (set (reg A) (and (reg A) (reg C)))
31724
-;; (set (reg C) (reg A)
31725
-(define_peephole2
31726
- [(set:SI (match_operand:SI 0 "register_operand" "")
31727
- (const_int -2))
31728
- (set:SI (match_dup 0)
31729
- (rotate:SI (match_dup 0)
31730
- (match_operand:SI 1 "register_operand" "")))
31731
- (set:SI (match_dup 0)
31732
- (and:SI (match_dup 0)
31733
- (match_operand:SI 2 "register_operand" "")))
31734
- (set:SI (match_dup 2) (match_dup 0))]
31735
- "dead_or_set_p (insn, operands[0])"
31736
- [(set:SI (match_dup 2)
31737
- (and:SI (match_dup 2)
31738
- (not:SI (ashift:SI (const_int 1)
31739
- (match_dup 1)))))]
31740
+;; Work around the fact that X=Y<0 is preferentially expanded as a shift.
31741
+(define_insn_and_split "*insv_cond_lt"
31742
+ [(set (zero_extract:SI
31743
+ (match_operand:SI 0 "register_operand" "+r")
31744
+ (const_int 1)
31745
+ (match_operand:SI 1 "const_int_operand" ""))
31746
+ (match_operator:SI 3 "rshift_operator"
31747
+ [(match_operand:SI 2 "register_operand" "r")
31748
+ (const_int 31)]))
31749
+ (clobber (reg:CC CC_REG))]
31750
+ ""
31751
+ "#"
31752
+ ""
31753
+ [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1))
31754
+ (lt:SI (match_dup 2) (const_int 0)))
31755
+ (clobber (reg:CC CC_REG))])]
31756
+ ""
31757
)
31758
31759
(define_expand "insv"
31760
- [(set:SI (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand") ;; Destination
31761
- (match_operand 1 "immediate_operand") ;; # of bits to set
31762
- (match_operand 2 "immediate_operand")) ;; Starting bit
31763
- (match_operand 3 "immediate_operand"))] ;; Bits to insert
31764
- ""
31765
- {
31766
- if (rx_expand_insv (operands))
31767
+ [(set (zero_extract:SI
31768
+ (match_operand:SI 0 "register_operand") ;; Destination
31769
+ (match_operand:SI 1 "const_int_operand") ;; # of bits to set
31770
+ (match_operand:SI 2 "nonmemory_operand")) ;; Starting bit
31771
+ (match_operand:SI 3 "nonmemory_operand"))] ;; Bits to insert
31772
+ ""
31773
+{
31774
+ /* We only handle single-bit inserts. */
31775
+ if (!CONST_INT_P (operands[1]) || INTVAL (operands[1]) != 1)
31776
+ FAIL;
31777
+
31778
+ /* Either the bit to insert or the position must be constant. */
31779
+ if (CONST_INT_P (operands[3]))
31780
+ operands[3] = GEN_INT (INTVAL (operands[3]) & 1);
31781
+ else if (CONST_INT_P (operands[2]))
31782
+ {
31783
+ emit_insn (gen_rx_insv_reg (operands[0], operands[2], operands[3]));
31784
DONE;
31785
+ }
31786
+ else
31787
FAIL;
31788
- }
31789
-)
31790
+})
31791
31792
;; Atomic exchange operation.
31793
31794
(define_insn "sync_lock_test_and_setsi"
31795
- [(set:SI (match_operand:SI 0 "register_operand" "=r,r")
31796
- (match_operand:SI 1 "rx_compare_operand" "=r,Q"))
31797
- (set:SI (match_dup 1)
31798
- (match_operand:SI 2 "register_operand" "0,0"))]
31799
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
31800
+ (match_operand:SI 1 "rx_compare_operand" "=r,Q"))
31801
+ (set (match_dup 1)
31802
+ (match_operand:SI 2 "register_operand" "0,0"))]
31803
""
31804
"xchg\t%1, %0"
31805
[(set_attr "length" "3,6")
31806
@@ -1462,9 +1965,9 @@
31807
;; Block move functions.
31808
31809
(define_expand "movstr"
31810
- [(set:SI (match_operand:BLK 1 "memory_operand") ;; Dest
31811
- (match_operand:BLK 2 "memory_operand")) ;; Source
31812
- (use (match_operand:SI 0 "register_operand")) ;; Updated Dest
31813
+ [(set (match_operand:BLK 1 "memory_operand") ;; Dest
31814
+ (match_operand:BLK 2 "memory_operand")) ;; Source
31815
+ (use (match_operand:SI 0 "register_operand")) ;; Updated Dest
31816
]
31817
""
31818
{
31819
@@ -1487,8 +1990,8 @@
31820
)
31821
31822
(define_insn "rx_movstr"
31823
- [(set:SI (mem:BLK (reg:SI 1))
31824
- (mem:BLK (reg:SI 2)))
31825
+ [(set (mem:BLK (reg:SI 1))
31826
+ (mem:BLK (reg:SI 2)))
31827
(unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_MOVSTR)
31828
(clobber (reg:SI 1))
31829
(clobber (reg:SI 2))
31830
@@ -1500,8 +2003,8 @@
31831
)
31832
31833
(define_insn "rx_strend"
31834
- [(set:SI (match_operand:SI 0 "register_operand" "=r")
31835
- (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
31836
+ [(set (match_operand:SI 0 "register_operand" "=r")
31837
+ (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
31838
(reg:SI 3)] UNSPEC_STRLEN))
31839
(clobber (reg:SI 1))
31840
(clobber (reg:SI 2))
31841
@@ -1582,8 +2085,8 @@
31842
)
31843
31844
(define_insn "rx_setmem"
31845
- [(set:BLK (mem:BLK (reg:SI 1)) (reg 2))
31846
- (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_SETMEM)
31847
+ [(set (mem:BLK (reg:SI 1))
31848
+ (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_SETMEM))
31849
(clobber (reg:SI 1))
31850
(clobber (reg:SI 3))]
31851
""
31852
@@ -1636,11 +2139,11 @@
31853
)
31854
31855
(define_insn "rx_cmpstrn"
31856
- [(set:SI (match_operand:SI 0 "register_operand" "=r")
31857
- (unspec_volatile:SI [(reg:SI 1) (reg:SI 2) (reg:SI 3)]
31858
- UNSPEC_CMPSTRN))
31859
- (use (match_operand:BLK 1 "memory_operand" "m"))
31860
- (use (match_operand:BLK 2 "memory_operand" "m"))
31861
+ [(set (match_operand:SI 0 "register_operand" "=r")
31862
+ (unspec_volatile:SI [(reg:SI 1) (reg:SI 2) (reg:SI 3)]
31863
+ UNSPEC_CMPSTRN))
31864
+ (use (match_operand:BLK 1 "memory_operand" "m"))
31865
+ (use (match_operand:BLK 2 "memory_operand" "m"))
31866
(clobber (reg:SI 1))
31867
(clobber (reg:SI 2))
31868
(clobber (reg:SI 3))
31869
@@ -1773,7 +2276,7 @@
31870
31871
;; Byte swap (two 16-bit values).
31872
(define_insn "revw"
31873
- [(set (match_operand:SI 0 "register_operand" "+r")
31874
+ [(set (match_operand:SI 0 "register_operand" "=r")
31875
(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
31876
UNSPEC_BUILTIN_REVW))]
31877
""
31878
@@ -1807,7 +2310,7 @@
31879
31880
;; Clear Processor Status Word
31881
(define_insn "clrpsw"
31882
- [(unspec:SI [(match_operand:SI 0 "immediate_operand" "i")]
31883
+ [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")]
31884
UNSPEC_BUILTIN_CLRPSW)
31885
(clobber (reg:CC CC_REG))]
31886
""
31887
@@ -1817,7 +2320,7 @@
31888
31889
;; Set Processor Status Word
31890
(define_insn "setpsw"
31891
- [(unspec:SI [(match_operand:SI 0 "immediate_operand" "i")]
31892
+ [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")]
31893
UNSPEC_BUILTIN_SETPSW)
31894
(clobber (reg:CC CC_REG))]
31895
""
31896
@@ -1828,7 +2331,7 @@
31897
;; Move from control register
31898
(define_insn "mvfc"
31899
[(set (match_operand:SI 0 "register_operand" "=r")
31900
- (unspec:SI [(match_operand:SI 1 "immediate_operand" "i")]
31901
+ (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")]
31902
UNSPEC_BUILTIN_MVFC))]
31903
""
31904
"mvfc\t%C1, %0"
31905
@@ -1837,7 +2340,7 @@
31906
31907
;; Move to control register
31908
(define_insn "mvtc"
31909
- [(unspec:SI [(match_operand:SI 0 "immediate_operand" "i,i")
31910
+ [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i,i")
31911
(match_operand:SI 1 "nonmemory_operand" "r,i")]
31912
UNSPEC_BUILTIN_MVTC)]
31913
""
31914
@@ -1852,7 +2355,7 @@
31915
31916
;; Move to interrupt priority level
31917
(define_insn "mvtipl"
31918
- [(unspec:SI [(match_operand:SI 0 "immediate_operand" "Uint04")]
31919
+ [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "Uint04")]
31920
UNSPEC_BUILTIN_MVTIPL)]
31921
""
31922
"mvtipl\t%0"
31923
27198
--- a/src/gcc/config/s390/s390.c
31924
27199
+++ b/src/gcc/config/s390/s390.c
31925
@@ -2830,12 +2830,16 @@
31926
it is most likely being used as an address, so
31927
prefer ADDR_REGS. If 'class' is not a superset
31928
of ADDR_REGS, e.g. FP_REGS, reject this reload. */
31929
- case PLUS:
31930
case LABEL_REF:
31931
case SYMBOL_REF:
31932
case CONST:
31933
+ if (!legitimate_reload_constant_p (op))
31934
+ return NO_REGS;
31935
+ /* fallthrough */
31936
+ case PLUS:
31937
+ /* load address will be used. */
31938
if (reg_class_subset_p (ADDR_REGS, rclass))
31939
- return ADDR_REGS;
31940
+ return ADDR_REGS;
31941
else
31942
return NO_REGS;
31943
31944
@@ -2951,12 +2955,16 @@
31945
31946
if (TARGET_Z10)
31947
{
31948
+ HOST_WIDE_INT offset;
31949
+ rtx symref;
31950
+
31951
/* On z10 several optimizer steps may generate larl operands with
31952
an odd addend. */
31953
if (in_p
31954
- && s390_symref_operand_p (x, NULL, NULL)
31955
+ && s390_symref_operand_p (x, &symref, &offset)
31956
&& mode == Pmode
31957
- && !s390_check_symref_alignment (x, 2))
31958
+ && !SYMBOL_REF_ALIGN1_P (symref)
31959
+ && (offset & 1) == 1)
31960
sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
31961
: CODE_FOR_reloadsi_larl_odd_addend_z10);
31962
31963
@@ -8170,7 +8178,7 @@
27200
@@ -8178,7 +8178,7 @@
31964
27201
31965
27202
p = rtvec_alloc (2);
31966
27203
32020
27257
- (and (match_code "mem")
32021
27258
- (and (match_operand 0 "memory_operand")
32022
27259
- (match_test "REG_P (XEXP (op, 0))"))))
32023
--- a/src/gcc/config/sparc/sparc.c
32024
+++ b/src/gcc/config/sparc/sparc.c
32025
@@ -363,7 +363,7 @@
32026
static int epilogue_renumber (rtx *, int);
32027
static bool sparc_assemble_integer (rtx, unsigned int, int);
32028
static int set_extends (rtx);
32029
-static void load_pic_register (void);
32030
+static void load_got_register (void);
32031
static int save_or_restore_regs (int, int, rtx, int, int);
32032
static void emit_save_or_restore_regs (int);
32033
static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
32034
@@ -966,6 +966,36 @@
32035
return 0;
32036
}
32037
32038
+/* Return true if the address of LABEL can be loaded by means of the
32039
+ mov{si,di}_pic_label_ref patterns in PIC mode. */
32040
+
32041
+static bool
32042
+can_use_mov_pic_label_ref (rtx label)
32043
+{
32044
+ /* VxWorks does not impose a fixed gap between segments; the run-time
32045
+ gap can be different from the object-file gap. We therefore can't
32046
+ assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
32047
+ are absolutely sure that X is in the same segment as the GOT.
32048
+ Unfortunately, the flexibility of linker scripts means that we
32049
+ can't be sure of that in general, so assume that GOT-relative
32050
+ accesses are never valid on VxWorks. */
32051
+ if (TARGET_VXWORKS_RTP)
32052
+ return false;
32053
+
32054
+ /* Similarly, if the label is non-local, it might end up being placed
32055
+ in a different section than the current one; now mov_pic_label_ref
32056
+ requires the label and the code to be in the same section. */
32057
+ if (LABEL_REF_NONLOCAL_P (label))
32058
+ return false;
32059
+
32060
+ /* Finally, if we are reordering basic blocks and partition into hot
32061
+ and cold sections, this might happen for any label. */
32062
+ if (flag_reorder_blocks_and_partition)
32063
+ return false;
32064
+
32065
+ return true;
32066
+}
32067
+
32068
/* Expand a move instruction. Return true if all work is done. */
32069
32070
bool
32071
@@ -1000,14 +1030,9 @@
32072
if (pic_address_needs_scratch (operands[1]))
32073
operands[1] = legitimize_pic_address (operands[1], NULL_RTX);
32074
32075
- /* VxWorks does not impose a fixed gap between segments; the run-time
32076
- gap can be different from the object-file gap. We therefore can't
32077
- assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
32078
- are absolutely sure that X is in the same segment as the GOT.
32079
- Unfortunately, the flexibility of linker scripts means that we
32080
- can't be sure of that in general, so assume that _G_O_T_-relative
32081
- accesses are never valid on VxWorks. */
32082
- if (GET_CODE (operands[1]) == LABEL_REF && !TARGET_VXWORKS_RTP)
32083
+ /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
32084
+ if (GET_CODE (operands[1]) == LABEL_REF
32085
+ && can_use_mov_pic_label_ref (operands[1]))
32086
{
32087
if (mode == SImode)
32088
{
32089
@@ -2907,26 +2932,39 @@
32090
}
32091
}
32092
32093
-/* PIC support. */
32094
-static GTY(()) bool pic_helper_needed = false;
32095
-static GTY(()) rtx pic_helper_symbol;
32096
-static GTY(()) rtx global_offset_table;
32097
+/* Global Offset Table support. */
32098
+static GTY(()) rtx got_helper_rtx = NULL_RTX;
32099
+static GTY(()) rtx global_offset_table_rtx = NULL_RTX;
32100
+
32101
+/* Return the SYMBOL_REF for the Global Offset Table. */
32102
+
32103
+static GTY(()) rtx sparc_got_symbol = NULL_RTX;
32104
+
32105
+static rtx
32106
+sparc_got (void)
32107
+{
32108
+ if (!sparc_got_symbol)
32109
+ sparc_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
32110
+
32111
+ return sparc_got_symbol;
32112
+}
32113
32114
/* Ensure that we are not using patterns that are not OK with PIC. */
32115
32116
int
32117
check_pic (int i)
32118
{
32119
+ rtx op;
32120
+
32121
switch (flag_pic)
32122
{
32123
case 1:
32124
- gcc_assert (GET_CODE (recog_data.operand[i]) != SYMBOL_REF
32125
- && (GET_CODE (recog_data.operand[i]) != CONST
32126
- || (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
32127
- && (XEXP (XEXP (recog_data.operand[i], 0), 0)
32128
- == global_offset_table)
32129
- && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
32130
- == CONST))));
32131
+ op = recog_data.operand[i];
32132
+ gcc_assert (GET_CODE (op) != SYMBOL_REF
32133
+ && (GET_CODE (op) != CONST
32134
+ || (GET_CODE (XEXP (op, 0)) == MINUS
32135
+ && XEXP (XEXP (op, 0), 0) == sparc_got ()
32136
+ && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST)));
32137
case 2:
32138
default:
32139
return 1;
32140
@@ -3161,9 +3199,9 @@
32141
return 1;
32142
}
32143
32144
-/* Construct the SYMBOL_REF for the tls_get_offset function. */
32145
+/* Return the SYMBOL_REF for the tls_get_addr function. */
32146
32147
-static GTY(()) rtx sparc_tls_symbol;
32148
+static GTY(()) rtx sparc_tls_symbol = NULL_RTX;
32149
32150
static rtx
32151
sparc_tls_get_addr (void)
32152
@@ -3174,21 +3212,28 @@
32153
return sparc_tls_symbol;
32154
}
32155
32156
+/* Return the Global Offset Table to be used in TLS mode. */
32157
+
32158
static rtx
32159
sparc_tls_got (void)
32160
{
32161
- rtx temp;
32162
+ /* In PIC mode, this is just the PIC offset table. */
32163
if (flag_pic)
32164
{
32165
crtl->uses_pic_offset_table = 1;
32166
return pic_offset_table_rtx;
32167
}
32168
32169
- if (!global_offset_table)
32170
- global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
32171
- temp = gen_reg_rtx (Pmode);
32172
- emit_move_insn (temp, global_offset_table);
32173
- return temp;
32174
+ /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
32175
+ the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
32176
+ if (TARGET_SUN_TLS && TARGET_ARCH32)
32177
+ {
32178
+ load_got_register ();
32179
+ return global_offset_table_rtx;
32180
+ }
32181
+
32182
+ /* In all other cases, we load a new pseudo with the GOT symbol. */
32183
+ return copy_to_reg (sparc_got ());
32184
}
32185
32186
/* Return true if X contains a thread-local symbol. */
32187
@@ -3369,7 +3414,7 @@
32188
32189
if (GET_CODE (orig) == SYMBOL_REF
32190
/* See the comment in sparc_expand_move. */
32191
- || (TARGET_VXWORKS_RTP && GET_CODE (orig) == LABEL_REF))
32192
+ || (GET_CODE (orig) == LABEL_REF && !can_use_mov_pic_label_ref (orig)))
32193
{
32194
rtx pic_ref, address;
32195
rtx insn;
32196
@@ -3420,11 +3465,13 @@
32197
}
32198
else
32199
{
32200
- pic_ref = gen_const_mem (Pmode,
32201
- gen_rtx_PLUS (Pmode,
32202
- pic_offset_table_rtx, address));
32203
+ pic_ref
32204
+ = gen_const_mem (Pmode,
32205
+ gen_rtx_PLUS (Pmode,
32206
+ pic_offset_table_rtx, address));
32207
insn = emit_move_insn (reg, pic_ref);
32208
}
32209
+
32210
/* Put a REG_EQUAL note on this insn, so that it can be optimized
32211
by loop. */
32212
set_unique_reg_note (insn, REG_EQUAL, orig);
32213
@@ -3462,9 +3509,8 @@
32214
return gen_rtx_PLUS (Pmode, base, offset);
32215
}
32216
else if (GET_CODE (orig) == LABEL_REF)
32217
- /* ??? Why do we do this? */
32218
- /* Now movsi_pic_label_ref uses it, but we ought to be checking that
32219
- the register is live instead, in case it is eliminated. */
32220
+ /* ??? We ought to be checking that the register is live instead, in case
32221
+ it is eliminated. */
32222
crtl->uses_pic_offset_table = 1;
32223
32224
return orig;
32225
@@ -3529,59 +3575,69 @@
32226
static void
32227
get_pc_thunk_name (char name[32], unsigned int regno)
32228
{
32229
- const char *pic_name = reg_names[regno];
32230
+ const char *reg_name = reg_names[regno];
32231
32232
/* Skip the leading '%' as that cannot be used in a
32233
symbol name. */
32234
- pic_name += 1;
32235
+ reg_name += 1;
32236
32237
if (USE_HIDDEN_LINKONCE)
32238
- sprintf (name, "__sparc_get_pc_thunk.%s", pic_name);
32239
+ sprintf (name, "__sparc_get_pc_thunk.%s", reg_name);
32240
else
32241
ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
32242
}
32243
32244
-/* Emit code to load the PIC register. */
32245
+/* Wrapper around the load_pcrel_sym{si,di} patterns. */
32246
32247
-static void
32248
-load_pic_register (void)
32249
+static rtx
32250
+gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2, rtx op3)
32251
{
32252
int orig_flag_pic = flag_pic;
32253
+ rtx insn;
32254
32255
- if (TARGET_VXWORKS_RTP)
32256
- {
32257
- emit_insn (gen_vxworks_load_got ());
32258
- emit_use (pic_offset_table_rtx);
32259
- return;
32260
- }
32261
-
32262
- /* If we haven't initialized the special PIC symbols, do so now. */
32263
- if (!pic_helper_needed)
32264
- {
32265
- char name[32];
32266
+ /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
32267
+ flag_pic = 0;
32268
+ if (TARGET_ARCH64)
32269
+ insn = gen_load_pcrel_symdi (op0, op1, op2, op3);
32270
+ else
32271
+ insn = gen_load_pcrel_symsi (op0, op1, op2, op3);
32272
+ flag_pic = orig_flag_pic;
32273
32274
- pic_helper_needed = true;
32275
+ return insn;
32276
+}
32277
32278
- get_pc_thunk_name (name, REGNO (pic_offset_table_rtx));
32279
- pic_helper_symbol = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
32280
+/* Emit code to load the GOT register. */
32281
32282
- global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
32283
- }
32284
+static void
32285
+load_got_register (void)
32286
+{
32287
+ /* In PIC mode, this will retrieve pic_offset_table_rtx. */
32288
+ if (!global_offset_table_rtx)
32289
+ global_offset_table_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
32290
32291
- flag_pic = 0;
32292
- if (TARGET_ARCH64)
32293
- emit_insn (gen_load_pcrel_symdi (pic_offset_table_rtx, global_offset_table,
32294
- pic_helper_symbol));
32295
+ if (TARGET_VXWORKS_RTP)
32296
+ emit_insn (gen_vxworks_load_got ());
32297
else
32298
- emit_insn (gen_load_pcrel_symsi (pic_offset_table_rtx, global_offset_table,
32299
- pic_helper_symbol));
32300
- flag_pic = orig_flag_pic;
32301
+ {
32302
+ /* The GOT symbol is subject to a PC-relative relocation so we need a
32303
+ helper function to add the PC value and thus get the final value. */
32304
+ if (!got_helper_rtx)
32305
+ {
32306
+ char name[32];
32307
+ get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM);
32308
+ got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
32309
+ }
32310
+
32311
+ emit_insn (gen_load_pcrel_sym (global_offset_table_rtx, sparc_got (),
32312
+ got_helper_rtx,
32313
+ GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM)));
32314
+ }
32315
32316
/* Need to emit this whether or not we obey regdecls,
32317
since setjmp/longjmp can cause life info to screw up.
32318
??? In the case where we don't obey regdecls, this is not sufficient
32319
since we may not fall out the bottom. */
32320
- emit_use (pic_offset_table_rtx);
32321
+ emit_use (global_offset_table_rtx);
32322
}
32323
32324
/* Emit a call instruction with the pattern given by PAT. ADDR is the
32325
@@ -4113,7 +4169,7 @@
32326
32327
/* Expand the function prologue. The prologue is responsible for reserving
32328
storage for the frame, saving the call-saved registers and loading the
32329
- PIC register if needed. */
32330
+ GOT register if needed. */
32331
32332
void
32333
sparc_expand_prologue (void)
32334
@@ -4215,9 +4271,9 @@
32335
if (num_gfregs)
32336
emit_save_or_restore_regs (SORR_SAVE);
32337
32338
- /* Load the PIC register if needed. */
32339
- if (flag_pic && crtl->uses_pic_offset_table)
32340
- load_pic_register ();
32341
+ /* Load the GOT register if needed. */
32342
+ if (crtl->uses_pic_offset_table)
32343
+ load_got_register ();
32344
}
32345
32346
/* This function generates the assembly code for function entry, which boils
32347
@@ -8705,7 +8761,7 @@
32348
/* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
32349
This is achieved by means of a manual dynamic stack space allocation in
32350
the current frame. We make the assumption that SEQ doesn't contain any
32351
- function calls, with the possible exception of calls to the PIC helper. */
32352
+ function calls, with the possible exception of calls to the GOT helper. */
32353
32354
static void
32355
emit_and_preserve (rtx seq, rtx reg, rtx reg2)
32356
@@ -8868,20 +8924,19 @@
32357
{
32358
/* The hoops we have to jump through in order to generate a sibcall
32359
without using delay slots... */
32360
- rtx spill_reg, spill_reg2, seq, scratch = gen_rtx_REG (Pmode, 1);
32361
+ rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
32362
32363
if (flag_pic)
32364
{
32365
spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
32366
- spill_reg2 = gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM);
32367
start_sequence ();
32368
- /* Delay emitting the PIC helper function because it needs to
32369
+ /* Delay emitting the GOT helper function because it needs to
32370
change the section and we are emitting assembly code. */
32371
- load_pic_register (); /* clobbers %o7 */
32372
+ load_got_register (); /* clobbers %o7 */
32373
scratch = legitimize_pic_address (funexp, scratch);
32374
seq = get_insns ();
32375
end_sequence ();
32376
- emit_and_preserve (seq, spill_reg, spill_reg2);
32377
+ emit_and_preserve (seq, spill_reg, pic_offset_table_rtx);
32378
}
32379
else if (TARGET_ARCH32)
32380
{
32381
@@ -9032,17 +9087,15 @@
32382
static void
32383
sparc_file_end (void)
32384
{
32385
- /* If need to emit the special PIC helper function, do so now. */
32386
- if (pic_helper_needed)
32387
+ /* If we need to emit the special GOT helper function, do so now. */
32388
+ if (got_helper_rtx)
32389
{
32390
- unsigned int regno = REGNO (pic_offset_table_rtx);
32391
- const char *pic_name = reg_names[regno];
32392
- char name[32];
32393
+ const char *name = XSTR (got_helper_rtx, 0);
32394
+ const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM];
32395
#ifdef DWARF2_UNWIND_INFO
32396
bool do_cfi;
32397
#endif
32398
32399
- get_pc_thunk_name (name, regno);
32400
if (USE_HIDDEN_LINKONCE)
32401
{
32402
tree decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
32403
@@ -9055,7 +9108,9 @@
32404
make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl));
32405
DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
32406
DECL_VISIBILITY_SPECIFIED (decl) = 1;
32407
+ resolve_unique_section (decl, 0, flag_function_sections);
32408
allocate_struct_function (decl, true);
32409
+ cfun->is_thunk = 1;
32410
current_function_decl = decl;
32411
init_varasm_status ();
32412
assemble_start_function (decl, name);
32413
@@ -9076,10 +9131,10 @@
32414
#endif
32415
if (flag_delayed_branch)
32416
fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
32417
- pic_name, pic_name);
32418
+ reg_name, reg_name);
32419
else
32420
fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
32421
- pic_name, pic_name);
32422
+ reg_name, reg_name);
32423
#ifdef DWARF2_UNWIND_INFO
32424
if (do_cfi)
32425
fprintf (asm_out_file, "\t.cfi_endproc\n");
32426
27260
--- a/src/gcc/config/sparc/sparc.h
32427
27261
+++ b/src/gcc/config/sparc/sparc.h
32428
@@ -964,10 +964,15 @@
32429
not be a register used by the prologue. */
32430
#define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
32431
32432
+/* Register which holds the global offset table, if any. */
32433
+
32434
+#define GLOBAL_OFFSET_TABLE_REGNUM 23
32435
+
32436
/* Register which holds offset table for position-independent
32437
data references. */
32438
32439
-#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
32440
+#define PIC_OFFSET_TABLE_REGNUM \
32441
+ (flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
32442
32443
/* Pick a default value we can notice from override_options:
32444
!v9: Default is on.
32445
@@ -1181,7 +1186,7 @@
27262
@@ -1186,7 +1186,7 @@
32446
27263
96, 97, 98, 99, /* %fcc0-3 */ \
32447
27264
100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */
32448
27265
32451
27268
32452
27269
extern char sparc_leaf_regs[];
32453
27270
#define LEAF_REGISTERS sparc_leaf_regs
32454
--- a/src/gcc/config/sparc/sparc.md
32455
+++ b/src/gcc/config/sparc/sparc.md
32456
@@ -1106,14 +1106,15 @@
32457
32458
;; Load in operand 0 the (absolute) address of operand 1, which is a symbolic
32459
;; value subject to a PC-relative relocation. Operand 2 is a helper function
32460
-;; that adds the PC value at the call point to operand 0.
32461
+;; that adds the PC value at the call point to register #(operand 3).
32462
32463
(define_insn "load_pcrel_sym<P:mode>"
32464
[(set (match_operand:P 0 "register_operand" "=r")
32465
(unspec:P [(match_operand:P 1 "symbolic_operand" "")
32466
- (match_operand:P 2 "call_address_operand" "")] UNSPEC_LOAD_PCREL_SYM))
32467
+ (match_operand:P 2 "call_address_operand" "")
32468
+ (match_operand:P 3 "const_int_operand" "")] UNSPEC_LOAD_PCREL_SYM))
32469
(clobber (reg:P 15))]
32470
- ""
32471
+ "REGNO (operands[0]) == INTVAL (operands[3])"
32472
{
32473
if (flag_delayed_branch)
32474
return "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\t add\t%0, %%lo(%a1+4), %0";
32475
27271
--- a/src/gcc/config/sparc/sync.md
32476
27272
+++ b/src/gcc/config/sparc/sync.md
32477
27273
@@ -1,5 +1,5 @@
32597
27393
giving preference to call-used registers. To minimize window
32598
27394
--- a/src/gcc/config.gcc
32599
27395
+++ b/src/gcc/config.gcc
32600
@@ -1,6 +1,6 @@
32601
# GCC target-specific configuration file.
32602
# Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
32603
-# 2008, 2009, 2010 Free Software Foundation, Inc.
32604
+# 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
32605
32606
#This file is part of GCC.
32607
32608
27396
@@ -513,26 +513,48 @@
32609
27397
*-*-gnu*)
32610
27398
tmake_file="$tmake_file t-gnu";;
32711
27499
extra_options="${extra_options} linux.opt"
32712
27500
;;
32713
27501
h8300-*-rtems*)
32714
@@ -1066,6 +1093,7 @@
32715
else
32716
tmake_file="$tmake_file pa/t-slibgcc-dwarf-ver"
32717
fi
32718
+ extra_parts="libgcc_stub.a"
32719
case x${enable_threads} in
32720
x | xyes | xposix )
32721
thread_file=posix
32722
@@ -1643,7 +1671,7 @@
27502
@@ -1644,7 +1671,7 @@
32723
27503
default_m68k_cpu=68020
32724
27504
default_cf_cpu=5206
32725
27505
tm_file="${tm_file} dbxelf.h elfos.h svr4.h linux.h glibc-stdint.h flat.h m68k/linux.h m68k/uclinux.h ./sysroot-suffix.h"
32728
27508
extra_options="${extra_options} linux.opt"
32729
27509
tmake_file="m68k/t-floatlib m68k/t-uclinux m68k/t-mlibs"
32730
27510
;;
32731
@@ -2630,6 +2658,16 @@
32732
arch_without_sse2=no
32733
arch_without_64bit=no
32734
case ${target} in
32735
+ i386-*-freebsd*)
32736
+ if test $fbsd_major -ge 6; then
32737
+ arch=i486
32738
+ else
32739
+ arch=i386
32740
+ fi
32741
+ cpu=generic
32742
+ arch_without_sse2=yes
32743
+ arch_without_64bit=yes
32744
+ ;;
32745
i386-*-*)
32746
arch=i386
32747
cpu=i386
32748
--- a/src/gcc/config.host
32749
+++ b/src/gcc/config.host
32750
@@ -1,6 +1,6 @@
32751
# GCC host-specific configuration file.
32752
-# Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2006, 2007, 2008, 2009
32753
-# Free Software Foundation, Inc.
32754
+# Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2006, 2007, 2008, 2009,
32755
+# 2011 Free Software Foundation, Inc.
32756
32757
#This file is part of GCC.
32758
32759
@@ -163,6 +163,10 @@
32760
prefix=/gnu
32761
local_prefix=/gnu/local
32762
;;
32763
+ alpha*-dec-osf*)
32764
+ out_host_hook_obj=host-osf.o
32765
+ host_xmake_file="${host_xmake_file} alpha/x-osf"
32766
+ ;;
32767
alpha*-dec-*vms*)
32768
host_xm_file="vms/xm-vms.h"
32769
host_xmake_file=vms/x-vms
32770
27511
--- a/src/gcc/config.in
32771
27512
+++ b/src/gcc/config.in
32772
27513
@@ -132,6 +132,12 @@
32888
27629
AC_SUBST(srcdir)
32889
27630
--- a/src/gcc/cp/ChangeLog
32890
27631
+++ b/src/gcc/cp/ChangeLog
32891
@@ -1,3 +1,76 @@
32892
+2011-03-28 Jason Merrill <jason@redhat.com>
32893
+
32894
+ Revert:
32895
+ PR c++/48289
32896
+ * pt.c (build_non_dependent_expr): Keep dereferences outside the
32897
+ NON_DEPENDENT_EXPR.
32898
+
32899
+2011-03-25 Jason Merrill <jason@redhat.com>
32900
+
32901
+ PR c++/48289
32902
+ * pt.c (build_non_dependent_expr): Keep dereferences outside the
32903
+ NON_DEPENDENT_EXPR.
32904
+
32905
+2011-03-11 Jason Merrill <jason@redhat.com>
32906
+
32907
+ PR c++/47125
32908
+ * pt.c (tsubst) [TYPENAME_TYPE]: Only give errors if tf_error.
32909
+
32910
+2011-03-10 Jason Merrill <jason@redhat.com>
32911
+
32912
+ PR c++/48029
32913
+ * pt.c (iterative_hash_template_arg): Remove special case for
32914
+ ARRAY_TYPE.
32915
+
32916
+2011-03-09 Jason Merrill <jason@redhat.com>
32917
+
32918
+ PR c++/44629
32919
+ * pt.c (unify): An unresolved overload is a nondeduced context.
32920
+
32921
+2011-03-08 Jason Merrill <jason@redhat.com>
32922
+
32923
+ PR c++/45651
32924
+ * pt.c (instantiate_decl): Don't clear DECL_INTERFACE_KNOWN on
32925
+ !TREE_PUBLIC decls.
32926
+
32927
+2011-03-08 Jason Merrill <jason@redhat.com>
32928
+
32929
+ PR c++/47289
32930
+ * pt.c (coerce_template_parms): Fix error recovery.
32931
+
32932
+2011-03-08 Dodji Seketeli <dodji@redhat.com>
32933
+
32934
+ PR c++/47705
32935
+ * pt.c (convert_nontype_argument): Only call decay_conversion on
32936
+ arrays.
32937
+
32938
+2011-03-08 Dodji Seketeli <dodji@redhat.com>
32939
+
32940
+ * name-lookup.c (binding_to_template_parms_of_scope_p): Only
32941
+ consider scopes of primary template definitions. Adjust comments.
32942
+
32943
+2011-03-08 Jason Merrill <jason@redhat.com>
32944
+
32945
+ PR c++/47488
32946
+ * mangle.c (write_template_arg_literal) [STRING_CST]: Sorry.
32947
+
32948
+2011-03-08 Richard Guenther <rguenther@suse.de>
32949
+
32950
+ PR tree-optimization/47278
32951
+ * decl.c (finish_function): Use decl_replaceable_p.
32952
+
32953
+2011-03-01 Jason Merrill <jason@redhat.com>
32954
+
32955
+ PR c++/46159
32956
+ * parser.c (cp_parser_primary_expression): Don't warn about a
32957
+ failed tentative parse.
32958
+
32959
+2011-02-26 Jason Merrill <jason@redhat.com>
32960
+
32961
+ PR c++/47904
32962
+ * tree.c (cp_tree_equal) [PARM_DECL]: Don't crash on
32963
+ DECL_ARTIFICIAL parms.
32964
+
32965
2010-12-16 Release Manager
27632
@@ -1,3 +1,9 @@
27633
+2011-04-27 Jason Merrill <jason@redhat.com>
27634
+
27635
+ PR c++/48046
27636
+ * parser.c (cp_parser_diagnose_invalid_type_name): Commit
27637
+ to tentative parse sooner.
27638
+
27639
2011-04-28 Release Manager
32966
27640
32967
* GCC 4.5.2 released.
27641
* GCC 4.5.3 released.
32968
27642
--- a/src/gcc/cp/call.c
32969
27643
+++ b/src/gcc/cp/call.c
32970
@@ -3946,6 +3946,10 @@
27644
@@ -3945,6 +3945,10 @@
32971
27645
/* In this case, there is always a common type. */
32972
27646
result_type = type_after_usual_arithmetic_conversions (arg2_type,
32973
27647
arg3_type);
32978
27652
32979
27653
if (TREE_CODE (arg2_type) == ENUMERAL_TYPE
32980
27654
&& TREE_CODE (arg3_type) == ENUMERAL_TYPE)
32981
@@ -5179,11 +5183,14 @@
27655
@@ -5178,11 +5182,14 @@
32982
27656
tree
32983
27657
convert_arg_to_ellipsis (tree arg)
32984
27658
{
32993
27667
/* [expr.call]
32994
27668
32995
27669
If the argument has integral or enumeration type that is subject
32996
@@ -5191,19 +5198,27 @@
27670
@@ -5190,19 +5197,27 @@
32997
27671
type that is subject to the floating point promotion
32998
27672
(_conv.fpprom_), the value of the argument is converted to the
32999
27673
promoted type before the call. */
33028
27702
{
33029
27703
/* [expr.call] 5.2.2/7:
33030
27704
Passing a potentially-evaluated argument of class type (Clause 9)
33031
@@ -5218,7 +5233,7 @@
27705
@@ -5217,7 +5232,7 @@
33032
27706
it is not potentially-evaluated. */
33033
27707
if (cp_unevaluated_operand == 0)
33034
27708
error ("cannot pass objects of non-trivially-copyable "
33037
27711
}
33038
27712
33039
27713
return arg;
33040
--- a/src/gcc/cp/decl.c
33041
+++ b/src/gcc/cp/decl.c
33042
@@ -12502,7 +12502,7 @@
33043
if (!processing_template_decl
33044
&& !cp_function_chain->can_throw
33045
&& !flag_non_call_exceptions
33046
- && !DECL_REPLACEABLE_P (fndecl))
33047
+ && !decl_replaceable_p (fndecl))
33048
TREE_NOTHROW (fndecl) = 1;
33049
33050
/* This must come after expand_function_end because cleanups might
33051
--- a/src/gcc/cp/mangle.c
33052
+++ b/src/gcc/cp/mangle.c
33053
@@ -2683,6 +2683,10 @@
33054
write_real_cst (value);
33055
break;
33056
33057
+ case STRING_CST:
33058
+ sorry ("string literal in function template signature");
33059
+ break;
33060
+
33061
default:
33062
gcc_unreachable ();
33063
}
33064
--- a/src/gcc/cp/name-lookup.c
33065
+++ b/src/gcc/cp/name-lookup.c
33066
@@ -4067,8 +4067,13 @@
33067
}
33068
33069
/* Subroutine of outer_binding.
33070
- Returns TRUE if BINDING is a binding to a template parameter of SCOPE,
33071
- FALSE otherwise. */
33072
+
33073
+ Returns TRUE if BINDING is a binding to a template parameter of
33074
+ SCOPE. In that case SCOPE is the scope of a primary template
33075
+ parameter -- in the sense of G++, i.e, a template that has its own
33076
+ template header.
33077
+
33078
+ Returns FALSE otherwise. */
33079
33080
static bool
33081
binding_to_template_parms_of_scope_p (cxx_binding *binding,
33082
@@ -4084,6 +4089,8 @@
33083
return (scope
33084
&& scope->this_entity
33085
&& get_template_info (scope->this_entity)
33086
+ && PRIMARY_TEMPLATE_P (TI_TEMPLATE
33087
+ (get_template_info (scope->this_entity)))
33088
&& parameter_of_template_p (binding_value,
33089
TI_TEMPLATE (get_template_info \
33090
(scope->this_entity))));
33091
27714
--- a/src/gcc/cp/parser.c
33092
27715
+++ b/src/gcc/cp/parser.c
33093
@@ -3341,8 +3341,14 @@
33094
if (c_dialect_objc ())
33095
/* We have an Objective-C++ message. */
33096
return cp_parser_objc_expression (parser);
33097
- maybe_warn_cpp0x (CPP0X_LAMBDA_EXPR);
33098
- return cp_parser_lambda_expression (parser);
33099
+ {
33100
+ tree lam = cp_parser_lambda_expression (parser);
33101
+ /* Don't warn about a failed tentative parse. */
33102
+ if (cp_parser_error_occurred (parser))
33103
+ return error_mark_node;
33104
+ maybe_warn_cpp0x (CPP0X_LAMBDA_EXPR);
33105
+ return lam;
33106
+ }
33107
33108
case CPP_OBJC_STRING:
33109
if (c_dialect_objc ())
33110
--- a/src/gcc/cp/pt.c
33111
+++ b/src/gcc/cp/pt.c
33112
@@ -1556,13 +1556,6 @@
33113
val = iterative_hash_object (code, val);
33114
return iterative_hash_template_arg (TREE_OPERAND (arg, 2), val);
33115
33116
- case ARRAY_TYPE:
33117
- /* layout_type sets structural equality for arrays of
33118
- incomplete type, so we can't rely on the canonical type
33119
- for hashing. */
33120
- val = iterative_hash_template_arg (TREE_TYPE (arg), val);
33121
- return iterative_hash_template_arg (TYPE_DOMAIN (arg), val);
33122
-
33123
case LAMBDA_EXPR:
33124
/* A lambda can't appear in a template arg, but don't crash on
33125
erroneous input. */
33126
@@ -4951,7 +4944,8 @@
33127
33128
/* Add the ADDR_EXPR now for the benefit of
33129
value_dependent_expression_p. */
33130
- if (TYPE_PTROBV_P (type))
33131
+ if (TYPE_PTROBV_P (type)
33132
+ && TREE_CODE (TREE_TYPE (expr)) == ARRAY_TYPE)
33133
expr = decay_conversion (expr);
33134
33135
/* If we are in a template, EXPR may be non-dependent, but still
33136
@@ -6043,7 +6037,7 @@
33137
sorry ("cannot expand %<%T%> into a fixed-length "
33138
"argument list", arg);
33139
}
33140
- return error_mark_node;
33141
+ ++lost;
33142
}
33143
}
33144
else if (require_all_args)
33145
@@ -6071,7 +6065,7 @@
33146
reported) that we are trying to recover from, e.g., a class
33147
template with a parameter list such as
33148
template<typename..., typename>. */
33149
- return error_mark_node;
33150
+ ++lost;
27716
@@ -2333,6 +2333,7 @@
27717
location_t location)
27718
{
27719
tree decl, old_scope;
27720
+ cp_parser_commit_to_tentative_parse (parser);
27721
/* Try to lookup the identifier. */
27722
old_scope = parser->scope;
27723
parser->scope = scope;
27724
@@ -2423,7 +2424,6 @@
33151
27725
else
33152
arg = convert_template_argument (TREE_VALUE (parm),
33153
arg, new_args, complain,
33154
@@ -10555,11 +10549,21 @@
33155
if (TREE_CODE (f) != TYPENAME_TYPE)
33156
{
33157
if (TYPENAME_IS_ENUM_P (t) && TREE_CODE (f) != ENUMERAL_TYPE)
33158
- error ("%qT resolves to %qT, which is not an enumeration type",
33159
- t, f);
33160
+ {
33161
+ if (complain & tf_error)
33162
+ error ("%qT resolves to %qT, which is not an enumeration type",
33163
+ t, f);
33164
+ else
33165
+ return error_mark_node;
33166
+ }
33167
else if (TYPENAME_IS_CLASS_P (t) && !CLASS_TYPE_P (f))
33168
- error ("%qT resolves to %qT, which is is not a class type",
33169
- t, f);
33170
+ {
33171
+ if (complain & tf_error)
33172
+ error ("%qT resolves to %qT, which is is not a class type",
33173
+ t, f);
33174
+ else
33175
+ return error_mark_node;
33176
+ }
33177
}
33178
33179
/* cv-quals from the template are discarded when
33180
@@ -15193,6 +15197,9 @@
33181
return 1;
33182
33183
default:
33184
+ /* An unresolved overload is a nondeduced context. */
33185
+ if (type_unknown_p (parm))
33186
+ return 0;
33187
gcc_assert (EXPR_P (parm));
33188
33189
/* We must be looking at an expression. This can happen with
33190
@@ -16720,8 +16727,13 @@
33191
if (!pattern_defined && expl_inst_class_mem_p
33192
&& DECL_EXPLICIT_INSTANTIATION (d))
33193
{
33194
- DECL_NOT_REALLY_EXTERN (d) = 0;
33195
- DECL_INTERFACE_KNOWN (d) = 0;
33196
+ /* Leave linkage flags alone on instantiations with anonymous
33197
+ visibility. */
33198
+ if (TREE_PUBLIC (d))
33199
+ {
33200
+ DECL_NOT_REALLY_EXTERN (d) = 0;
33201
+ DECL_INTERFACE_KNOWN (d) = 0;
33202
+ }
33203
SET_DECL_IMPLICIT_INSTANTIATION (d);
27726
gcc_unreachable ();
33204
27727
}
33205
33206
--- a/src/gcc/cp/tree.c
33207
+++ b/src/gcc/cp/tree.c
33208
@@ -2089,12 +2089,18 @@
33209
33210
case PARM_DECL:
33211
/* For comparing uses of parameters in late-specified return types
33212
- with an out-of-class definition of the function. */
33213
- if (same_type_p (TREE_TYPE (t1), TREE_TYPE (t2))
33214
- && DECL_PARM_INDEX (t1) == DECL_PARM_INDEX (t2))
33215
- return true;
33216
- else
33217
- return false;
33218
+ with an out-of-class definition of the function, but can also come
33219
+ up for expressions that involve 'this' in a member function
33220
+ template. */
33221
+ if (same_type_p (TREE_TYPE (t1), TREE_TYPE (t2)))
33222
+ {
33223
+ if (DECL_ARTIFICIAL (t1) ^ DECL_ARTIFICIAL (t2))
33224
+ return false;
33225
+ if (DECL_ARTIFICIAL (t1)
33226
+ || DECL_PARM_INDEX (t1) == DECL_PARM_INDEX (t2))
33227
+ return true;
33228
+ }
33229
+ return false;
33230
33231
case VAR_DECL:
33232
case CONST_DECL:
27728
- cp_parser_commit_to_tentative_parse (parser);
27729
}
27730
27731
/* Check for a common situation where a type-name should be present,
33233
27732
--- a/src/gcc/cp/typeck.c
33234
27733
+++ b/src/gcc/cp/typeck.c
33235
27734
@@ -260,6 +260,7 @@
33381
27880
DEBUG_COUNTER (if_after_combine)
33382
27881
--- a/src/gcc/ddg.c
33383
27882
+++ b/src/gcc/ddg.c
33384
@@ -60,6 +60,8 @@
33385
static ddg_edge_ptr create_ddg_edge (ddg_node_ptr, ddg_node_ptr, dep_type,
33386
dep_data_type, int, int);
33387
static void add_edge_to_ddg (ddg_ptr g, ddg_edge_ptr);
33388
+static ddg_node_ptr get_node_of_insn_uid (ddg_ptr, int);
33389
+
33390
33391
/* Auxiliary variable for mem_read_insn_p/mem_write_insn_p. */
33392
static bool mem_ref_p;
33393
@@ -450,12 +452,65 @@
33394
sched_free_deps (head, tail, false);
33395
}
33396
33397
+/* Given DOLOOP_INSNS which holds the instructions that
33398
+ belong to the do-loop part; mark closing_branch_deps field in ddg G
33399
+ as TRUE if the do-loop part's instructions are dependent on the other
33400
+ loop instructions. Otherwise mark it as FALSE. */
33401
+static void
33402
+check_closing_branch_deps (ddg_ptr g, sbitmap doloop_insns)
33403
+{
33404
+ sbitmap_iterator sbi;
33405
+ unsigned int u = 0;
33406
+
33407
+ EXECUTE_IF_SET_IN_SBITMAP (doloop_insns, 0, u, sbi)
33408
+ {
33409
+ ddg_edge_ptr e;
33410
+ ddg_node_ptr u_node = get_node_of_insn_uid (g, u);
33411
+
33412
+ gcc_assert (u_node);
33413
+
33414
+ for (e = u_node->in; e != 0; e = e->next_in)
33415
+ {
33416
+ ddg_node_ptr v_node = e->src;
33417
+
33418
+ if (((unsigned int) INSN_UID (v_node->insn) == u)
33419
+ || DEBUG_INSN_P (v_node->insn))
33420
+ continue;
33421
+
33422
+ /* Ignore dependencies between memory writes and the
33423
+ jump. */
33424
+ if (JUMP_P (u_node->insn)
33425
+ && e->type == OUTPUT_DEP
33426
+ && mem_write_insn_p (v_node->insn))
33427
+ continue;
33428
+ if (!TEST_BIT (doloop_insns, INSN_UID (v_node->insn)))
33429
+ {
33430
+ g->closing_branch_deps = 1;
33431
+ return;
33432
+ }
33433
+ }
33434
+ for (e = u_node->out; e != 0; e = e->next_out)
33435
+ {
33436
+ ddg_node_ptr v_node = e->dest;
33437
+
33438
+ if (((unsigned int) INSN_UID (v_node->insn) == u)
33439
+ || DEBUG_INSN_P (v_node->insn))
33440
+ continue;
33441
+ if (!TEST_BIT (doloop_insns, INSN_UID (v_node->insn)))
33442
+ {
33443
+ g->closing_branch_deps = 1;
33444
+ return;
33445
+ }
33446
+ }
33447
+ }
33448
+ g->closing_branch_deps = 0;
33449
+}
33450
33451
/* Given a basic block, create its DDG and return a pointer to a variable
33452
of ddg type that represents it.
33453
Initialize the ddg structure fields to the appropriate values. */
33454
ddg_ptr
33455
-create_ddg (basic_block bb, int closing_branch_deps)
33456
+create_ddg (basic_block bb, sbitmap doloop_insns)
33457
{
33458
ddg_ptr g;
33459
rtx insn, first_note;
33460
@@ -465,7 +520,6 @@
33461
g = (ddg_ptr) xcalloc (1, sizeof (struct ddg));
33462
33463
g->bb = bb;
33464
- g->closing_branch_deps = closing_branch_deps;
33465
33466
/* Count the number of insns in the BB. */
33467
for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb));
33468
@@ -538,6 +592,11 @@
33469
/* Build the data dependency graph. */
33470
build_intra_loop_deps (g);
33471
build_inter_loop_deps (g);
33472
+
33473
+ /* Check whether the do-loop part is decoupled from the other loop
33474
+ instructions. */
33475
+ check_closing_branch_deps (g, doloop_insns);
33476
+
33477
return g;
33478
}
33479
33480
@@ -830,6 +889,18 @@
33481
return &g->nodes[i];
33482
return NULL;
33483
}
33484
+
33485
+/* Given the uid of an instruction UID return the node that represents it. */
33486
+static ddg_node_ptr
33487
+get_node_of_insn_uid (ddg_ptr g, int uid)
33488
+{
33489
+ int i;
33490
+
33491
+ for (i = 0; i < g->num_nodes; i++)
33492
+ if (uid == INSN_UID (g->nodes[i].insn))
33493
+ return &g->nodes[i];
33494
+ return NULL;
33495
+}
33496
33497
/* Given a set OPS of nodes in the DDG, find the set of their successors
33498
which are not in OPS, and set their bits in SUCC. Bits corresponding to
33499
--- a/src/gcc/ddg.h
33500
+++ b/src/gcc/ddg.h
33501
@@ -167,7 +167,7 @@
33502
};
33503
33504
33505
-ddg_ptr create_ddg (basic_block, int closing_branch_deps);
33506
+ddg_ptr create_ddg (basic_block, sbitmap);
33507
void free_ddg (ddg_ptr);
33508
33509
void print_ddg (FILE *, ddg_ptr);
27883
@@ -197,6 +197,11 @@
27884
}
27885
}
27886
27887
+ /* If a true dep edge enters the branch create an anti edge in the
27888
+ opposite direction to prevent the creation of reg-moves. */
27889
+ if ((DEP_TYPE (link) == REG_DEP_TRUE) && JUMP_P (dest_node->insn))
27890
+ create_ddg_dep_no_link (g, dest_node, src_node, ANTI_DEP, REG_DEP, 1);
27891
+
27892
latency = dep_cost (link);
27893
e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance);
27894
add_edge_to_ddg (g, e);
33510
27895
--- a/src/gcc/df-problems.c
33511
27896
+++ b/src/gcc/df-problems.c
33512
27897
@@ -3748,9 +3748,22 @@
33535
27920
bitmap_set_bit (defs, DF_REF_REGNO (def));
33536
27921
}
33537
27922
}
33538
@@ -3921,7 +3934,7 @@
27923
@@ -3903,13 +3916,9 @@
27924
the block, starting with the first one.
27925
----------------------------------------------------------------------------*/
27926
27927
-/* Apply the artificial uses and defs at the top of BB in a forwards
27928
- direction. ??? This is wrong; defs mark the point where a pseudo
27929
- becomes live when scanning forwards (unless a def is unused). Since
27930
- there are no REG_UNUSED notes for artificial defs, passes that
27931
- require artificial defs probably should not call this function
27932
- unless (as is the case for fwprop) they are correct when liveness
27933
- bitmaps are *under*estimated. */
27934
+/* Initialize the LIVE bitmap, which should be copied from DF_LIVE_IN or
27935
+ DF_LR_IN for basic block BB, for forward scanning by marking artificial
27936
+ defs live. */
27937
27938
void
27939
df_simulate_initialize_forwards (basic_block bb, bitmap live)
27940
@@ -3921,7 +3930,7 @@
33539
27941
{
33540
27942
df_ref def = *def_rec;
33541
27943
if (DF_REF_FLAGS (def) & DF_REF_AT_TOP)
33544
27946
}
33545
27947
}
33546
27948
33547
@@ -3942,7 +3955,7 @@
27949
@@ -3942,7 +3951,7 @@
33548
27950
while here the scan is performed forwards! So, first assume that the
33549
27951
def is live, and if this is not true REG_UNUSED notes will rectify the
33550
27952
situation. */
35067
29469
35068
29470
--- a/src/gcc/expr.c
35069
29471
+++ b/src/gcc/expr.c
29472
@@ -1537,7 +1537,7 @@
29473
if (nregs == 0)
29474
return;
29475
29476
- if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x))
29477
+ if (CONSTANT_P (x) && !targetm.legitimate_constant_p (mode, x))
29478
x = validize_mem (force_const_mem (mode, x));
29479
29480
/* See if the machine can do this with a load multiple insn. */
35070
29481
@@ -1749,7 +1749,7 @@
35071
29482
&& (!REG_P (tmps[i]) || GET_MODE (tmps[i]) != mode))
35072
29483
tmps[i] = extract_bit_field (tmps[i], bytelen * BITS_PER_UNIT,
35103
29514
NULL_RTX, copy_mode, copy_mode));
35104
29515
}
35105
29516
29517
@@ -2366,7 +2366,7 @@
29518
offset -= size;
29519
29520
cst = (*constfun) (constfundata, offset, mode);
29521
- if (!LEGITIMATE_CONSTANT_P (cst))
29522
+ if (!targetm.legitimate_constant_p (mode, cst))
29523
return 0;
29524
29525
if (!reverse)
35106
29526
@@ -2970,7 +2970,7 @@
35107
29527
}
35108
29528
35112
29532
}
35113
29533
35114
29534
/* A subroutine of emit_move_insn_1. Yet another lowpart generator.
29535
@@ -3440,7 +3440,7 @@
29536
29537
y_cst = y;
29538
29539
- if (!LEGITIMATE_CONSTANT_P (y))
29540
+ if (!targetm.legitimate_constant_p (mode, y))
29541
{
29542
y = force_const_mem (mode, y);
29543
29544
@@ -3496,7 +3496,7 @@
29545
29546
REAL_VALUE_FROM_CONST_DOUBLE (r, y);
29547
29548
- if (LEGITIMATE_CONSTANT_P (y))
29549
+ if (targetm.legitimate_constant_p (dstmode, y))
29550
oldcost = rtx_cost (y, SET, speed);
29551
else
29552
oldcost = rtx_cost (force_const_mem (dstmode, y), SET, speed);
29553
@@ -3519,7 +3519,7 @@
29554
29555
trunc_y = CONST_DOUBLE_FROM_REAL_VALUE (r, srcmode);
29556
29557
- if (LEGITIMATE_CONSTANT_P (trunc_y))
29558
+ if (targetm.legitimate_constant_p (srcmode, trunc_y))
29559
{
29560
/* Skip if the target needs extra instructions to perform
29561
the extension. */
29562
@@ -3932,7 +3932,7 @@
29563
by setting SKIP to 0. */
29564
skip = (reg_parm_stack_space == 0) ? 0 : not_stack;
29565
29566
- if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x))
29567
+ if (CONSTANT_P (x) && !targetm.legitimate_constant_p (mode, x))
29568
x = validize_mem (force_const_mem (mode, x));
29569
29570
/* If X is a hard register in a non-integer mode, copy it into a pseudo;
35115
29571
@@ -4233,6 +4233,13 @@
35116
29572
35117
29573
to_rtx = expand_normal (tem);
35138
29594
emit_insn (insn);
35139
29595
return;
35140
29596
}
35141
@@ -4730,7 +4740,10 @@
35142
/* If store_expr stores a DECL whose DECL_RTL(exp) == TARGET,
35143
but TARGET is not valid memory reference, TEMP will differ
35144
from TARGET although it is really the same location. */
35145
- && !(alt_rtl && rtx_equal_p (alt_rtl, target))
35146
+ && !(alt_rtl
35147
+ && rtx_equal_p (alt_rtl, target)
35148
+ && !side_effects_p (alt_rtl)
35149
+ && !side_effects_p (target))
35150
/* If there's nothing to copy, don't bother. Don't call
35151
expr_size unless necessary, because some front-ends (C++)
35152
expr_size-hook must not be given objects that are not
35153
@@ -5838,6 +5851,8 @@
29597
@@ -5841,6 +5851,8 @@
35154
29598
|| bitpos % GET_MODE_ALIGNMENT (mode))
35155
29599
&& SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (target)))
35156
29600
|| (bitpos % BITS_PER_UNIT != 0)))
35159
29603
/* If the RHS and field are a constant size and the size of the
35160
29604
RHS isn't the same size as the bitfield, we must use bitfield
35161
29605
operations. */
35162
@@ -5990,6 +6005,12 @@
29606
@@ -5993,6 +6005,12 @@
35163
29607
mode = DECL_MODE (field);
35164
29608
else if (DECL_MODE (field) == BLKmode)
35165
29609
blkmode_bitfield = true;
35172
29616
35173
29617
*punsignedp = DECL_UNSIGNED (field);
35174
29618
}
35175
@@ -7221,10 +7242,7 @@
29619
@@ -7224,10 +7242,7 @@
35176
29620
optab this_optab;
35177
29621
rtx subtarget, original_target;
35178
29622
int ignore;
35183
29627
location_t loc = ops->location;
35184
29628
tree treeop0, treeop1;
35185
29629
#define REDUCE_BIT_FIELD(expr) (reduce_bit_field \
35186
@@ -7244,7 +7262,8 @@
29630
@@ -7247,7 +7262,8 @@
35187
29631
exactly those that are valid in gimple expressions that aren't
35188
29632
GIMPLE_SINGLE_RHS (or invalid). */
35189
29633
gcc_assert (get_gimple_rhs_class (code) == GIMPLE_UNARY_RHS
35193
29637
35194
29638
ignore = (target == const0_rtx
35195
29639
|| ((CONVERT_EXPR_CODE_P (code)
35196
@@ -7419,58 +7438,6 @@
29640
@@ -7422,58 +7438,6 @@
35197
29641
fold_convert_loc (loc, ssizetype,
35198
29642
treeop1));
35199
29643
case PLUS_EXPR:
35252
29696
/* If we are adding a constant, a VAR_DECL that is sp, fp, or ap, and
35253
29697
something else, make sure we add the register to the constant and
35254
29698
then to the other thing. This case can occur during strength
35255
@@ -7585,57 +7552,6 @@
29699
@@ -7588,57 +7552,6 @@
35256
29700
return REDUCE_BIT_FIELD (simplify_gen_binary (PLUS, mode, op0, op1));
35257
29701
35258
29702
case MINUS_EXPR:
35310
29754
/* For initializers, we are allowed to return a MINUS of two
35311
29755
symbolic constants. Here we handle all cases when both operands
35312
29756
are constant. */
35313
@@ -7676,13 +7592,15 @@
29757
@@ -7679,13 +7592,15 @@
35314
29758
35315
29759
goto binop2;
35316
29760
35332
29776
/* If first operand is constant, swap them.
35333
29777
Thus the following special case checks need only
35334
29778
check the second operand. */
35335
@@ -7693,123 +7611,61 @@
29779
@@ -7696,123 +7611,61 @@
35336
29780
treeop1 = t1;
35337
29781
}
35338
29782
35483
29927
temp = expand_binop (mode, other_optab, op0, op1, target,
35484
29928
unsignedp, OPTAB_LIB_WIDEN);
35485
29929
hipart = gen_highpart (innermode, temp);
35486
@@ -7822,7 +7678,53 @@
29930
@@ -7825,7 +7678,53 @@
35487
29931
}
35488
29932
}
35489
29933
}
35538
29982
return REDUCE_BIT_FIELD (expand_mult (mode, op0, op1, target, unsignedp));
35539
29983
35540
29984
case TRUNC_DIV_EXPR:
35541
@@ -8308,6 +8210,8 @@
29985
@@ -8311,6 +8210,8 @@
35542
29986
location_t loc = EXPR_LOCATION (exp);
35543
29987
struct separate_ops ops;
35544
29988
tree treeop0, treeop1, treeop2;
35547
29991
35548
29992
type = TREE_TYPE (exp);
35549
29993
mode = TYPE_MODE (type);
35550
@@ -8420,15 +8324,17 @@
29994
@@ -8423,15 +8324,17 @@
35551
29995
base variable. This unnecessarily allocates a pseudo, see how we can
35552
29996
reuse it, if partition base vars have it set already. */
35553
29997
if (!currently_expanding_to_rtl)
35574
30018
goto expand_decl_rtl;
35575
30019
35576
30020
case PARM_DECL:
35577
@@ -8458,6 +8364,19 @@
30021
@@ -8461,6 +8364,19 @@
35578
30022
expand_decl_rtl:
35579
30023
gcc_assert (decl_rtl);
35580
30024
decl_rtl = copy_rtx (decl_rtl);
35594
30038
35595
30039
/* Ensure variable marked as used even if it doesn't go through
35596
30040
a parser. If it hasn't be used yet, write out an external
35597
@@ -8517,15 +8436,21 @@
30041
@@ -8520,15 +8436,21 @@
35598
30042
/* If the mode of DECL_RTL does not match that of the decl, it
35599
30043
must be a promoted value. We return a SUBREG of the wanted mode,
35600
30044
but mark it so that we know that it was already extended. */
35622
30066
gcc_assert (GET_MODE (decl_rtl) == pmode);
35623
30067
35624
30068
temp = gen_lowpart_SUBREG (mode, decl_rtl);
35625
@@ -8729,6 +8654,7 @@
30069
@@ -8732,6 +8654,7 @@
35626
30070
35627
30071
/* Nor can the insn generator. */
35628
30072
insn = GEN_FCN (icode) (reg, temp);
35630
30074
emit_insn (insn);
35631
30075
35632
30076
return reg;
35633
@@ -8941,6 +8867,7 @@
30077
@@ -8944,6 +8867,7 @@
35634
30078
HOST_WIDE_INT bitsize, bitpos;
35635
30079
tree offset;
35636
30080
int volatilep = 0, must_force_mem;
35638
30082
tree tem = get_inner_reference (exp, &bitsize, &bitpos, &offset,
35639
30083
&mode1, &unsignedp, &volatilep, true);
35640
30084
rtx orig_op0, memloc;
35641
@@ -8950,6 +8877,11 @@
30085
@@ -8953,6 +8877,11 @@
35642
30086
infinitely recurse. */
35643
30087
gcc_assert (tem != exp);
35644
30088
35650
30094
/* If TEM's type is a union of variable size, pass TARGET to the inner
35651
30095
computation, since it will need a temporary and TARGET is known
35652
30096
to have to do. This occurs in unchecked conversion in Ada. */
35653
@@ -8966,6 +8898,14 @@
30097
@@ -8969,6 +8898,14 @@
35654
30098
|| modifier == EXPAND_STACK_PARM)
35655
30099
? modifier : EXPAND_NORMAL);
35656
30100
35665
30109
mode2
35666
30110
= CONSTANT_P (op0) ? TYPE_MODE (TREE_TYPE (tem)) : GET_MODE (op0);
35667
30111
35668
@@ -9091,6 +9031,12 @@
30112
@@ -9014,7 +8951,7 @@
30113
constant and we don't need a memory reference. */
30114
if (CONSTANT_P (op0)
30115
&& mode2 != BLKmode
30116
- && LEGITIMATE_CONSTANT_P (op0)
30117
+ && targetm.legitimate_constant_p (mode2, op0)
30118
&& !must_force_mem)
30119
op0 = force_reg (mode2, op0);
30120
30121
@@ -9094,6 +9031,12 @@
35669
30122
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT
35670
30123
&& modifier != EXPAND_CONST_ADDRESS
35671
30124
&& modifier != EXPAND_INITIALIZER)
35678
30131
/* If the field isn't aligned enough to fetch as a memref,
35679
30132
fetch it as a bit field. */
35680
30133
|| (mode1 != BLKmode
35681
@@ -9151,7 +9097,7 @@
30134
@@ -9154,7 +9097,7 @@
35682
30135
if (MEM_P (op0) && REG_P (XEXP (op0, 0)))
35683
30136
mark_reg_pointer (XEXP (op0, 0), MEM_ALIGN (op0));
35684
30137
35700
30153
extern rtx expand_mult (enum machine_mode, rtx, rtx, rtx, int);
35701
30154
--- a/src/gcc/final.c
35702
30155
+++ b/src/gcc/final.c
35703
@@ -2428,7 +2428,7 @@
30156
@@ -2241,6 +2241,11 @@
30157
location_t loc;
30158
expanded_location expanded;
30159
30160
+ /* Make sure we flush any queued register saves in case this
30161
+ clobbers affected registers. */
30162
+ if (dwarf2out_do_frame ())
30163
+ dwarf2out_frame_debug (insn, false);
30164
+
30165
/* There's no telling what that did to the condition codes. */
30166
CC_STATUS_INIT;
30167
30168
@@ -2428,7 +2433,7 @@
35704
30169
delete_insn (insn);
35705
30170
break;
35706
30171
}
35711
30176
35712
30177
--- a/src/gcc/fold-const.c
35713
30178
+++ b/src/gcc/fold-const.c
35714
@@ -4217,11 +4217,16 @@
30179
@@ -2784,8 +2784,6 @@
30180
30181
case VOID_TYPE:
30182
tem = fold_ignored_result (arg);
30183
- if (TREE_CODE (tem) == MODIFY_EXPR)
30184
- goto fold_convert_exit;
30185
return fold_build1_loc (loc, NOP_EXPR, type, tem);
30186
30187
default:
30188
@@ -4217,11 +4215,16 @@
35715
30189
35716
30190
/* See if we can find a mode to refer to this field. We should be able to,
35717
30191
but fail if we can't. */
35733
30207
if (nmode == VOIDmode)
35734
30208
return 0;
35735
30209
35736
@@ -5751,6 +5756,76 @@
30210
@@ -5751,6 +5754,76 @@
35737
30211
const_binop (BIT_XOR_EXPR, c, temp, 0));
35738
30212
}
35739
30213
35810
30284
/* Find ways of folding logical expressions of LHS and RHS:
35811
30285
Try to merge two comparisons to the same innermost item.
35812
30286
Look for range tests like "ch >= '0' && ch <= '9'".
35813
@@ -12555,6 +12630,22 @@
30287
@@ -12555,6 +12628,22 @@
35814
30288
if (0 != (tem = fold_range_test (loc, code, type, op0, op1)))
35815
30289
return tem;
35816
30290
35833
30307
/* Check for the possibility of merging component references. If our
35834
30308
lhs is another similar operation, try to merge its rhs with our
35835
30309
rhs. Then try to merge our lhs and rhs. */
35836
--- a/src/gcc/fortran/ChangeLog
35837
+++ b/src/gcc/fortran/ChangeLog
35838
@@ -1,3 +1,98 @@
35839
+2011-04-05 Duncan Sands <baldrick@free.fr>
35840
+
35841
+ * f95-lang.c (build_builtin_fntypes): Swap frexp and scalbn parameter
35842
+ types.
35843
+
35844
+2011-03-13 Paul Thomas <pault@gcc.gnu.org>
35845
+
35846
+ PR fortran/47348
35847
+ * trans-array.c (get_array_ctor_all_strlen): Move up in file.
35848
+ (get_array_ctor_var_strlen): Add block dummy and add call to
35849
+ get_array_ctor_all_strlen instead of giving up on substrings.
35850
+ Call gcc_unreachable for default case.
35851
+ (get_array_ctor_strlen): Add extra argument to in call to
35852
+ get_array_ctor_var_strlen.
35853
+
35854
+2011-01-27 Tobias Burnus <burnus@net-b.de>
35855
+
35856
+ Backport from mainline
35857
+ 2011-02-26 Tobias Burnus <burnus@net-b.de>
35858
+
35859
+ PR fortran/47886
35860
+ * openmp.c (gfc_resolve_omp_directive): Resolve if()
35861
+ condition of OpenMP's task.
35862
+
35863
+2011-02-19 Tobias Burnus
35864
+
35865
+ PR fortran/47775
35866
+ * trans-expr.c (arrayfunc_assign_needs_temporary): Use
35867
+ esym to check whether the specific procedure returns an
35868
+ allocatable or pointer.
35869
+
35870
+2011-02-14 Tobias Burnus <burnus@net-b.de>
35871
+
35872
+ PR fortran/47569
35873
+ * interface.c (compare_parameter): Avoid ICE with
35874
+ character components.
35875
+
35876
+2011-01-25 Tobias Burnus <burnus@net-b.de>
35877
+
35878
+ Backport from mainline
35879
+ 2011-01-17 Jakub Jelinek <jakub@redhat.com>
35880
+
35881
+ PR fortran/47331
35882
+ * gfortran.h (struct gfc_omp_saved_state): New type.
35883
+ (gfc_omp_save_and_clear_state, gfc_omp_restore_state): New prototypes.
35884
+ * resolve.c (resolve_global_procedure): Call it around gfc_resolve
35885
+ call.
35886
+ * openmp.c (gfc_omp_save_and_clear_state, gfc_omp_restore_state): New
35887
+ functions.
35888
+
35889
+2011-01-25 Tobias Burnus <burnus@net-b.de>
35890
+
35891
+ PR fortran/47448
35892
+ * interface.c (gfc_check_operator_interface): Fix
35893
+ defined-assignment check.
35894
+
35895
+2011-01-21 Tobias Burnus <burnus@net-b.de>
35896
+
35897
+ PR fortran/47394
35898
+ * error.c (gfc_error_now, gfc_fatal_error, gfc_error_check):
35899
+ Use defined instead of magic number exit status codes.
35900
+ * scanner.c (include_line, gfc_new_file): Ditto.
35901
+ * gfortranspec.c (lang_specific_driver): Ditto.
35902
+
35903
+2011-01-16 Jakub Jelinek <jakub@redhat.com>
35904
+
35905
+ Backport from mainline
35906
+ 2010-12-14 Jakub Jelinek <jakub@redhat.com>
35907
+
35908
+ PR fortran/46874
35909
+ * trans-openmp.c (gfc_trans_omp_array_reduction): Handle allocatable
35910
+ dummy variables.
35911
+
35912
+2011-01-16 Thomas Koenig <tkoenig@gcc.gnu.org>
35913
+
35914
+ Backport from trunk
35915
+ PR fortran/45777
35916
+ * symbol.c (gfc_symbols_could_alias): Strip gfc_ prefix,
35917
+ make static and move in front of its only caller, to ...
35918
+ * trans-array.c (symbols_could_alias): ... here.
35919
+ Pass information about pointer and target status as
35920
+ arguments. Allocatable arrays don't alias anything
35921
+ unless they have the POINTER attribute.
35922
+ (gfc_could_be_alias): Keep track of pointer and target
35923
+ status when following references. Also check if typespecs
35924
+ of components match those of other components or symbols.
35925
+ * gfortran.h: Remove prototype for gfc_symbols_could_alias.
35926
+
35927
+2011-01-02 Thomas Koenig <tkoenig@gcc.gnu.org>
35928
+
35929
+ Backport from mainline
35930
+ PR fortran/45338
35931
+ * resolve.c (resolve_operator): Mark function for user-defined
35932
+ operator as referenced.
35933
+
35934
2010-12-16 Release Manager
35935
35936
* GCC 4.5.2 released.
35937
--- a/src/gcc/fortran/error.c
35938
+++ b/src/gcc/fortran/error.c
35939
@@ -939,7 +939,7 @@
35940
buffer_flag = i;
35941
35942
if (flag_fatal_errors)
35943
- exit (1);
35944
+ exit (FATAL_EXIT_CODE);
35945
}
35946
35947
35948
@@ -956,7 +956,7 @@
35949
error_print (_("Fatal Error:"), _(gmsgid), argp);
35950
va_end (argp);
35951
35952
- exit (3);
35953
+ exit (FATAL_EXIT_CODE);
35954
}
35955
35956
35957
@@ -1019,7 +1019,7 @@
35958
gfc_increment_error_count();
35959
35960
if (flag_fatal_errors)
35961
- exit (1);
35962
+ exit (FATAL_EXIT_CODE);
35963
}
35964
35965
return rc;
35966
--- a/src/gcc/fortran/f95-lang.c
35967
+++ b/src/gcc/fortran/f95-lang.c
35968
@@ -646,19 +646,20 @@
35969
/* type (*) (type, type) */
35970
tmp = tree_cons (NULL_TREE, type, tmp);
35971
fntype[1] = build_function_type (type, tmp);
35972
- /* type (*) (int, type) */
35973
+ /* type (*) (type, int) */
35974
tmp = tree_cons (NULL_TREE, integer_type_node, void_list_node);
35975
tmp = tree_cons (NULL_TREE, type, tmp);
35976
fntype[2] = build_function_type (type, tmp);
35977
/* type (*) (void) */
35978
fntype[3] = build_function_type (type, void_list_node);
35979
/* type (*) (type, &int) */
35980
- tmp = tree_cons (NULL_TREE, type, void_list_node);
35981
- tmp = tree_cons (NULL_TREE, build_pointer_type (integer_type_node), tmp);
35982
+ tmp = tree_cons (NULL_TREE, build_pointer_type (integer_type_node),
35983
+ void_list_node);
35984
+ tmp = tree_cons (NULL_TREE, type, tmp);
35985
fntype[4] = build_function_type (type, tmp);
35986
/* type (*) (type, int) */
35987
- tmp = tree_cons (NULL_TREE, type, void_list_node);
35988
- tmp = tree_cons (NULL_TREE, integer_type_node, tmp);
35989
+ tmp = tree_cons (NULL_TREE, integer_type_node, void_list_node);
35990
+ tmp = tree_cons (NULL_TREE, type, tmp);
35991
fntype[5] = build_function_type (type, tmp);
35992
}
35993
35994
--- a/src/gcc/fortran/gfortran.h
35995
+++ b/src/gcc/fortran/gfortran.h
35996
@@ -2483,8 +2483,6 @@
35997
int gfc_get_ha_symbol (const char *, gfc_symbol **);
35998
int gfc_get_ha_sym_tree (const char *, gfc_symtree **);
35999
36000
-int gfc_symbols_could_alias (gfc_symbol *, gfc_symbol *);
36001
-
36002
void gfc_undo_symbols (void);
36003
void gfc_commit_symbols (void);
36004
void gfc_commit_symbol (gfc_symbol *);
36005
@@ -2577,11 +2575,14 @@
36006
gfc_expr *gfc_get_parentheses (gfc_expr *);
36007
36008
/* openmp.c */
36009
+struct gfc_omp_saved_state { void *ptrs[2]; int ints[1]; };
36010
void gfc_free_omp_clauses (gfc_omp_clauses *);
36011
void gfc_resolve_omp_directive (gfc_code *, gfc_namespace *);
36012
void gfc_resolve_do_iterator (gfc_code *, gfc_symbol *);
36013
void gfc_resolve_omp_parallel_blocks (gfc_code *, gfc_namespace *);
36014
void gfc_resolve_omp_do_blocks (gfc_code *, gfc_namespace *);
36015
+void gfc_omp_save_and_clear_state (struct gfc_omp_saved_state *);
36016
+void gfc_omp_restore_state (struct gfc_omp_saved_state *);
36017
36018
/* expr.c */
36019
void gfc_free_actual_arglist (gfc_actual_arglist *);
36020
--- a/src/gcc/fortran/gfortranspec.c
36021
+++ b/src/gcc/fortran/gfortranspec.c
36022
@@ -375,7 +375,7 @@
36023
You may redistribute copies of GNU Fortran\n\
36024
under the terms of the GNU General Public License.\n\
36025
For more information about these matters, see the file named COPYING\n\n"));
36026
- exit (0);
36027
+ exit (SUCCESS_EXIT_CODE);
36028
break;
36029
36030
case OPTION_help:
36031
--- a/src/gcc/fortran/interface.c
36032
+++ b/src/gcc/fortran/interface.c
36033
@@ -624,11 +624,12 @@
36034
36035
/* Allowed are (per F2003, 12.3.2.1.2 Defined assignments):
36036
- First argument an array with different rank than second,
36037
- - Types and kinds do not conform, and
36038
+ - First argument is a scalar and second an array,
36039
+ - Types and kinds do not conform, or
36040
- First argument is of derived type. */
36041
if (sym->formal->sym->ts.type != BT_DERIVED
36042
&& sym->formal->sym->ts.type != BT_CLASS
36043
- && (r1 == 0 || r1 == r2)
36044
+ && (r2 == 0 || r1 == r2)
36045
&& (sym->formal->sym->ts.type == sym->formal->next->sym->ts.type
36046
|| (gfc_numeric_ts (&sym->formal->sym->ts)
36047
&& gfc_numeric_ts (&sym->formal->next->sym->ts))))
36048
@@ -1385,7 +1386,7 @@
36049
int ranks_must_agree, int is_elemental, locus *where)
36050
{
36051
gfc_ref *ref;
36052
- bool rank_check;
36053
+ bool rank_check, is_pointer;
36054
36055
/* If the formal arg has type BT_VOID, it's to one of the iso_c_binding
36056
procs c_f_pointer or c_f_procpointer, and we need to accept most
36057
@@ -1468,22 +1469,56 @@
36058
return 1;
36059
36060
/* At this point, we are considering a scalar passed to an array. This
36061
- is valid (cf. F95 12.4.1.1; F2003 12.4.1.2),
36062
+ is valid (cf. F95 12.4.1.1, F2003 12.4.1.2, and F2008 12.5.2.4),
36063
- if the actual argument is (a substring of) an element of a
36064
- non-assumed-shape/non-pointer array;
36065
- - (F2003) if the actual argument is of type character. */
36066
+ non-assumed-shape/non-pointer/non-polymorphic array; or
36067
+ - (F2003) if the actual argument is of type character of default/c_char
36068
+ kind. */
36069
+
36070
+ is_pointer = actual->expr_type == EXPR_VARIABLE
36071
+ ? actual->symtree->n.sym->attr.pointer : false;
36072
36073
for (ref = actual->ref; ref; ref = ref->next)
36074
- if (ref->type == REF_ARRAY && ref->u.ar.type == AR_ELEMENT)
36075
- break;
36076
+ {
36077
+ if (ref->type == REF_COMPONENT)
36078
+ is_pointer = ref->u.c.component->attr.pointer;
36079
+ else if (ref->type == REF_ARRAY && ref->u.ar.type == AR_ELEMENT
36080
+ && ref->u.ar.dimen > 0
36081
+ && (!ref->next
36082
+ || (ref->next->type == REF_SUBSTRING && !ref->next->next)))
36083
+ break;
36084
+ }
36085
36086
- /* Not an array element. */
36087
- if (formal->ts.type == BT_CHARACTER
36088
- && (ref == NULL
36089
- || (actual->expr_type == EXPR_VARIABLE
36090
- && (actual->symtree->n.sym->as->type == AS_ASSUMED_SHAPE
36091
- || actual->symtree->n.sym->attr.pointer))))
36092
+ if (actual->ts.type == BT_CLASS && actual->expr_type != EXPR_NULL)
36093
{
36094
+ if (where)
36095
+ gfc_error ("Polymorphic scalar passed to array dummy argument '%s' "
36096
+ "at %L", formal->name, &actual->where);
36097
+ return 0;
36098
+ }
36099
+
36100
+ if (actual->expr_type != EXPR_NULL && ref && actual->ts.type != BT_CHARACTER
36101
+ && (is_pointer || ref->u.ar.as->type == AS_ASSUMED_SHAPE))
36102
+ {
36103
+ if (where)
36104
+ gfc_error ("Element of assumed-shaped or pointer "
36105
+ "array passed to array dummy argument '%s' at %L",
36106
+ formal->name, &actual->where);
36107
+ return 0;
36108
+ }
36109
+
36110
+ if (actual->ts.type == BT_CHARACTER && actual->expr_type != EXPR_NULL
36111
+ && (!ref || is_pointer || ref->u.ar.as->type == AS_ASSUMED_SHAPE))
36112
+ {
36113
+ if (formal->ts.kind != 1 && (gfc_option.allow_std & GFC_STD_GNU) == 0)
36114
+ {
36115
+ if (where)
36116
+ gfc_error ("Extension: Scalar non-default-kind, non-C_CHAR-kind "
36117
+ "CHARACTER actual argument with array dummy argument "
36118
+ "'%s' at %L", formal->name, &actual->where);
36119
+ return 0;
36120
+ }
36121
+
36122
if (where && (gfc_option.allow_std & GFC_STD_F2003) == 0)
36123
{
36124
gfc_error ("Fortran 2003: Scalar CHARACTER actual argument with "
36125
@@ -1496,7 +1531,8 @@
36126
else
36127
return 1;
36128
}
36129
- else if (ref == NULL && actual->expr_type != EXPR_NULL)
36130
+
36131
+ if (ref == NULL && actual->expr_type != EXPR_NULL)
36132
{
36133
if (where)
36134
gfc_error ("Rank mismatch in argument '%s' at %L (%d and %d)",
36135
@@ -1505,17 +1541,6 @@
36136
return 0;
36137
}
36138
36139
- if (actual->expr_type == EXPR_VARIABLE
36140
- && actual->symtree->n.sym->as
36141
- && (actual->symtree->n.sym->as->type == AS_ASSUMED_SHAPE
36142
- || actual->symtree->n.sym->attr.pointer))
36143
- {
36144
- if (where)
36145
- gfc_error ("Element of assumed-shaped array passed to dummy "
36146
- "argument '%s' at %L", formal->name, &actual->where);
36147
- return 0;
36148
- }
36149
-
36150
return 1;
36151
}
36152
36153
--- a/src/gcc/fortran/openmp.c
36154
+++ b/src/gcc/fortran/openmp.c
36155
@@ -1363,6 +1363,31 @@
36156
}
36157
36158
36159
+/* Save and clear openmp.c private state. */
36160
+
36161
+void
36162
+gfc_omp_save_and_clear_state (struct gfc_omp_saved_state *state)
36163
+{
36164
+ state->ptrs[0] = omp_current_ctx;
36165
+ state->ptrs[1] = omp_current_do_code;
36166
+ state->ints[0] = omp_current_do_collapse;
36167
+ omp_current_ctx = NULL;
36168
+ omp_current_do_code = NULL;
36169
+ omp_current_do_collapse = 0;
36170
+}
36171
+
36172
+
36173
+/* Restore openmp.c private state from the saved state. */
36174
+
36175
+void
36176
+gfc_omp_restore_state (struct gfc_omp_saved_state *state)
36177
+{
36178
+ omp_current_ctx = (struct omp_context *) state->ptrs[0];
36179
+ omp_current_do_code = (gfc_code *) state->ptrs[1];
36180
+ omp_current_do_collapse = state->ints[0];
36181
+}
36182
+
36183
+
36184
/* Note a DO iterator variable. This is special in !$omp parallel
36185
construct, where they are predetermined private. */
36186
36187
@@ -1521,6 +1546,7 @@
36188
case EXEC_OMP_PARALLEL_SECTIONS:
36189
case EXEC_OMP_SECTIONS:
36190
case EXEC_OMP_SINGLE:
36191
+ case EXEC_OMP_TASK:
36192
if (code->ext.omp_clauses)
36193
resolve_omp_clauses (code);
36194
break;
36195
--- a/src/gcc/fortran/resolve.c
36196
+++ b/src/gcc/fortran/resolve.c
36197
@@ -1810,11 +1810,14 @@
36198
if (!gsym->ns->resolved)
36199
{
36200
gfc_dt_list *old_dt_list;
36201
+ struct gfc_omp_saved_state old_omp_state;
36202
36203
/* Stash away derived types so that the backend_decls do not
36204
get mixed up. */
36205
old_dt_list = gfc_derived_types;
36206
gfc_derived_types = NULL;
36207
+ /* And stash away openmp state. */
36208
+ gfc_omp_save_and_clear_state (&old_omp_state);
36209
36210
gfc_resolve (gsym->ns);
36211
36212
@@ -1824,6 +1827,8 @@
36213
36214
/* Restore the derived types of this namespace. */
36215
gfc_derived_types = old_dt_list;
36216
+ /* And openmp state. */
36217
+ gfc_omp_restore_state (&old_omp_state);
36218
}
36219
36220
/* Make sure that translation for the gsymbol occurs before
36221
@@ -3577,9 +3582,12 @@
36222
sprintf (msg, _("Operand of user operator '%s' at %%L is %s"),
36223
e->value.op.uop->name, gfc_typename (&op1->ts));
36224
else
36225
- sprintf (msg, _("Operands of user operator '%s' at %%L are %s/%s"),
36226
- e->value.op.uop->name, gfc_typename (&op1->ts),
36227
- gfc_typename (&op2->ts));
36228
+ {
36229
+ sprintf (msg, _("Operands of user operator '%s' at %%L are %s/%s"),
36230
+ e->value.op.uop->name, gfc_typename (&op1->ts),
36231
+ gfc_typename (&op2->ts));
36232
+ e->value.op.uop->op->sym->attr.referenced = 1;
36233
+ }
36234
36235
goto bad_op;
36236
36237
--- a/src/gcc/fortran/scanner.c
36238
+++ b/src/gcc/fortran/scanner.c
36239
@@ -1841,7 +1841,7 @@
36240
36241
filename = gfc_widechar_to_char (begin, -1);
36242
if (load_file (filename, NULL, false) == FAILURE)
36243
- exit (1);
36244
+ exit (FATAL_EXIT_CODE);
36245
36246
gfc_free (filename);
36247
return true;
36248
@@ -2045,7 +2045,7 @@
36249
printf ("%s:%3d %s\n", LOCATION_FILE (line_head->location),
36250
LOCATION_LINE (line_head->location), line_head->line);
36251
36252
- exit (0);
36253
+ exit (SUCCESS_EXIT_CODE);
36254
#endif
36255
36256
return result;
36257
--- a/src/gcc/fortran/symbol.c
36258
+++ b/src/gcc/fortran/symbol.c
36259
@@ -2733,41 +2733,6 @@
36260
return i;
36261
}
36262
36263
-/* Return true if both symbols could refer to the same data object. Does
36264
- not take account of aliasing due to equivalence statements. */
36265
-
36266
-int
36267
-gfc_symbols_could_alias (gfc_symbol *lsym, gfc_symbol *rsym)
36268
-{
36269
- /* Aliasing isn't possible if the symbols have different base types. */
36270
- if (gfc_compare_types (&lsym->ts, &rsym->ts) == 0)
36271
- return 0;
36272
-
36273
- /* Pointers can point to other pointers, target objects and allocatable
36274
- objects. Two allocatable objects cannot share the same storage. */
36275
- if (lsym->attr.pointer
36276
- && (rsym->attr.pointer || rsym->attr.allocatable || rsym->attr.target))
36277
- return 1;
36278
- if (lsym->attr.target && rsym->attr.pointer)
36279
- return 1;
36280
- if (lsym->attr.allocatable && rsym->attr.pointer)
36281
- return 1;
36282
-
36283
- /* Special case: Argument association, cf. F90 12.4.1.6, F2003 12.4.1.7
36284
- and F2008 12.5.2.13 items 3b and 4b. The pointer case (a) is already
36285
- checked above. */
36286
- if (lsym->attr.target && rsym->attr.target
36287
- && ((lsym->attr.dummy
36288
- && (!lsym->attr.dimension || lsym->as->type == AS_ASSUMED_SHAPE))
36289
- || (rsym->attr.dummy
36290
- && (!rsym->attr.dimension
36291
- || rsym->as->type == AS_ASSUMED_SHAPE))))
36292
- return 1;
36293
-
36294
- return 0;
36295
-}
36296
-
36297
-
36298
/* Undoes all the changes made to symbols in the current statement.
36299
This subroutine is made simpler due to the fact that attributes are
36300
never removed once added. */
36301
--- a/src/gcc/fortran/trans-array.c
36302
+++ b/src/gcc/fortran/trans-array.c
36303
@@ -1483,11 +1483,55 @@
36304
}
36305
36306
36307
+/* A catch-all to obtain the string length for anything that is not a
36308
+ a substring of non-constant length, a constant, array or variable. */
36309
+
36310
+static void
36311
+get_array_ctor_all_strlen (stmtblock_t *block, gfc_expr *e, tree *len)
36312
+{
36313
+ gfc_se se;
36314
+ gfc_ss *ss;
36315
+
36316
+ /* Don't bother if we already know the length is a constant. */
36317
+ if (*len && INTEGER_CST_P (*len))
36318
+ return;
36319
+
36320
+ if (!e->ref && e->ts.u.cl && e->ts.u.cl->length
36321
+ && e->ts.u.cl->length->expr_type == EXPR_CONSTANT)
36322
+ {
36323
+ /* This is easy. */
36324
+ gfc_conv_const_charlen (e->ts.u.cl);
36325
+ *len = e->ts.u.cl->backend_decl;
36326
+ }
36327
+ else
36328
+ {
36329
+ /* Otherwise, be brutal even if inefficient. */
36330
+ ss = gfc_walk_expr (e);
36331
+ gfc_init_se (&se, NULL);
36332
+
36333
+ /* No function call, in case of side effects. */
36334
+ se.no_function_call = 1;
36335
+ if (ss == gfc_ss_terminator)
36336
+ gfc_conv_expr (&se, e);
36337
+ else
36338
+ gfc_conv_expr_descriptor (&se, e, ss);
36339
+
36340
+ /* Fix the value. */
36341
+ *len = gfc_evaluate_now (se.string_length, &se.pre);
36342
+
36343
+ gfc_add_block_to_block (block, &se.pre);
36344
+ gfc_add_block_to_block (block, &se.post);
36345
+
36346
+ e->ts.u.cl->backend_decl = *len;
36347
+ }
36348
+}
36349
+
36350
+
36351
/* Figure out the string length of a variable reference expression.
36352
Used by get_array_ctor_strlen. */
36353
36354
static void
36355
-get_array_ctor_var_strlen (gfc_expr * expr, tree * len)
36356
+get_array_ctor_var_strlen (stmtblock_t *block, gfc_expr * expr, tree * len)
36357
{
36358
gfc_ref *ref;
36359
gfc_typespec *ts;
36360
@@ -1514,7 +1558,11 @@
36361
case REF_SUBSTRING:
36362
if (ref->u.ss.start->expr_type != EXPR_CONSTANT
36363
|| ref->u.ss.end->expr_type != EXPR_CONSTANT)
36364
- break;
36365
+ {
36366
+ /* Note that this might evaluate expr. */
36367
+ get_array_ctor_all_strlen (block, expr, len);
36368
+ return;
36369
+ }
36370
mpz_init_set_ui (char_len, 1);
36371
mpz_add (char_len, char_len, ref->u.ss.end->value.integer);
36372
mpz_sub (char_len, char_len, ref->u.ss.start->value.integer);
36373
@@ -1524,10 +1572,7 @@
36374
return;
36375
36376
default:
36377
- /* TODO: Substrings are tricky because we can't evaluate the
36378
- expression more than once. For now we just give up, and hope
36379
- we can figure it out elsewhere. */
36380
- return;
36381
+ gcc_unreachable ();
36382
}
36383
}
36384
36385
@@ -1535,49 +1580,6 @@
36386
}
36387
36388
36389
-/* A catch-all to obtain the string length for anything that is not a
36390
- constant, array or variable. */
36391
-static void
36392
-get_array_ctor_all_strlen (stmtblock_t *block, gfc_expr *e, tree *len)
36393
-{
36394
- gfc_se se;
36395
- gfc_ss *ss;
36396
-
36397
- /* Don't bother if we already know the length is a constant. */
36398
- if (*len && INTEGER_CST_P (*len))
36399
- return;
36400
-
36401
- if (!e->ref && e->ts.u.cl && e->ts.u.cl->length
36402
- && e->ts.u.cl->length->expr_type == EXPR_CONSTANT)
36403
- {
36404
- /* This is easy. */
36405
- gfc_conv_const_charlen (e->ts.u.cl);
36406
- *len = e->ts.u.cl->backend_decl;
36407
- }
36408
- else
36409
- {
36410
- /* Otherwise, be brutal even if inefficient. */
36411
- ss = gfc_walk_expr (e);
36412
- gfc_init_se (&se, NULL);
36413
-
36414
- /* No function call, in case of side effects. */
36415
- se.no_function_call = 1;
36416
- if (ss == gfc_ss_terminator)
36417
- gfc_conv_expr (&se, e);
36418
- else
36419
- gfc_conv_expr_descriptor (&se, e, ss);
36420
-
36421
- /* Fix the value. */
36422
- *len = gfc_evaluate_now (se.string_length, &se.pre);
36423
-
36424
- gfc_add_block_to_block (block, &se.pre);
36425
- gfc_add_block_to_block (block, &se.post);
36426
-
36427
- e->ts.u.cl->backend_decl = *len;
36428
- }
36429
-}
36430
-
36431
-
36432
/* Figure out the string length of a character array constructor.
36433
If len is NULL, don't calculate the length; this happens for recursive calls
36434
when a sub-array-constructor is an element but not at the first position,
36435
@@ -1619,7 +1621,7 @@
36436
case EXPR_VARIABLE:
36437
is_const = false;
36438
if (len)
36439
- get_array_ctor_var_strlen (c->expr, len);
36440
+ get_array_ctor_var_strlen (block, c->expr, len);
36441
break;
36442
36443
default:
36444
@@ -3389,6 +3391,37 @@
36445
}
36446
}
36447
36448
+/* Return true if both symbols could refer to the same data object. Does
36449
+ not take account of aliasing due to equivalence statements. */
36450
+
36451
+static int
36452
+symbols_could_alias (gfc_symbol *lsym, gfc_symbol *rsym, bool lsym_pointer,
36453
+ bool lsym_target, bool rsym_pointer, bool rsym_target)
36454
+{
36455
+ /* Aliasing isn't possible if the symbols have different base types. */
36456
+ if (gfc_compare_types (&lsym->ts, &rsym->ts) == 0)
36457
+ return 0;
36458
+
36459
+ /* Pointers can point to other pointers and target objects. */
36460
+
36461
+ if ((lsym_pointer && (rsym_pointer || rsym_target))
36462
+ || (rsym_pointer && (lsym_pointer || lsym_target)))
36463
+ return 1;
36464
+
36465
+ /* Special case: Argument association, cf. F90 12.4.1.6, F2003 12.4.1.7
36466
+ and F2008 12.5.2.13 items 3b and 4b. The pointer case (a) is already
36467
+ checked above. */
36468
+ if (lsym->attr.target && rsym->attr.target
36469
+ && ((lsym->attr.dummy
36470
+ && (!lsym->attr.dimension || lsym->as->type == AS_ASSUMED_SHAPE))
36471
+ || (rsym->attr.dummy
36472
+ && (!rsym->attr.dimension
36473
+ || rsym->as->type == AS_ASSUMED_SHAPE))))
36474
+ return 1;
36475
+
36476
+ return 0;
36477
+}
36478
+
36479
36480
/* Return true if the two SS could be aliased, i.e. both point to the same data
36481
object. */
36482
@@ -3401,10 +3434,18 @@
36483
gfc_ref *rref;
36484
gfc_symbol *lsym;
36485
gfc_symbol *rsym;
36486
+ bool lsym_pointer, lsym_target, rsym_pointer, rsym_target;
36487
36488
lsym = lss->expr->symtree->n.sym;
36489
rsym = rss->expr->symtree->n.sym;
36490
- if (gfc_symbols_could_alias (lsym, rsym))
36491
+
36492
+ lsym_pointer = lsym->attr.pointer;
36493
+ lsym_target = lsym->attr.target;
36494
+ rsym_pointer = rsym->attr.pointer;
36495
+ rsym_target = rsym->attr.target;
36496
+
36497
+ if (symbols_could_alias (lsym, rsym, lsym_pointer, lsym_target,
36498
+ rsym_pointer, rsym_target))
36499
return 1;
36500
36501
if (rsym->ts.type != BT_DERIVED
36502
@@ -3419,27 +3460,75 @@
36503
if (lref->type != REF_COMPONENT)
36504
continue;
36505
36506
- if (gfc_symbols_could_alias (lref->u.c.sym, rsym))
36507
+ lsym_pointer = lsym_pointer || lref->u.c.sym->attr.pointer;
36508
+ lsym_target = lsym_target || lref->u.c.sym->attr.target;
36509
+
36510
+ if (symbols_could_alias (lref->u.c.sym, rsym, lsym_pointer, lsym_target,
36511
+ rsym_pointer, rsym_target))
36512
return 1;
36513
36514
+ if ((lsym_pointer && (rsym_pointer || rsym_target))
36515
+ || (rsym_pointer && (lsym_pointer || lsym_target)))
36516
+ {
36517
+ if (gfc_compare_types (&lref->u.c.component->ts,
36518
+ &rsym->ts))
36519
+ return 1;
36520
+ }
36521
+
36522
for (rref = rss->expr->ref; rref != rss->data.info.ref;
36523
rref = rref->next)
36524
{
36525
if (rref->type != REF_COMPONENT)
36526
continue;
36527
36528
- if (gfc_symbols_could_alias (lref->u.c.sym, rref->u.c.sym))
36529
+ rsym_pointer = rsym_pointer || rref->u.c.sym->attr.pointer;
36530
+ rsym_target = lsym_target || rref->u.c.sym->attr.target;
36531
+
36532
+ if (symbols_could_alias (lref->u.c.sym, rref->u.c.sym,
36533
+ lsym_pointer, lsym_target,
36534
+ rsym_pointer, rsym_target))
36535
return 1;
36536
+
36537
+ if ((lsym_pointer && (rsym_pointer || rsym_target))
36538
+ || (rsym_pointer && (lsym_pointer || lsym_target)))
36539
+ {
36540
+ if (gfc_compare_types (&lref->u.c.component->ts,
36541
+ &rref->u.c.sym->ts))
36542
+ return 1;
36543
+ if (gfc_compare_types (&lref->u.c.sym->ts,
36544
+ &rref->u.c.component->ts))
36545
+ return 1;
36546
+ if (gfc_compare_types (&lref->u.c.component->ts,
36547
+ &rref->u.c.component->ts))
36548
+ return 1;
36549
+ }
36550
}
36551
}
36552
36553
+ lsym_pointer = lsym->attr.pointer;
36554
+ lsym_target = lsym->attr.target;
36555
+ lsym_pointer = lsym->attr.pointer;
36556
+ lsym_target = lsym->attr.target;
36557
+
36558
for (rref = rss->expr->ref; rref != rss->data.info.ref; rref = rref->next)
36559
{
36560
if (rref->type != REF_COMPONENT)
36561
break;
36562
36563
- if (gfc_symbols_could_alias (rref->u.c.sym, lsym))
36564
+ rsym_pointer = rsym_pointer || rref->u.c.sym->attr.pointer;
36565
+ rsym_target = lsym_target || rref->u.c.sym->attr.target;
36566
+
36567
+ if (symbols_could_alias (rref->u.c.sym, lsym,
36568
+ lsym_pointer, lsym_target,
36569
+ rsym_pointer, rsym_target))
36570
return 1;
36571
+
36572
+ if ((lsym_pointer && (rsym_pointer || rsym_target))
36573
+ || (rsym_pointer && (lsym_pointer || lsym_target)))
36574
+ {
36575
+ if (gfc_compare_types (&lsym->ts, &rref->u.c.component->ts))
36576
+ return 1;
36577
+ }
36578
}
36579
36580
return 0;
36581
--- a/src/gcc/fortran/trans-expr.c
36582
+++ b/src/gcc/fortran/trans-expr.c
36583
@@ -5051,9 +5051,13 @@
36584
if (gfc_ref_needs_temporary_p (expr1->ref))
36585
return true;
36586
36587
- /* Functions returning pointers need temporaries. */
36588
- if (expr2->symtree->n.sym->attr.pointer
36589
- || expr2->symtree->n.sym->attr.allocatable)
36590
+ /* Functions returning pointers or allocatables need temporaries. */
36591
+ c = expr2->value.function.esym
36592
+ ? (expr2->value.function.esym->attr.pointer
36593
+ || expr2->value.function.esym->attr.allocatable)
36594
+ : (expr2->symtree->n.sym->attr.pointer
36595
+ || expr2->symtree->n.sym->attr.allocatable);
36596
+ if (c)
36597
return true;
36598
36599
/* Character array functions need temporaries unless the
36600
--- a/src/gcc/fortran/trans-openmp.c
36601
+++ b/src/gcc/fortran/trans-openmp.c
36602
@@ -480,13 +480,23 @@
36603
gfc_symbol init_val_sym, outer_sym, intrinsic_sym;
36604
gfc_expr *e1, *e2, *e3, *e4;
36605
gfc_ref *ref;
36606
- tree decl, backend_decl, stmt;
36607
+ tree decl, backend_decl, stmt, type, outer_decl;
36608
locus old_loc = gfc_current_locus;
36609
const char *iname;
36610
gfc_try t;
36611
36612
decl = OMP_CLAUSE_DECL (c);
36613
gfc_current_locus = where;
36614
+ type = TREE_TYPE (decl);
36615
+ outer_decl = create_tmp_var_raw (type, NULL);
36616
+ if (TREE_CODE (decl) == PARM_DECL
36617
+ && TREE_CODE (type) == REFERENCE_TYPE
36618
+ && GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (type))
36619
+ && GFC_TYPE_ARRAY_AKIND (TREE_TYPE (type)) == GFC_ARRAY_ALLOCATABLE)
36620
+ {
36621
+ decl = build_fold_indirect_ref (decl);
36622
+ type = TREE_TYPE (type);
36623
+ }
36624
36625
/* Create a fake symbol for init value. */
36626
memset (&init_val_sym, 0, sizeof (init_val_sym));
36627
@@ -505,7 +515,9 @@
36628
outer_sym.attr.dummy = 0;
36629
outer_sym.attr.result = 0;
36630
outer_sym.attr.flavor = FL_VARIABLE;
36631
- outer_sym.backend_decl = create_tmp_var_raw (TREE_TYPE (decl), NULL);
36632
+ outer_sym.backend_decl = outer_decl;
36633
+ if (decl != OMP_CLAUSE_DECL (c))
36634
+ outer_sym.backend_decl = build_fold_indirect_ref (outer_decl);
36635
36636
/* Create fake symtrees for it. */
36637
symtree1 = gfc_new_symtree (&root1, sym->name);
36638
@@ -622,12 +634,12 @@
36639
36640
/* Create the init statement list. */
36641
pushlevel (0);
36642
- if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (decl))
36643
- && GFC_TYPE_ARRAY_AKIND (TREE_TYPE (decl)) == GFC_ARRAY_ALLOCATABLE)
36644
+ if (GFC_DESCRIPTOR_TYPE_P (type)
36645
+ && GFC_TYPE_ARRAY_AKIND (type) == GFC_ARRAY_ALLOCATABLE)
36646
{
36647
/* If decl is an allocatable array, it needs to be allocated
36648
with the same bounds as the outer var. */
36649
- tree type = TREE_TYPE (decl), rank, size, esize, ptr;
36650
+ tree rank, size, esize, ptr;
36651
stmtblock_t block;
36652
36653
gfc_start_block (&block);
36654
@@ -663,8 +675,8 @@
36655
36656
/* Create the merge statement list. */
36657
pushlevel (0);
36658
- if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (decl))
36659
- && GFC_TYPE_ARRAY_AKIND (TREE_TYPE (decl)) == GFC_ARRAY_ALLOCATABLE)
36660
+ if (GFC_DESCRIPTOR_TYPE_P (type)
36661
+ && GFC_TYPE_ARRAY_AKIND (type) == GFC_ARRAY_ALLOCATABLE)
36662
{
36663
/* If decl is an allocatable array, it needs to be deallocated
36664
afterwards. */
36665
@@ -684,7 +696,7 @@
36666
OMP_CLAUSE_REDUCTION_MERGE (c) = stmt;
36667
36668
/* And stick the placeholder VAR_DECL into the clause as well. */
36669
- OMP_CLAUSE_REDUCTION_PLACEHOLDER (c) = outer_sym.backend_decl;
36670
+ OMP_CLAUSE_REDUCTION_PLACEHOLDER (c) = outer_decl;
36671
36672
gfc_current_locus = old_loc;
36673
36674
30310
--- a/src/gcc/function.c
36675
30311
+++ b/src/gcc/function.c
36676
30312
@@ -147,9 +147,6 @@
39676
33312
#define YY_MORE_ADJ 0
39677
33313
#define YY_RESTORE_YY_MORE_OFFSET
39678
33314
char *yytext;
39679
-#line 1 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39680
+#line 1 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33315
-#line 1 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33316
+#line 1 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39681
33317
/* -*- indented-text -*- */
39682
33318
/* Process source files and output type information.
39683
33319
Copyright (C) 2002, 2003, 2004, 2005, 2007, 2008, 2009
39685
33321
along with GCC; see the file COPYING3. If not see
39686
33322
<http://www.gnu.org/licenses/>. */
39687
33323
#define YY_NO_INPUT 1
39688
-#line 25 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39689
+#line 25 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33324
-#line 25 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33325
+#line 25 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39690
33326
#include "bconfig.h"
39691
33327
#include "system.h"
39692
33328
39734
33370
register char *yy_cp, *yy_bp;
39735
33371
register int yy_act;
39736
33372
39737
-#line 59 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39738
+#line 59 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33373
-#line 59 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33374
+#line 59 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39739
33375
39740
33376
/* Do this on entry to yylex(): */
39741
33377
*yylval = 0;
39768
33404
(yy_c_buf_p) = yy_cp -= 1;
39769
33405
YY_DO_BEFORE_ACTION; /* set up yytext again */
39770
33406
YY_RULE_SETUP
39771
-#line 70 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39772
+#line 70 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33407
-#line 70 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33408
+#line 70 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39773
33409
{
39774
33410
BEGIN(in_struct);
39775
33411
return TYPEDEF;
39777
33413
(yy_c_buf_p) = yy_cp -= 1;
39778
33414
YY_DO_BEFORE_ACTION; /* set up yytext again */
39779
33415
YY_RULE_SETUP
39780
-#line 74 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39781
+#line 74 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33416
-#line 74 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33417
+#line 74 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39782
33418
{
39783
33419
BEGIN(in_struct);
39784
33420
return STRUCT;
39786
33422
(yy_c_buf_p) = yy_cp -= 1;
39787
33423
YY_DO_BEFORE_ACTION; /* set up yytext again */
39788
33424
YY_RULE_SETUP
39789
-#line 78 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39790
+#line 78 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33425
-#line 78 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33426
+#line 78 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39791
33427
{
39792
33428
BEGIN(in_struct);
39793
33429
return UNION;
39795
33431
(yy_c_buf_p) = yy_cp -= 1;
39796
33432
YY_DO_BEFORE_ACTION; /* set up yytext again */
39797
33433
YY_RULE_SETUP
39798
-#line 82 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39799
+#line 82 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33434
-#line 82 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33435
+#line 82 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39800
33436
{
39801
33437
BEGIN(in_struct);
39802
33438
return EXTERN;
39804
33440
(yy_c_buf_p) = yy_cp -= 1;
39805
33441
YY_DO_BEFORE_ACTION; /* set up yytext again */
39806
33442
YY_RULE_SETUP
39807
-#line 86 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39808
+#line 86 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33443
-#line 86 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33444
+#line 86 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39809
33445
{
39810
33446
BEGIN(in_struct);
39811
33447
return STATIC;
39813
33449
(yy_c_buf_p) = yy_cp -= 1;
39814
33450
YY_DO_BEFORE_ACTION; /* set up yytext again */
39815
33451
YY_RULE_SETUP
39816
-#line 91 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39817
+#line 91 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33452
-#line 91 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33453
+#line 91 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39818
33454
{
39819
33455
BEGIN(in_struct);
39820
33456
return DEFVEC_OP;
39822
33458
(yy_c_buf_p) = yy_cp -= 1;
39823
33459
YY_DO_BEFORE_ACTION; /* set up yytext again */
39824
33460
YY_RULE_SETUP
39825
-#line 95 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39826
+#line 95 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33461
-#line 95 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33462
+#line 95 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39827
33463
{
39828
33464
BEGIN(in_struct);
39829
33465
return DEFVEC_I;
39831
33467
(yy_c_buf_p) = yy_cp -= 1;
39832
33468
YY_DO_BEFORE_ACTION; /* set up yytext again */
39833
33469
YY_RULE_SETUP
39834
-#line 99 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39835
+#line 99 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33470
-#line 99 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33471
+#line 99 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39836
33472
{
39837
33473
BEGIN(in_struct);
39838
33474
return DEFVEC_ALLOC;
39840
33476
39841
33477
case 9:
39842
33478
YY_RULE_SETUP
39843
-#line 107 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39844
+#line 107 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33479
-#line 107 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33480
+#line 107 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39845
33481
{ BEGIN(in_struct_comment); }
39846
33482
YY_BREAK
39847
33483
case 10:
39848
33484
/* rule 10 can match eol */
39849
33485
YY_RULE_SETUP
39850
-#line 109 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39851
+#line 109 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33486
-#line 109 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33487
+#line 109 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39852
33488
{ update_lineno (yytext, yyleng); }
39853
33489
YY_BREAK
39854
33490
case 11:
39855
33491
/* rule 11 can match eol */
39856
33492
YY_RULE_SETUP
39857
-#line 110 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39858
+#line 110 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33493
-#line 110 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33494
+#line 110 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39859
33495
{ lexer_line.line++; }
39860
33496
YY_BREAK
39861
33497
case 12:
39863
33499
(yy_c_buf_p) = yy_cp = yy_bp + 5;
39864
33500
YY_DO_BEFORE_ACTION; /* set up yytext again */
39865
33501
YY_RULE_SETUP
39866
-#line 112 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39867
+#line 112 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33502
-#line 112 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33503
+#line 112 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39868
33504
/* don't care */
39869
33505
YY_BREAK
39870
33506
case 13:
39872
33508
(yy_c_buf_p) = yy_cp = yy_bp + 3;
39873
33509
YY_DO_BEFORE_ACTION; /* set up yytext again */
39874
33510
YY_RULE_SETUP
39875
-#line 113 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39876
+#line 113 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33511
-#line 113 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33512
+#line 113 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39877
33513
{ return GTY_TOKEN; }
39878
33514
YY_BREAK
39879
33515
case 14:
39881
33517
(yy_c_buf_p) = yy_cp = yy_bp + 3;
39882
33518
YY_DO_BEFORE_ACTION; /* set up yytext again */
39883
33519
YY_RULE_SETUP
39884
-#line 114 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39885
+#line 114 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33520
-#line 114 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33521
+#line 114 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39886
33522
{ return VEC_TOKEN; }
39887
33523
YY_BREAK
39888
33524
case 15:
39890
33526
(yy_c_buf_p) = yy_cp = yy_bp + 5;
39891
33527
YY_DO_BEFORE_ACTION; /* set up yytext again */
39892
33528
YY_RULE_SETUP
39893
-#line 115 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39894
+#line 115 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33529
-#line 115 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33530
+#line 115 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39895
33531
{ return UNION; }
39896
33532
YY_BREAK
39897
33533
case 16:
39899
33535
(yy_c_buf_p) = yy_cp = yy_bp + 6;
39900
33536
YY_DO_BEFORE_ACTION; /* set up yytext again */
39901
33537
YY_RULE_SETUP
39902
-#line 116 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39903
+#line 116 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33538
-#line 116 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33539
+#line 116 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39904
33540
{ return STRUCT; }
39905
33541
YY_BREAK
39906
33542
case 17:
39908
33544
(yy_c_buf_p) = yy_cp = yy_bp + 4;
39909
33545
YY_DO_BEFORE_ACTION; /* set up yytext again */
39910
33546
YY_RULE_SETUP
39911
-#line 117 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39912
+#line 117 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33547
-#line 117 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33548
+#line 117 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39913
33549
{ return ENUM; }
39914
33550
YY_BREAK
39915
33551
case 18:
39917
33553
(yy_c_buf_p) = yy_cp = yy_bp + 9;
39918
33554
YY_DO_BEFORE_ACTION; /* set up yytext again */
39919
33555
YY_RULE_SETUP
39920
-#line 118 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39921
+#line 118 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33556
-#line 118 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33557
+#line 118 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39922
33558
{ return PTR_ALIAS; }
39923
33559
YY_BREAK
39924
33560
case 19:
39926
33562
(yy_c_buf_p) = yy_cp = yy_bp + 10;
39927
33563
YY_DO_BEFORE_ACTION; /* set up yytext again */
39928
33564
YY_RULE_SETUP
39929
-#line 119 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39930
+#line 119 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33565
-#line 119 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33566
+#line 119 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39931
33567
{ return NESTED_PTR; }
39932
33568
YY_BREAK
39933
33569
case 20:
39934
33570
YY_RULE_SETUP
39935
-#line 120 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39936
+#line 120 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33571
-#line 120 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33572
+#line 120 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39937
33573
{ return NUM; }
39938
33574
YY_BREAK
39939
33575
case 21:
39941
33577
(yy_c_buf_p) = yy_cp -= 1;
39942
33578
YY_DO_BEFORE_ACTION; /* set up yytext again */
39943
33579
YY_RULE_SETUP
39944
-#line 121 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39945
+#line 121 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33580
-#line 121 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33581
+#line 121 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39946
33582
{
39947
33583
*yylval = XDUPVAR (const char, yytext, yyleng, yyleng+1);
39948
33584
return PARAM_IS;
39950
33586
*yy_cp = (yy_hold_char); /* undo effects of setting up yytext */
39951
33587
(yy_c_buf_p) = yy_cp -= 1;
39952
33588
YY_DO_BEFORE_ACTION; /* set up yytext again */
39953
-#line 127 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39954
+#line 127 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33589
-#line 127 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33590
+#line 127 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39955
33591
case 23:
39956
33592
/* rule 23 can match eol */
39957
33593
YY_RULE_SETUP
39958
-#line 127 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39959
+#line 127 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33594
-#line 127 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33595
+#line 127 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39960
33596
{
39961
33597
size_t len;
39962
33598
39964
33600
(yy_c_buf_p) = yy_cp -= 1;
39965
33601
YY_DO_BEFORE_ACTION; /* set up yytext again */
39966
33602
YY_RULE_SETUP
39967
-#line 139 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39968
+#line 139 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33603
-#line 139 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33604
+#line 139 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39969
33605
{
39970
33606
*yylval = XDUPVAR (const char, yytext, yyleng, yyleng+1);
39971
33607
return ID;
39973
33609
case 25:
39974
33610
/* rule 25 can match eol */
39975
33611
YY_RULE_SETUP
39976
-#line 144 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39977
+#line 144 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33612
-#line 144 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33613
+#line 144 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39978
33614
{
39979
33615
*yylval = XDUPVAR (const char, yytext+1, yyleng-2, yyleng-1);
39980
33616
return STRING;
39982
33618
case 26:
39983
33619
/* rule 26 can match eol */
39984
33620
YY_RULE_SETUP
39985
-#line 149 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39986
+#line 149 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33621
-#line 149 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33622
+#line 149 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39987
33623
{
39988
33624
*yylval = XDUPVAR (const char, yytext+1, yyleng-2, yyleng-1);
39989
33625
return ARRAY;
39991
33627
case 27:
39992
33628
/* rule 27 can match eol */
39993
33629
YY_RULE_SETUP
39994
-#line 153 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
39995
+#line 153 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33630
-#line 153 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33631
+#line 153 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
39996
33632
{
39997
33633
*yylval = XDUPVAR (const char, yytext+1, yyleng-2, yyleng);
39998
33634
return CHAR;
40000
33636
YY_BREAK
40001
33637
case 28:
40002
33638
YY_RULE_SETUP
40003
-#line 158 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40004
+#line 158 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33639
-#line 158 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33640
+#line 158 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40005
33641
{ return ELLIPSIS; }
40006
33642
YY_BREAK
40007
33643
case 29:
40008
33644
YY_RULE_SETUP
40009
-#line 159 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40010
+#line 159 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33645
-#line 159 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33646
+#line 159 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40011
33647
{ return yytext[0]; }
40012
33648
YY_BREAK
40013
33649
/* ignore pp-directives */
40014
33650
case 30:
40015
33651
/* rule 30 can match eol */
40016
33652
YY_RULE_SETUP
40017
-#line 162 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40018
+#line 162 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33653
-#line 162 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33654
+#line 162 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40019
33655
{lexer_line.line++;}
40020
33656
YY_BREAK
40021
33657
case 31:
40022
33658
YY_RULE_SETUP
40023
-#line 164 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40024
+#line 164 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33659
-#line 164 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33660
+#line 164 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40025
33661
{
40026
33662
error_at_line (&lexer_line, "unexpected character `%s'", yytext);
40027
33663
}
40029
33665
40030
33666
case 32:
40031
33667
YY_RULE_SETUP
40032
-#line 169 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40033
+#line 169 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33668
-#line 169 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33669
+#line 169 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40034
33670
{ BEGIN(in_comment); }
40035
33671
YY_BREAK
40036
33672
case 33:
40037
33673
/* rule 33 can match eol */
40038
33674
YY_RULE_SETUP
40039
-#line 170 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40040
+#line 170 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33675
-#line 170 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33676
+#line 170 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40041
33677
{ lexer_line.line++; }
40042
33678
YY_BREAK
40043
33679
case 34:
40044
-#line 172 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40045
+#line 172 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33680
-#line 172 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33681
+#line 172 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40046
33682
case 35:
40047
33683
/* rule 35 can match eol */
40048
-#line 173 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40049
+#line 173 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33684
-#line 173 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33685
+#line 173 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40050
33686
case 36:
40051
33687
/* rule 36 can match eol */
40052
33688
YY_RULE_SETUP
40053
-#line 173 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40054
+#line 173 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33689
-#line 173 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33690
+#line 173 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40055
33691
/* do nothing */
40056
33692
YY_BREAK
40057
33693
case 37:
40058
33694
/* rule 37 can match eol */
40059
33695
YY_RULE_SETUP
40060
-#line 174 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40061
+#line 174 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33696
-#line 174 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33697
+#line 174 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40062
33698
{ update_lineno (yytext, yyleng); }
40063
33699
YY_BREAK
40064
33700
case 38:
40066
33702
(yy_c_buf_p) = yy_cp = yy_bp + 1;
40067
33703
YY_DO_BEFORE_ACTION; /* set up yytext again */
40068
33704
YY_RULE_SETUP
40069
-#line 175 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40070
+#line 175 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33705
-#line 175 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33706
+#line 175 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40071
33707
/* do nothing */
40072
33708
YY_BREAK
40073
33709
40074
33710
case 39:
40075
33711
/* rule 39 can match eol */
40076
33712
YY_RULE_SETUP
40077
-#line 178 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40078
+#line 178 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33713
-#line 178 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33714
+#line 178 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40079
33715
{ lexer_line.line++; }
40080
33716
YY_BREAK
40081
33717
case 40:
40082
-#line 180 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40083
+#line 180 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33718
-#line 180 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33719
+#line 180 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40084
33720
case 41:
40085
33721
YY_RULE_SETUP
40086
-#line 180 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40087
+#line 180 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33722
-#line 180 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33723
+#line 180 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40088
33724
/* do nothing */
40089
33725
YY_BREAK
40090
33726
case 42:
40092
33728
(yy_c_buf_p) = yy_cp = yy_bp + 1;
40093
33729
YY_DO_BEFORE_ACTION; /* set up yytext again */
40094
33730
YY_RULE_SETUP
40095
-#line 181 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40096
+#line 181 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33731
-#line 181 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33732
+#line 181 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40097
33733
/* do nothing */
40098
33734
YY_BREAK
40099
33735
40100
33736
case 43:
40101
33737
YY_RULE_SETUP
40102
-#line 183 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40103
+#line 183 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33738
-#line 183 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33739
+#line 183 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40104
33740
{ BEGIN(INITIAL); }
40105
33741
YY_BREAK
40106
33742
case 44:
40107
33743
YY_RULE_SETUP
40108
-#line 184 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40109
+#line 184 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33744
-#line 184 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33745
+#line 184 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40110
33746
{ BEGIN(in_struct); }
40111
33747
YY_BREAK
40112
33748
case 45:
40113
-#line 187 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40114
+#line 187 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33749
-#line 187 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33750
+#line 187 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40115
33751
case 46:
40116
33752
YY_RULE_SETUP
40117
-#line 187 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40118
+#line 187 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33753
-#line 187 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33754
+#line 187 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40119
33755
{
40120
33756
error_at_line (&lexer_line,
40121
33757
"unterminated comment or string; unexpected EOF");
40123
33759
case 47:
40124
33760
/* rule 47 can match eol */
40125
33761
YY_RULE_SETUP
40126
-#line 192 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40127
+#line 192 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33762
-#line 192 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33763
+#line 192 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40128
33764
/* do nothing */
40129
33765
YY_BREAK
40130
33766
case 48:
40131
33767
YY_RULE_SETUP
40132
-#line 194 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40133
+#line 194 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33768
-#line 194 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33769
+#line 194 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40134
33770
YY_FATAL_ERROR( "flex scanner jammed" );
40135
33771
YY_BREAK
40136
33772
-#line 1642 "gengtype-lex.c"
40176
33812
40177
33813
#define YYTABLES_NAME "yytables"
40178
33814
40179
-#line 194 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l"
40180
+#line 194 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.04-0/gcc/gengtype-lex.l"
33815
-#line 194 "/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/gengtype-lex.l"
33816
+#line 194 "/home/ams/tmp/linaro/gcc-4.5/gcc-linaro-4.5-2011.05-0/gcc/gengtype-lex.l"
40181
33817
40182
33818
40183
33819
40540
34176
+ enum tree_code, tree, tree);
40541
34177
+
40542
34178
#endif /* GCC_GIMPLE_H */
40543
--- a/src/gcc/graphite-sese-to-poly.c
40544
+++ b/src/gcc/graphite-sese-to-poly.c
40545
@@ -715,7 +715,7 @@
40546
gcc_assert (TREE_CODE (e) == INTEGER_CST);
40547
40548
value_init (val);
40549
- value_set_si (val, int_cst_value (e));
40550
+ tree_int_to_gmp (e, val);
40551
add_value_to_dim (l, expr, val);
40552
value_clear (val);
40553
}
40554
@@ -729,16 +729,13 @@
40555
{
40556
Value val;
40557
ppl_Coefficient_t coef;
40558
- int v = int_cst_value (cst);
40559
+ tree type = TREE_TYPE (cst);
40560
40561
value_init (val);
40562
- value_set_si (val, 0);
40563
40564
/* Necessary to not get "-1 = 2^n - 1". */
40565
- if (v < 0)
40566
- value_sub_int (val, val, -v);
40567
- else
40568
- value_add_int (val, val, v);
40569
+ mpz_set_double_int (val, double_int_sext (tree_to_double_int (cst),
40570
+ TYPE_PRECISION (type)), false);
40571
40572
value_multiply (val, val, k);
40573
ppl_new_Coefficient (&coef);
40574
@@ -816,7 +813,7 @@
40575
Value val;
40576
gcc_assert (host_integerp (TREE_OPERAND (e, 1), 0));
40577
value_init (val);
40578
- value_set_si (val, int_cst_value (TREE_OPERAND (e, 1)));
40579
+ tree_int_to_gmp (TREE_OPERAND (e, 1), val);
40580
value_multiply (val, val, k);
40581
scan_tree_for_params (s, TREE_OPERAND (e, 0), c, val);
40582
value_clear (val);
40583
@@ -831,7 +828,7 @@
40584
Value val;
40585
gcc_assert (host_integerp (TREE_OPERAND (e, 0), 0));
40586
value_init (val);
40587
- value_set_si (val, int_cst_value (TREE_OPERAND (e, 0)));
40588
+ tree_int_to_gmp (TREE_OPERAND (e, 0), val);
40589
value_multiply (val, val, k);
40590
scan_tree_for_params (s, TREE_OPERAND (e, 1), c, val);
40591
value_clear (val);
40592
@@ -1717,10 +1714,13 @@
40593
/* subscript - low >= 0 */
40594
if (host_integerp (low, 0))
40595
{
40596
+ tree minus_low;
40597
+
40598
ppl_new_Linear_Expression_with_dimension (&expr, accessp_nb_dims);
40599
ppl_set_coef (expr, subscript, 1);
40600
40601
- ppl_set_inhomogeneous (expr, -int_cst_value (low));
40602
+ minus_low = fold_build1 (NEGATE_EXPR, TREE_TYPE (low), low);
40603
+ ppl_set_inhomogeneous_tree (expr, minus_low);
40604
40605
ppl_new_Constraint (&cstr, expr, PPL_CONSTRAINT_TYPE_GREATER_OR_EQUAL);
40606
ppl_Polyhedron_add_constraint (accesses, cstr);
40607
@@ -1740,7 +1740,7 @@
40608
ppl_new_Linear_Expression_with_dimension (&expr, accessp_nb_dims);
40609
ppl_set_coef (expr, subscript, -1);
40610
40611
- ppl_set_inhomogeneous (expr, int_cst_value (high));
40612
+ ppl_set_inhomogeneous_tree (expr, high);
40613
40614
ppl_new_Constraint (&cstr, expr, PPL_CONSTRAINT_TYPE_GREATER_OR_EQUAL);
40615
ppl_Polyhedron_add_constraint (accesses, cstr);
40616
--- a/src/gcc/graphite.c
40617
+++ b/src/gcc/graphite.c
40618
@@ -210,6 +210,7 @@
40619
return false;
40620
}
40621
40622
+ scev_reset ();
40623
recompute_all_dominators ();
40624
initialize_original_copy_tables ();
40625
cloog_initialize ();
40626
34179
--- a/src/gcc/gthr-posix.h
40627
34180
+++ b/src/gcc/gthr-posix.h
40628
@@ -1,7 +1,7 @@
40629
/* Threads compatibility routines for libgcc2 and libobjc. */
40630
/* Compile this one with gcc. */
40631
/* Copyright (C) 1997, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
40632
- 2008, 2009 Free Software Foundation, Inc.
40633
+ 2008, 2009, 2011 Free Software Foundation, Inc.
40634
40635
This file is part of GCC.
40636
40637
34181
@@ -124,7 +124,9 @@
40638
34182
__gthrw(pthread_equal)
40639
34183
__gthrw(pthread_self)
40661
34205
return __gthread_active_ptr != 0;
40662
34206
}
40663
34207
40664
@@ -250,61 +260,34 @@
40665
calls in shared flavors of the HP-UX C library. Most of the stubs
40666
have no functionality. The details are described in the "libc cumulative
40667
patch" for each subversion of HP-UX 11. There are two special interfaces
40668
- provided for checking whether an application is linked to a pthread
40669
+ provided for checking whether an application is linked to a shared pthread
40670
library or not. However, these interfaces aren't available in early
40671
- libc versions. We also can't use pthread_once as some libc versions
40672
- call the init function. So, we use pthread_create to check whether it
40673
- is possible to create a thread or not. The stub implementation returns
40674
- the error number ENOSYS. */
40675
+ libpthread libraries. We also need a test that works for archive
40676
+ libraries. We can't use pthread_once as some libc versions call the
40677
+ init function. We also can't use pthread_create or pthread_attr_init
40678
+ as these create a thread and thereby prevent changing the default stack
40679
+ size. The function pthread_default_stacksize_np is available in both
40680
+ the archive and shared versions of libpthread. It can be used to
40681
+ determine the default pthread stack size. There is a stub in some
40682
+ shared libc versions which returns a zero size if pthreads are not
40683
+ active. We provide an equivalent stub to handle cases where libc
40684
+ doesn't provide one. */
40685
40686
#if defined(__hppa__) && defined(__hpux__)
40687
40688
-#include <errno.h>
40689
-
40690
static volatile int __gthread_active = -1;
40691
40692
-static void *
40693
-__gthread_start (void *__arg __attribute__((unused)))
40694
-{
40695
- return NULL;
40696
-}
40697
-
40698
-static void __gthread_active_init (void) __attribute__((noinline));
40699
-static void
40700
-__gthread_active_init (void)
40701
-{
40702
- static pthread_mutex_t __gthread_active_mutex = PTHREAD_MUTEX_INITIALIZER;
40703
- pthread_t __t;
40704
- pthread_attr_t __a;
40705
- int __result;
40706
-
40707
- __gthrw_(pthread_mutex_lock) (&__gthread_active_mutex);
40708
- if (__gthread_active < 0)
40709
- {
40710
- __gthrw_(pthread_attr_init) (&__a);
40711
- __gthrw_(pthread_attr_setdetachstate) (&__a, PTHREAD_CREATE_DETACHED);
40712
- __result = __gthrw_(pthread_create) (&__t, &__a, __gthread_start, NULL);
40713
- if (__result != ENOSYS)
40714
- __gthread_active = 1;
40715
- else
40716
- __gthread_active = 0;
40717
- __gthrw_(pthread_attr_destroy) (&__a);
40718
- }
40719
- __gthrw_(pthread_mutex_unlock) (&__gthread_active_mutex);
40720
-}
40721
-
40722
static inline int
40723
__gthread_active_p (void)
40724
{
40725
/* Avoid reading __gthread_active twice on the main code path. */
40726
int __gthread_active_latest_value = __gthread_active;
40727
+ size_t __s;
40728
40729
- /* This test is not protected to avoid taking a lock on the main code
40730
- path so every update of __gthread_active in a threaded program must
40731
- be atomic with regard to the result of the test. */
40732
if (__builtin_expect (__gthread_active_latest_value < 0, 0))
40733
{
40734
- __gthread_active_init ();
40735
+ pthread_default_stacksize_np (0, &__s);
40736
+ __gthread_active = __s ? 1 : 0;
40737
__gthread_active_latest_value = __gthread_active;
40738
}
40739
40740
--- a/src/gcc/gthr-posix95.h
40741
+++ b/src/gcc/gthr-posix95.h
40742
@@ -1,6 +1,7 @@
40743
/* Threads compatibility routines for libgcc2 and libobjc. */
40744
/* Compile this one with gcc. */
40745
-/* Copyright (C) 2004, 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
40746
+/* Copyright (C) 2004, 2005, 2007, 2008, 2009, 2011
40747
+ Free Software Foundation, Inc.
40748
40749
This file is part of GCC.
40750
40751
@@ -184,61 +185,34 @@
40752
calls in shared flavors of the HP-UX C library. Most of the stubs
40753
have no functionality. The details are described in the "libc cumulative
40754
patch" for each subversion of HP-UX 11. There are two special interfaces
40755
- provided for checking whether an application is linked to a pthread
40756
+ provided for checking whether an application is linked to a shared pthread
40757
library or not. However, these interfaces aren't available in early
40758
- libc versions. We also can't use pthread_once as some libc versions
40759
- call the init function. So, we use pthread_create to check whether it
40760
- is possible to create a thread or not. The stub implementation returns
40761
- the error number ENOSYS. */
40762
+ pthread libraries. We also need a test that works for archive
40763
+ libraries. We can't use pthread_once as some libc versions call the
40764
+ init function. We also can't use pthread_create or pthread_attr_init
40765
+ as these create a thread and thereby prevent changing the default stack
40766
+ size. The function pthread_default_stacksize_np is available in both
40767
+ the archive and shared versions of libpthread. It can be used to
40768
+ determine the default pthread stack size. There is a stub in some
40769
+ shared libc versions which returns a zero size if pthreads are not
40770
+ active. We provide an equivalent stub to handle cases where libc
40771
+ doesn't provide one. */
40772
40773
#if defined(__hppa__) && defined(__hpux__)
40774
40775
-#include <errno.h>
40776
-
40777
static volatile int __gthread_active = -1;
40778
40779
-static void *
40780
-__gthread_start (void *arg __attribute__((unused)))
40781
-{
40782
- return NULL;
40783
-}
40784
-
40785
-static void __gthread_active_init (void) __attribute__((noinline));
40786
-static void
40787
-__gthread_active_init (void)
40788
-{
40789
- static pthread_mutex_t __gthread_active_mutex = PTHREAD_MUTEX_INITIALIZER;
40790
- pthread_t t;
40791
- pthread_attr_t a;
40792
- int result;
40793
-
40794
- __gthrw_(pthread_mutex_lock) (&__gthread_active_mutex);
40795
- if (__gthread_active < 0)
40796
- {
40797
- __gthrw_(pthread_attr_init) (&a);
40798
- __gthrw_(pthread_attr_setdetachstate) (&a, PTHREAD_CREATE_DETACHED);
40799
- result = __gthrw_(pthread_create) (&t, &a, __gthread_start, NULL);
40800
- if (result != ENOSYS)
40801
- __gthread_active = 1;
40802
- else
40803
- __gthread_active = 0;
40804
- __gthrw_(pthread_attr_destroy) (&a);
40805
- }
40806
- __gthrw_(pthread_mutex_unlock) (&__gthread_active_mutex);
40807
-}
40808
-
40809
static inline int
40810
__gthread_active_p (void)
40811
{
40812
/* Avoid reading __gthread_active twice on the main code path. */
40813
int __gthread_active_latest_value = __gthread_active;
40814
+ size_t __s;
40815
40816
- /* This test is not protected to avoid taking a lock on the main code
40817
- path so every update of __gthread_active in a threaded program must
40818
- be atomic with regard to the result of the test. */
40819
if (__builtin_expect (__gthread_active_latest_value < 0, 0))
40820
{
40821
- __gthread_active_init ();
40822
+ pthread_default_stacksize_np (0, &__s);
40823
+ __gthread_active = __s ? 1 : 0;
40824
__gthread_active_latest_value = __gthread_active;
40825
}
40826
40827
34208
--- a/src/gcc/haifa-sched.c
40828
34209
+++ b/src/gcc/haifa-sched.c
40829
34210
@@ -4231,7 +4231,7 @@
40844
34225
40845
34226
if (e)
40846
34227
{
40847
@@ -5234,6 +5234,11 @@
34228
@@ -5236,6 +5236,11 @@
40848
34229
gcc_assert (/* Usual case. */
40849
34230
(EDGE_COUNT (bb->succs) > 1
40850
34231
&& !BARRIER_P (NEXT_INSN (head)))
40856
34237
/* Or jump to the next instruction. */
40857
34238
|| (EDGE_COUNT (bb->succs) == 1
40858
34239
&& (BB_HEAD (EDGE_I (bb->succs, 0)->dest)
34240
--- a/src/gcc/hooks.c
34241
+++ b/src/gcc/hooks.c
34242
@@ -86,6 +86,15 @@
34243
return true;
34244
}
34245
34246
+/* Generic hook that takes (enum machine_mode, unsigned HOST_WIDE_INT)
34247
+ and returns false. */
34248
+bool
34249
+hook_bool_mode_uhwi_false (enum machine_mode mode ATTRIBUTE_UNUSED,
34250
+ unsigned HOST_WIDE_INT value ATTRIBUTE_UNUSED)
34251
+{
34252
+ return false;
34253
+}
34254
+
34255
/* Generic hook that takes (FILE *, const char *) and does nothing. */
34256
void
34257
hook_void_FILEptr_constcharptr (FILE *a ATTRIBUTE_UNUSED, const char *b ATTRIBUTE_UNUSED)
34258
--- a/src/gcc/hooks.h
34259
+++ b/src/gcc/hooks.h
34260
@@ -32,6 +32,8 @@
34261
extern bool hook_bool_mode_false (enum machine_mode);
34262
extern bool hook_bool_mode_const_rtx_false (enum machine_mode, const_rtx);
34263
extern bool hook_bool_mode_const_rtx_true (enum machine_mode, const_rtx);
34264
+extern bool hook_bool_mode_uhwi_false (enum machine_mode,
34265
+ unsigned HOST_WIDE_INT);
34266
extern bool hook_bool_tree_false (tree);
34267
extern bool hook_bool_const_tree_false (const_tree);
34268
extern bool hook_bool_tree_true (tree);
40859
34269
--- a/src/gcc/ifcvt.c
40860
34270
+++ b/src/gcc/ifcvt.c
40861
34271
@@ -88,6 +88,8 @@
41164
34574
return FALSE;
41165
34575
41166
34576
/* Conversion went ok, including moving the insns and fixing up the
41167
@@ -3815,12 +4006,35 @@
34577
@@ -3815,12 +4006,34 @@
41168
34578
41169
34579
static int
41170
34580
dead_or_predicable (basic_block test_bb, basic_block merge_bb,
41172
34582
+ basic_block other_bb, edge dest_edge, int reversep)
41173
34583
{
41174
34584
- rtx head, end, jump, earliest = NULL_RTX, old_dest, new_label = NULL_RTX;
34585
- bitmap merge_set = NULL;
41175
34586
+ basic_block new_dest = dest_edge->dest;
41176
34587
+ rtx head, end, jump, earliest = NULL_RTX, old_dest;
41177
bitmap merge_set = NULL;
41178
+ bitmap merge_set_noclobber = NULL;
34588
+ bitmap merge_set = NULL, merge_set_noclobber = NULL;
41179
34589
/* Number of pending changes. */
41180
34590
int n_validated_changes = 0;
41181
34591
+ rtx new_dest_label;
41202
34612
41203
34613
jump = BB_END (test_bb);
41204
34614
41205
@@ -3956,6 +4170,7 @@
41206
end of the block. */
34615
@@ -3951,11 +4164,14 @@
34616
34617
/* Collect:
34618
MERGE_SET = set of registers set in MERGE_BB
34619
+ MERGE_SET_NOCLOBBER = like MERGE_SET, but only includes registers
34620
+ that are really set, not just clobbered.
34621
TEST_LIVE = set of registers live at EARLIEST
34622
- TEST_SET = set of registers set between EARLIEST and the
34623
- end of the block. */
34624
+ TEST_SET = set of registers set between EARLIEST and the
34625
+ end of the block. */
41207
34626
41208
34627
merge_set = BITMAP_ALLOC (®_obstack);
41209
34628
+ merge_set_noclobber = BITMAP_ALLOC (®_obstack);
41210
34629
41211
34630
/* If we allocated new pseudos (e.g. in the conditional move
41212
34631
expander called from noce_emit_cmove), we must resize the
41213
@@ -3974,6 +4189,7 @@
41214
df_ref def = *def_rec;
41215
bitmap_set_bit (merge_set, DF_REF_REGNO (def));
41216
}
41217
+ df_simulate_find_noclobber_defs (insn, merge_set_noclobber);
34632
@@ -3967,13 +4183,8 @@
34633
{
34634
if (NONDEBUG_INSN_P (insn))
34635
{
34636
- unsigned int uid = INSN_UID (insn);
34637
- df_ref *def_rec;
34638
- for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++)
34639
- {
34640
- df_ref def = *def_rec;
34641
- bitmap_set_bit (merge_set, DF_REF_REGNO (def));
34642
- }
34643
+ df_simulate_find_defs (insn, merge_set);
34644
+ df_simulate_find_noclobber_defs (insn, merge_set_noclobber);
41218
34645
}
41219
34646
}
41220
34647
41221
@@ -3984,7 +4200,7 @@
34648
@@ -3984,7 +4195,7 @@
41222
34649
unsigned i;
41223
34650
bitmap_iterator bi;
41224
34651
41227
34654
{
41228
34655
if (i < FIRST_PSEUDO_REGISTER
41229
34656
&& ! fixed_regs[i]
41230
@@ -4020,7 +4236,7 @@
34657
@@ -4015,12 +4226,14 @@
34658
}
34659
34660
/* We can perform the transformation if
34661
- MERGE_SET & (TEST_SET | TEST_LIVE)
34662
+ MERGE_SET_NOCLOBBER & TEST_SET
34663
+ and
34664
+ MERGE_SET & TEST_LIVE
34665
and
41231
34666
TEST_SET & DF_LIVE_IN (merge_bb)
41232
34667
are empty. */
41233
34668
41236
34671
|| bitmap_intersect_p (merge_set, test_live)
41237
34672
|| bitmap_intersect_p (test_set, df_get_live_in (merge_bb)))
41238
34673
intersect = true;
41239
@@ -4040,10 +4256,9 @@
34674
@@ -4040,10 +4253,9 @@
41240
34675
old_dest = JUMP_LABEL (jump);
41241
34676
if (other_bb != new_dest)
41242
34677
{
41249
34684
goto cancel;
41250
34685
}
41251
34686
41252
@@ -4054,7 +4269,7 @@
34687
@@ -4054,7 +4266,7 @@
41253
34688
41254
34689
if (other_bb != new_dest)
41255
34690
{
41258
34693
41259
34694
redirect_edge_succ (BRANCH_EDGE (test_bb), new_dest);
41260
34695
if (reversep)
41261
@@ -4108,6 +4323,7 @@
34696
@@ -4104,10 +4316,11 @@
34697
unsigned i;
34698
bitmap_iterator bi;
34699
34700
- EXECUTE_IF_SET_IN_BITMAP (merge_set, 0, i, bi)
34701
+ EXECUTE_IF_SET_IN_BITMAP (merge_set_noclobber, 0, i, bi)
41262
34702
remove_reg_equal_equiv_notes_for_regno (i);
41263
34703
41264
34704
BITMAP_FREE (merge_set);
41265
+ BITMAP_FREE (merge_set_noclobber);
34705
+ BITMAP_FREE (merge_set_noclobber);
41266
34706
}
41267
34707
41268
34708
reorder_insns (head, end, PREV_INSN (earliest));
41269
@@ -4128,7 +4344,10 @@
34709
@@ -4128,7 +4341,10 @@
41270
34710
cancel_changes (0);
41271
34711
fail:
41272
34712
if (merge_set)
41673
35113
41674
35114
The subroutines redirect_jump and invert_jump are used
41675
35115
from other passes as well. */
41676
@@ -194,7 +195,7 @@
41677
rtx prev_nonjump_insn = NULL;
41678
41679
for (insn = f; insn; insn = NEXT_INSN (insn))
41680
- if (INSN_P (insn))
41681
+ if (NONDEBUG_INSN_P (insn))
41682
{
41683
mark_jump_label (PATTERN (insn), insn, 0);
41684
41685
35116
@@ -742,10 +743,10 @@
41686
35117
return (GET_CODE (x) == IF_THEN_ELSE
41687
35118
&& ((GET_CODE (XEXP (x, 2)) == PC
41762
35193
const char *fmt;
41763
35194
41764
35195
- if (code == LABEL_REF)
41765
+ if ((code == LABEL_REF && XEXP (x, 0) == olabel)
41766
+ || x == olabel)
41767
{
35196
- {
41768
35197
- if (XEXP (x, 0) == olabel)
41769
35198
- {
41770
35199
- rtx n;
41778
35207
- }
41779
35208
- }
41780
35209
- else if (code == RETURN && olabel == 0)
41781
- {
35210
+ if ((code == LABEL_REF && XEXP (x, 0) == olabel)
35211
+ || x == olabel)
35212
{
41782
35213
- if (nlabel)
41783
35214
- x = gen_rtx_LABEL_REF (Pmode, nlabel);
41784
35215
- else
41869
35300
/* Undefined labels will remain outside the insn stream. */
41870
35301
&& INSN_UID (olabel))
41871
35302
delete_related_insns (olabel);
41872
@@ -1728,7 +1731,13 @@
41873
41874
case 'i':
41875
if (XINT (x, i) != XINT (y, i))
41876
- return 0;
41877
+ {
41878
+ if (((code == ASM_OPERANDS && i == 6)
41879
+ || (code == ASM_INPUT && i == 1))
41880
+ && locator_eq (XINT (x, i), XINT (y, i)))
41881
+ break;
41882
+ return 0;
41883
+ }
41884
break;
41885
41886
case 't':
41887
35303
--- a/src/gcc/loop-doloop.c
41888
35304
+++ b/src/gcc/loop-doloop.c
41889
35305
@@ -78,6 +78,8 @@
42104
35520
42105
35521
--- a/src/gcc/modulo-sched.c
42106
35522
+++ b/src/gcc/modulo-sched.c
42107
@@ -116,8 +116,10 @@
35523
@@ -84,14 +84,13 @@
35524
II cycles (i.e. use register copies to prevent a def from overwriting
35525
itself before reaching the use).
35526
35527
- SMS works with countable loops (1) whose control part can be easily
35528
- decoupled from the rest of the loop and (2) whose loop count can
35529
- be easily adjusted. This is because we peel a constant number of
35530
- iterations into a prologue and epilogue for which we want to avoid
35531
- emitting the control part, and a kernel which is to iterate that
35532
- constant number of iterations less than the original loop. So the
35533
- control part should be a set of insns clearly identified and having
35534
- its own iv, not otherwise used in the loop (at-least for now), which
35535
+ SMS works with countable loops whose loop count can be easily
35536
+ adjusted. This is because we peel a constant number of iterations
35537
+ into a prologue and epilogue for which we want to avoid emitting
35538
+ the control part, and a kernel which is to iterate that constant
35539
+ number of iterations less than the original loop. So the control
35540
+ part should be a set of insns clearly identified and having its
35541
+ own iv, not otherwise used in the loop (at-least for now), which
35542
initializes a register before the loop to the number of iterations.
35543
Currently SMS relies on the do-loop pattern to recognize such loops,
35544
where (1) the control part comprises of all insns defining and/or
35545
@@ -116,8 +115,10 @@
42108
35546
42109
35547
/* The number of different iterations the nodes in ps span, assuming
42110
35548
the stage boundaries are placed efficiently. */
42111
35549
-#define PS_STAGE_COUNT(ps) ((PS_MAX_CYCLE (ps) - PS_MIN_CYCLE (ps) \
42112
35550
- + 1 + (ps)->ii - 1) / (ps)->ii)
42113
+#define CALC_STAGE_COUNT(min_cycle,max_cycle,ii) ((max_cycle - min_cycle \
35551
+#define CALC_STAGE_COUNT(max_cycle,min_cycle,ii) ((max_cycle - min_cycle \
42114
35552
+ + 1 + ii - 1) / ii)
42115
35553
+/* The stage count of ps. */
42116
35554
+#define PS_STAGE_COUNT(ps) (((partial_schedule_ptr)(ps))->stage_count)
42117
35555
42118
35556
/* A single instruction in the partial schedule. */
42119
35557
struct ps_insn
42120
@@ -155,6 +157,8 @@
35558
@@ -155,6 +156,8 @@
42121
35559
int max_cycle;
42122
35560
42123
35561
ddg_ptr g; /* The DDG of the insns in the partial schedule. */
42126
35564
};
42127
35565
42128
35566
/* We use this to record all the register replacements we do in
42129
@@ -195,6 +199,7 @@
35567
@@ -195,7 +198,7 @@
42130
35568
rtx, rtx);
42131
35569
static void duplicate_insns_of_cycles (partial_schedule_ptr,
42132
35570
int, int, int, rtx);
35571
-
42133
35572
+static int calculate_stage_count (partial_schedule_ptr ps);
42134
42135
35573
#define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
42136
35574
#define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
42137
@@ -310,10 +315,10 @@
35575
#define SCHED_FIRST_REG_MOVE(x) \
35576
@@ -310,10 +313,10 @@
42138
35577
either a single (parallel) branch-on-count or a (non-parallel)
42139
35578
branch immediately preceded by a single (decrement) insn. */
42140
35579
first_insn_not_to_check = (GET_CODE (PATTERN (tail)) == PARALLEL ? tail
42143
35582
42144
35583
for (insn = head; insn != first_insn_not_to_check; insn = NEXT_INSN (insn))
42145
35584
- if (reg_mentioned_p (reg, insn))
42146
+ if (reg_mentioned_p (reg, insn) && NONDEBUG_INSN_P (insn))
35585
+ if (reg_mentioned_p (reg, insn) && !DEBUG_INSN_P (insn))
42147
35586
{
42148
35587
if (dump_file)
42149
35588
{
42150
@@ -332,6 +337,24 @@
42151
#endif
42152
}
42153
42154
+/* Mark in DOLOOP_INSNS the instructions that belong to the do-loop part.
42155
+ Use TAIL to recognize that part. */
42156
+static void
42157
+mark_doloop_insns (sbitmap doloop_insns, rtx tail)
42158
+{
42159
+ rtx first_insn_not_to_check, insn;
42160
+
42161
+ /* This is the first instruction which belongs the doloop part. */
42162
+ first_insn_not_to_check = (GET_CODE (PATTERN (tail)) == PARALLEL ? tail
42163
+ : prev_nondebug_insn (tail));
42164
+
42165
+ sbitmap_zero (doloop_insns);
42166
+ for (insn = first_insn_not_to_check; insn != NEXT_INSN (tail);
42167
+ insn = NEXT_INSN (insn))
42168
+ if (NONDEBUG_INSN_P (insn))
42169
+ SET_BIT (doloop_insns, INSN_UID (insn));
42170
+}
42171
+
42172
/* Check if COUNT_REG is set to a constant in the PRE_HEADER block, so
42173
that the number of iterations is a compile-time constant. If so,
42174
return the rtx that sets COUNT_REG to a constant, and set COUNT to
42175
@@ -569,13 +592,12 @@
35589
@@ -569,13 +572,12 @@
42176
35590
}
42177
35591
}
42178
35592
42189
35603
int ii = ps->ii;
42190
35604
ps_insn_ptr crr_insn;
42191
35605
42192
@@ -584,6 +606,10 @@
35606
@@ -584,19 +586,43 @@
42193
35607
{
42194
35608
ddg_node_ptr u = crr_insn->node;
42195
35609
int normalized_time = SCHED_TIME (u) - amount;
42196
35610
+ int new_min_cycle = PS_MIN_CYCLE (ps) - amount;
42197
+ /* The first cycle in row zero after the rotation. */
42198
+ int new_first_cycle_in_row_zero =
42199
+ new_min_cycle + ii - SMODULO (new_min_cycle, ii);
35611
+ int sc_until_cycle_zero, stage;
42200
35612
42201
if (dump_file)
42202
fprintf (dump_file, "crr_insn->node=%d, crr_insn->cycle=%d,\
42203
@@ -592,8 +618,30 @@
35613
- if (dump_file)
35614
- fprintf (dump_file, "crr_insn->node=%d, crr_insn->cycle=%d,\
35615
- min_cycle=%d\n", crr_insn->node->cuid, SCHED_TIME
35616
- (u), ps->min_cycle);
35617
+ if (dump_file)
35618
+ {
35619
+ /* Print the scheduling times after the rotation. */
35620
+ fprintf (dump_file, "crr_insn->node=%d (insn id %d), "
35621
+ "crr_insn->cycle=%d, min_cycle=%d", crr_insn->node->cuid,
35622
+ INSN_UID (crr_insn->node->insn), SCHED_TIME (u),
35623
+ normalized_time);
35624
+ if (JUMP_P (crr_insn->node->insn))
35625
+ fprintf (dump_file, " (branch)");
35626
+ fprintf (dump_file, "\n");
35627
+ }
35628
+
42204
35629
gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
42205
35630
gcc_assert (SCHED_TIME (u) <= ps->max_cycle);
42206
35631
SCHED_TIME (u) = normalized_time;
42207
35632
- SCHED_ROW (u) = normalized_time % ii;
42208
35633
- SCHED_STAGE (u) = normalized_time / ii;
42209
+ crr_insn->cycle = normalized_time;
42210
35634
+ SCHED_ROW (u) = SMODULO (normalized_time, ii);
42211
+
42212
+ /* If min_cycle is in row zero after the rotation then
42213
+ the stage count can be calculated by dividing the cycle
42214
+ with ii. Otherwise, the calculation is done by dividing the
42215
+ SMSed kernel into two intervals:
42216
+
42217
+ 1) min_cycle <= interval 0 < first_cycle_in_row_zero
42218
+ 2) first_cycle_in_row_zero <= interval 1 < max_cycle
42219
+
42220
+ Cycles in interval 0 are in stage 0. The stage of cycles
42221
+ in interval 1 should be added by 1 to take interval 0 into
42222
+ account. */
42223
+ if (SMODULO (new_min_cycle, ii) == 0)
42224
+ SCHED_STAGE (u) = normalized_time / ii;
42225
+ else
42226
+ {
42227
+ if (crr_insn->cycle < new_first_cycle_in_row_zero)
42228
+ SCHED_STAGE (u) = 0;
42229
+ else
42230
+ SCHED_STAGE (u) =
42231
+ ((SCHED_TIME (u) - new_first_cycle_in_row_zero) / ii) + 1;
35635
+
35636
+ /* The calculation of stage count is done adding the number
35637
+ of stages before cycle zero and after cycle zero. */
35638
+ sc_until_cycle_zero = CALC_STAGE_COUNT (-1, new_min_cycle, ii);
35639
+
35640
+ if (SCHED_TIME (u) < 0)
35641
+ {
35642
+ stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
35643
+ SCHED_STAGE (u) = sc_until_cycle_zero - stage;
35644
+ }
35645
+ else
35646
+ {
35647
+ stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
35648
+ SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
42232
35649
+ }
42233
35650
}
42234
35651
}
42235
42236
@@ -646,9 +694,12 @@
35652
-
35653
+
35654
/* Set SCHED_COLUMN of each node according to its position in PS. */
35655
static void
35656
set_columns_for_ps (partial_schedule_ptr ps)
35657
@@ -646,9 +672,12 @@
42237
35658
42238
35659
/* Do not duplicate any insn which refers to count_reg as it
42239
35660
belongs to the control part.
42240
+ If closing_branch_deps is true the closing branch is scheduled
42241
+ as well and thus should be ignored.
35661
+ The closing branch is scheduled as well and thus should
35662
+ be ignored.
42242
35663
TODO: This should be done by analyzing the control part of
42243
35664
the loop. */
42244
35665
- if (reg_mentioned_p (count_reg, u_node->insn))
42247
35668
continue;
42248
35669
42249
35670
if (for_prolog)
42250
@@ -894,7 +945,8 @@
42251
basic_block condition_bb = NULL;
42252
edge latch_edge;
42253
gcov_type trip_count = 0;
42254
-
42255
+ sbitmap doloop_insns;
42256
+
42257
loop_optimizer_init (LOOPS_HAVE_PREHEADERS
42258
| LOOPS_HAVE_RECORDED_EXITS);
42259
if (number_of_loops () <= 1)
42260
@@ -919,6 +971,7 @@
42261
setup_sched_infos ();
42262
haifa_sched_init ();
42263
42264
+ doloop_insns = sbitmap_alloc (get_max_uid () + 1);
42265
/* Allocate memory to hold the DDG array one entry for each loop.
42266
We use loop->num as index into this array. */
42267
g_arr = XCNEWVEC (ddg_ptr, number_of_loops ());
42268
@@ -1009,9 +1062,11 @@
35671
@@ -1009,9 +1038,11 @@
42269
35672
continue;
42270
35673
}
42271
35674
42280
35683
??? Should handle auto-increment insns.
42281
35684
??? Should handle insns defining subregs. */
42282
35685
for (insn = head; insn != NEXT_INSN (tail); insn = NEXT_INSN (insn))
42283
@@ -1021,7 +1076,8 @@
35686
@@ -1021,7 +1052,8 @@
42284
35687
if (CALL_P (insn)
42285
35688
|| BARRIER_P (insn)
42286
35689
|| (NONDEBUG_INSN_P (insn) && !JUMP_P (insn)
42290
35693
|| (FIND_REG_INC_NOTE (insn, NULL_RTX) != 0)
42291
35694
|| (INSN_P (insn) && (set = single_set (insn))
42292
35695
&& GET_CODE (SET_DEST (set)) == SUBREG))
42293
@@ -1048,14 +1104,16 @@
42294
35696
@@ -1049,7 +1081,11 @@
42295
35697
continue;
42296
35698
}
42297
-
35699
42298
35700
- if (! (g = create_ddg (bb, 0)))
42299
+ mark_doloop_insns (doloop_insns, tail);
42300
+ if (! (g = create_ddg (bb, doloop_insns)))
35701
+ /* Always schedule the closing branch with the rest of the
35702
+ instructions. The branch is rotated to be in row ii-1 at the
35703
+ end of the scheduling procedure to make sure it's the last
35704
+ instruction in the iteration. */
35705
+ if (! (g = create_ddg (bb, 1)))
42301
35706
{
42302
35707
if (dump_file)
42303
35708
fprintf (dump_file, "SMS create_ddg failed\n");
42304
continue;
42305
}
42306
-
42307
+ if (dump_file)
42308
+ fprintf (dump_file, "SMS closing_branch_deps: %d\n",
42309
+ g->closing_branch_deps);
42310
g_arr[loop->num] = g;
42311
if (dump_file)
42312
fprintf (dump_file, "...OK\n");
42313
@@ -1157,11 +1215,13 @@
35709
@@ -1157,14 +1193,17 @@
42314
35710
42315
35711
ps = sms_schedule_by_order (g, mii, maxii, node_order);
42316
35712
42319
35715
- gcc_assert(stage_count >= 1);
42320
35716
- }
42321
35717
-
42322
+ if (ps)
42323
+ {
42324
+ stage_count = calculate_stage_count (ps);
42325
+ gcc_assert(stage_count >= 1);
42326
+ PS_STAGE_COUNT(ps) = stage_count;
42327
+ }
42328
+
42329
/* Stage count of 1 means that there is no interleaving between
42330
iterations, let the scheduling passes do the job. */
42331
if (stage_count <= 1
42332
@@ -1182,17 +1242,7 @@
35718
- /* Stage count of 1 means that there is no interleaving between
35719
- iterations, let the scheduling passes do the job. */
35720
- if (stage_count <= 1
35721
+ if (ps)
35722
+ {
35723
+ stage_count = calculate_stage_count (ps);
35724
+ gcc_assert(stage_count >= 1);
35725
+ PS_STAGE_COUNT(ps) = stage_count;
35726
+ }
35727
+
35728
+ /* The default value of PARAM_SMS_MIN_SC is 2 as stage count of
35729
+ 1 means that there is no interleaving between iterations thus
35730
+ we let the scheduling passes do the job in this case. */
35731
+ if (stage_count < (unsigned) PARAM_VALUE (PARAM_SMS_MIN_SC)
35732
|| (count_init && (loop_count <= stage_count))
35733
|| (flag_branch_probabilities && (trip_count <= stage_count)))
35734
{
35735
@@ -1182,32 +1221,24 @@
42333
35736
else
42334
35737
{
42335
35738
struct undo_replace_buff_elem *reg_move_replaces;
42336
-
35739
+ int amount = SCHED_TIME (g->closing_branch) + 1;
35740
+
35741
+ /* Set the stage boundaries. The closing_branch was scheduled
35742
+ and should appear in the last (ii-1) row. */
35743
+ reset_sched_times (ps, amount);
35744
+ rotate_partial_schedule (ps, amount);
35745
+ set_columns_for_ps (ps);
35746
42337
35747
- if (dump_file)
42338
35748
- {
42339
- fprintf (dump_file,
42340
- "SMS succeeded %d %d (with ii, sc)\n", ps->ii,
42341
- stage_count);
42342
- print_partial_schedule (ps, dump_file);
35749
+ canon_loop (loop);
35750
+
35751
+ if (dump_file)
35752
+ {
35753
fprintf (dump_file,
35754
"SMS succeeded %d %d (with ii, sc)\n", ps->ii,
35755
stage_count);
35756
print_partial_schedule (ps, dump_file);
42343
35757
- fprintf (dump_file,
42344
35758
- "SMS Branch (%d) will later be scheduled at cycle %d.\n",
42345
35759
- g->closing_branch->cuid, PS_MIN_CYCLE (ps) - 1);
42346
- }
42347
+ int amount;
42348
42349
/* Set the stage boundaries. If the DDG is built with closing_branch_deps,
42350
the closing_branch was scheduled and should appear in the last (ii-1)
42351
@@ -1202,12 +1252,28 @@
42352
TODO: Revisit the issue of scheduling the insns of the
42353
control part relative to the branch when the control part
42354
has more than one insn. */
35760
}
35761
-
35762
- /* Set the stage boundaries. If the DDG is built with closing_branch_deps,
35763
- the closing_branch was scheduled and should appear in the last (ii-1)
35764
- row. Otherwise, we are free to schedule the branch, and we let nodes
35765
- that were scheduled at the first PS_MIN_CYCLE cycle appear in the first
35766
- row; this should reduce stage_count to minimum.
35767
- TODO: Revisit the issue of scheduling the insns of the
35768
- control part relative to the branch when the control part
35769
- has more than one insn. */
42355
35770
- normalize_sched_times (ps);
42356
35771
- rotate_partial_schedule (ps, PS_MIN_CYCLE (ps));
42357
+ amount = (g->closing_branch_deps)? SCHED_TIME (g->closing_branch) + 1:
42358
+ PS_MIN_CYCLE (ps);
42359
+ reset_sched_times (ps, amount);
42360
+ rotate_partial_schedule (ps, amount);
42361
+
42362
set_columns_for_ps (ps);
42363
42364
canon_loop (loop);
42365
42366
+ if (dump_file)
42367
+ {
42368
+ fprintf (dump_file,
42369
+ "SMS succeeded %d %d (with ii, sc)\n", ps->ii,
42370
+ stage_count);
42371
+ print_partial_schedule (ps, dump_file);
42372
+ if (!g->closing_branch_deps)
42373
+ fprintf (dump_file,
42374
+ "SMS Branch (%d) will later be scheduled at \
42375
+ cycle %d.\n",
42376
+ g->closing_branch->cuid, PS_MIN_CYCLE (ps) - 1);
42377
+ }
42378
+
35772
- set_columns_for_ps (ps);
35773
-
35774
- canon_loop (loop);
35775
-
35776
+
42379
35777
/* case the BCT count is not known , Do loop-versioning */
42380
35778
if (count_reg && ! count_init)
42381
35779
{
42382
@@ -1252,6 +1318,7 @@
42383
}
42384
42385
free (g_arr);
42386
+ sbitmap_free (doloop_insns);
42387
42388
/* Release scheduler data, needed until now because of DFA. */
42389
haifa_sched_finish ();
42390
@@ -1759,8 +1826,9 @@
42391
RESET_BIT (tobe_scheduled, u);
35780
@@ -1760,12 +1791,6 @@
42392
35781
continue;
42393
35782
}
42394
-
35783
42395
35784
- if (JUMP_P (insn)) /* Closing branch handled later. */
42396
+ /* Closing branch handled later unless closing_branch_deps
42397
+ is true. */
42398
+ if (JUMP_P (insn) && !g->closing_branch_deps)
42399
{
42400
RESET_BIT (tobe_scheduled, u);
42401
continue;
42402
@@ -1893,8 +1961,8 @@
35785
- {
35786
- RESET_BIT (tobe_scheduled, u);
35787
- continue;
35788
- }
35789
-
35790
if (TEST_BIT (sched_nodes, u))
35791
continue;
35792
35793
@@ -1893,8 +1918,8 @@
42403
35794
if (dump_file)
42404
35795
fprintf (dump_file, "split_row=%d\n", split_row);
42405
35796
42410
35801
42411
35802
rows_new = (ps_insn_ptr *) xcalloc (new_ii, sizeof (ps_insn_ptr));
42412
35803
for (row = 0; row < split_row; row++)
42413
@@ -2571,6 +2639,7 @@
35804
@@ -2571,6 +2596,7 @@
42414
35805
ps_insn_ptr next_ps_i;
42415
35806
ps_insn_ptr first_must_follow = NULL;
42416
35807
ps_insn_ptr last_must_precede = NULL;
42418
35809
int row;
42419
35810
42420
35811
if (! ps_i)
42421
@@ -2597,8 +2666,37 @@
35812
@@ -2597,8 +2623,37 @@
42422
35813
else
42423
35814
last_must_precede = next_ps_i;
42424
35815
}
42431
35822
+ last_in_row = next_ps_i;
42432
35823
}
42433
35824
42434
+ /* If closing_branch_deps is true we are scheduling the closing
42435
+ branch as well. Make sure there is no dependent instruction after
42436
+ it as the branch should be the last instruction. */
35825
+ /* The closing branch is scheduled as well. Make sure there is no
35826
+ dependent instruction after it as the branch should be the last
35827
+ instruction in the row. */
42437
35828
+ if (JUMP_P (ps_i->node->insn))
42438
35829
+ {
42439
35830
+ if (first_must_follow)
42456
35847
/* Now insert the node after INSERT_AFTER_PSI. */
42457
35848
42458
35849
if (! last_must_precede)
42459
@@ -2820,6 +2918,54 @@
35850
@@ -2820,6 +2875,24 @@
42460
35851
return ps_i;
42461
35852
}
42462
35853
42463
+/* Calculate the stage count of the partial schedule PS. */
35854
+/* Calculate the stage count of the partial schedule PS. The calculation
35855
+ takes into account the rotation to bring the closing branch to row
35856
+ ii-1. */
42464
35857
+int
42465
35858
+calculate_stage_count (partial_schedule_ptr ps)
42466
35859
+{
42467
+ int stage_count;
42468
+
42469
+ /* If closing_branch_deps is false then the stage
42470
+ boundaries are placed efficiently, meaning that min_cycle will be
42471
+ placed at row 0. Otherwise, the closing branch will be placed in
42472
+ row ii-1. For the later case we assume the final SMSed kernel can
42473
+ be divided into two intervals. This assumption is used for the
42474
+ stage count calculation:
42475
+
42476
+ 1) min_cycle <= interval 0 < first_cycle_in_row_zero
42477
+ 2) first_cycle_in_row_zero <= interval 1 < max_cycle
42478
+ */
42479
+ stage_count =
42480
+ CALC_STAGE_COUNT (PS_MIN_CYCLE (ps), PS_MAX_CYCLE (ps), ps->ii);
42481
+ if (ps->g->closing_branch_deps)
42482
+ {
42483
+ int new_min_cycle;
42484
+ int new_min_cycle_row;
42485
+ int rotation_amount = SCHED_TIME (ps->g->closing_branch) + 1;
42486
+
42487
+ /* This is the new value of min_cycle after the final rotation to
42488
+ bring closing branch into row ii-1. */
42489
+ new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount;
42490
+ /* This is the row which the the new min_cycle will be placed in. */
42491
+ new_min_cycle_row = SMODULO (new_min_cycle, ps->ii);
42492
+ /* If the row of min_cycle is zero then interval 0 is empty.
42493
+ Otherwise, we need to calculate interval 1 and add it by one
42494
+ to take interval 0 into account. */
42495
+ if (new_min_cycle_row != 0)
42496
+ {
42497
+ int new_max_cycle, first_cycle_in_row_zero;
42498
+
42499
+ new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount;
42500
+ first_cycle_in_row_zero =
42501
+ new_min_cycle + ps->ii - new_min_cycle_row;
42502
+
42503
+ stage_count =
42504
+ CALC_STAGE_COUNT (first_cycle_in_row_zero, new_max_cycle,
42505
+ ps->ii) + 1;
42506
+ }
42507
+ }
35860
+ int rotation_amount = (SCHED_TIME (ps->g->closing_branch)) + 1;
35861
+ int new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount;
35862
+ int new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount;
35863
+ int stage_count = CALC_STAGE_COUNT (-1, new_min_cycle, ps->ii);
35864
+
35865
+ /* The calculation of stage count is done adding the number of stages
35866
+ before cycle zero and after cycle zero. */
35867
+ stage_count += CALC_STAGE_COUNT (new_max_cycle, 0, ps->ii);
35868
+
42508
35869
+ return stage_count;
42509
35870
+}
42510
35871
+
42661
36022
/* This parameter limits the number of insns in a loop that will be unrolled,
42662
36023
and by how much the loop is unrolled.
42663
36024
42664
@@ -803,6 +826,11 @@
36025
@@ -301,6 +324,11 @@
36026
"sms-max-ii-factor",
36027
"A factor for tuning the upper bound that swing modulo scheduler uses for scheduling a loop",
36028
100, 0, 0)
36029
+/* The minimum value of stage count that swing modulo scheduler will generate. */
36030
+DEFPARAM(PARAM_SMS_MIN_SC,
36031
+ "sms-min-sc",
36032
+ "The minimum value of stage count that swing modulo scheduler will generate.",
36033
+ 2, 1, 1)
36034
DEFPARAM(PARAM_SMS_DFA_HISTORY,
36035
"sms-dfa-history",
36036
"The number of cycles the swing modulo scheduler considers when checking conflicts using DFA",
36037
@@ -803,6 +831,11 @@
42665
36038
"a pointer to an aggregate with",
42666
36039
2, 0, 0)
42667
36040
44202
37575
#include "real.h"
44203
37576
#include "toplev.h"
44204
37577
#include "basic-block.h"
44205
@@ -2082,6 +2082,7 @@
37578
@@ -932,7 +932,9 @@
37579
return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
37580
|| mode == VOIDmode)
37581
&& (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
37582
- && LEGITIMATE_CONSTANT_P (op));
37583
+ && targetm.legitimate_constant_p (mode == VOIDmode
37584
+ ? GET_MODE (op)
37585
+ : mode, op));
37586
37587
/* Except for certain constants with VOIDmode, already checked for,
37588
OP's mode must match MODE if MODE specifies a mode. */
37589
@@ -1109,7 +1111,9 @@
37590
&& (GET_MODE (op) == mode || mode == VOIDmode
37591
|| GET_MODE (op) == VOIDmode)
37592
&& (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
37593
- && LEGITIMATE_CONSTANT_P (op));
37594
+ && targetm.legitimate_constant_p (mode == VOIDmode
37595
+ ? GET_MODE (op)
37596
+ : mode, op));
37597
}
37598
37599
/* Returns 1 if OP is an operand that is a CONST_INT. */
37600
@@ -1175,7 +1179,9 @@
37601
return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
37602
|| mode == VOIDmode)
37603
&& (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
37604
- && LEGITIMATE_CONSTANT_P (op));
37605
+ && targetm.legitimate_constant_p (mode == VOIDmode
37606
+ ? GET_MODE (op)
37607
+ : mode, op));
37608
}
37609
37610
if (GET_MODE (op) != mode && mode != VOIDmode)
37611
@@ -2082,6 +2088,7 @@
44206
37612
recog_data.operand_loc,
44207
37613
recog_data.constraints,
44208
37614
recog_data.operand_mode, NULL);
44210
37616
if (noperands > 0)
44211
37617
{
44212
37618
const char *p = recog_data.constraints[0];
44213
@@ -2111,6 +2112,7 @@
37619
@@ -2111,6 +2118,7 @@
44214
37620
for (i = 0; i < noperands; i++)
44215
37621
{
44216
37622
recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
44218
37624
recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
44219
37625
/* VOIDmode match_operands gets mode from their real operand. */
44220
37626
if (recog_data.operand_mode[i] == VOIDmode)
44221
@@ -2909,6 +2911,10 @@
37627
@@ -2909,6 +2917,10 @@
44222
37628
44223
37629
static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
44224
37630
static int peep2_current;
44229
37635
/* The number of instructions available to match a peep2. */
44230
37636
int peep2_current_count;
44231
37637
44232
@@ -2917,6 +2923,16 @@
37638
@@ -2917,6 +2929,16 @@
44233
37639
DF_LIVE_OUT for the block. */
44234
37640
#define PEEP2_EOB pc_rtx
44235
37641
44246
37652
/* Return the Nth non-note insn after `current', or return NULL_RTX if it
44247
37653
does not exist. Used by the recognizer to find the next insn to match
44248
37654
in a multi-insn pattern. */
44249
@@ -2926,9 +2942,7 @@
37655
@@ -2926,9 +2948,7 @@
44250
37656
{
44251
37657
gcc_assert (n <= peep2_current_count);
44252
37658
44257
37663
44258
37664
return peep2_insn_data[n].insn;
44259
37665
}
44260
@@ -2941,9 +2955,7 @@
37666
@@ -2941,9 +2961,7 @@
44261
37667
{
44262
37668
gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
44263
37669
44268
37674
44269
37675
gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
44270
37676
44271
@@ -2959,9 +2971,7 @@
37677
@@ -2959,9 +2977,7 @@
44272
37678
44273
37679
gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
44274
37680
44279
37685
44280
37686
gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
44281
37687
44282
@@ -2996,12 +3006,8 @@
37688
@@ -2996,12 +3012,8 @@
44283
37689
gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1);
44284
37690
gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1);
44285
37691
44294
37700
44295
37701
gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
44296
37702
REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
44297
@@ -3010,8 +3016,7 @@
37703
@@ -3010,8 +3022,7 @@
44298
37704
{
44299
37705
HARD_REG_SET this_live;
44300
37706
44304
37710
gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
44305
37711
REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before);
44306
37712
IOR_HARD_REG_SET (live, this_live);
44307
@@ -3104,19 +3109,234 @@
37713
@@ -3104,19 +3115,234 @@
44308
37714
COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
44309
37715
}
44310
37716
44542
37948
df_analyze ();
44543
37949
44544
37950
/* Initialize the regsets we're going to use. */
44545
@@ -3126,214 +3346,59 @@
37951
@@ -3126,214 +3352,59 @@
44546
37952
44547
37953
FOR_EACH_BB_REVERSE (bb)
44548
37954
{
44799
38205
}
44800
38206
}
44801
38207
44802
@@ -3341,7 +3406,7 @@
38208
@@ -3341,7 +3412,7 @@
44803
38209
for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
44804
38210
BITMAP_FREE (peep2_insn_data[i].live_before);
44805
38211
BITMAP_FREE (live);
44910
38316
}
44911
38317
}
44912
38318
else
44913
--- a/src/gcc/regmove.c
44914
+++ b/src/gcc/regmove.c
44915
@@ -513,7 +513,7 @@
44916
rtx src_reg = XEXP (src, 0);
44917
int src_no = REGNO (src_reg);
44918
int dst_no = REGNO (dest);
44919
- rtx p, set;
44920
+ rtx p, set, set_insn;
44921
enum machine_mode old_mode;
44922
basic_block bb = BLOCK_FOR_INSN (insn);
44923
44924
@@ -551,6 +551,7 @@
44925
GET_MODE_BITSIZE (GET_MODE (src_reg))))
44926
return;
44927
44928
+ set_insn = p;
44929
old_mode = GET_MODE (src_reg);
44930
PUT_MODE (src_reg, GET_MODE (src));
44931
XEXP (src, 0) = SET_SRC (set);
44932
@@ -583,9 +584,19 @@
44933
}
44934
else
44935
{
44936
- rtx note = find_reg_note (p, REG_EQUAL, NULL_RTX);
44937
+ rtx note = find_reg_note (set_insn, REG_EQUAL, NULL_RTX);
44938
if (note)
44939
- remove_note (p, note);
44940
+ {
44941
+ if (rtx_equal_p (XEXP (note, 0), XEXP (src, 0)))
44942
+ {
44943
+ XEXP (note, 0)
44944
+ = gen_rtx_fmt_e (GET_CODE (src), GET_MODE (src),
44945
+ XEXP (note, 0));
44946
+ df_notes_rescan (set_insn);
44947
+ }
44948
+ else
44949
+ remove_note (set_insn, note);
44950
+ }
44951
}
44952
}
44953
44954
38319
--- a/src/gcc/regrename.c
44955
38320
+++ b/src/gcc/regrename.c
44956
38321
@@ -26,7 +26,6 @@
44980
38345
/* Don't count an input operand that is constrained to match
44981
38346
the early clobber operand. */
44982
38347
&& ! (this_alternative_matches[j] == i
38348
@@ -4739,7 +4739,8 @@
38349
simplify_gen_subreg (GET_MODE (x), reg_equiv_constant[regno],
38350
GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
38351
gcc_assert (tem);
38352
- if (CONSTANT_P (tem) && !LEGITIMATE_CONSTANT_P (tem))
38353
+ if (CONSTANT_P (tem)
38354
+ && !targetm.legitimate_constant_p (GET_MODE (x), tem))
38355
{
38356
tem = force_const_mem (GET_MODE (x), tem);
38357
i = find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
38358
@@ -6061,7 +6062,7 @@
38359
enum reload_type type, int ind_levels)
38360
{
38361
if (CONSTANT_P (x)
38362
- && (! LEGITIMATE_CONSTANT_P (x)
38363
+ && (!targetm.legitimate_constant_p (mode, x)
38364
|| PREFERRED_RELOAD_CLASS (x, rclass) == NO_REGS))
38365
{
38366
x = force_const_mem (mode, x);
38367
@@ -6071,7 +6072,7 @@
38368
38369
else if (GET_CODE (x) == PLUS
38370
&& CONSTANT_P (XEXP (x, 1))
38371
- && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1))
38372
+ && (!targetm.legitimate_constant_p (GET_MODE (x), XEXP (x, 1))
38373
|| PREFERRED_RELOAD_CLASS (XEXP (x, 1), rclass) == NO_REGS))
38374
{
38375
rtx tem;
44983
38376
--- a/src/gcc/reload.h
44984
38377
+++ b/src/gcc/reload.h
44985
38378
@@ -347,6 +347,10 @@
44995
38388
44996
38389
--- a/src/gcc/reload1.c
44997
38390
+++ b/src/gcc/reload1.c
44998
@@ -1,7 +1,7 @@
44999
/* Reload pseudo regs into hard regs for insns that require hard regs.
45000
Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
45001
- 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
45002
- Free Software Foundation, Inc.
45003
+ 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
45004
+ 2011 Free Software Foundation, Inc.
45005
45006
This file is part of GCC.
45007
45008
38391
@@ -413,6 +413,7 @@
45009
38392
static void set_label_offsets (rtx, rtx, int);
45010
38393
static void check_eliminable_occurrences (rtx);
45722
39105
/* Loop through all elimination pairs.
45723
39106
Recalculate the number not at initial offset.
45724
39107
45725
@@ -3907,6 +4077,168 @@
39108
@@ -3907,6 +4077,170 @@
45726
39109
ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
45727
39110
}
45728
39111
}
45813
39196
+ }
45814
39197
+ else if (function_invariant_p (x))
45815
39198
+ {
39199
+ enum machine_mode mode;
39200
+
39201
+ mode = GET_MODE (SET_DEST (set));
45816
39202
+ if (GET_CODE (x) == PLUS)
45817
39203
+ {
45818
39204
+ /* This is PLUS of frame pointer and a constant,
45825
39211
+ reg_equiv_invariant[i] = x;
45826
39212
+ num_eliminable_invariants++;
45827
39213
+ }
45828
+ else if (LEGITIMATE_CONSTANT_P (x))
39214
+ else if (targetm.legitimate_constant_p (mode, x))
45829
39215
+ reg_equiv_constant[i] = x;
45830
39216
+ else
45831
39217
+ {
45832
+ reg_equiv_memory_loc[i]
45833
+ = force_const_mem (GET_MODE (SET_DEST (set)), x);
39218
+ reg_equiv_memory_loc[i] = force_const_mem (mode, x);
45834
39219
+ if (! reg_equiv_memory_loc[i])
45835
39220
+ reg_equiv_init[i] = NULL_RTX;
45836
39221
+ }
45891
39276
45892
39277
/* Kick all pseudos out of hard register REGNO.
45893
39278
45894
@@ -5657,7 +5989,7 @@
39279
@@ -5657,7 +5991,7 @@
45895
39280
return 1;
45896
39281
if (GET_CODE (x) == PLUS
45897
39282
&& (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
45900
39285
return 1;
45901
39286
return 0;
45902
39287
}
45903
@@ -6266,17 +6598,6 @@
45904
&& (rld[r].nregs == max_group_size
45905
|| ! reg_classes_intersect_p (rld[r].rclass, group_class)))
45906
search_equiv = rld[r].in;
45907
- /* If this is an output reload from a simple move insn, look
45908
- if an equivalence for the input is available. */
45909
- else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
45910
- {
45911
- rtx set = single_set (insn);
45912
-
45913
- if (set
45914
- && rtx_equal_p (rld[r].out, SET_DEST (set))
45915
- && CONSTANT_P (SET_SRC (set)))
45916
- search_equiv = SET_SRC (set);
45917
- }
45918
45919
if (search_equiv)
45920
{
45921
@@ -7759,10 +8080,22 @@
45922
/* Maybe the spill reg contains a copy of reload_out. */
45923
if (rld[r].out != 0
45924
&& (REG_P (rld[r].out)
45925
-#ifdef AUTO_INC_DEC
45926
- || ! rld[r].out_reg
45927
-#endif
45928
- || REG_P (rld[r].out_reg)))
45929
+ || (rld[r].out_reg
45930
+ ? REG_P (rld[r].out_reg)
45931
+ /* The reload value is an auto-modification of
45932
+ some kind. For PRE_INC, POST_INC, PRE_DEC
45933
+ and POST_DEC, we record an equivalence
45934
+ between the reload register and the operand
45935
+ on the optimistic assumption that we can make
45936
+ the equivalence hold. reload_as_needed must
45937
+ then either make it hold or invalidate the
45938
+ equivalence.
45939
+
45940
+ PRE_MODIFY and POST_MODIFY addresses are reloaded
45941
+ somewhat differently, and allowing them here leads
45942
+ to problems. */
45943
+ : (GET_CODE (rld[r].out) != POST_MODIFY
45944
+ && GET_CODE (rld[r].out) != PRE_MODIFY))))
45945
{
45946
rtx reg;
45947
enum machine_mode mode;
45948
@@ -8706,7 +9039,7 @@
45949
be used as an address. */
45950
45951
if (! post)
45952
- emit_insn (gen_move_insn (reloadreg, incloc));
45953
+ add_insn = emit_insn (gen_move_insn (reloadreg, incloc));
45954
45955
return add_insn;
45956
}
45957
39288
--- a/src/gcc/reorg.c
45958
39289
+++ b/src/gcc/reorg.c
45959
39290
@@ -161,8 +161,11 @@
46644
39975
case SCRATCH:
46645
39976
/* SCRATCH must be shared because they represent distinct values. */
46646
39977
return orig;
46647
@@ -429,7 +431,15 @@
46648
case 'n':
46649
case 'i':
46650
if (XINT (x, i) != XINT (y, i))
46651
- return 0;
46652
+ {
46653
+#ifndef GENERATOR_FILE
46654
+ if (((code == ASM_OPERANDS && i == 6)
46655
+ || (code == ASM_INPUT && i == 1))
46656
+ && locator_eq (XINT (x, i), XINT (y, i)))
46657
+ break;
46658
+#endif
46659
+ return 0;
46660
+ }
46661
break;
46662
46663
case 'V':
46664
@@ -549,7 +559,15 @@
46665
case 'n':
46666
case 'i':
46667
if (XINT (x, i) != XINT (y, i))
46668
- return 0;
46669
+ {
46670
+#ifndef GENERATOR_FILE
46671
+ if (((code == ASM_OPERANDS && i == 6)
46672
+ || (code == ASM_INPUT && i == 1))
46673
+ && locator_eq (XINT (x, i), XINT (y, i)))
46674
+ break;
46675
+#endif
46676
+ return 0;
46677
+ }
46678
break;
46679
46680
case 'V':
46681
39978
--- a/src/gcc/rtl.def
46682
39979
+++ b/src/gcc/rtl.def
46683
39980
@@ -296,6 +296,10 @@
46757
40054
break;
46758
40055
--- a/src/gcc/sel-sched-ir.c
46759
40056
+++ b/src/gcc/sel-sched-ir.c
46760
@@ -686,7 +686,7 @@
40057
@@ -688,7 +688,7 @@
46761
40058
46762
40059
/* Find fallthrough edge. */
46763
40060
gcc_assert (BLOCK_FOR_INSN (insn)->prev_bb);
46768
40065
|| (candidate->src != BLOCK_FOR_INSN (last_scheduled_insn)
46769
40066
--- a/src/gcc/sel-sched.c
46770
40067
+++ b/src/gcc/sel-sched.c
46771
@@ -617,8 +617,8 @@
40068
@@ -618,8 +618,8 @@
46772
40069
if (bb == BLOCK_FOR_INSN (succ))
46773
40070
return true;
46774
40071
46779
40076
else
46780
40077
return false;
46781
40078
46782
@@ -4911,7 +4911,7 @@
40079
@@ -4914,7 +4914,7 @@
46783
40080
next = PREV_INSN (insn);
46784
40081
BND_TO (bnd) = insn;
46785
40082
46788
40085
block_next = ft_edge->dest;
46789
40086
/* There must be a fallthrough block (or where should go
46790
40087
control flow in case of false jump predicate otherwise?). */
40088
--- a/src/gcc/simplify-rtx.c
40089
+++ b/src/gcc/simplify-rtx.c
40090
@@ -2417,6 +2417,46 @@
40091
XEXP (op0, 1), mode),
40092
op1);
40093
40094
+ /* Given (xor (and A B) C), using P^Q == (~P&Q) | (~Q&P),
40095
+ we can transform like this:
40096
+ (A&B)^C == ~(A&B)&C | ~C&(A&B)
40097
+ == (~A|~B)&C | ~C&(A&B) * DeMorgan's Law
40098
+ == ~A&C | ~B&C | A&(~C&B) * Distribute and re-order
40099
+ Attempt a few simplifications when B and C are both constants. */
40100
+ if (GET_CODE (op0) == AND
40101
+ && CONST_INT_P (op1)
40102
+ && CONST_INT_P (XEXP (op0, 1)))
40103
+ {
40104
+ rtx a = XEXP (op0, 0);
40105
+ rtx b = XEXP (op0, 1);
40106
+ rtx c = op1;
40107
+ HOST_WIDE_INT bval = INTVAL (b);
40108
+ HOST_WIDE_INT cval = INTVAL (c);
40109
+
40110
+ rtx na_c
40111
+ = simplify_binary_operation (AND, mode,
40112
+ simplify_gen_unary (NOT, mode, a, mode),
40113
+ c);
40114
+ if ((~cval & bval) == 0)
40115
+ {
40116
+ /* Try to simplify ~A&C | ~B&C. */
40117
+ if (na_c != NULL_RTX)
40118
+ return simplify_gen_binary (IOR, mode, na_c,
40119
+ GEN_INT (~bval & cval));
40120
+ }
40121
+ else
40122
+ {
40123
+ /* If ~A&C is zero, simplify A&(~C&B) | ~B&C. */
40124
+ if (na_c == const0_rtx)
40125
+ {
40126
+ rtx a_nc_b = simplify_gen_binary (AND, mode, a,
40127
+ GEN_INT (~cval & bval));
40128
+ return simplify_gen_binary (IOR, mode, a_nc_b,
40129
+ GEN_INT (~bval & cval));
40130
+ }
40131
+ }
40132
+ }
40133
+
40134
/* (xor (comparison foo bar) (const_int 1)) can become the reversed
40135
comparison if STORE_FLAG_VALUE is 1. */
40136
if (STORE_FLAG_VALUE == 1
46791
40137
--- a/src/gcc/stmt.c
46792
40138
+++ b/src/gcc/stmt.c
46793
40139
@@ -117,7 +117,8 @@
46937
40283
};
46938
40284
46939
40285
/* Determine whether "1 << x" is relatively cheap in word_mode. */
46940
@@ -2130,10 +2152,193 @@
40286
@@ -2130,10 +2152,195 @@
46941
40287
return CODE_LABEL_NUMBER (d2->label) - CODE_LABEL_NUMBER (d1->label);
46942
40288
}
46943
40289
47101
40447
+set_jump_prob (rtx jump, int prob, int *inv_scale)
47102
40448
+{
47103
40449
+ /* j[i] = p[i] * scale / REG_BR_PROB_BASE. */
47104
+ int jump_prob = prob * REG_BR_PROB_BASE / *inv_scale;
40450
+ int jump_prob = (*inv_scale > 0
40451
+ ? prob * REG_BR_PROB_BASE / *inv_scale
40452
+ : REG_BR_PROB_BASE / 2);
47105
40453
+ /* f[i] = REG_BR_PROB_BASE - j[i]. */
47106
40454
+ int fallthrough_prob = REG_BR_PROB_BASE - jump_prob;
47107
40455
+
47133
40481
47134
40482
INDEX_EXPR is the value being switched on, which is of
47135
40483
type INDEX_TYPE. MINVAL is the lowest case value of in
47136
@@ -2147,14 +2352,17 @@
40484
@@ -2147,14 +2354,17 @@
47137
40485
47138
40486
static void
47139
40487
emit_case_bit_tests (tree index_type, tree index_expr, tree minval,
47153
40501
47154
40502
count = 0;
47155
40503
for (n = nodes; n; n = n->right)
47156
@@ -2169,8 +2377,11 @@
40504
@@ -2169,8 +2379,11 @@
47157
40505
gcc_assert (count < MAX_CASE_BIT_TESTS);
47158
40506
test[i].hi = 0;
47159
40507
test[i].lo = 0;
47165
40513
count++;
47166
40514
}
47167
40515
else
47168
@@ -2181,10 +2392,11 @@
40516
@@ -2181,10 +2394,11 @@
47169
40517
hi = tree_low_cst (fold_build2 (MINUS_EXPR, index_type,
47170
40518
n->high, minval), 1);
47171
40519
for (j = lo; j <= hi; j++)
47181
40529
}
47182
40530
47183
40531
qsort (test, count, sizeof(*test), case_bit_test_cmp);
47184
@@ -2198,20 +2410,20 @@
40532
@@ -2198,20 +2412,20 @@
47185
40533
mode = TYPE_MODE (index_type);
47186
40534
expr = expand_normal (range);
47187
40535
if (default_label)
47211
40559
}
47212
40560
47213
40561
if (default_label)
47214
@@ -2382,7 +2594,8 @@
40562
@@ -2382,7 +2596,8 @@
47215
40563
range = maxval;
47216
40564
}
47217
40565
emit_case_bit_tests (index_type, index_expr, minval, range,
47223
40571
/* If range of values is much bigger than number of values,
47224
40572
--- a/src/gcc/stor-layout.c
47225
40573
+++ b/src/gcc/stor-layout.c
47226
@@ -619,11 +619,15 @@
40574
@@ -507,6 +507,34 @@
40575
return MIN (BIGGEST_ALIGNMENT, MAX (1, mode_base_align[mode]*BITS_PER_UNIT));
40576
}
40577
40578
+/* Return the natural mode of an array, given that it is SIZE bytes in
40579
+ total and has elements of type ELEM_TYPE. */
40580
+
40581
+static enum machine_mode
40582
+mode_for_array (tree elem_type, tree size)
40583
+{
40584
+ tree elem_size;
40585
+ unsigned HOST_WIDE_INT int_size, int_elem_size;
40586
+ bool limit_p;
40587
+
40588
+ /* One-element arrays get the component type's mode. */
40589
+ elem_size = TYPE_SIZE (elem_type);
40590
+ if (simple_cst_equal (size, elem_size))
40591
+ return TYPE_MODE (elem_type);
40592
+
40593
+ limit_p = true;
40594
+ if (host_integerp (size, 1) && host_integerp (elem_size, 1))
40595
+ {
40596
+ int_size = tree_low_cst (size, 1);
40597
+ int_elem_size = tree_low_cst (elem_size, 1);
40598
+ if (int_elem_size > 0
40599
+ && int_size % int_elem_size == 0
40600
+ && targetm.array_mode_supported_p (TYPE_MODE (elem_type),
40601
+ int_size / int_elem_size))
40602
+ limit_p = false;
40603
+ }
40604
+ return mode_for_size_tree (size, MODE_INT, limit_p);
40605
+}
40606
40607
/* Subroutine of layout_decl: Force alignment required for the data type.
40608
But if the decl itself wants greater alignment, don't override that. */
40609
@@ -619,11 +647,15 @@
47227
40610
}
47228
40611
47229
40612
/* See if we can use an ordinary integer mode for a bit-field.
47242
40625
{
47243
40626
enum machine_mode xmode
47244
40627
= mode_for_size_tree (DECL_SIZE (decl), MODE_INT, 1);
47245
@@ -2029,11 +2033,6 @@
47246
#else
47247
TYPE_ALIGN (type) = MAX (TYPE_ALIGN (element), BITS_PER_UNIT);
47248
#endif
47249
- if (!TYPE_SIZE (element))
47250
- /* We don't know the size of the underlying element type, so
47251
- our alignment calculations will be wrong, forcing us to
47252
- fall back on structural equality. */
47253
- SET_TYPE_STRUCTURAL_EQUALITY (type);
47254
TYPE_USER_ALIGN (type) = TYPE_USER_ALIGN (element);
47255
SET_TYPE_MODE (type, BLKmode);
47256
if (TYPE_SIZE (type) != 0
40628
@@ -2040,14 +2072,8 @@
40629
&& (TYPE_MODE (TREE_TYPE (type)) != BLKmode
40630
|| TYPE_NO_FORCE_BLK (TREE_TYPE (type))))
40631
{
40632
- /* One-element arrays get the component type's mode. */
40633
- if (simple_cst_equal (TYPE_SIZE (type),
40634
- TYPE_SIZE (TREE_TYPE (type))))
40635
- SET_TYPE_MODE (type, TYPE_MODE (TREE_TYPE (type)));
40636
- else
40637
- SET_TYPE_MODE (type, mode_for_size_tree (TYPE_SIZE (type),
40638
- MODE_INT, 1));
40639
-
40640
+ SET_TYPE_MODE (type, mode_for_array (TREE_TYPE (type),
40641
+ TYPE_SIZE (type)));
40642
if (TYPE_MODE (type) != BLKmode
40643
&& STRICT_ALIGNMENT && TYPE_ALIGN (type) < BIGGEST_ALIGNMENT
40644
&& TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (TYPE_MODE (type)))
47257
40645
--- a/src/gcc/system.h
47258
40646
+++ b/src/gcc/system.h
47259
40647
@@ -761,7 +761,8 @@
47279
40667
#ifndef TARGET_ASM_FILE_START_APP_OFF
47280
40668
#define TARGET_ASM_FILE_START_APP_OFF false
47281
40669
#endif
47282
@@ -1030,6 +1034,7 @@
40670
@@ -549,12 +553,17 @@
40671
#define TARGET_VECTOR_MODE_SUPPORTED_P hook_bool_mode_false
40672
#endif
40673
40674
+#ifndef TARGET_ARRAY_MODE_SUPPORTED_P
40675
+#define TARGET_ARRAY_MODE_SUPPORTED_P hook_bool_mode_uhwi_false
40676
+#endif
40677
+
40678
/* In hooks.c. */
40679
#define TARGET_CANNOT_MODIFY_JUMPS_P hook_bool_void_false
40680
#define TARGET_BRANCH_TARGET_REGISTER_CLASS \
40681
default_branch_target_register_class
40682
#define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED hook_bool_bool_false
40683
#define TARGET_HAVE_CONDITIONAL_EXECUTION default_have_conditional_execution
40684
+#define TARGET_LEGITIMATE_CONSTANT_P default_legitimate_constant_p
40685
#define TARGET_CANNOT_FORCE_CONST_MEM hook_bool_rtx_false
40686
#define TARGET_CANNOT_COPY_INSN_P NULL
40687
#define TARGET_COMMUTATIVE_P hook_bool_const_rtx_commutative_p
40688
@@ -957,6 +966,7 @@
40689
TARGET_BRANCH_TARGET_REGISTER_CLASS, \
40690
TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED, \
40691
TARGET_HAVE_CONDITIONAL_EXECUTION, \
40692
+ TARGET_LEGITIMATE_CONSTANT_P, \
40693
TARGET_CANNOT_FORCE_CONST_MEM, \
40694
TARGET_CANNOT_COPY_INSN_P, \
40695
TARGET_COMMUTATIVE_P, \
40696
@@ -981,6 +991,7 @@
40697
TARGET_ADDR_SPACE_HOOKS, \
40698
TARGET_SCALAR_MODE_SUPPORTED_P, \
40699
TARGET_VECTOR_MODE_SUPPORTED_P, \
40700
+ TARGET_ARRAY_MODE_SUPPORTED_P, \
40701
TARGET_RTX_COSTS, \
40702
TARGET_ADDRESS_COST, \
40703
TARGET_ALLOCATE_INITIAL_VALUE, \
40704
@@ -1030,6 +1041,7 @@
47283
40705
TARGET_EMUTLS, \
47284
40706
TARGET_OPTION_HOOKS, \
47285
40707
TARGET_EXTRA_LIVE_ON_ENTRY, \
47289
40711
TARGET_HAVE_SWITCHABLE_BSS_SECTIONS, \
47290
40712
--- a/src/gcc/target.h
47291
40713
+++ b/src/gcc/target.h
47292
@@ -1179,6 +1179,10 @@
40714
@@ -645,7 +645,10 @@
40715
/* Return true if the target supports conditional execution. */
40716
bool (* have_conditional_execution) (void);
40717
40718
- /* True if the constant X cannot be placed in the constant pool. */
40719
+ /* See tm.texi. */
40720
+ bool (* legitimate_constant_p) (enum machine_mode, rtx);
40721
+
40722
+ /* True if the constant X cannot be placed in the constant pool. */
40723
bool (* cannot_force_const_mem) (rtx);
40724
40725
/* True if the insn X cannot be duplicated. */
40726
@@ -764,6 +767,9 @@
40727
for further details. */
40728
bool (* vector_mode_supported_p) (enum machine_mode mode);
40729
40730
+ /* See tm.texi. */
40731
+ bool (* array_mode_supported_p) (enum machine_mode, unsigned HOST_WIDE_INT);
40732
+
40733
/* Compute a (partial) cost for rtx X. Return true if the complete
40734
cost has been computed, and false if subexpressions should be
40735
scanned. In either case, *TOTAL contains the cost result. */
40736
@@ -1179,6 +1185,10 @@
47293
40737
bits in the bitmap passed in. */
47294
40738
void (*live_on_entry) (bitmap);
47295
40739
47300
40744
/* True if unwinding tables should be generated by default. */
47301
40745
bool unwind_tables_default;
47302
40746
40747
--- a/src/gcc/targhooks.c
40748
+++ b/src/gcc/targhooks.c
40749
@@ -1008,4 +1008,15 @@
40750
#endif
40751
}
40752
40753
+bool
40754
+default_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
40755
+ rtx x ATTRIBUTE_UNUSED)
40756
+{
40757
+#ifdef LEGITIMATE_CONSTANT_P
40758
+ return LEGITIMATE_CONSTANT_P (x);
40759
+#else
40760
+ return true;
40761
+#endif
40762
+}
40763
+
40764
#include "gt-targhooks.h"
40765
--- a/src/gcc/targhooks.h
40766
+++ b/src/gcc/targhooks.h
40767
@@ -132,3 +132,4 @@
40768
extern rtx default_addr_space_convert (rtx, tree, tree);
40769
extern unsigned int default_case_values_threshold (void);
40770
extern bool default_have_conditional_execution (void);
40771
+extern bool default_legitimate_constant_p (enum machine_mode, rtx);
47303
40772
--- a/src/gcc/testsuite/ChangeLog
47304
40773
+++ b/src/gcc/testsuite/ChangeLog
47305
@@ -1,3 +1,450 @@
47306
+2011-03-31 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
47307
+
47308
+ PR target/16292
47309
+ * gfortran.dg/g77/cabs.f: Only xfail execution on mips-sgi-irix6*
47310
+ with -O0 except with -mabi=32.
47311
+
47312
+2011-03-28 Jason Merrill <jason@redhat.com>
47313
+
47314
+ Revert:
47315
+ * g++.dg/cpp0x/move1.C: New.
47316
+
47317
+2011-03-28 Richard Sandiford <richard.sandiford@linaro.org>
47318
+
47319
+ PR target/47553
47320
+ * gcc.target/arm/neon-vld-1.c: New test.
47321
+
47322
+2011-03-25 Jason Merrill <jason@redhat.com>
47323
+
47324
+ * g++.dg/cpp0x/move1.C: New.
47325
+
47326
+2011-03-21 Michael Meissner <meissner@linux.vnet.ibm.com>
47327
+
47328
+ PR preprocessor/48192
47329
+ Backport from trunk
47330
+ * gcc.target/powerpc/pr48192.c: New file.
47331
+
47332
+2011-03-18 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
47333
+
47334
+ PR middle-end/47405
47335
+ * gcc.dg/torture/20090618-1.c: Skip on mips-sgi-irix*.
47336
+
47337
+2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
47338
+
47339
+ PR rtl-optimization/47166
47340
+ * gcc.c-torture/execute/postmod-1.c: New test.
47341
+
47342
+2011-03-13 Thomas Koenig <tkoenig@gcc.gnu.org>
47343
+
47344
+ PR libfortran/48066
47345
+ Backport from trunk
47346
+ * gfortran.dg/intrinsic_ifunction_2.f90: Correct PR number.
47347
+
47348
+2011-03-13 Paul Thomas <pault@gcc.gnu.org>
47349
+
47350
+ PR fortran/47348
47351
+ * gfortran.dg/array_constructor_36.f90 : New test.
47352
+ * gfortran.dg/bounds_check_10.f90 : Change dg-output message to
47353
+ allow for comparison between different elements of the array
47354
+ constructor at different levels of optimization.
47355
+
47356
+2011-03-11 Jason Merrill <jason@redhat.com>
47357
+
47358
+ * g++.dg/template/error45.C: New.
47359
+
47360
+2011-03-10 Jason Merrill <jason@redhat.com>
47361
+
47362
+ * g++.dg/template/array22.C: New.
47363
+
47364
+2011-03-11 Richard Guenther <rguenther@suse.de>
47365
+
47366
+ PR tree-optimization/47278
47367
+ * gcc.dg/torture/pr47278-1.c: Require visibility support.
47368
+ * gcc.dg/torture/pr47278-2.c: Likewise.
47369
+
47370
+2011-03-09 Jason Merrill <jason@redhat.com>
47371
+
47372
+ * g++.dg/template/nontype22.C: New.
47373
+
47374
+2011-03-08 Jason Merrill <jason@redhat.com>
47375
+
47376
+ * g++.dg/template/anon5.C: New.
47377
+
47378
+2011-03-08 Jason Merrill <jason@redhat.com>
47379
+
47380
+ * g++.dg/cpp0x/variadic105.C: New.
47381
+
47382
+2011-03-08 Jason Merrill <jason@redhat.com>
47383
+
47384
+ * g++.dg/template/nontype21.C: New.
47385
+
47386
+2011-03-08 Dodji Seketeli <dodji@redhat.com>
47387
+
47388
+ * g++.dg/lookup/template3.C: New test.
47389
+
47390
+2011-03-08 Richard Guenther <rguenther@suse.de>
47391
+
47392
+ Backport from mainline
47393
+ 2010-10-18 Richard Guenther <rguenther@suse.de>
47394
+
47395
+ PR tree-optimization/45967
47396
+ * gcc.dg/torture/pr45967.c: New testcase.
47397
+ * gcc.dg/torture/pr45967-2.c: Likewise.
47398
+ * gcc.dg/torture/pr45967-3.c: Likewise.
47399
+ * gcc.dg/torture/pr39074-2.c: Adjust.
47400
+ * gcc.dg/torture/pta-escape-1.c: Likewise
47401
+ * gcc.dg/torture/pta-ptrarith-1.c: Likewise
47402
+ * gcc.dg/tree-ssa/pta-callused.c: Likewise
47403
+ * gcc.dg/tree-ssa/pta-escape-1.c: Likewise
47404
+ * gcc.dg/tree-ssa/pta-escape-2.c: Likewise
47405
+ * gcc.dg/tree-ssa/pta-escape-3.c: Likewise
47406
+ * gcc.dg/tree-ssa/ssa-pre-21.c: Likewise
47407
+
47408
+2011-03-08 Richard Guenther <rguenther@suse.de>
47409
+
47410
+ PR tree-optimization/47278
47411
+ * gcc.dg/torture/pr47278-1.c: New testcase.
47412
+ * gcc.dg/torture/pr47278-2.c: Likewise.
47413
+
47414
+2011-03-07 Pat Haugen <pthaugen@us.ibm.com>
47415
+
47416
+ Backport from mainline
47417
+ 2011-03-07 Pat Haugen <pthaugen@us.ibm.com>
47418
+
47419
+ PR target/47862
47420
+ * gcc.target/powerpc/pr47862.c: New.
47421
+
47422
+2011-03-06 Jerry DeLisle <jvdelisle@gcc.gnu.org>
47423
+
47424
+ Backport from mainline
47425
+ PR libgfortran/47778
47426
+ * gfortran.dg/namelist_71.f90: New test.
47427
+
47428
+2011-03-04 Jerry DeLisle <jvdelisle@gcc.gnu.org>
47429
+
47430
+ Backport from mainline
47431
+ PR libgfortran/47878
47432
+ * gfortran.dg/pr47878.f90: New test.
47433
+
47434
+2011-03-01 Jason Merrill <jason@redhat.com>
47435
+
47436
+ * g++.dg/cpp0x/lambda/lambda-98.C: New.
47437
+
47438
+2011-03-02 Richard Guenther <rguenther@suse.de>
47439
+
47440
+ Backport from mainline
47441
+ 2011-02-07 Richard Guenther <rguenther@suse.de>
47442
+
47443
+ PR tree-optimization/47615
47444
+ * g++.dg/opt/pr47615.C: New testcase.
47445
+
47446
+2011-03-01 Richard Guenther <rguenther@suse.de>
47447
+
47448
+ Backport from mainline
47449
+ 2011-02-08 Richard Guenther <rguenther@suse.de>
47450
+
47451
+ PR middle-end/47639
47452
+ * g++.dg/opt/pr47639.c: New testcase.
47453
+
47454
+2011-03-01 Richard Guenther <rguenther@suse.de>
47455
+
47456
+ Backport from mainline
47457
+ 2011-03-01 Richard Guenther <rguenther@suse.de>
47458
+
47459
+ PR tree-optimization/47890
47460
+ * gcc.dg/torture/pr47890.c: New testcase.
47461
+
47462
+ 2010-12-01 Richard Guenther <rguenther@suse.de>
47463
+
47464
+ PR tree-optimization/46723
47465
+ * gcc.dg/torture/pr46723.c: New testcase.
47466
+
47467
+2011-02-26 Jason Merrill <jason@redhat.com>
47468
+
47469
+ * g++.dg/template/this-targ1.C: New.
47470
+
47471
+2011-02-19 Alexandre Oliva <aoliva@redhat.com>
47472
+
47473
+ PR tree-optimization/46620
47474
+ * gcc.dg/pr46620.c: New.
47475
+
47476
+2011-02-19 Tobias Burnus
47477
+
47478
+ PR fortran/47775
47479
+ * gfortran.dg/func_result_6.f90: New.
47480
+
47481
+2011-02-17 Uros Bizjak <ubizjak@gmail.com>
47482
+
47483
+ PR target/43653
47484
+ * gcc.target/i386/pr43653.c: New test.
47485
+
47486
+2011-02-14 Tobias Burnus <burnus@net-b.de>
47487
+
47488
+ * gfortran.dg/argument_checking_13.f90: Update dg-error.
47489
+ * gfortran.dg/argument_checking_17.f90: New.
47490
+
47491
+2011-02-10 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
47492
+
47493
+ PR target/46610
47494
+ * gcc.target/mips/save-restore-1.c: Skip on mips-sgi-irix6*.
47495
+ * gcc.target/mips/save-restore-3.c: Likewise.
47496
+ * gcc.target/mips/save-restore-4.c: Likewise.
47497
+ * gcc.target/mips/save-restore-5.c: Likewise.
47498
+
47499
+ PR target/47683
47500
+ * g++.dg/tree-prof/partition1.C: Skip on mips-sgi-irix*.
47501
+ * g++.dg/tree-prof/partition2.C: Likewise.
47502
+
47503
+2011-02-07 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
47504
+
47505
+ Backport from mainline:
47506
+ 2010-07-23 Uros Bizjak <ubizjak@gmail.com>
47507
+
47508
+ * lib/target-supports.exp (check_avx_hw_available): New procedure.
47509
+ (check_effective_target_avx_runtime): New procedure.
47510
+
47511
+ * gcc.dg/compat/vector-1b_main.c: Use avx_runtime effective target.
47512
+ Remove cpuid.h include and __get_cpuid test.
47513
+ * gcc.dg/compat/vector-2b_main.c: Ditto.
47514
+
47515
+ * gcc.target/i386/avx-check.h (main): Also check bit_OSXSAVE.
47516
+
47517
+2011-02-03 Michael Meissner <meissner@linux.vnet.ibm.com>
47518
+
47519
+ Backport from mainline:
47520
+ 2011-02-02 Michael Meissner <meissner@linux.vnet.ibm.com>
47521
+ PR target/47272
47522
+ * gcc.target/powerpc/vsx-builtin-8.c: New file, test vec_vsx_ld
47523
+ and vec_vsx_st.
47524
+
47525
+ * gcc.target/powerpc/avoid-indexed-addresses.c: Disable altivec
47526
+ and vsx so a default --with-cpu=power7 doesn't give an error
47527
+ when -mavoid-indexed-addresses is used.
47528
+
47529
+ * gcc.target/powerpc/ppc32-abi-dfp-1.c: Rewrite to use an asm
47530
+ wrapper function to save the arguments and then jump to the real
47531
+ function, rather than depending on the compiler not to move stuff
47532
+ before an asm.
47533
+ * gcc.target/powerpc/ppc64-abi-dfp-2.c: Ditto.
47534
+
47535
+2011-02-03 Jonathan Wakely <jwakely.gcc@gmail.com>
47536
+
47537
+ PR c++/47589
47538
+ * g++.dg/pr47589.C: New test.
47539
+
47540
+2011-02-01 Richard Guenther <rguenther@suse.de>
47541
+
47542
+ PR tree-optimization/47541
47543
+ * g++.dg/torture/pr47541.C: New testcase.
47544
+
47545
+2011-01-31 Nathan Froyd <froydnj@codesourcery.com>
47546
+
47547
+ Backport from mainline:
47548
+ 2010-12-30 Nathan Froyd <froydnj@codesourcery.com>
47549
+
47550
+ PR target/44606
47551
+ * gcc.dg/pr44606.c: New test.
47552
+
47553
+2011-01-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
47554
+
47555
+ * gcc.dg/tree-ssa/pr42585.c: Disable on power, arm, sh, s390 and
47556
+ s390x.
47557
+
47558
+2011-01-26 Eric Botcazou <ebotcazou@adacore.com>
47559
+
47560
+ * gcc.c-torture/compile/20110126-1.c: New test.
47561
+
47562
+2011-01-25 Tobias Burnus <burnus@net-b.de>
47563
+
47564
+ Backport from mainline
47565
+ 2011-01-17 Jakub Jelinek <jakub@redhat.com>
47566
+
47567
+ PR fortran/47331
47568
+ * gfortran.dg/gomp/pr47331.f90: New test.
47569
+
47570
+2011-01-25 Tobias Burnus <burnus@net-b.de>
47571
+
47572
+ PR fortran/47448
47573
+ * gfortran.dg/redefined_intrinsic_assignment_2.f90: New.
47574
+
47575
+2011-01-25 Richard Guenther <rguenther@suse.de>
47576
+
47577
+ PR middle-end/47411
47578
+ * gcc.dg/torture/pr47411.c: New testcase.
47579
+
47580
+2011-01-24 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
47581
+
47582
+ * gfortran.dg/cray_pointers_2.f90: Avoid cycling through
47583
+ optimization options.
47584
+
47585
+2011-01-24 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
47586
+
47587
+ * gfortran.dg/array_constructor_33.f90: Use dg-timeout-factor 4.
47588
+
47589
+2011-01-21 Richard Guenther <rguenther@suse.de>
47590
+
47591
+ PR tree-optimization/47365
47592
+ * gcc.dg/torture/pr47365.c: New testcase.
47593
+ * gcc.dg/tree-ssa/pr47392.c: Likewise.
47594
+
47595
+2011-01-21 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
47596
+
47597
+ * g++.dg/other/anon5.C: Skip on mips-sgi-irix*.
47598
+
47599
+2011-01-17 Eric Botcazou <ebotcazou@adacore.com>
47600
+
47601
+ Backport from mainline
47602
+ 2010-11-22 Eric Botcazou <ebotcazou@adacore.com>
47603
+
47604
+ * gcc.dg/pr28796-2.c: SKIP on SPARC/Solaris 8.
47605
+
47606
+ PR rtl-optimization/46603
47607
+ * gcc.dg/vect/slp-multitypes-2.c: XFAIL execution on SPARC 32-bit.
47608
+
47609
+ 2010-08-31 Bingfeng Mei <bmei@broadcom.com>
47610
+
47611
+ * gcc.dg/vect/pr43430-1.c: Requires vect_condition target.
47612
+
47613
+2011-01-17 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
47614
+
47615
+ * g++.old-deja/g++.other/init19.C: Don't XFAIL on mips-sgi-irix*.
47616
+
47617
+2011-01-17 H.J. Lu <hongjiu.lu@intel.com>
47618
+
47619
+ Backport from mainline
47620
+ 2011-01-17 H.J. Lu <hongjiu.lu@intel.com>
47621
+
47622
+ PR target/47318
47623
+ * gcc.target/i386/avx-vmaskmovpd-1.c: New.
47624
+ * gcc.target/i386/avx-vmaskmovpd-2.c: Likewise.
47625
+ * gcc.target/i386/avx-vmaskmovps-1.c: Likewise.
47626
+ * gcc.target/i386/avx-vmaskmovps-1.c: Likewise.
47627
+
47628
+ * gcc.target/i386/avx-vmaskmovpd-256-1.c (avx_test): Load mask
47629
+ as __m256i.
47630
+ * gcc.target/i386/avx-vmaskmovpd-256-2.c (avx_test): Likewise.
47631
+ * gcc.target/i386/avx-vmaskmovps-256-1.c (avx_test): Likewise.
47632
+ * gcc.target/i386/avx-vmaskmovps-256-2.c (avx_test): Likewise.
47633
+
47634
+2011-01-17 Richard Guenther <rguenther@suse.de>
47635
+
47636
+ Backport from mainline
47637
+ PR tree-optimization/47286
47638
+ * gcc.dg/tree-ssa/pr47286.c: New testcase.
47639
+
47640
+ PR tree-optimization/44592
47641
+ * gfortran.dg/pr44592.f90: New testcase.
47642
+
47643
+2011-01-16 Jakub Jelinek <jakub@redhat.com>
47644
+
47645
+ Backport from mainline
47646
+ 2011-01-07 Jakub Jelinek <jakub@redhat.com>
47647
+
47648
+ PR target/47201
47649
+ * gcc.dg/pr47201.c: New test.
47650
+
47651
+ 2011-01-06 Jakub Jelinek <jakub@redhat.com>
47652
+
47653
+ PR c/47150
47654
+ * gcc.c-torture/compile/pr47150.c: New test.
47655
+
47656
+ 2010-12-21 Jakub Jelinek <jakub@redhat.com>
47657
+
47658
+ PR target/46880
47659
+ * gcc.target/i386/pr46880.c: New test.
47660
+
47661
+ PR middle-end/45852
47662
+ * gcc.target/i386/pr45852.c: New test.
47663
+
47664
+ 2010-12-16 Jakub Jelinek <jakub@redhat.com>
47665
+
47666
+ PR tree-optimization/43655
47667
+ * g++.dg/opt/pr43655.C: New test.
47668
+
47669
+ PR debug/46893
47670
+ * gcc.dg/pr46893.c: New test.
47671
+
47672
+ 2010-12-10 Jakub Jelinek <jakub@redhat.com>
47673
+
47674
+ PR rtl-optimization/46804
47675
+ * gfortran.dg/pr46804.f90: New test.
47676
+
47677
+ PR rtl-optimization/46865
47678
+ * gcc.target/i386/pr46865-1.c: New test.
47679
+ * gcc.target/i386/pr46865-2.c: New test.
47680
+
47681
+ PR tree-optimization/46864
47682
+ * g++.dg/opt/pr46864.C: New test.
47683
+
47684
+2011-01-13 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
47685
+
47686
+ * gfortran.dg/cray_pointers_2.f90: Use dg-timeout-factor 4.
47687
+
47688
+2011-01-12 Eric Botcazou <ebotcazou@adacore.com>
47689
+
47690
+ PR testsuite/33033
47691
+ * gcc.dg/20061124-1.c: Pass -mcpu=v9 on the SPARC.
47692
+
47693
+2011-02-01 Thomas Koenig <tkoenig@gcc.gnu.org>
47694
+
47695
+ Backport from mainline
47696
+ PR fortran/45338
47697
+ * gfortran.dg/userdef_operator_2.f90: New test case.
47698
+
47699
+2010-12-27 Yao Qi <yao@codesourcery.com>
47700
+
47701
+ Backport from mainline:
47702
+ 2010-10-14 Yao Qi <yao@codesourcery.com>
47703
+
47704
+ PR target/45447
47705
+ * gcc.target/arm/pr45447.c: New test.
47706
+
47707
+2010-12-24 Eric Botcazou <ebotcazou@adacore.com>
47708
+
47709
+ * gnat.dg/opt13_pkg.ad[sb]: Fix line ending.
47710
+
47711
+2010-12-22 Sebastian Pop <sebastian.pop@amd.com>
47712
+
47713
+ PR tree-optimization/46758
47714
+ * gcc.dg/graphite/run-id-pr46758.c: New.
47715
+
47716
+2010-12-23 Sebastian Pop <sebastian.pop@amd.com>
47717
+
47718
+ PR tree-optimization/45552
47719
+ * gcc.dg/graphite/pr45552.c
47720
+
47721
+
47722
+2010-12-23 Sebastian Pop <sebastian.pop@amd.com>
47723
+
47724
+ PR tree-optimization/43023
47725
+ * gfortran.dg/ldist-1.f90: Adjust pattern.
47726
+ * gfortran.dg/ldist-pr43023.f90: New.
47727
+
47728
+2010-12-21 Martin Jambor <mjambor@suse.cz>
47729
+
47730
+ PR middle-end/46734
47731
+ * g++.dg/tree-ssa/pr46734.C: New test.
47732
+
47733
+2010-12-18 Alexandre Oliva <aoliva@redhat.com>
47734
+
47735
+ PR debug/46756
47736
+ * gfortran.dg/debug/pr46756.f: New.
47737
+
47738
+2010-12-18 Alexandre Oliva <aoliva@redhat.com>
47739
+
47740
+ PR debug/46782
47741
+ * gcc.dg/debug/pr46782.c: New.
47742
+
47743
+2010-12-17 Daniel Kraft <d@domob.eu>
47744
+
47745
+ PR fortran/46794
47746
+ * gfortran.dg/power2.f90: Initialize variables.
47747
+
47748
+2010-12-16 Eric Botcazou <ebotcazou@adacore.com>
47749
+
47750
+ * gnat.dg/opt13.adb: New test.
47751
+ * gnat.dg/opt13_pkg.ad[sb]: New helper.
47752
+
47753
2010-12-16 Release Manager
47754
47755
* GCC 4.5.2 released.
47756
@@ -11,7 +458,7 @@
47757
47758
Backport from mainline
47759
2010-12-06 Jakub Jelinek <jakub@redhat.com>
47760
-
47761
+
47762
PR target/43897
47763
* gcc.target/ia64/pr43897.c: New test.
47764
47765
@@ -30,7 +477,7 @@
47766
* gcc.dg/pr46499-2.c: New test.
47767
47768
2010-11-20 Jakub Jelinek <jakub@redhat.com>
47769
-
47770
+
47771
PR c++/46538
47772
* g++.dg/other/error34.C: New test.
47773
40774
@@ -1,3 +1,53 @@
40775
+2010-05-05 Ira Rosen <ira.rosen@linaro.org>
40776
+
40777
+ Backport from mainline:
40778
+ 2011-04-18 Ulrich Weigand <ulrich.weigand@linaro.org>
40779
+ Ira Rosen <ira.rosen@linaro.org>
40780
+
40781
+ PR target/48252
40782
+ * gcc.target/arm/pr48252.c: New test.
40783
+
40784
+2011-05-04 Uros Bizjak <ubizjak@gmail.com>
40785
+
40786
+ Backport from mainline
40787
+ 2011-04-21 Uros Bizjak <ubizjak@gmail.com>
40788
+
40789
+ PR target/48708
40790
+ * gcc.target/i386/pr48708.c: New test.
40791
+
40792
+2011-05-04 Uros Bizjak <ubizjak@gmail.com>
40793
+
40794
+ Backport from mainline
40795
+ 2010-12-08 H.J. Lu <hongjiu.lu@intel.com>
40796
+
40797
+ * gcc.target/i386/sse2-init-v2di-2.c: Add "-dp" and update
40798
+ expected scan.
40799
+
40800
+2011-05-03 Jakub Jelinek <jakub@redhat.com>
40801
+
40802
+ PR target/48774
40803
+ * gcc.dg/pr48774.c: New test.
40804
+
40805
+ Backport from mainline
40806
+ 2011-04-30 Jakub Jelinek <jakub@redhat.com>
40807
+
40808
+ PR tree-optimization/48809
40809
+ * gcc.c-torture/execute/pr48809.c: New test.
40810
+
40811
+ 2011-04-27 Jakub Jelinek <jakub@redhat.com>
40812
+
40813
+ PR c/48742
40814
+ * gcc.c-torture/compile/pr48742.c: New test.
40815
+
40816
+ 2011-04-23 Jakub Jelinek <jakub@redhat.com>
40817
+
40818
+ PR c/48685
40819
+ * gcc.dg/pr48685.c: New test.
40820
+
40821
+2011-04-27 Jason Merrill <jason@redhat.com>
40822
+
40823
+ * g++.dg/parse/ambig6.C: New.
40824
+
40825
2011-04-28 Release Manager
40826
40827
* GCC 4.5.3 released.
47774
40828
--- a/src/gcc/testsuite/c-c++-common/abi-bf.c
47775
40829
+++ b/src/gcc/testsuite/c-c++-common/abi-bf.c
47776
40830
@@ -0,0 +1,3 @@
47816
40870
47817
40871
#include <arm_neon.h>
47818
40872
47819
--- a/src/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-98.C
47820
+++ b/src/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-98.C
47821
@@ -0,0 +1,8 @@
47822
+// PR c++/46159
47823
+// { dg-options -std=c++98 }
47824
+
47825
+void
47826
+f()
47827
+{
47828
+ int **p = new(int(*[2]));
47829
+}
47830
--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic105.C
47831
+++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic105.C
47832
@@ -0,0 +1,24 @@
47833
+// PR c++/47289
47834
+// { dg-options -std=c++0x }
47835
+// { dg-prune-output "note" }
47836
+
47837
+template <template <typename... __ARGS> class _F, typename... _ARGS>
47838
+auto reverse (_ARGS... args) -> decltype(_F<_ARGS...>::call_function(args...)) {
47839
+ return _F<_ARGS...>::call_function(args...);
47840
+}
47841
+
47842
+template <typename _T>
47843
+_T sum(_T x) { return x; }
47844
+
47845
+template <typename _T, typename... _ARGS>
47846
+_T sum(_T x, _ARGS... args) { return x + sum(args...); }
47847
+
47848
+template <typename _T, typename... _ARGS>
47849
+struct call_sum {
47850
+ static _T call_function(_T x1, _ARGS... args) { return sum(x1, args...); }
47851
+};
47852
+
47853
+int main() {
47854
+ // This shouldn't be an error; this is bug 35722.
47855
+ reverse<call_sum>(1,2); // { dg-bogus "no match" "" { xfail *-*-* } }
47856
+}
47857
40873
--- a/src/gcc/testsuite/g++.dg/debug/dwarf2/self-ref-1.C
47858
40874
+++ b/src/gcc/testsuite/g++.dg/debug/dwarf2/self-ref-1.C
47859
40875
@@ -0,0 +1,28 @@
47992
41008
+
47993
41009
+// { dg-final { scan-tree-dump-not "v = {}" "gimple" } }
47994
41010
+// { dg-final { cleanup-tree-dump "gimple" } }
47995
--- a/src/gcc/testsuite/g++.dg/lookup/template3.C
47996
+++ b/src/gcc/testsuite/g++.dg/lookup/template3.C
47997
@@ -0,0 +1,35 @@
47998
+// Origin PR c++/47957
47999
+// { dg-do compile }
48000
+
48001
+struct S
48002
+{
48003
+ int m;
48004
+
48005
+ S()
48006
+ : m(0)
48007
+ {
48008
+ }
48009
+};
48010
+
48011
+struct Base
48012
+{
48013
+ typedef S T;
48014
+};
48015
+
48016
+template<class T>
48017
+struct Derived : public Base
48018
+{
48019
+ int
48020
+ foo()
48021
+ {
48022
+ T a; // This is Base::T, not the template parameter.
48023
+ return a.m;
48024
+ }
48025
+};
48026
+
48027
+int
48028
+main()
48029
+{
48030
+ Derived<char> d;
48031
+ return d.foo();
48032
+}
48033
41011
--- a/src/gcc/testsuite/g++.dg/opt/combine.C
48034
41012
+++ b/src/gcc/testsuite/g++.dg/opt/combine.C
48035
41013
@@ -0,0 +1,72 @@
48105
41083
+ QScriptValue data = context->callee () ;
48106
41084
+ QScriptDebuggerBackendPrivate *self = qscriptvalue_cast<QScriptDebuggerBackendPrivate*> (data) ;
48107
41085
+}
48108
--- a/src/gcc/testsuite/g++.dg/opt/pr43655.C
48109
+++ b/src/gcc/testsuite/g++.dg/opt/pr43655.C
48110
@@ -0,0 +1,34 @@
48111
+// PR tree-optimization/43655
48112
+// { dg-do run }
48113
+// { dg-options "-O0 -ftree-ter" }
48114
+
48115
+extern "C" void abort ();
48116
+
48117
+struct C
48118
+{
48119
+ C (int i) : val(i) { }
48120
+ C (const C& c) : val(c.val) { }
48121
+ ~C (void) { val = 999; }
48122
+ C& operator = (const C& c) { val = c.val; return *this; }
48123
+ C& inc (int i) { val += i; return *this; }
48124
+ int val;
48125
+};
48126
+
48127
+C
48128
+f ()
48129
+{
48130
+ return C (3);
48131
+}
48132
+
48133
+C
48134
+f (int i)
48135
+{
48136
+ return f ().inc (i);
48137
+}
48138
+
48139
+int
48140
+main ()
48141
+{
48142
+ if (f (2).val != 5)
48143
+ abort ();
48144
+}
48145
--- a/src/gcc/testsuite/g++.dg/opt/pr46864.C
48146
+++ b/src/gcc/testsuite/g++.dg/opt/pr46864.C
48147
@@ -0,0 +1,26 @@
48148
+// PR tree-optimization/46864
48149
+// { dg-do compile }
48150
+// { dg-options "-O -fnon-call-exceptions" }
48151
+
48152
+int baz ();
48153
+
48154
+struct S
48155
+{
48156
+ int k;
48157
+ bool bar () throw ()
48158
+ {
48159
+ int m = baz ();
48160
+ for (int i = 0; i < m; i++)
48161
+ k = i;
48162
+ return m;
48163
+ }
48164
+};
48165
+
48166
+extern S *s;
48167
+
48168
+void
48169
+foo ()
48170
+{
48171
+ while (baz () && s->bar ())
48172
+ ;
48173
+}
48174
--- a/src/gcc/testsuite/g++.dg/opt/pr47615.C
48175
+++ b/src/gcc/testsuite/g++.dg/opt/pr47615.C
48176
@@ -0,0 +1,711 @@
48177
+// { dg-do compile }
48178
+// { dg-options "-O -fstrict-aliasing -ftree-pre -fno-tree-fre -fno-tree-sra" }
48179
+
48180
+typedef __SIZE_TYPE__ size_t;
48181
+namespace std
48182
+{
48183
+ template < class _T1, class > struct pair
48184
+ {
48185
+ _T1 first;
48186
+ };
48187
+}
48188
+namespace __gnu_cxx
48189
+{
48190
+ template < typename _Tp > class new_allocator
48191
+ {
48192
+ public:
48193
+ typedef size_t size_type;
48194
+ typedef _Tp * pointer;
48195
+ typedef _Tp const_pointer;
48196
+ typedef _Tp & reference;
48197
+ typedef const _Tp & const_reference;
48198
+ template < typename _Tp1 > struct rebind
48199
+ {
48200
+ typedef new_allocator < _Tp1 > other;
48201
+ };
48202
+ };
48203
+}
48204
+namespace std
48205
+{
48206
+template < typename _Tp > class allocator:
48207
+ public __gnu_cxx::new_allocator < _Tp >
48208
+ {};
48209
+ template < typename, typename, typename > struct binary_function;
48210
+ template < typename _Tp > struct less:binary_function < _Tp, _Tp, bool >
48211
+ {};
48212
+}
48213
+namespace __gnu_cxx
48214
+{
48215
+ namespace typelist
48216
+ {
48217
+ struct null_type;
48218
+ template < typename Root > struct node
48219
+ {
48220
+ typedef Root root;
48221
+ };
48222
+ template < typename, typename > struct chain;
48223
+ namespace detail
48224
+ {
48225
+ template < typename, int >struct chain_at_index_;
48226
+ template
48227
+ <
48228
+ typename
48229
+ Hd, typename Tl > struct chain_at_index_ <chain < Hd, Tl >, 0 >
48230
+ {
48231
+ typedef Hd type;
48232
+ };
48233
+ template
48234
+ <
48235
+ typename
48236
+ Hd, typename Tl, int i > struct chain_at_index_ <chain < Hd, Tl >, i >
48237
+ {
48238
+ typedef typename chain_at_index_ < Tl, i - 1 >::type type;
48239
+ };
48240
+ }
48241
+ template < typename Typelist, int i > struct at_index
48242
+ {
48243
+ typedef typename Typelist::root root_type;
48244
+ typedef detail::chain_at_index_ < root_type, i > index_type;
48245
+ typedef typename index_type::type type;
48246
+ };
48247
+ template < typename T1, typename T2 > struct create2
48248
+ {
48249
+ typedef node < chain < T1, chain < T2, null_type > > >type;
48250
+ };
48251
+ }
48252
+}
48253
+namespace std
48254
+{
48255
+ namespace tr1
48256
+ {
48257
+ template < typename _Tp, _Tp __v > struct integral_constant
48258
+ {
48259
+ static const _Tp value = __v;
48260
+ };
48261
+ typedef integral_constant < bool, false > false_type;
48262
+ template < typename, typename > struct is_same:false_type
48263
+ {};
48264
+ }
48265
+}
48266
+using std::tr1::is_same;
48267
+namespace __gnu_pbds
48268
+{
48269
+ struct null_mapped_type;
48270
+ struct rb_tree_tag;
48271
+ namespace detail
48272
+ {
48273
+ template < typename, typename, typename > struct basic_tree_policy_base;
48274
+ template
48275
+ <
48276
+ typename
48277
+ Const_Node_Iterator,
48278
+ typename
48279
+ Allocator
48280
+ >
48281
+ struct
48282
+ basic_tree_policy_base
48283
+ <Const_Node_Iterator, Const_Node_Iterator, Allocator >
48284
+ {};
48285
+ }
48286
+ template
48287
+ < typename, typename, typename, typename > struct null_tree_node_update;
48288
+template < typename Const_Node_Iterator, typename Node_Iterator, typename, typename Allocator > class tree_order_statistics_node_update:
48289
+ detail::basic_tree_policy_base
48290
+ < Const_Node_Iterator, Node_Iterator, Allocator >
48291
+ {
48292
+ public:
48293
+ typedef Allocator allocator_type;
48294
+ typedef typename allocator_type::size_type size_type;
48295
+ typedef size_type metadata_type;
48296
+ typedef Const_Node_Iterator const_node_iterator;
48297
+ typedef Node_Iterator node_iterator;
48298
+ typedef
48299
+ typename
48300
+ allocator_type::template
48301
+ rebind < metadata_type >::other::reference metadata_reference;
48302
+ void operator () (node_iterator, const_node_iterator) const;
48303
+ };
48304
+ template
48305
+ <
48306
+ typename
48307
+ Const_Node_Iterator,
48308
+ class
48309
+ Node_Iterator,
48310
+ class
48311
+ Cmp_Fn,
48312
+ class
48313
+ Allocator
48314
+ >
48315
+ inline
48316
+ void
48317
+ tree_order_statistics_node_update
48318
+ <
48319
+ Const_Node_Iterator,
48320
+ Node_Iterator,
48321
+ Cmp_Fn,
48322
+ Allocator
48323
+ >::operator
48324
+ () (node_iterator node_it, const_node_iterator end_nd_it) const
48325
+ {
48326
+ node_iterator l_child_it;
48327
+ size_type
48328
+ l_rank = (l_child_it == end_nd_it) ? : l_child_it.get_metadata ();
48329
+ node_iterator r_child_it = node_it.get_r_child ();
48330
+ size_type
48331
+ r_rank = (r_child_it == end_nd_it) ? : r_child_it.get_metadata ();
48332
+ const_cast
48333
+ < metadata_reference > (node_it.get_metadata ()) = l_rank + r_rank;
48334
+ }
48335
+ namespace
48336
+ {
48337
+ template < typename, typename, typename, bool > struct value_type_base;
48338
+ template
48339
+ <
48340
+ typename
48341
+ Key,
48342
+ typename
48343
+ Allocator
48344
+ > struct value_type_base <Key, null_mapped_type, Allocator, false >
48345
+ {
48346
+ typedef Key value_type;
48347
+ typedef
48348
+ typename
48349
+ Allocator::template rebind < value_type >::other value_type_allocator;
48350
+ typedef typename value_type_allocator::pointer pointer;
48351
+ typedef typename value_type_allocator::const_pointer const_pointer;
48352
+ typedef typename value_type_allocator::reference reference;
48353
+ typedef typename value_type_allocator::const_reference const_reference;
48354
+ };
48355
+ template
48356
+ <
48357
+ typename
48358
+ Key,
48359
+ typename
48360
+ Mapped, typename Alloc, bool Store_Extra > struct vt_base_selector
48361
+ {
48362
+ typedef value_type_base < Key, Mapped, Alloc, Store_Extra > type;
48363
+ };
48364
+ template
48365
+ <
48366
+ typename
48367
+ Key,
48368
+ typename
48369
+ Mapped,
48370
+ typename
48371
+ Alloc,
48372
+ bool
48373
+ Store_Extra
48374
+ >
48375
+ struct
48376
+ types_traits:vt_base_selector < Key, Mapped, Alloc, Store_Extra >::type
48377
+ {};
48378
+ template < typename, class, class > struct dumconst_node_iterator;
48379
+ template
48380
+ <
48381
+ typename
48382
+ Key,
48383
+ typename
48384
+ Mapped,
48385
+ class,
48386
+ class
48387
+ Node_And_It_Traits, class Allocator > class bin_search_tree_no_data_
48388
+ {
48389
+ protected:
48390
+ typedef
48391
+ typename
48392
+ Allocator::template
48393
+ rebind
48394
+ < typename Node_And_It_Traits::node >::other::pointer node_pointer;
48395
+ typedef
48396
+ typename
48397
+ types_traits
48398
+ < Key, Mapped, Allocator, false >::const_reference const_reference;
48399
+ typedef typename Node_And_It_Traits::point_iterator point_iterator;
48400
+ typedef typename Node_And_It_Traits::node_update node_update;
48401
+ void rotate_right (node_pointer);
48402
+ template
48403
+ <
48404
+ typename
48405
+ Node_Update_ > void apply_update (node_pointer, Node_Update_ *);
48406
+ };
48407
+ template
48408
+ <
48409
+ typename
48410
+ Key,
48411
+ typename
48412
+ Mapped,
48413
+ class
48414
+ Cmp_Fn,
48415
+ class
48416
+ Node_And_It_Traits,
48417
+ class
48418
+ Allocator
48419
+ >
48420
+ void
48421
+ bin_search_tree_no_data_
48422
+ <
48423
+ Key,
48424
+ Mapped,
48425
+ Cmp_Fn, Node_And_It_Traits, Allocator >::rotate_right (node_pointer p_x)
48426
+ {
48427
+ node_pointer p_y = p_x->m_p_parent;
48428
+ p_y->m_p_right = p_x;
48429
+ apply_update (p_x, this);
48430
+ apply_update (p_x->m_p_parent, (node_update *) this);
48431
+ }
48432
+ template
48433
+ <
48434
+ typename
48435
+ Key,
48436
+ typename
48437
+ Mapped,
48438
+ class
48439
+ Cmp_Fn,
48440
+ class
48441
+ Node_And_It_Traits,
48442
+ class
48443
+ Allocator
48444
+ >
48445
+ template
48446
+ <
48447
+ typename
48448
+ Node_Update_
48449
+ >
48450
+ void
48451
+ bin_search_tree_no_data_
48452
+ <
48453
+ Key,
48454
+ Mapped,
48455
+ Cmp_Fn,
48456
+ Node_And_It_Traits,
48457
+ Allocator >::apply_update (node_pointer p_nd, Node_Update_ *)
48458
+ {
48459
+ node_update ()((p_nd), ((0)));
48460
+ }
48461
+ }
48462
+ namespace detail
48463
+ {
48464
+ template < typename Key, typename Mapped, typename Cmp_Fn, typename Node_And_It_Traits, typename Allocator > class rb_tree_no_data_:
48465
+ bin_search_tree_no_data_
48466
+ < Key, Mapped, Cmp_Fn, Node_And_It_Traits, Allocator >
48467
+ {
48468
+ typedef
48469
+ bin_search_tree_no_data_
48470
+ < Key, Mapped, Cmp_Fn, Node_And_It_Traits, Allocator > base_type;
48471
+ typedef typename base_type::node_pointer node_pointer;
48472
+ public:
48473
+ typedef typename base_type::const_reference const_reference;
48474
+ typedef typename base_type::point_iterator point_iterator;
48475
+ std::pair < point_iterator, bool > insert (const_reference);
48476
+ void insert_fixup (node_pointer);
48477
+ };
48478
+ template
48479
+ <
48480
+ typename
48481
+ Key,
48482
+ typename
48483
+ Mapped,
48484
+ typename
48485
+ Cmp_Fn,
48486
+ typename
48487
+ Node_And_It_Traits,
48488
+ typename
48489
+ Allocator
48490
+ >
48491
+ std::pair
48492
+ <
48493
+ typename
48494
+ rb_tree_no_data_
48495
+ <
48496
+ Key,
48497
+ Mapped,
48498
+ Cmp_Fn,
48499
+ Node_And_It_Traits,
48500
+ Allocator
48501
+ >::point_iterator,
48502
+ bool
48503
+ >
48504
+ rb_tree_no_data_
48505
+ <
48506
+ Key,
48507
+ Mapped,
48508
+ Cmp_Fn, Node_And_It_Traits, Allocator >::insert (const_reference)
48509
+ {
48510
+ std::pair < point_iterator, bool > ins_pair;
48511
+{
48512
+ insert_fixup (ins_pair.first.m_p_nd);
48513
+ }
48514
+ }
48515
+ template
48516
+ <
48517
+ typename
48518
+ Key,
48519
+ typename
48520
+ Mapped,
48521
+ typename
48522
+ Cmp_Fn,
48523
+ typename
48524
+ Node_And_It_Traits,
48525
+ typename
48526
+ Allocator
48527
+ >
48528
+ void
48529
+ rb_tree_no_data_
48530
+ <
48531
+ Key,
48532
+ Mapped,
48533
+ Cmp_Fn,
48534
+ Node_And_It_Traits, Allocator >::insert_fixup (node_pointer p_nd)
48535
+ {
48536
+{
48537
+{
48538
+{
48539
+ rotate_right (p_nd);
48540
+ }
48541
+ }
48542
+ }
48543
+ }
48544
+ template
48545
+ <
48546
+ typename,
48547
+ typename, typename, typename, typename > struct container_base_dispatch;
48548
+ template
48549
+ <
48550
+ typename
48551
+ Key,
48552
+ typename
48553
+ Policy_Tl,
48554
+ typename
48555
+ Alloc
48556
+ >
48557
+ struct
48558
+ container_base_dispatch
48559
+ <Key, null_mapped_type, rb_tree_tag, Policy_Tl, Alloc >
48560
+ {
48561
+ typedef __gnu_cxx::typelist::at_index < Policy_Tl, 0 > at0;
48562
+ typedef typename at0::type at0t;
48563
+ typedef __gnu_cxx::typelist::at_index < Policy_Tl, 1 > at1;
48564
+ typedef typename at1::type at1t;
48565
+ typedef
48566
+ rb_tree_no_data_ < Key, null_mapped_type, at0t, at1t, Alloc > type;
48567
+ };
48568
+ template
48569
+ <
48570
+ typename
48571
+ Node_Pointer,
48572
+ typename,
48573
+ typename,
48574
+ typename,
48575
+ typename, typename, bool, class > class bin_search_tree_const_it_
48576
+ {
48577
+ public:
48578
+ Node_Pointer m_p_nd;
48579
+ };
48580
+ template
48581
+ <
48582
+ typename
48583
+ Node,
48584
+ class
48585
+ Const_Iterator,
48586
+ class Iterator, class Allocator > class bin_search_tree_const_node_it_
48587
+ {
48588
+ typedef
48589
+ typename
48590
+ Allocator::template rebind < Node >::other::pointer node_pointer;
48591
+ public:
48592
+ typedef typename Node::metadata_type metadata_type;
48593
+ typedef
48594
+ typename
48595
+ Allocator::template
48596
+ rebind
48597
+ < metadata_type >::other::const_reference const_metadata_reference;
48598
+ bin_search_tree_const_node_it_ (node_pointer p_nd):
48599
+ m_p_nd ((p_nd))
48600
+ {}
48601
+ const_metadata_reference get_metadata ()
48602
+ {
48603
+ return (m_p_nd->get_metadata ());
48604
+ }
48605
+ bin_search_tree_const_node_it_ ()
48606
+ {}
48607
+ bin_search_tree_const_node_it_
48608
+ < Node, Const_Iterator, Iterator, Allocator > get_r_child ()
48609
+ {
48610
+ return ((m_p_nd->m_p_right));
48611
+ }
48612
+ bool operator == (bin_search_tree_const_node_it_)
48613
+ {}
48614
+ node_pointer m_p_nd;
48615
+ };
48616
+ template
48617
+ <
48618
+ typename,
48619
+ typename,
48620
+ class,
48621
+ template
48622
+ <
48623
+ typename,
48624
+ class,
48625
+ class, class > class, class, class > struct bin_search_tree_traits;
48626
+ template
48627
+ <
48628
+ typename
48629
+ Key,
48630
+ class
48631
+ Cmp_Fn,
48632
+ template
48633
+ <
48634
+ typename,
48635
+ class,
48636
+ class,
48637
+ class
48638
+ >
48639
+ class
48640
+ Node_Update,
48641
+ class
48642
+ Node,
48643
+ class
48644
+ Allocator
48645
+ >
48646
+ struct
48647
+ bin_search_tree_traits
48648
+ <Key, null_mapped_type, Cmp_Fn, Node_Update, Node, Allocator >
48649
+ {
48650
+ typedef
48651
+ types_traits < Key, null_mapped_type, Allocator, false > type_traits;
48652
+ typedef Node node;
48653
+ typedef
48654
+ bin_search_tree_const_it_
48655
+ <
48656
+ typename
48657
+ Allocator::template
48658
+ rebind
48659
+ <
48660
+ node
48661
+ >::other::pointer,
48662
+ typename
48663
+ type_traits::value_type,
48664
+ typename
48665
+ type_traits::pointer,
48666
+ typename
48667
+ type_traits::const_pointer,
48668
+ typename
48669
+ type_traits::reference,
48670
+ typename
48671
+ type_traits::const_reference, true, Allocator > const_point_iterator;
48672
+ typedef const_point_iterator point_iterator;
48673
+ typedef
48674
+ bin_search_tree_const_node_it_
48675
+ <
48676
+ Node,
48677
+ const_point_iterator, point_iterator, Allocator > const_node_iterator;
48678
+ typedef const_node_iterator node_iterator;
48679
+ typedef
48680
+ Node_Update
48681
+ < const_node_iterator, node_iterator, Cmp_Fn, Allocator > node_update;
48682
+ };
48683
+ template < typename Node_Update, bool > struct tree_metadata_helper
48684
+ {
48685
+ typedef typename Node_Update::metadata_type type;
48686
+ };
48687
+ template
48688
+ <
48689
+ typename
48690
+ Key,
48691
+ typename
48692
+ Data,
48693
+ class
48694
+ Cmp_Fn,
48695
+ template
48696
+ <
48697
+ typename,
48698
+ class,
48699
+ class,
48700
+ class
48701
+ >
48702
+ class Node_Update, class Allocator > struct tree_node_metadata_selector
48703
+ {
48704
+ typedef
48705
+ dumconst_node_iterator < Key, Data, Allocator > dumconst_node_it;
48706
+ enum
48707
+ {
48708
+ null_update = is_same < Node_Update < dumconst_node_it,
48709
+ dumconst_node_it,
48710
+ Cmp_Fn,
48711
+ Allocator >,
48712
+ null_tree_node_update < dumconst_node_it,
48713
+ dumconst_node_it,
48714
+ Cmp_Fn,
48715
+ Allocator > >::value
48716
+ };
48717
+ typedef
48718
+ typename
48719
+ tree_metadata_helper
48720
+ <
48721
+ Node_Update
48722
+ <
48723
+ dumconst_node_it,
48724
+ dumconst_node_it, Cmp_Fn, Allocator >, null_update >::type type;
48725
+ };
48726
+ template
48727
+ <
48728
+ typename,
48729
+ typename,
48730
+ class,
48731
+ template
48732
+ <
48733
+ typename,
48734
+ class, class, class > class, class, class > struct tree_traits;
48735
+ template < typename Value_Type, class Metadata, class Allocator > struct rb_tree_node_
48736
+ {
48737
+ typedef Metadata metadata_type;
48738
+ typedef
48739
+ typename
48740
+ Allocator::template
48741
+ rebind
48742
+ <
48743
+ rb_tree_node_
48744
+ < Value_Type, Metadata, Allocator > >::other::pointer node_pointer;
48745
+ typedef
48746
+ typename
48747
+ Allocator::template
48748
+ rebind < metadata_type >::other::reference metadata_reference;
48749
+ metadata_reference get_metadata ()
48750
+ {
48751
+ return m_metadata;
48752
+ }
48753
+ node_pointer m_p_right;
48754
+ node_pointer m_p_parent;
48755
+ metadata_type m_metadata;
48756
+ };
48757
+ template
48758
+ <
48759
+ typename
48760
+ Key,
48761
+ typename
48762
+ Mapped,
48763
+ typename
48764
+ Cmp_Fn,
48765
+ template
48766
+ <
48767
+ typename,
48768
+ class,
48769
+ class,
48770
+ class
48771
+ >
48772
+ class
48773
+ Node_Update,
48774
+ typename
48775
+ Allocator
48776
+ >
48777
+ struct
48778
+ tree_traits
48779
+ <Key,
48780
+ Mapped,
48781
+ Cmp_Fn,
48782
+ Node_Update,
48783
+ rb_tree_tag,
48784
+ Allocator
48785
+ >:bin_search_tree_traits
48786
+ <
48787
+ Key,
48788
+ Mapped,
48789
+ Cmp_Fn,
48790
+ Node_Update,
48791
+ rb_tree_node_
48792
+ <
48793
+ typename
48794
+ types_traits
48795
+ <
48796
+ Key,
48797
+ Mapped,
48798
+ Allocator,
48799
+ false
48800
+ >::value_type,
48801
+ typename
48802
+ tree_node_metadata_selector
48803
+ <
48804
+ Key,
48805
+ Mapped, Cmp_Fn, Node_Update, Allocator >::type, Allocator >, Allocator >
48806
+ {};
48807
+ }
48808
+template < typename Key, typename Mapped, typename Tag, typename Policy_Tl, typename Allocator > class container_base:
48809
+ public
48810
+ detail::container_base_dispatch
48811
+ < Key, Mapped, Tag, Policy_Tl, Allocator >::type
48812
+ {};
48813
+template < typename Key, typename Mapped, typename Tag, typename, typename Policy_Tl, typename Allocator > class basic_tree:
48814
+ public
48815
+ container_base < Key, Mapped, Tag, Policy_Tl, Allocator >
48816
+ {};
48817
+ template
48818
+ <
48819
+ typename
48820
+ Key,
48821
+ typename
48822
+ Mapped,
48823
+ typename
48824
+ Cmp_Fn
48825
+ =
48826
+ std::less
48827
+ <
48828
+ Key
48829
+ >,
48830
+ typename
48831
+ Tag
48832
+ =
48833
+ rb_tree_tag,
48834
+ template
48835
+ <
48836
+ typename,
48837
+ typename,
48838
+ typename,
48839
+ typename
48840
+ >
48841
+ class
48842
+ Node_Update
48843
+ =
48844
+ null_tree_node_update,
48845
+ typename
48846
+ Allocator
48847
+ =
48848
+ std::allocator
48849
+ <
48850
+ char
48851
+ > >class
48852
+ tree:public
48853
+ basic_tree
48854
+ <
48855
+ Key,
48856
+ Mapped,
48857
+ Tag,
48858
+ detail::tree_traits
48859
+ <
48860
+ Key,
48861
+ Mapped,
48862
+ Cmp_Fn,
48863
+ Node_Update,
48864
+ Tag,
48865
+ Allocator
48866
+ >,
48867
+ typename
48868
+ __gnu_cxx::typelist::create2
48869
+ <
48870
+ Cmp_Fn,
48871
+ detail::tree_traits
48872
+ < Key, Mapped, Cmp_Fn, Node_Update, Tag, Allocator > >::type, Allocator >
48873
+ {};
48874
+}
48875
+using namespace std;
48876
+using namespace __gnu_pbds;
48877
+typedef
48878
+ tree
48879
+ <
48880
+ int,
48881
+ null_mapped_type,
48882
+ less < int >, rb_tree_tag, tree_order_statistics_node_update > set_t;
48883
+main ()
48884
+{
48885
+ set_t s;
48886
+ s.insert (12);
48887
+}
48888
--- a/src/gcc/testsuite/g++.dg/opt/pr47639.c
48889
+++ b/src/gcc/testsuite/g++.dg/opt/pr47639.c
48890
@@ -0,0 +1,17 @@
48891
+// { dg-do compile }
48892
+// { dg-options "-fnon-call-exceptions" }
48893
+
48894
+typedef int __attribute__ ((vector_size (8))) vec;
48895
+
48896
+vec foo (vec v1, vec v2)
48897
+{
48898
+ try
48899
+ {
48900
+ return v1 / v2;
48901
+ }
48902
+ catch (...)
48903
+ {
48904
+ throw;
48905
+ }
48906
+}
48907
+
48908
--- a/src/gcc/testsuite/g++.dg/other/anon5.C
48909
+++ b/src/gcc/testsuite/g++.dg/other/anon5.C
48910
@@ -1,5 +1,5 @@
48911
// PR c++/34094
48912
-// { dg-do link { target { ! { *-*-darwin* *-*-hpux* *-*-solaris2.* alpha*-dec-osf* } } } }
48913
+// { dg-do link { target { ! { *-*-darwin* *-*-hpux* *-*-solaris2.* alpha*-dec-osf* mips-sgi-irix* } } } }
48914
// { dg-options "-g" }
48915
48916
namespace {
48917
41086
--- a/src/gcc/testsuite/g++.dg/other/armv7m-1.C
48918
41087
+++ b/src/gcc/testsuite/g++.dg/other/armv7m-1.C
48919
41088
@@ -0,0 +1,69 @@
48986
41155
+ exit (0);
48987
41156
+}
48988
41157
+#endif
48989
--- a/src/gcc/testsuite/g++.dg/pr47589.C
48990
+++ b/src/gcc/testsuite/g++.dg/pr47589.C
48991
@@ -0,0 +1,26 @@
48992
+// PR c++/47589
48993
+// { dg-do compile }
48994
+
48995
+struct F
48996
+{
48997
+ typedef void(*Cb)();
48998
+
48999
+ F(Cb);
49000
+};
49001
+
49002
+struct C
49003
+{
49004
+ template<class D> static void f();
49005
+};
49006
+
49007
+template<class D>
49008
+struct TF : F
49009
+{
49010
+ TF() : F(C::f<D>) { }
49011
+};
49012
+
49013
+struct DTC : TF<DTC>
49014
+{
49015
+ DTC() { }
49016
+};
49017
+
49018
--- a/src/gcc/testsuite/g++.dg/template/anon5.C
49019
+++ b/src/gcc/testsuite/g++.dg/template/anon5.C
49020
@@ -0,0 +1,6 @@
49021
+// PR c++/45651
49022
+
49023
+namespace { template <int T> struct A {}; }
49024
+template <int T> struct B { void f(A<T>); };
49025
+template struct B<1>;
49026
+template<int T> void B<T>::f(A<T>) {}
49027
--- a/src/gcc/testsuite/g++.dg/template/array22.C
49028
+++ b/src/gcc/testsuite/g++.dg/template/array22.C
49029
@@ -0,0 +1,14 @@
49030
+// PR c++/48029
49031
+
49032
+template <class T> struct A { };
49033
+template <class T, class U> struct B
49034
+{
49035
+ struct N { };
49036
+ typedef U u;
49037
+};
49038
+
49039
+typedef B<int, A<int>(*)[2]> btype;
49040
+A<int> v1[2];
49041
+btype v2;
49042
+
49043
+
49044
--- a/src/gcc/testsuite/g++.dg/template/error45.C
49045
+++ b/src/gcc/testsuite/g++.dg/template/error45.C
49046
@@ -0,0 +1,22 @@
49047
+// PR c++/47125
49048
+
49049
+template < bool, typename >
49050
+struct enable_if {};
49051
+
49052
+template < typename T >
49053
+struct enable_if< true, T >
49054
+{
49055
+ typedef T type;
49056
+};
49057
+
49058
+template < typename T >
49059
+struct enable_if< true, T >::type
49060
+f( T x );
49061
+
49062
+void
49063
+g( void )
49064
+{
49065
+ f< int >( 0 ); // { dg-error "no match" }
49066
+}
49067
+
49068
+// { dg-prune-output "note" }
49069
--- a/src/gcc/testsuite/g++.dg/template/nontype21.C
49070
+++ b/src/gcc/testsuite/g++.dg/template/nontype21.C
49071
@@ -0,0 +1,7 @@
49072
+// PR c++/47705
49073
+
49074
+template<char const * const x> class Something { };
49075
+
49076
+extern char const xyz;
49077
+
49078
+class SomethingElse:public Something<xyz> { }; // { dg-error "xyz. is a variable" }
49079
--- a/src/gcc/testsuite/g++.dg/template/nontype22.C
49080
+++ b/src/gcc/testsuite/g++.dg/template/nontype22.C
49081
@@ -0,0 +1,11 @@
49082
+// PR c++/44629
49083
+// The proper mangling is unclear.
49084
+
49085
+template<typename T> int cmp1(T a, T b);
49086
+template<typename T, int (*cmp)(T, T) = cmp1> struct A { };
49087
+template <typename T> void f (A<T> &); // { dg-bogus "" "" { xfail *-*-* } }
49088
+void g()
49089
+{
49090
+ A<char> a;
49091
+ f(a);
49092
+}
49093
--- a/src/gcc/testsuite/g++.dg/template/this-targ1.C
49094
+++ b/src/gcc/testsuite/g++.dg/template/this-targ1.C
49095
@@ -0,0 +1,23 @@
49096
+// PR c++/47904
49097
+
49098
+template <bool>
49099
+struct S
49100
+{
49101
+};
49102
+
49103
+template <class T>
49104
+class U
49105
+{
49106
+ T t;
49107
+ int foo () const
49108
+ {
49109
+ S <sizeof (t) == 1> s;
49110
+ return 1;
49111
+ }
49112
+ int bar () const
49113
+ {
49114
+ S <sizeof (t) == 1> s;
49115
+ return 1;
49116
+ }
49117
+};
49118
+
49119
--- a/src/gcc/testsuite/g++.dg/torture/pr47541.C
49120
+++ b/src/gcc/testsuite/g++.dg/torture/pr47541.C
49121
@@ -0,0 +1,27 @@
49122
+/* { dg-do run } */
49123
+
49124
+struct Dummy {};
49125
+struct RefCount : public Dummy {
49126
+ ~RefCount(); /* Has to be non-pod. */
49127
+ int *a;
49128
+ int *b;
49129
+};
49130
+RefCount::~RefCount(){}
49131
+struct Wrapper : public Dummy { RefCount ref; };
49132
+void __attribute__((noinline,noclone))
49133
+Push(Wrapper ptr)
49134
+{
49135
+ *ptr.ref.b = 0;
49136
+}
49137
+extern "C" void abort (void);
41158
--- a/src/gcc/testsuite/g++.dg/parse/ambig6.C
41159
+++ b/src/gcc/testsuite/g++.dg/parse/ambig6.C
41160
@@ -0,0 +1,12 @@
41161
+// PR c++/48046
41162
+
41163
+namespace N1 { typedef int T; } // { dg-error "" }
41164
+namespace N2 { typedef float T; } // { dg-error "" }
41165
+
49138
41166
+int main()
49139
41167
+{
49140
+ int a = 1, b = 1;
49141
+ Wrapper x;
49142
+ x.ref.a = &a;
49143
+ x.ref.b = &b;
49144
+ Push(x);
49145
+ if (b != 0)
49146
+ abort ();
49147
+ return 0;
49148
+}
49149
--- a/src/gcc/testsuite/g++.dg/tree-prof/partition1.C
49150
+++ b/src/gcc/testsuite/g++.dg/tree-prof/partition1.C
49151
@@ -1,5 +1,6 @@
49152
/* { dg-require-effective-target freorder } */
49153
/* { dg-options "-O2 -freorder-blocks-and-partition" } */
49154
+/* { dg-skip-if "PR target/47683" { mips-sgi-irix* } } */
49155
49156
struct A { A () __attribute__((noinline)); ~A () __attribute__((noinline)); };
49157
A::A () { asm volatile ("" : : : "memory"); }
49158
--- a/src/gcc/testsuite/g++.dg/tree-prof/partition2.C
49159
+++ b/src/gcc/testsuite/g++.dg/tree-prof/partition2.C
49160
@@ -1,6 +1,7 @@
49161
// PR middle-end/45458
49162
// { dg-require-effective-target freorder }
49163
// { dg-options "-fnon-call-exceptions -freorder-blocks-and-partition" }
49164
+// { dg-skip-if "PR target/47683" { mips-sgi-irix* } }
49165
49166
int
49167
main ()
49168
--- a/src/gcc/testsuite/g++.dg/tree-ssa/pr46734.C
49169
+++ b/src/gcc/testsuite/g++.dg/tree-ssa/pr46734.C
49170
@@ -0,0 +1,34 @@
49171
+/* { dg-do compile } */
49172
+/* { dg-options "-O -fipa-sra" } */
49173
+
49174
+struct A
49175
+{
49176
+ int *p;
49177
+ A() {p = (int *) -1;}
49178
+ ~A() {if (p && p != (int *) -1) *p = 0;}
49179
+};
49180
+
49181
+struct B
49182
+{
49183
+ A a;
49184
+ char data[23];
49185
+ B() : a() {data[0] = 0;}
49186
+};
49187
+
49188
+extern A ga;
49189
+extern int *gi;
49190
+extern void *gz;
49191
+extern B *gb;
49192
+
49193
+static int * __attribute__ ((noinline)) foo (B *b, void *z)
49194
+{
49195
+ __builtin_memcpy (gz, z, 28);
49196
+ ga = b->a;
49197
+ return b->a.p;
49198
+}
49199
+
49200
+int *bar (B *b, void *z)
49201
+{
49202
+ gb = b;
49203
+ return foo (b, z);
41168
+ using namespace N1;
41169
+ using namespace N2;
41170
+
41171
+ static T t; // { dg-error "" }
49204
41172
+}
49205
41173
--- a/src/gcc/testsuite/g++.dg/tree-ssa/sink-1.C
49206
41174
+++ b/src/gcc/testsuite/g++.dg/tree-ssa/sink-1.C
49368
41336
+ d = (__typeof__(f + 1.0))f; /* { dg-bogus "implicit" } */
49369
41337
+ s = sizeof (i ? f : d); /* { dg-bogus "implicit" } */
49370
41338
+}
49371
--- a/src/gcc/testsuite/g++.old-deja/g++.other/init19.C
49372
+++ b/src/gcc/testsuite/g++.old-deja/g++.other/init19.C
49373
@@ -1,4 +1,4 @@
49374
-// { dg-do run { xfail { { ! cxa_atexit } && { ! *-*-solaris2* } } } }
49375
+// { dg-do run { xfail { { ! cxa_atexit } && { ! { mips-sgi-irix* *-*-solaris2* } } } } }
49376
#include <stdlib.h>
49377
49378
#define assert(x) do { if (! (x)) abort(); } while (0)
49379
41339
--- a/src/gcc/testsuite/gcc.c-torture/compile/20101217-1.c
49380
41340
+++ b/src/gcc/testsuite/gcc.c-torture/compile/20101217-1.c
49381
41341
@@ -0,0 +1,36 @@
49415
41375
+ }
49416
41376
+return 0;
49417
41377
+}
49418
--- a/src/gcc/testsuite/gcc.c-torture/compile/20110126-1.c
49419
+++ b/src/gcc/testsuite/gcc.c-torture/compile/20110126-1.c
49420
@@ -0,0 +1,18 @@
49421
+/* PR rtl-optimization/44469 */
49422
+/* Testcase by Siarhei Siamashka <siarhei.siamashka@gmail.com> */
49423
+
49424
+int a (int *t, const char *p)
49425
+{
49426
+ if (*t == 0)
49427
+ {
49428
+ }
49429
+ else if (*t == 1)
49430
+ {
49431
+ p = (const char *)t;
49432
+ }
49433
+ else
49434
+ __builtin_unreachable();
49435
+ if (p[0])
49436
+ return 0;
49437
+ return 1;
49438
+}
49439
41378
--- a/src/gcc/testsuite/gcc.c-torture/compile/pr44788.c
49440
41379
+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr44788.c
49441
41380
@@ -0,0 +1,8 @@
49447
41386
+ mlt_buffer1[i] = i * decode_buffer[t];
49448
41387
+ }
49449
41388
+}
49450
--- a/src/gcc/testsuite/gcc.c-torture/compile/pr47150.c
49451
+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr47150.c
49452
@@ -0,0 +1,11 @@
49453
+/* PR c/47150 */
49454
+
49455
+float _Complex foo (float, float);
41389
--- a/src/gcc/testsuite/gcc.c-torture/compile/pr48742.c
41390
+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr48742.c
41391
@@ -0,0 +1,15 @@
41392
+/* PR c/48742 */
41393
+
41394
+void baz (int);
41395
+
41396
+int
41397
+foo (void)
41398
+{
41399
+ return 1 / 0 > 0;
41400
+}
49456
41401
+
49457
41402
+void
49458
+bar ()
41403
+bar (void)
49459
41404
+{
49460
+ float w = 2;
49461
+ float _Complex b;
49462
+ b = 0.5 * (foo (0, w) + foo (1, w) / w);
41405
+ baz (1 <= 2 % (3 >> 1 > 5 / 6 == 3));
49463
41406
+}
49464
41407
--- a/src/gcc/testsuite/gcc.c-torture/execute/20100416-1.c
49465
41408
+++ b/src/gcc/testsuite/gcc.c-torture/execute/20100416-1.c
49504
41447
+ }
49505
41448
+ return 0;
49506
41449
+}
49507
--- a/src/gcc/testsuite/gcc.c-torture/execute/postmod-1.c
49508
+++ b/src/gcc/testsuite/gcc.c-torture/execute/postmod-1.c
49509
@@ -0,0 +1,62 @@
49510
+#define DECLARE_ARRAY(A) array##A[0x10]
49511
+#define DECLARE_COUNTER(A) counter##A = 0
49512
+#define DECLARE_POINTER(A) *pointer##A = array##A + x
49513
+/* Create a loop that allows post-modification of pointerA, followed by
49514
+ a use of the post-modified address. */
49515
+#define BEFORE(A) counter##A += *pointer##A, pointer##A += 3
49516
+#define AFTER(A) counter##A += pointer##A[x]
49517
+
49518
+/* Set up the arrays so that one iteration of the loop sets the counter
49519
+ to 3.0f. */
49520
+#define INIT_ARRAY(A) array##A[1] = 1.0f, array##A[5] = 2.0f
49521
+
49522
+/* Check that the loop worked correctly for all values. */
49523
+#define CHECK_ARRAY(A) exit_code |= (counter##A != 3.0f)
49524
+
49525
+/* Having 6 copies triggered the bug for ARM and Thumb. */
49526
+#define MANY(A) A (0), A (1), A (2), A (3), A (4), A (5)
49527
+
49528
+/* Each addendA should be allocated a register. */
49529
+#define INIT_VOLATILE(A) addend##A = vol
49530
+#define ADD_VOLATILE(A) vol += addend##A
49531
+
49532
+/* Having 5 copies triggered the bug for ARM and Thumb. */
49533
+#define MANY2(A) A (0), A (1), A (2), A (3), A (4)
49534
+
49535
+float MANY (DECLARE_ARRAY);
49536
+float MANY (DECLARE_COUNTER);
49537
+
49538
+volatile int stop = 1;
49539
+volatile int vol;
49540
+
49541
+void __attribute__((noinline))
49542
+foo (int x)
49543
+{
49544
+ float MANY (DECLARE_POINTER);
49545
+ int i;
49546
+
49547
+ do
49548
+ {
49549
+ MANY (BEFORE);
49550
+ MANY (AFTER);
49551
+ /* Create an inner loop that should ensure the code above
49552
+ has registers free for reload inheritance. */
49553
+ {
49554
+ int MANY2 (INIT_VOLATILE);
49555
+ for (i = 0; i < 10; i++)
49556
+ MANY2 (ADD_VOLATILE);
49557
+ }
49558
+ }
49559
+ while (!stop);
49560
+}
49561
+
49562
+int
49563
+main (void)
49564
+{
49565
+ int exit_code = 0;
49566
+
49567
+ MANY (INIT_ARRAY);
49568
+ foo (1);
49569
+ MANY (CHECK_ARRAY);
49570
+ return exit_code;
49571
+}
49572
41450
--- a/src/gcc/testsuite/gcc.c-torture/execute/pr40657.c
49573
41451
+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr40657.c
49574
41452
@@ -0,0 +1,23 @@
49665
41543
+ abort ();
49666
41544
+ return 0;
49667
41545
+}
49668
--- a/src/gcc/testsuite/gcc.dg/20061124-1.c
49669
+++ b/src/gcc/testsuite/gcc.dg/20061124-1.c
49670
@@ -1,5 +1,6 @@
49671
/* { dg-do run } */
49672
/* { dg-require-effective-target sync_char_short } */
49673
+/* { dg-options "-mcpu=v9" { target sparc*-*-* } } */
49674
49675
/* This testcase failed on s390 because no compare instruction for
49676
the check of FLAG was emitted. */
41546
--- a/src/gcc/testsuite/gcc.c-torture/execute/pr48809.c
41547
+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr48809.c
41548
@@ -0,0 +1,60 @@
41549
+/* PR tree-optimization/48809 */
41550
+
41551
+extern void abort (void);
41552
+
41553
+int
41554
+foo (signed char x)
41555
+{
41556
+ int y = 0;
41557
+ switch (x)
41558
+ {
41559
+ case 0: y = 1; break;
41560
+ case 1: y = 7; break;
41561
+ case 2: y = 2; break;
41562
+ case 3: y = 19; break;
41563
+ case 4: y = 5; break;
41564
+ case 5: y = 17; break;
41565
+ case 6: y = 31; break;
41566
+ case 7: y = 8; break;
41567
+ case 8: y = 28; break;
41568
+ case 9: y = 16; break;
41569
+ case 10: y = 31; break;
41570
+ case 11: y = 12; break;
41571
+ case 12: y = 15; break;
41572
+ case 13: y = 111; break;
41573
+ case 14: y = 17; break;
41574
+ case 15: y = 10; break;
41575
+ case 16: y = 31; break;
41576
+ case 17: y = 7; break;
41577
+ case 18: y = 2; break;
41578
+ case 19: y = 19; break;
41579
+ case 20: y = 5; break;
41580
+ case 21: y = 107; break;
41581
+ case 22: y = 31; break;
41582
+ case 23: y = 8; break;
41583
+ case 24: y = 28; break;
41584
+ case 25: y = 106; break;
41585
+ case 26: y = 31; break;
41586
+ case 27: y = 102; break;
41587
+ case 28: y = 105; break;
41588
+ case 29: y = 111; break;
41589
+ case 30: y = 17; break;
41590
+ case 31: y = 10; break;
41591
+ case 32: y = 31; break;
41592
+ case 98: y = 18; break;
41593
+ case -62: y = 19; break;
41594
+ }
41595
+ return y;
41596
+}
41597
+
41598
+int
41599
+main ()
41600
+{
41601
+ if (foo (98) != 18 || foo (97) != 0 || foo (99) != 0)
41602
+ abort ();
41603
+ if (foo (-62) != 19 || foo (-63) != 0 || foo (-61) != 0)
41604
+ abort ();
41605
+ if (foo (28) != 105 || foo (27) != 102 || foo (29) != 111)
41606
+ abort ();
41607
+ return 0;
41608
+}
49677
41609
--- a/src/gcc/testsuite/gcc.dg/20101010-1.c
49678
41610
+++ b/src/gcc/testsuite/gcc.dg/20101010-1.c
49679
41611
@@ -0,0 +1,14 @@
49849
41781
}
49850
41782
49851
41783
int main(void)
49852
--- a/src/gcc/testsuite/gcc.dg/compat/vector-1b_main.c
49853
+++ b/src/gcc/testsuite/gcc.dg/compat/vector-1b_main.c
49854
@@ -1,12 +1,10 @@
49855
/* { dg-skip-if "test AVX vector" { ! { i?86-*-* x86_64-*-* } } } */
49856
-/* { dg-require-effective-target avx } */
49857
+/* { dg-require-effective-target avx_runtime } */
49858
49859
/* Test compatibility of vector types: layout between separately-compiled
49860
modules, parameter passing, and function return. This test uses
49861
vectors of integer values. */
49862
49863
-#include "cpuid.h"
49864
-
49865
extern void vector_1_x (void);
49866
extern void exit (int);
49867
int fails;
49868
@@ -14,14 +12,6 @@
49869
int
49870
main ()
49871
{
49872
- unsigned int eax, ebx, ecx, edx;
49873
-
49874
- if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
49875
- return 0;
49876
-
49877
- /* Run AVX vector test only if host has AVX support. */
49878
- if (ecx & bit_AVX)
49879
- vector_1_x ();
49880
-
49881
+ vector_1_x ();
49882
exit (0);
49883
}
49884
--- a/src/gcc/testsuite/gcc.dg/compat/vector-2b_main.c
49885
+++ b/src/gcc/testsuite/gcc.dg/compat/vector-2b_main.c
49886
@@ -1,12 +1,10 @@
49887
/* { dg-skip-if "test AVX support" { ! { i?86-*-* x86_64-*-* } } } */
49888
-/* { dg-require-effective-target avx } */
49889
+/* { dg-require-effective-target avx_runtime } */
49890
49891
/* Test compatibility of vector types: layout between separately-compiled
49892
modules, parameter passing, and function return. This test uses
49893
vectors of floating points values. */
49894
49895
-#include "cpuid.h"
49896
-
49897
extern void vector_2_x (void);
49898
extern void exit (int);
49899
int fails;
49900
@@ -14,14 +12,6 @@
49901
int
49902
main ()
49903
{
49904
- unsigned int eax, ebx, ecx, edx;
49905
-
49906
- if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
49907
- return 0;
49908
-
49909
- /* Run AVX vector test only if host has AVX support. */
49910
- if (ecx & bit_AVX)
49911
- vector_2_x ();
49912
-
49913
+ vector_2_x ();
49914
exit (0);
49915
}
49916
--- a/src/gcc/testsuite/gcc.dg/debug/pr46782.c
49917
+++ b/src/gcc/testsuite/gcc.dg/debug/pr46782.c
49918
@@ -0,0 +1,11 @@
49919
+/* PR debug/46782 */
49920
+/* { dg-do compile } */
49921
+/* { dg-options "-w -O0 -fvar-tracking -fcompare-debug" } */
49922
+
49923
+void foo (int i)
49924
+{
49925
+ if (i)
49926
+ i++;
49927
+ while (i)
49928
+ ;
49929
+}
49930
41784
--- a/src/gcc/testsuite/gcc.dg/extend-1.c
49931
41785
+++ b/src/gcc/testsuite/gcc.dg/extend-1.c
49932
41786
@@ -0,0 +1,13 @@
50060
41914
abort ();
50061
41915
50062
41916
return 0;
50063
--- a/src/gcc/testsuite/gcc.dg/graphite/pr45552.c
50064
+++ b/src/gcc/testsuite/gcc.dg/graphite/pr45552.c
50065
@@ -0,0 +1,46 @@
50066
+typedef struct
50067
+{
50068
+ double z;
50069
+} Vector;
50070
+typedef struct
50071
+{
50072
+ float *vertex;
50073
+ float *normal;
50074
+} VertexArray;
50075
+typedef struct
50076
+{
50077
+ Vector *vertex;
50078
+ int num_vertex;
50079
+} ObjectSmooth;
50080
+typedef struct
50081
+{
50082
+ int num_cells;
50083
+} State;
50084
+static void *array_from_ObjectSmooth( ObjectSmooth *obj )
50085
+{
50086
+ int i, j;
50087
+ VertexArray *array = (VertexArray *) __builtin_malloc( sizeof( VertexArray ) );
50088
+ array->vertex = (float *) __builtin_malloc( 3*sizeof(float)*obj->num_vertex );
50089
+ array->normal = (float *) __builtin_malloc( 3*sizeof(float)*obj->num_vertex );
50090
+ for (i=0, j=0; i<obj->num_vertex; ++i) {
50091
+ array->normal[j++] = 9;
50092
+ array->vertex[j] = obj->vertex[i].z;
50093
+ array->normal[j++] = 1;
50094
+ }
50095
+}
50096
+static void draw_cell( void )
50097
+{
50098
+ glCallList( array_from_ObjectSmooth( (ObjectSmooth *) __builtin_malloc(10) ));
50099
+}
50100
+static int render( State *st)
50101
+{
50102
+ int b;
50103
+ for (b=0; b<st->num_cells; ++b) {
50104
+ draw_cell();
50105
+ draw_cell();
50106
+ }
50107
+}
50108
+reshape_glcells( int width, int height )
50109
+{
50110
+ render( 0 );
50111
+}
50112
--- a/src/gcc/testsuite/gcc.dg/graphite/run-id-pr46758.c
50113
+++ b/src/gcc/testsuite/gcc.dg/graphite/run-id-pr46758.c
50114
@@ -0,0 +1,18 @@
50115
+int
50116
+movegt (int y, long long a)
50117
+{
50118
+ int i;
50119
+ int ret = 0;
50120
+ for (i = 0; i < y; i++)
50121
+ if (a == -1LL << 33)
50122
+ ret = -1;
50123
+ return ret;
50124
+}
50125
+
50126
+int
50127
+main ()
50128
+{
50129
+ if (movegt (1, -1LL << 33) != -1)
50130
+ __builtin_abort ();
50131
+ return 0;
50132
+}
50133
41917
--- a/src/gcc/testsuite/gcc.dg/memcpy-3.c
50134
41918
+++ b/src/gcc/testsuite/gcc.dg/memcpy-3.c
50135
41919
@@ -0,0 +1,11 @@
50197
41981
+/* { dg-final { scan-tree-dump-not " < " "optimized" } } */
50198
41982
+/* { dg-final { scan-tree-dump-not " == " "optimized" } } */
50199
41983
+/* { dg-final { cleanup-tree-dump "optimized" } } */
50200
--- a/src/gcc/testsuite/gcc.dg/pr28796-2.c
50201
+++ b/src/gcc/testsuite/gcc.dg/pr28796-2.c
50202
@@ -2,6 +2,7 @@
50203
/* { dg-options "-O2 -funsafe-math-optimizations -fno-finite-math-only -DUNSAFE" } */
50204
/* { dg-add-options ieee } */
50205
/* { dg-skip-if "No Inf/NaN support" { spu-*-* } } */
50206
+/* { dg-skip-if "Bug in _Q_dtoq" { sparc*-sun-solaris2.8 } } */
50207
50208
#include "tg-tests.h"
50209
50210
41984
--- a/src/gcc/testsuite/gcc.dg/pr39874.c
50211
41985
+++ b/src/gcc/testsuite/gcc.dg/pr39874.c
50212
41986
@@ -0,0 +1,29 @@
50325
42099
+ foo (0);
50326
42100
+ return 0;
50327
42101
+}
50328
--- a/src/gcc/testsuite/gcc.dg/pr44606.c
50329
+++ b/src/gcc/testsuite/gcc.dg/pr44606.c
50330
@@ -0,0 +1,52 @@
50331
+/* PR target/44606 */
50332
+/* { dg-do run } */
50333
+/* { dg-options "-O2" } */
50334
+
50335
+#include <stdio.h>
50336
+
50337
+extern void abort (void);
50338
+
50339
+ typedef struct _PixelPacket { unsigned char r, g, b; }
50340
+ PixelPacket;
50341
+#define ARRAYLEN(X) (sizeof(X)/sizeof(X[0]))
50342
+PixelPacket q[6];
50343
+#define COLS (ARRAYLEN(q) - 1)
50344
+PixelPacket p[2*COLS + 22];
50345
+#define Minify(POS, WEIGHT) do { \
50346
+ total_r += (WEIGHT)*(p[POS].r); \
50347
+ total_g += (WEIGHT)*(p[POS].g); \
50348
+ total_b += (WEIGHT)*(p[POS].b); \
50349
+} while (0)
50350
+unsigned long columns = COLS;
50351
+int main(void)
50352
+{
50353
+ static const unsigned char answers[COLS] = { 31, 32, 34, 35, 36 };
50354
+ unsigned long x;
50355
+ for (x = 0; x < sizeof(p)/sizeof(p[0]); x++) {
50356
+ p[x].b = (x + 34) | 1;
50357
+ }
50358
+ for (x = 0; x < columns; x++) {
50359
+ double total_r = 0, total_g = 0, total_b = 0;
50360
+ double saved_r = 0, saved_g = 0, saved_b = 0;
50361
+ Minify(2*x + 0, 3.0);
50362
+ Minify(2*x + 1, 7.0);
50363
+ Minify(2*x + 2, 7.0);
50364
+ saved_r = total_r;
50365
+ saved_g = total_g;
50366
+ Minify(2*x + 11, 15.0);
50367
+ Minify(2*x + 12, 7.0);
50368
+ Minify(2*x + 18, 7.0);
50369
+ Minify(2*x + 19, 15.0);
50370
+ Minify(2*x + 20, 15.0);
50371
+ Minify(2*x + 21, 7.0);
50372
+ q[x].r = (unsigned char)(total_r/128.0 + 0.5);
50373
+ q[x].g = (unsigned char)(total_g/128.0 + 0.5);
50374
+ q[x].b = (unsigned char)(total_b/128.0 + 0.5);
50375
+ fprintf(stderr, "r:%f g:%f b:%f\n", saved_r, saved_g, saved_b);
50376
+ }
50377
+ for (x = 0; x < COLS; x++) {
50378
+ if (answers[x] != q[x].b)
50379
+ abort();
50380
+ }
50381
+ return 0;
50382
+}
50383
42102
--- a/src/gcc/testsuite/gcc.dg/pr45101.c
50384
42103
+++ b/src/gcc/testsuite/gcc.dg/pr45101.c
50385
42104
@@ -0,0 +1,15 @@
50444
42163
+ bar(&i);
50445
42164
+ *p = i;
50446
42165
+}
50447
--- a/src/gcc/testsuite/gcc.dg/pr46620.c
50448
+++ b/src/gcc/testsuite/gcc.dg/pr46620.c
50449
@@ -0,0 +1,76 @@
50450
+/* PR tree-optimization/46620 */
50451
+/* SRA bitfield grouping used to lose track at padding bitfields in
50452
+ the middle of a word. */
50453
+/* { dg-do run } */
50454
+/* { dg-options "-O2" } */
50455
+
50456
+#include <stdlib.h>
50457
+
50458
+struct PCT
50459
+{
50460
+ unsigned char pi1 : 4;
50461
+ unsigned char pi2 : 3;
50462
+ unsigned char pif : 5;
50463
+
50464
+ unsigned char sl : 2;
50465
+ unsigned char uc : 1;
50466
+ unsigned char st : 1;
50467
+
50468
+ unsigned char p : 1;
50469
+ unsigned char cs : 1;
50470
+ unsigned char ss : 1;
50471
+
50472
+ unsigned char pc : 3;
50473
+ unsigned char dmv : 4;
50474
+ unsigned char cv : 4;
50475
+};
50476
+
50477
+struct rt
50478
+{
50479
+ struct rt* d;
50480
+ void (*edo)(void * const);
50481
+ short lId;
50482
+ char dac;
50483
+};
50484
+
50485
+struct pedr
50486
+{
50487
+ struct rt re;
50488
+ struct PCT pc;
50489
+ unsigned char mid;
50490
+} ;
50491
+
50492
+void __attribute__((__noinline__))
50493
+rei(struct rt* const me, unsigned short anId, void *ad )
50494
+{
50495
+ asm volatile ("");
50496
+}
50497
+
50498
+void __attribute__((__noinline__))
50499
+pedrdo(void * const p)
50500
+{
50501
+ asm volatile ("");
50502
+}
50503
+
50504
+void __attribute__((__noinline__))
50505
+pedri (struct pedr* const me, struct PCT ppc, unsigned char pmid)
50506
+{
50507
+ rei(&(me->re), 0x7604, 0);
50508
+ me->pc = ppc;
50509
+ me->mid = pmid;
50510
+ (me)->re.edo = pedrdo;
50511
+}
50512
+
50513
+int main()
50514
+{
50515
+ struct PCT ps;
50516
+ struct pedr pm;
50517
+
50518
+ pm.pc.dmv = 0;
50519
+ ps.dmv = 1;
50520
+ pedri(&pm, ps, 32);
50521
+
50522
+ if (pm.pc.dmv != 1)
50523
+ abort ();
50524
+ exit (0);
50525
+}
50526
--- a/src/gcc/testsuite/gcc.dg/pr46893.c
50527
+++ b/src/gcc/testsuite/gcc.dg/pr46893.c
50528
@@ -0,0 +1,13 @@
50529
+/* PR debug/46893 */
50530
+/* { dg-do compile } */
50531
+/* { dg-options "-O -g" } */
50532
+
50533
+void
50534
+foo (void)
50535
+{
50536
+ union { unsigned long long l; double d; } u = { 0x7ff0000000000000ULL };
50537
+ double v = 0, w = -u.d;
50538
+
50539
+ if (w)
50540
+ w = v;
50541
+}
50542
42166
--- a/src/gcc/testsuite/gcc.dg/pr46909.c
50543
42167
+++ b/src/gcc/testsuite/gcc.dg/pr46909.c
50544
42168
@@ -0,0 +1,17 @@
50559
42183
+
50560
42184
+/* { dg-final { scan-tree-dump "optimizing two comparisons to x_\[0-9\]+\\(D\\) != 4" "ifcombine" } } */
50561
42185
+/* { dg-final { cleanup-tree-dump "ifcombine" } } */
50562
--- a/src/gcc/testsuite/gcc.dg/pr47201.c
50563
+++ b/src/gcc/testsuite/gcc.dg/pr47201.c
50564
@@ -0,0 +1,18 @@
50565
+/* PR target/47201 */
42186
--- a/src/gcc/testsuite/gcc.dg/pr48685.c
42187
+++ b/src/gcc/testsuite/gcc.dg/pr48685.c
42188
@@ -0,0 +1,11 @@
42189
+/* PR c/48685 */
50566
42190
+/* { dg-do compile } */
50567
+/* { dg-options "-O -fpic -g" { target fpic } } */
42191
+/* { dg-options "-O2" } */
50568
42192
+
50569
+union U
42193
+int
42194
+main ()
50570
42195
+{
50571
+ __UINTPTR_TYPE__ m;
50572
+ float d;
50573
+} u;
50574
+
50575
+int
42196
+ int v = 1;
42197
+ (void) (1 == 2 ? (void) 0 : (v = 0));
42198
+ return v;
42199
+}
42200
--- a/src/gcc/testsuite/gcc.dg/pr48774.c
42201
+++ b/src/gcc/testsuite/gcc.dg/pr48774.c
42202
@@ -0,0 +1,38 @@
42203
+/* PR target/48774 */
42204
+/* { dg-do run } */
42205
+/* { dg-options "-O2 -funroll-loops" } */
42206
+
42207
+extern void abort (void);
42208
+unsigned long int s[24]
42209
+ = { 12, ~1, 12, ~2, 12, ~4, 12, ~8, 12, ~16, 12, ~32,
42210
+ 12, ~64, 12, ~128, 12, ~256, 12, ~512, 12, ~1024, 12, ~2048 };
42211
+struct { int n; unsigned long *e[12]; } g
42212
+ = { 12, { &s[0], &s[2], &s[4], &s[6], &s[8], &s[10], &s[12], &s[14],
42213
+ &s[16], &s[18], &s[20], &s[22] } };
42214
+int c[12];
42215
+
42216
+__attribute__((noinline, noclone)) void
50576
42217
+foo (void)
50577
42218
+{
50578
+ union U v = {
50579
+ (__UINTPTR_TYPE__)&u
50580
+ };
50581
+ return u.d == v.d;
42219
+ int i, j;
42220
+ for (i = 0; i < g.n; i++)
42221
+ for (j = 0; j < g.n; j++)
42222
+ {
42223
+ if (i == j && j < g.e[0][0] && (g.e[i][1] & (1UL << j)))
42224
+ abort ();
42225
+ if (j < g.e[0][0] && (g.e[i][1] & (1UL << j)))
42226
+ c[i]++;
42227
+ }
42228
+}
42229
+
42230
+int
42231
+main ()
42232
+{
42233
+ int i;
42234
+ asm volatile ("" : "+m" (s), "+m" (g), "+m" (c));
42235
+ foo ();
42236
+ for (i = 0; i < 12; i++)
42237
+ if (c[i] != 11)
42238
+ abort ();
42239
+ return 0;
50582
42240
+}
50583
42241
--- a/src/gcc/testsuite/gcc.dg/switch-bittest.c
50584
42242
+++ b/src/gcc/testsuite/gcc.dg/switch-bittest.c
50636
42294
+/* { dg-final { scan-rtl-dump-times "REG_BR_PROB" 2 "expand" { target mips*-*-* } } } */
50637
42295
+/* { dg-final { scan-rtl-dump-times "heuristics" 0 "expand" { target mips*-*-* } } } */
50638
42296
+/* { dg-final { cleanup-rtl-dump "expand" } } */
50639
--- a/src/gcc/testsuite/gcc.dg/torture/20090618-1.c
50640
+++ b/src/gcc/testsuite/gcc.dg/torture/20090618-1.c
50641
@@ -1,5 +1,6 @@
50642
/* { dg-do run } */
50643
/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
50644
+/* { dg-skip-if "PR middle-end/47405" { mips-sgi-irix* } } */
50645
50646
extern void abort (void);
50647
50648
42297
--- a/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c
50649
42298
+++ b/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c
50650
42299
@@ -1,7 +1,8 @@
50707
42356
50708
42357
#include "arm-fp16-ops.h"
50709
42358
50710
--- a/src/gcc/testsuite/gcc.dg/torture/pr39074-2.c
50711
+++ b/src/gcc/testsuite/gcc.dg/torture/pr39074-2.c
50712
@@ -30,5 +30,5 @@
50713
return 0;
50714
}
50715
50716
-/* { dg-final { scan-tree-dump "y.._., points-to non-local, points-to escaped, points-to vars: { i }" "alias" } } */
50717
+/* { dg-final { scan-tree-dump "y.._., points-to vars: { i }" "alias" } } */
50718
/* { dg-final { cleanup-tree-dump "alias" } } */
50719
--- a/src/gcc/testsuite/gcc.dg/torture/pr45967-2.c
50720
+++ b/src/gcc/testsuite/gcc.dg/torture/pr45967-2.c
50721
@@ -0,0 +1,24 @@
50722
+/* { dg-do run } */
50723
+
50724
+extern void abort (void);
50725
+int b;
50726
+void
50727
+foo (void *p_, int *q)
50728
+{
50729
+ int *p;
50730
+ int i;
50731
+ for (i = 0; i < sizeof(int *); ++i)
50732
+ ((char *)&p)[i] = ((char *)p_)[i];
50733
+ if (b)
50734
+ p = q;
50735
+ *p = 1;
50736
+}
50737
+int main()
50738
+{
50739
+ int i = 0, j;
50740
+ int *p = &i;
50741
+ foo (&p, &j);
50742
+ if (i != 1)
50743
+ abort ();
50744
+ return 0;
50745
+}
50746
--- a/src/gcc/testsuite/gcc.dg/torture/pr45967-3.c
50747
+++ b/src/gcc/testsuite/gcc.dg/torture/pr45967-3.c
50748
@@ -0,0 +1,21 @@
50749
+/* { dg-do run } */
50750
+
50751
+extern void abort (void);
50752
+void
50753
+foo (void *p_)
50754
+{
50755
+ int *p;
50756
+ int i;
50757
+ for (i = 0; i < sizeof(int *); ++i)
50758
+ ((char *)&p)[i] = ((char *)p_)[i];
50759
+ *p = 1;
50760
+}
50761
+int main()
50762
+{
50763
+ int i = 0;
50764
+ int *p = &i;
50765
+ foo (&p);
50766
+ if (i != 1)
50767
+ abort ();
50768
+ return 0;
50769
+}
50770
--- a/src/gcc/testsuite/gcc.dg/torture/pr45967.c
50771
+++ b/src/gcc/testsuite/gcc.dg/torture/pr45967.c
50772
@@ -0,0 +1,21 @@
50773
+/* { dg-do run } */
50774
+
50775
+extern void abort (void);
50776
+void __attribute__((noinline,noclone))
50777
+foo (void *p_)
50778
+{
50779
+ int *p;
50780
+ int i;
50781
+ for (i = 0; i < sizeof(int *); ++i)
50782
+ ((char *)&p)[i] = ((char *)p_)[i];
50783
+ *p = 1;
50784
+}
50785
+int main()
50786
+{
50787
+ int i = 0;
50788
+ int *p = &i;
50789
+ foo (&p);
50790
+ if (i != 1)
50791
+ abort ();
50792
+ return 0;
50793
+}
50794
--- a/src/gcc/testsuite/gcc.dg/torture/pr46723.c
50795
+++ b/src/gcc/testsuite/gcc.dg/torture/pr46723.c
50796
@@ -0,0 +1,10 @@
50797
+/* { dg-do compile } */
50798
+
50799
+short *m;
50800
+void test()
50801
+{
50802
+ short x = 128;
50803
+ unsigned int i;
50804
+ for (i = 0; i < 128; ++i, x = (unsigned short)x + 1)
50805
+ m[i] = x;
50806
+}
50807
--- a/src/gcc/testsuite/gcc.dg/torture/pr47278-1.c
50808
+++ b/src/gcc/testsuite/gcc.dg/torture/pr47278-1.c
50809
@@ -0,0 +1,5 @@
50810
+/* { dg-do run } */
50811
+/* { dg-require-visibility "" } */
50812
+/* { dg-additional-sources "pr47278-2.c" } */
50813
+
50814
+int foo (void) { return 1; }
50815
--- a/src/gcc/testsuite/gcc.dg/torture/pr47278-2.c
50816
+++ b/src/gcc/testsuite/gcc.dg/torture/pr47278-2.c
50817
@@ -0,0 +1,15 @@
50818
+/* { dg-require-visibility "" } */
50819
+
50820
+extern void abort (void);
50821
+
50822
+int __attribute__((weak,visibility("hidden"))) foo (void)
50823
+{
50824
+ return 0;
50825
+}
50826
+
50827
+int main()
50828
+{
50829
+ if (foo() != 1)
50830
+ abort ();
50831
+ return 0;
50832
+}
50833
--- a/src/gcc/testsuite/gcc.dg/torture/pr47365.c
50834
+++ b/src/gcc/testsuite/gcc.dg/torture/pr47365.c
50835
@@ -0,0 +1,39 @@
50836
+/* { dg-do run } */
50837
+
50838
+struct A
50839
+{
50840
+ int i;
50841
+};
50842
+
50843
+struct B
50844
+{
50845
+ struct A a[2];
50846
+};
50847
+
50848
+int i = 1;
50849
+struct B b = { 0, 3 };
50850
+
50851
+static void
50852
+test ()
50853
+{
50854
+ if (b.a[0].i != i)
50855
+ {
50856
+ int t = b.a[0].i;
50857
+ b.a[0] = b.a[1];
50858
+ b.a[1].i = t;
50859
+ }
50860
+
50861
+ if (b.a[1].i == i)
50862
+ __builtin_abort ();
50863
+
50864
+ if (b.a[0].i == 0)
50865
+ __builtin_abort ();
50866
+}
50867
+
50868
+int
50869
+main ()
50870
+{
50871
+ test ();
50872
+ return 0;
50873
+}
50874
+
50875
--- a/src/gcc/testsuite/gcc.dg/torture/pr47411.c
50876
+++ b/src/gcc/testsuite/gcc.dg/torture/pr47411.c
50877
@@ -0,0 +1,42 @@
50878
+/* { dg-do compile } */
50879
+
50880
+typedef long unsigned int size_t;
50881
+
50882
+static __inline void *
50883
+__inline_memcpy_chk (void *__dest, const void *__src, size_t __len)
50884
+{
50885
+ return __builtin___memcpy_chk (__dest, __src, __len, __builtin_object_size (__dest, 0));
50886
+}
50887
+
50888
+extern void *xmalloc (size_t) __attribute__ ((__malloc__));
50889
+
50890
+struct htab { void ** entries; };
50891
+
50892
+typedef struct htab *htab_t;
50893
+
50894
+extern void ** htab_find_slot (htab_t, const void *);
50895
+
50896
+enum mode_class { MODE_RANDOM, MODE_CC, MODE_INT, MAX_MODE_CLASS };
50897
+
50898
+struct mode_data
50899
+{
50900
+ struct mode_data *next;
50901
+ enum mode_class cl;
50902
+};
50903
+
50904
+static const struct mode_data blank_mode = { 0, MAX_MODE_CLASS };
50905
+
50906
+static htab_t modes_by_name;
50907
+
50908
+struct mode_data *
50909
+new_mode (void)
50910
+{
50911
+ struct mode_data *m
50912
+ = ((struct mode_data *) xmalloc (sizeof (struct mode_data)));
50913
+
50914
+ ((__builtin_object_size (m, 0) != (size_t) -1) ? __builtin___memcpy_chk (m, &blank_mode, sizeof (struct mode_data), __builtin_object_size (m, 0)) : __inline_memcpy_chk (m, &blank_mode, sizeof (struct mode_data)));
50915
+
50916
+ *htab_find_slot (modes_by_name, m) = m;
50917
+
50918
+ return m;
50919
+}
50920
--- a/src/gcc/testsuite/gcc.dg/torture/pr47890.c
50921
+++ b/src/gcc/testsuite/gcc.dg/torture/pr47890.c
50922
@@ -0,0 +1,9 @@
50923
+/* { dg-do compile } */
50924
+
50925
+void f(char *s)
50926
+{
50927
+ signed short i;
50928
+
50929
+ for (i = 0; i < 19; i = i + 1)
50930
+ s[i] = i;
50931
+}
50932
--- a/src/gcc/testsuite/gcc.dg/torture/pta-escape-1.c
50933
+++ b/src/gcc/testsuite/gcc.dg/torture/pta-escape-1.c
50934
@@ -30,5 +30,5 @@
50935
return 0;
50936
}
50937
50938
-/* { dg-final { scan-tree-dump "ESCAPED = { ESCAPED NONLOCAL i }" "alias" } } */
50939
+/* { dg-final { scan-tree-dump "ESCAPED = {\[^\n\}\]* i \[^\n\}\]*}" "alias" } } */
50940
/* { dg-final { cleanup-tree-dump "alias" } } */
50941
--- a/src/gcc/testsuite/gcc.dg/torture/pta-ptrarith-1.c
50942
+++ b/src/gcc/testsuite/gcc.dg/torture/pta-ptrarith-1.c
50943
@@ -29,5 +29,5 @@
50944
return 0;
50945
}
50946
50947
-/* { dg-final { scan-tree-dump "ESCAPED = { ESCAPED NONLOCAL f .* i }" "alias" } } */
50948
+/* { dg-final { scan-tree-dump "ESCAPED = {\[^\n\}\]* i f \[^\n\}\]*}" "alias" } } */
50949
/* { dg-final { cleanup-tree-dump "alias" } } */
50950
42359
--- a/src/gcc/testsuite/gcc.dg/torture/volatile-pic-1.c
50951
42360
+++ b/src/gcc/testsuite/gcc.dg/torture/volatile-pic-1.c
50952
42361
@@ -0,0 +1,20 @@
50970
42379
+ bar ();
50971
42380
+ return 0;
50972
42381
+}
50973
--- a/src/gcc/testsuite/gcc.dg/tree-ssa/pr42585.c
50974
+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr42585.c
50975
@@ -32,6 +32,9 @@
50976
}
50977
50978
/* The local aggregates . */
50979
-/* { dg-final { scan-tree-dump-times "struct _fat_ptr _ans" 0 "optimized"} } */
50980
-/* { dg-final { scan-tree-dump-times "struct _fat_ptr _T2" 0 "optimized"} } */
50981
+/* Whether the structs are totally scalarized or not depends on the
50982
+ MOVE_RATIO macro defintion in the back end. The scalarization will
50983
+ not take place when using small values for MOVE_RATIO. */
50984
+/* { dg-final { scan-tree-dump-times "struct _fat_ptr _ans" 0 "optimized" { target { ! "powerpc*-*-* arm-*-* sh*-*-* s390*-*-*" } } } } */
50985
+/* { dg-final { scan-tree-dump-times "struct _fat_ptr _T2" 0 "optimized" { target { ! "powerpc*-*-* arm-*-* sh*-*-* s390*-*-*" } } } } */
50986
/* { dg-final { cleanup-tree-dump "optimized" } } */
50987
42382
--- a/src/gcc/testsuite/gcc.dg/tree-ssa/pr45144.c
50988
42383
+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr45144.c
50989
42384
@@ -0,0 +1,46 @@
51033
42428
+
51034
42429
+/* { dg-final { scan-tree-dump "x = a;" "optimized"} } */
51035
42430
+/* { dg-final { cleanup-tree-dump "optimized" } } */
51036
--- a/src/gcc/testsuite/gcc.dg/tree-ssa/pr47286.c
51037
+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr47286.c
51038
@@ -0,0 +1,20 @@
51039
+/* { dg-do compile } */
51040
+/* { dg-skip-if "" { ! { i?86-*-* x86_64-*-* } } { "*" } { "" } } */
51041
+/* { dg-options "-O2 -fdump-tree-optimized" } */
51042
+
51043
+struct thread_info { int preempt_count; };
51044
+static inline struct thread_info *current_thread_info(void)
51045
+{
51046
+ register struct thread_info *sp asm("esp");
51047
+ return sp;
51048
+}
51049
+void testcase(void)
51050
+{
51051
+ current_thread_info()->preempt_count += 1;
51052
+}
51053
+
51054
+/* We have to make sure that alias analysis treats sp as pointing
51055
+ to globals and thus the store not optimized away. */
51056
+
51057
+/* { dg-final { scan-tree-dump "->preempt_count =" "optimized" } } */
51058
+/* { dg-final { cleanup-tree-dump "optimized" } } */
51059
--- a/src/gcc/testsuite/gcc.dg/tree-ssa/pr47392.c
51060
+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr47392.c
51061
@@ -0,0 +1,42 @@
51062
+/* { dg-do run } */
51063
+/* { dg-options "-O2 -fdump-tree-pre-stats" } */
51064
+
51065
+struct A
51066
+{
51067
+ int i;
51068
+};
51069
+
51070
+struct B
51071
+{
51072
+ struct A a[2];
51073
+};
51074
+
51075
+int i = 1;
51076
+struct B b = { 0, 3 };
51077
+
51078
+static void
51079
+test ()
51080
+{
51081
+ if (b.a[0].i != i)
51082
+ {
51083
+ int t = b.a[0].i;
51084
+ b.a[0] = b.a[1];
51085
+ b.a[1].i = t;
51086
+ }
51087
+
51088
+ if (b.a[1].i == i)
51089
+ __builtin_abort ();
51090
+
51091
+ if (b.a[0].i == 0)
51092
+ __builtin_abort ();
51093
+}
51094
+
51095
+int
51096
+main ()
51097
+{
51098
+ test ();
51099
+ return 0;
51100
+}
51101
+
51102
+/* { dg-final { scan-tree-dump "Eliminated: 1" "pre" } } */
51103
+/* { dg-final { cleanup-tree-dump "pre" } } */
51104
--- a/src/gcc/testsuite/gcc.dg/tree-ssa/pta-callused.c
51105
+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pta-callused.c
51106
@@ -22,6 +22,6 @@
51107
return *foo (&q);
51108
}
51109
51110
-/* { dg-final { scan-tree-dump "CALLUSED = { f.* i q }" "alias" } } */
51111
+/* { dg-final { scan-tree-dump "CALLUSED = { ESCAPED NONLOCAL f.* i q }" "alias" } } */
51112
/* { dg-final { cleanup-tree-dump "alias" } } */
51113
51114
--- a/src/gcc/testsuite/gcc.dg/tree-ssa/pta-escape-1.c
51115
+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pta-escape-1.c
51116
@@ -33,5 +33,5 @@
51117
return 0;
51118
}
51119
51120
-/* { dg-final { scan-tree-dump "ESCAPED, points-to non-local, points-to vars: { x }" "alias" } } */
51121
+/* { dg-final { scan-tree-dump "ESCAPED, points-to non-local, points-to NULL, points-to vars: { x }" "alias" } } */
51122
/* { dg-final { cleanup-tree-dump "alias" } } */
51123
--- a/src/gcc/testsuite/gcc.dg/tree-ssa/pta-escape-2.c
51124
+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pta-escape-2.c
51125
@@ -34,5 +34,5 @@
51126
return 0;
51127
}
51128
51129
-/* { dg-final { scan-tree-dump "ESCAPED, points-to non-local, points-to vars: { x }" "alias" } } */
51130
+/* { dg-final { scan-tree-dump "ESCAPED, points-to non-local, points-to NULL, points-to vars: { x }" "alias" } } */
51131
/* { dg-final { cleanup-tree-dump "alias" } } */
51132
--- a/src/gcc/testsuite/gcc.dg/tree-ssa/pta-escape-3.c
51133
+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pta-escape-3.c
51134
@@ -38,5 +38,5 @@
51135
return 0;
51136
}
51137
51138
-/* { dg-final { scan-tree-dump "ESCAPED, points-to non-local, points-to vars: { x }" "alias" } } */
51139
+/* { dg-final { scan-tree-dump "ESCAPED, points-to non-local, points-to NULL, points-to vars: { x }" "alias" } } */
51140
/* { dg-final { cleanup-tree-dump "alias" } } */
51141
--- a/src/gcc/testsuite/gcc.dg/tree-ssa/ssa-pre-21.c
51142
+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/ssa-pre-21.c
51143
@@ -11,5 +11,5 @@
51144
51145
/* There should be only two loads left. */
51146
51147
-/* { dg-final { scan-tree-dump-times "= \\\*D" 2 "pre" } } */
51148
+/* { dg-final { scan-tree-dump-times "= \\\*D\[^\n;\]*;" 2 "pre" } } */
51149
/* { dg-final { cleanup-tree-dump "pre" } } */
51150
42431
--- a/src/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-8.c
51151
42432
+++ b/src/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-8.c
51152
42433
@@ -46,5 +46,5 @@
51164
42445
51165
42446
#include <stdarg.h>
51166
42447
#include "tree-vect.h"
51167
--- a/src/gcc/testsuite/gcc.dg/vect/pr43430-1.c
51168
+++ b/src/gcc/testsuite/gcc.dg/vect/pr43430-1.c
51169
@@ -35,5 +35,5 @@
51170
return foo (data_ch1, data_ch2, 1);
51171
}
51172
51173
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
51174
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_condition } } } */
51175
/* { dg-final { cleanup-tree-dump "vect" } } */
51176
42448
--- a/src/gcc/testsuite/gcc.dg/vect/slp-25.c
51177
42449
+++ b/src/gcc/testsuite/gcc.dg/vect/slp-25.c
51178
42450
@@ -1,4 +1,5 @@
51189
42461
51190
42462
#include <stdarg.h>
51191
42463
#include <stdio.h>
51192
--- a/src/gcc/testsuite/gcc.dg/vect/slp-multitypes-2.c
51193
+++ b/src/gcc/testsuite/gcc.dg/vect/slp-multitypes-2.c
51194
@@ -1,4 +1,5 @@
51195
/* { dg-require-effective-target vect_int } */
51196
+/* { dg-do run { xfail { sparc*-*-* && ilp32 } } } PR rtl-opt/46603 */
51197
51198
#include <stdarg.h>
51199
#include <stdio.h>
51200
42464
--- a/src/gcc/testsuite/gcc.dg/vect/vect-109.c
51201
42465
+++ b/src/gcc/testsuite/gcc.dg/vect/vect-109.c
51202
42466
@@ -1,4 +1,5 @@
60898
52162
}
60899
52163
60900
52164
-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
60901
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52165
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
60902
52166
/* { dg-final { cleanup-saved-temps } } */
60903
52167
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
60904
52168
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
60917
52181
}
60918
52182
60919
52183
-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
60920
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52184
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
60921
52185
/* { dg-final { cleanup-saved-temps } } */
60922
52186
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
60923
52187
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
60936
52200
}
60937
52201
60938
52202
-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
60939
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52203
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
60940
52204
/* { dg-final { cleanup-saved-temps } } */
60941
52205
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
60942
52206
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
60955
52219
}
60956
52220
60957
52221
-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
60958
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52222
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
60959
52223
/* { dg-final { cleanup-saved-temps } } */
60960
52224
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
60961
52225
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
60974
52238
}
60975
52239
60976
52240
-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
60977
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52241
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
60978
52242
/* { dg-final { cleanup-saved-temps } } */
60979
52243
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
60980
52244
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
60993
52257
}
60994
52258
60995
52259
-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
60996
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52260
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
60997
52261
/* { dg-final { cleanup-saved-temps } } */
60998
52262
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
60999
52263
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
61012
52276
}
61013
52277
61014
52278
-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61015
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52279
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61016
52280
/* { dg-final { cleanup-saved-temps } } */
61017
52281
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
61018
52282
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
61031
52295
}
61032
52296
61033
52297
-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61034
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52298
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61035
52299
/* { dg-final { cleanup-saved-temps } } */
61036
52300
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
61037
52301
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
61050
52314
}
61051
52315
61052
52316
-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61053
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52317
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61054
52318
/* { dg-final { cleanup-saved-temps } } */
61055
52319
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
61056
52320
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
61069
52333
}
61070
52334
61071
52335
-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61072
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52336
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61073
52337
/* { dg-final { cleanup-saved-temps } } */
61074
52338
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
61075
52339
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
61088
52352
}
61089
52353
61090
52354
-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61091
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52355
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61092
52356
/* { dg-final { cleanup-saved-temps } } */
61093
52357
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
61094
52358
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
61107
52371
}
61108
52372
61109
52373
-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61110
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52374
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61111
52375
/* { dg-final { cleanup-saved-temps } } */
61112
52376
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
61113
52377
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
61126
52390
}
61127
52391
61128
52392
-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61129
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52393
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61130
52394
/* { dg-final { cleanup-saved-temps } } */
61131
52395
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
61132
52396
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
61145
52409
}
61146
52410
61147
52411
-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61148
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52412
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61149
52413
/* { dg-final { cleanup-saved-temps } } */
61150
52414
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
61151
52415
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
61164
52428
}
61165
52429
61166
52430
-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61167
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52431
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61168
52432
/* { dg-final { cleanup-saved-temps } } */
61169
52433
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
61170
52434
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
61183
52447
}
61184
52448
61185
52449
-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61186
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52450
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61187
52451
/* { dg-final { cleanup-saved-temps } } */
61188
52452
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
61189
52453
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
61202
52466
}
61203
52467
61204
52468
-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61205
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52469
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61206
52470
/* { dg-final { cleanup-saved-temps } } */
61207
52471
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
61208
52472
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
61221
52485
}
61222
52486
61223
52487
-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61224
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52488
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61225
52489
/* { dg-final { cleanup-saved-temps } } */
61226
52490
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
61227
52491
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
61240
52504
}
61241
52505
61242
52506
-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61243
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52507
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61244
52508
/* { dg-final { cleanup-saved-temps } } */
61245
52509
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
61246
52510
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
61259
52523
}
61260
52524
61261
52525
-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61262
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52526
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61263
52527
/* { dg-final { cleanup-saved-temps } } */
61264
52528
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
61265
52529
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
61278
52542
}
61279
52543
61280
52544
-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61281
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52545
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61282
52546
/* { dg-final { cleanup-saved-temps } } */
61283
52547
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
61284
52548
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
61297
52561
}
61298
52562
61299
52563
-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61300
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52564
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61301
52565
/* { dg-final { cleanup-saved-temps } } */
61302
52566
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
61303
52567
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
61316
52580
}
61317
52581
61318
52582
-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61319
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52583
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61320
52584
/* { dg-final { cleanup-saved-temps } } */
61321
52585
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
61322
52586
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
61335
52599
}
61336
52600
61337
52601
-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61338
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52602
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61339
52603
/* { dg-final { cleanup-saved-temps } } */
61340
52604
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
61341
52605
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
61354
52618
}
61355
52619
61356
52620
-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61357
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52621
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61358
52622
/* { dg-final { cleanup-saved-temps } } */
61359
52623
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
61360
52624
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
61373
52637
}
61374
52638
61375
52639
-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61376
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52640
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61377
52641
/* { dg-final { cleanup-saved-temps } } */
61378
52642
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
61379
52643
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
61392
52656
}
61393
52657
61394
52658
-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61395
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52659
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61396
52660
/* { dg-final { cleanup-saved-temps } } */
61397
52661
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
61398
52662
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
61411
52675
}
61412
52676
61413
52677
-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61414
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52678
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61415
52679
/* { dg-final { cleanup-saved-temps } } */
61416
52680
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
61417
52681
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
61430
52694
}
61431
52695
61432
52696
-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61433
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52697
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61434
52698
/* { dg-final { cleanup-saved-temps } } */
61435
52699
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
61436
52700
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
61449
52713
}
61450
52714
61451
52715
-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61452
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52716
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61453
52717
/* { dg-final { cleanup-saved-temps } } */
61454
52718
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
61455
52719
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
61468
52732
}
61469
52733
61470
52734
-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61471
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52735
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61472
52736
/* { dg-final { cleanup-saved-temps } } */
61473
52737
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
61474
52738
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
61487
52751
}
61488
52752
61489
52753
-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61490
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52754
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61491
52755
/* { dg-final { cleanup-saved-temps } } */
61492
52756
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
61493
52757
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
61506
52770
}
61507
52771
61508
52772
-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61509
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52773
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61510
52774
/* { dg-final { cleanup-saved-temps } } */
61511
52775
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
61512
52776
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
61525
52789
}
61526
52790
61527
52791
-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61528
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52792
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61529
52793
/* { dg-final { cleanup-saved-temps } } */
61530
52794
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
61531
52795
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
61544
52808
}
61545
52809
61546
52810
-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61547
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52811
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61548
52812
/* { dg-final { cleanup-saved-temps } } */
61549
52813
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
61550
52814
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
61563
52827
}
61564
52828
61565
52829
-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61566
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52830
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61567
52831
/* { dg-final { cleanup-saved-temps } } */
61568
52832
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
61569
52833
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
61582
52846
}
61583
52847
61584
52848
-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61585
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52849
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61586
52850
/* { dg-final { cleanup-saved-temps } } */
61587
52851
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
61588
52852
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
61601
52865
}
61602
52866
61603
52867
-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61604
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52868
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61605
52869
/* { dg-final { cleanup-saved-temps } } */
61606
52870
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
61607
52871
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
61620
52884
}
61621
52885
61622
52886
-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61623
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52887
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61624
52888
/* { dg-final { cleanup-saved-temps } } */
61625
52889
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
61626
52890
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
61639
52903
}
61640
52904
61641
52905
-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61642
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52906
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61643
52907
/* { dg-final { cleanup-saved-temps } } */
61644
52908
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
61645
52909
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
61658
52922
}
61659
52923
61660
52924
-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61661
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52925
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61662
52926
/* { dg-final { cleanup-saved-temps } } */
61663
52927
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
61664
52928
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
61677
52941
}
61678
52942
61679
52943
-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61680
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52944
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61681
52945
/* { dg-final { cleanup-saved-temps } } */
61682
52946
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
61683
52947
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
61696
52960
}
61697
52961
61698
52962
-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61699
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52963
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61700
52964
/* { dg-final { cleanup-saved-temps } } */
61701
52965
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
61702
52966
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
61715
52979
}
61716
52980
61717
52981
-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61718
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
52982
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61719
52983
/* { dg-final { cleanup-saved-temps } } */
61720
52984
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
61721
52985
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
61734
52998
}
61735
52999
61736
53000
-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61737
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53001
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61738
53002
/* { dg-final { cleanup-saved-temps } } */
61739
53003
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
61740
53004
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
61753
53017
}
61754
53018
61755
53019
-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61756
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53020
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61757
53021
/* { dg-final { cleanup-saved-temps } } */
61758
53022
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
61759
53023
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
61772
53036
}
61773
53037
61774
53038
-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61775
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53039
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61776
53040
/* { dg-final { cleanup-saved-temps } } */
61777
53041
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
61778
53042
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
61791
53055
}
61792
53056
61793
53057
-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61794
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53058
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61795
53059
/* { dg-final { cleanup-saved-temps } } */
61796
53060
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
61797
53061
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
61810
53074
}
61811
53075
61812
53076
-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61813
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53077
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61814
53078
/* { dg-final { cleanup-saved-temps } } */
61815
53079
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
61816
53080
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
61829
53093
}
61830
53094
61831
53095
-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61832
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53096
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61833
53097
/* { dg-final { cleanup-saved-temps } } */
61834
53098
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
61835
53099
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
61848
53112
}
61849
53113
61850
53114
-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61851
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53115
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61852
53116
/* { dg-final { cleanup-saved-temps } } */
61853
53117
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
61854
53118
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
61867
53131
}
61868
53132
61869
53133
-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61870
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53134
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61871
53135
/* { dg-final { cleanup-saved-temps } } */
61872
53136
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
61873
53137
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
61886
53150
}
61887
53151
61888
53152
-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61889
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53153
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61890
53154
/* { dg-final { cleanup-saved-temps } } */
61891
53155
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
61892
53156
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
61905
53169
}
61906
53170
61907
53171
-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61908
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53172
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61909
53173
/* { dg-final { cleanup-saved-temps } } */
61910
53174
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
61911
53175
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
61924
53188
}
61925
53189
61926
53190
-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61927
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53191
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61928
53192
/* { dg-final { cleanup-saved-temps } } */
61929
53193
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
61930
53194
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
61943
53207
}
61944
53208
61945
53209
-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61946
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53210
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61947
53211
/* { dg-final { cleanup-saved-temps } } */
61948
53212
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
61949
53213
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
61962
53226
}
61963
53227
61964
53228
-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61965
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53229
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61966
53230
/* { dg-final { cleanup-saved-temps } } */
61967
53231
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
61968
53232
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
61981
53245
}
61982
53246
61983
53247
-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
61984
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53248
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
61985
53249
/* { dg-final { cleanup-saved-temps } } */
61986
53250
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
61987
53251
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
62000
53264
}
62001
53265
62002
53266
-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62003
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53267
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62004
53268
/* { dg-final { cleanup-saved-temps } } */
62005
53269
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
62006
53270
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
62019
53283
}
62020
53284
62021
53285
-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62022
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53286
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62023
53287
/* { dg-final { cleanup-saved-temps } } */
62024
53288
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
62025
53289
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
62038
53302
}
62039
53303
62040
53304
-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62041
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53305
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62042
53306
/* { dg-final { cleanup-saved-temps } } */
62043
53307
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
62044
53308
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
62057
53321
}
62058
53322
62059
53323
-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62060
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53324
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62061
53325
/* { dg-final { cleanup-saved-temps } } */
62062
53326
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
62063
53327
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
62076
53340
}
62077
53341
62078
53342
-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62079
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53343
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62080
53344
/* { dg-final { cleanup-saved-temps } } */
62081
53345
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
62082
53346
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
62095
53359
}
62096
53360
62097
53361
-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62098
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53362
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62099
53363
/* { dg-final { cleanup-saved-temps } } */
62100
53364
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
62101
53365
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
62114
53378
}
62115
53379
62116
53380
-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62117
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53381
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62118
53382
/* { dg-final { cleanup-saved-temps } } */
62119
53383
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
62120
53384
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
62133
53397
}
62134
53398
62135
53399
-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62136
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53400
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62137
53401
/* { dg-final { cleanup-saved-temps } } */
62138
53402
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
62139
53403
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
62152
53416
}
62153
53417
62154
53418
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62155
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53419
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62156
53420
/* { dg-final { cleanup-saved-temps } } */
62157
53421
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
62158
53422
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
62171
53435
}
62172
53436
62173
53437
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62174
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53438
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62175
53439
/* { dg-final { cleanup-saved-temps } } */
62176
53440
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
62177
53441
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
62190
53454
}
62191
53455
62192
53456
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62193
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53457
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62194
53458
/* { dg-final { cleanup-saved-temps } } */
62195
53459
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
62196
53460
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
62209
53473
}
62210
53474
62211
53475
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62212
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53476
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62213
53477
/* { dg-final { cleanup-saved-temps } } */
62214
53478
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
62215
53479
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
62228
53492
}
62229
53493
62230
53494
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62231
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53495
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62232
53496
/* { dg-final { cleanup-saved-temps } } */
62233
53497
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
62234
53498
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
62247
53511
}
62248
53512
62249
53513
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62250
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53514
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62251
53515
/* { dg-final { cleanup-saved-temps } } */
62252
53516
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
62253
53517
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
62267
53531
62268
53532
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62269
53533
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62270
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
62271
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53534
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
53535
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62272
53536
/* { dg-final { cleanup-saved-temps } } */
62273
53537
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
62274
53538
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
62288
53552
62289
53553
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62290
53554
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62291
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
62292
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53555
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
53556
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62293
53557
/* { dg-final { cleanup-saved-temps } } */
62294
53558
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
62295
53559
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
62309
53573
62310
53574
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62311
53575
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62312
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
62313
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53576
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
53577
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62314
53578
/* { dg-final { cleanup-saved-temps } } */
62315
53579
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
62316
53580
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
62330
53594
62331
53595
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62332
53596
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62333
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
62334
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53597
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
53598
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62335
53599
/* { dg-final { cleanup-saved-temps } } */
62336
53600
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
62337
53601
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
62351
53615
62352
53616
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62353
53617
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62354
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
62355
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53618
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
53619
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62356
53620
/* { dg-final { cleanup-saved-temps } } */
62357
53621
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
62358
53622
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
62372
53636
62373
53637
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62374
53638
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62375
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
62376
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53639
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
53640
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62377
53641
/* { dg-final { cleanup-saved-temps } } */
62378
53642
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
62379
53643
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
62393
53657
62394
53658
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62395
53659
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62396
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
62397
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53660
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
53661
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62398
53662
/* { dg-final { cleanup-saved-temps } } */
62399
53663
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
62400
53664
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
62414
53678
62415
53679
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62416
53680
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62417
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
62418
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53681
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
53682
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62419
53683
/* { dg-final { cleanup-saved-temps } } */
62420
53684
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
62421
53685
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
62435
53699
62436
53700
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62437
53701
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62438
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
62439
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53702
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
53703
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62440
53704
/* { dg-final { cleanup-saved-temps } } */
62441
53705
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
62442
53706
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
62455
53719
}
62456
53720
62457
53721
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62458
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53722
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62459
53723
/* { dg-final { cleanup-saved-temps } } */
62460
53724
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
62461
53725
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
62474
53738
}
62475
53739
62476
53740
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62477
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53741
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62478
53742
/* { dg-final { cleanup-saved-temps } } */
62479
53743
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
62480
53744
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
62493
53757
}
62494
53758
62495
53759
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62496
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53760
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62497
53761
/* { dg-final { cleanup-saved-temps } } */
62498
53762
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
62499
53763
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
62512
53776
}
62513
53777
62514
53778
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62515
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53779
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62516
53780
/* { dg-final { cleanup-saved-temps } } */
62517
53781
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
62518
53782
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
62531
53795
}
62532
53796
62533
53797
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62534
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53798
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62535
53799
/* { dg-final { cleanup-saved-temps } } */
62536
53800
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
62537
53801
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
62550
53814
}
62551
53815
62552
53816
-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62553
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53817
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62554
53818
/* { dg-final { cleanup-saved-temps } } */
62555
53819
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
62556
53820
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
62569
53833
}
62570
53834
62571
53835
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62572
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53836
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62573
53837
/* { dg-final { cleanup-saved-temps } } */
62574
53838
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
62575
53839
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
62588
53852
}
62589
53853
62590
53854
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62591
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53855
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62592
53856
/* { dg-final { cleanup-saved-temps } } */
62593
53857
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
62594
53858
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
62607
53871
}
62608
53872
62609
53873
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62610
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53874
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62611
53875
/* { dg-final { cleanup-saved-temps } } */
62612
53876
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
62613
53877
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
62626
53890
}
62627
53891
62628
53892
-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62629
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53893
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62630
53894
/* { dg-final { cleanup-saved-temps } } */
62631
53895
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
62632
53896
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
62645
53909
}
62646
53910
62647
53911
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62648
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53912
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62649
53913
/* { dg-final { cleanup-saved-temps } } */
62650
53914
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
62651
53915
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
62664
53928
}
62665
53929
62666
53930
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62667
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53931
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62668
53932
/* { dg-final { cleanup-saved-temps } } */
62669
53933
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
62670
53934
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
62683
53947
}
62684
53948
62685
53949
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62686
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53950
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62687
53951
/* { dg-final { cleanup-saved-temps } } */
62688
53952
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
62689
53953
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
62702
53966
}
62703
53967
62704
53968
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62705
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53969
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62706
53970
/* { dg-final { cleanup-saved-temps } } */
62707
53971
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
62708
53972
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
62721
53985
}
62722
53986
62723
53987
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62724
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
53988
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62725
53989
/* { dg-final { cleanup-saved-temps } } */
62726
53990
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
62727
53991
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
62740
54004
}
62741
54005
62742
54006
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62743
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54007
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62744
54008
/* { dg-final { cleanup-saved-temps } } */
62745
54009
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
62746
54010
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
62759
54023
}
62760
54024
62761
54025
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62762
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54026
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62763
54027
/* { dg-final { cleanup-saved-temps } } */
62764
54028
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
62765
54029
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
62778
54042
}
62779
54043
62780
54044
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62781
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54045
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62782
54046
/* { dg-final { cleanup-saved-temps } } */
62783
54047
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
62784
54048
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
62797
54061
}
62798
54062
62799
54063
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62800
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54064
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62801
54065
/* { dg-final { cleanup-saved-temps } } */
62802
54066
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
62803
54067
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
62816
54080
}
62817
54081
62818
54082
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62819
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54083
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62820
54084
/* { dg-final { cleanup-saved-temps } } */
62821
54085
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
62822
54086
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
62835
54099
}
62836
54100
62837
54101
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62838
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54102
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62839
54103
/* { dg-final { cleanup-saved-temps } } */
62840
54104
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
62841
54105
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
62854
54118
}
62855
54119
62856
54120
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62857
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54121
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62858
54122
/* { dg-final { cleanup-saved-temps } } */
62859
54123
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
62860
54124
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
62873
54137
}
62874
54138
62875
54139
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62876
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54140
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62877
54141
/* { dg-final { cleanup-saved-temps } } */
62878
54142
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
62879
54143
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
62892
54156
}
62893
54157
62894
54158
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62895
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54159
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62896
54160
/* { dg-final { cleanup-saved-temps } } */
62897
54161
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
62898
54162
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
62911
54175
}
62912
54176
62913
54177
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62914
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54178
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62915
54179
/* { dg-final { cleanup-saved-temps } } */
62916
54180
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
62917
54181
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
62930
54194
}
62931
54195
62932
54196
-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62933
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54197
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62934
54198
/* { dg-final { cleanup-saved-temps } } */
62935
54199
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
62936
54200
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
62949
54213
}
62950
54214
62951
54215
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62952
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54216
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62953
54217
/* { dg-final { cleanup-saved-temps } } */
62954
54218
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
62955
54219
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
62968
54232
}
62969
54233
62970
54234
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62971
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54235
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62972
54236
/* { dg-final { cleanup-saved-temps } } */
62973
54237
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
62974
54238
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
62987
54251
}
62988
54252
62989
54253
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
62990
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54254
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
62991
54255
/* { dg-final { cleanup-saved-temps } } */
62992
54256
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
62993
54257
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
63006
54270
}
63007
54271
63008
54272
-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63009
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54273
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63010
54274
/* { dg-final { cleanup-saved-temps } } */
63011
54275
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
63012
54276
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
63025
54289
}
63026
54290
63027
54291
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63028
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54292
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63029
54293
/* { dg-final { cleanup-saved-temps } } */
63030
54294
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
63031
54295
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
63044
54308
}
63045
54309
63046
54310
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63047
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54311
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63048
54312
/* { dg-final { cleanup-saved-temps } } */
63049
54313
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
63050
54314
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
63063
54327
}
63064
54328
63065
54329
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63066
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54330
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63067
54331
/* { dg-final { cleanup-saved-temps } } */
63068
54332
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
63069
54333
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
63082
54346
}
63083
54347
63084
54348
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63085
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54349
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63086
54350
/* { dg-final { cleanup-saved-temps } } */
63087
54351
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
63088
54352
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
63101
54365
}
63102
54366
63103
54367
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63104
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54368
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63105
54369
/* { dg-final { cleanup-saved-temps } } */
63106
54370
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
63107
54371
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
63120
54384
}
63121
54385
63122
54386
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63123
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54387
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63124
54388
/* { dg-final { cleanup-saved-temps } } */
63125
54389
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
63126
54390
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
63139
54403
}
63140
54404
63141
54405
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63142
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54406
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63143
54407
/* { dg-final { cleanup-saved-temps } } */
63144
54408
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
63145
54409
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
63159
54423
63160
54424
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63161
54425
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63162
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
63163
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54426
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
54427
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63164
54428
/* { dg-final { cleanup-saved-temps } } */
63165
54429
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
63166
54430
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
63180
54444
63181
54445
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63182
54446
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63183
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
63184
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54447
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
54448
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63185
54449
/* { dg-final { cleanup-saved-temps } } */
63186
54450
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
63187
54451
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
63201
54465
63202
54466
-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63203
54467
-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63204
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
63205
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54468
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
54469
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63206
54470
/* { dg-final { cleanup-saved-temps } } */
63207
54471
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
63208
54472
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
63222
54486
63223
54487
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63224
54488
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63225
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
63226
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54489
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
54490
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63227
54491
/* { dg-final { cleanup-saved-temps } } */
63228
54492
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
63229
54493
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
63243
54507
63244
54508
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63245
54509
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63246
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
63247
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54510
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
54511
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63248
54512
/* { dg-final { cleanup-saved-temps } } */
63249
54513
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
63250
54514
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
63264
54528
63265
54529
-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63266
54530
-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63267
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
63268
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54531
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
54532
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63269
54533
/* { dg-final { cleanup-saved-temps } } */
63270
54534
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
63271
54535
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
63285
54549
63286
54550
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63287
54551
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63288
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
63289
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54552
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
54553
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63290
54554
/* { dg-final { cleanup-saved-temps } } */
63291
54555
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
63292
54556
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
63306
54570
63307
54571
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63308
54572
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63309
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
63310
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54573
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
54574
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63311
54575
/* { dg-final { cleanup-saved-temps } } */
63312
54576
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
63313
54577
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
63327
54591
63328
54592
-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63329
54593
-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63330
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
63331
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54594
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
54595
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63332
54596
/* { dg-final { cleanup-saved-temps } } */
63333
54597
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
63334
54598
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
63347
54611
}
63348
54612
63349
54613
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63350
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54614
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63351
54615
/* { dg-final { cleanup-saved-temps } } */
63352
54616
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
63353
54617
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
63366
54630
}
63367
54631
63368
54632
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63369
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54633
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63370
54634
/* { dg-final { cleanup-saved-temps } } */
63371
54635
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
63372
54636
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
63385
54649
}
63386
54650
63387
54651
-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63388
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54652
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63389
54653
/* { dg-final { cleanup-saved-temps } } */
63390
54654
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
63391
54655
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
63404
54668
}
63405
54669
63406
54670
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63407
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54671
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63408
54672
/* { dg-final { cleanup-saved-temps } } */
63409
54673
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
63410
54674
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
63423
54687
}
63424
54688
63425
54689
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63426
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54690
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63427
54691
/* { dg-final { cleanup-saved-temps } } */
63428
54692
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
63429
54693
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
63442
54706
}
63443
54707
63444
54708
-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63445
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54709
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63446
54710
/* { dg-final { cleanup-saved-temps } } */
63447
54711
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
63448
54712
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
63461
54725
}
63462
54726
63463
54727
-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63464
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54728
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63465
54729
/* { dg-final { cleanup-saved-temps } } */
63466
54730
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
63467
54731
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
63480
54744
}
63481
54745
63482
54746
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63483
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54747
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63484
54748
/* { dg-final { cleanup-saved-temps } } */
63485
54749
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
63486
54750
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
63499
54763
}
63500
54764
63501
54765
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63502
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54766
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63503
54767
/* { dg-final { cleanup-saved-temps } } */
63504
54768
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
63505
54769
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
63518
54782
}
63519
54783
63520
54784
-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63521
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54785
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63522
54786
/* { dg-final { cleanup-saved-temps } } */
63523
54787
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
63524
54788
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
63537
54801
}
63538
54802
63539
54803
-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63540
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54804
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63541
54805
/* { dg-final { cleanup-saved-temps } } */
63542
54806
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
63543
54807
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
63556
54820
}
63557
54821
63558
54822
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63559
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54823
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63560
54824
/* { dg-final { cleanup-saved-temps } } */
63561
54825
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
63562
54826
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
63575
54839
}
63576
54840
63577
54841
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63578
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54842
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63579
54843
/* { dg-final { cleanup-saved-temps } } */
63580
54844
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
63581
54845
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
63594
54858
}
63595
54859
63596
54860
-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63597
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54861
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63598
54862
/* { dg-final { cleanup-saved-temps } } */
63599
54863
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
63600
54864
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
63613
54877
}
63614
54878
63615
54879
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63616
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54880
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63617
54881
/* { dg-final { cleanup-saved-temps } } */
63618
54882
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
63619
54883
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
63632
54896
}
63633
54897
63634
54898
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63635
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54899
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63636
54900
/* { dg-final { cleanup-saved-temps } } */
63637
54901
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
63638
54902
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
63651
54915
}
63652
54916
63653
54917
-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63654
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54918
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63655
54919
/* { dg-final { cleanup-saved-temps } } */
63656
54920
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
63657
54921
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
63670
54934
}
63671
54935
63672
54936
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63673
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54937
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63674
54938
/* { dg-final { cleanup-saved-temps } } */
63675
54939
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
63676
54940
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
63689
54953
}
63690
54954
63691
54955
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63692
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54956
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63693
54957
/* { dg-final { cleanup-saved-temps } } */
63694
54958
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
63695
54959
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
63708
54972
}
63709
54973
63710
54974
-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63711
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54975
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63712
54976
/* { dg-final { cleanup-saved-temps } } */
63713
54977
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
63714
54978
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
63727
54991
}
63728
54992
63729
54993
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63730
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
54994
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63731
54995
/* { dg-final { cleanup-saved-temps } } */
63732
54996
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
63733
54997
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
63746
55010
}
63747
55011
63748
55012
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63749
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55013
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63750
55014
/* { dg-final { cleanup-saved-temps } } */
63751
55015
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
63752
55016
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
63765
55029
}
63766
55030
63767
55031
-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63768
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55032
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63769
55033
/* { dg-final { cleanup-saved-temps } } */
63770
55034
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
63771
55035
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
63784
55048
}
63785
55049
63786
55050
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63787
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55051
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63788
55052
/* { dg-final { cleanup-saved-temps } } */
63789
55053
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
63790
55054
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
63803
55067
}
63804
55068
63805
55069
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63806
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55070
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63807
55071
/* { dg-final { cleanup-saved-temps } } */
63808
55072
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
63809
55073
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
63822
55086
}
63823
55087
63824
55088
-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63825
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55089
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63826
55090
/* { dg-final { cleanup-saved-temps } } */
63827
55091
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
63828
55092
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
63841
55105
}
63842
55106
63843
55107
-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63844
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55108
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63845
55109
/* { dg-final { cleanup-saved-temps } } */
63846
55110
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
63847
55111
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
63860
55124
}
63861
55125
63862
55126
-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63863
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55127
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63864
55128
/* { dg-final { cleanup-saved-temps } } */
63865
55129
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
63866
55130
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
63879
55143
}
63880
55144
63881
55145
-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63882
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55146
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63883
55147
/* { dg-final { cleanup-saved-temps } } */
63884
55148
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
63885
55149
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
63898
55162
}
63899
55163
63900
55164
-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63901
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55165
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63902
55166
/* { dg-final { cleanup-saved-temps } } */
63903
55167
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
63904
55168
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
63917
55181
}
63918
55182
63919
55183
-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63920
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55184
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63921
55185
/* { dg-final { cleanup-saved-temps } } */
63922
55186
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
63923
55187
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
63936
55200
}
63937
55201
63938
55202
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63939
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55203
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63940
55204
/* { dg-final { cleanup-saved-temps } } */
63941
55205
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
63942
55206
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
63955
55219
}
63956
55220
63957
55221
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63958
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55222
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63959
55223
/* { dg-final { cleanup-saved-temps } } */
63960
55224
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
63961
55225
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
63974
55238
}
63975
55239
63976
55240
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63977
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55241
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63978
55242
/* { dg-final { cleanup-saved-temps } } */
63979
55243
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
63980
55244
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
63993
55257
}
63994
55258
63995
55259
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
63996
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55260
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
63997
55261
/* { dg-final { cleanup-saved-temps } } */
63998
55262
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
63999
55263
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
64012
55276
}
64013
55277
64014
55278
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64015
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55279
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64016
55280
/* { dg-final { cleanup-saved-temps } } */
64017
55281
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
64018
55282
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
64031
55295
}
64032
55296
64033
55297
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64034
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55298
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64035
55299
/* { dg-final { cleanup-saved-temps } } */
64036
55300
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
64037
55301
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
64051
55315
64052
55316
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64053
55317
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64054
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
64055
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55318
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
55319
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64056
55320
/* { dg-final { cleanup-saved-temps } } */
64057
55321
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
64058
55322
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
64072
55336
64073
55337
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64074
55338
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64075
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
64076
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55339
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
55340
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64077
55341
/* { dg-final { cleanup-saved-temps } } */
64078
55342
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
64079
55343
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
64093
55357
64094
55358
-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64095
55359
-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64096
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
64097
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55360
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
55361
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64098
55362
/* { dg-final { cleanup-saved-temps } } */
64099
55363
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
64100
55364
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
64114
55378
64115
55379
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64116
55380
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64117
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
64118
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55381
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
55382
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64119
55383
/* { dg-final { cleanup-saved-temps } } */
64120
55384
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
64121
55385
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
64135
55399
64136
55400
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64137
55401
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64138
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
64139
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55402
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
55403
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64140
55404
/* { dg-final { cleanup-saved-temps } } */
64141
55405
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
64142
55406
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
64156
55420
64157
55421
-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64158
55422
-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64159
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
64160
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55423
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
55424
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64161
55425
/* { dg-final { cleanup-saved-temps } } */
64162
55426
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
64163
55427
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
64177
55441
64178
55442
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64179
55443
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64180
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
64181
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55444
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
55445
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64182
55446
/* { dg-final { cleanup-saved-temps } } */
64183
55447
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
64184
55448
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
64198
55462
64199
55463
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64200
55464
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64201
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
64202
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55465
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
55466
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64203
55467
/* { dg-final { cleanup-saved-temps } } */
64204
55468
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
64205
55469
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
64219
55483
64220
55484
-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64221
55485
-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64222
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
64223
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55486
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
55487
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64224
55488
/* { dg-final { cleanup-saved-temps } } */
64225
55489
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
64226
55490
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
64239
55503
}
64240
55504
64241
55505
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64242
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55506
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64243
55507
/* { dg-final { cleanup-saved-temps } } */
64244
55508
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
64245
55509
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
64258
55522
}
64259
55523
64260
55524
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64261
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55525
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64262
55526
/* { dg-final { cleanup-saved-temps } } */
64263
55527
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
64264
55528
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
64277
55541
}
64278
55542
64279
55543
-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64280
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55544
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64281
55545
/* { dg-final { cleanup-saved-temps } } */
64282
55546
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
64283
55547
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
64296
55560
}
64297
55561
64298
55562
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64299
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55563
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64300
55564
/* { dg-final { cleanup-saved-temps } } */
64301
55565
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
64302
55566
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
64315
55579
}
64316
55580
64317
55581
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64318
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55582
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64319
55583
/* { dg-final { cleanup-saved-temps } } */
64320
55584
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
64321
55585
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
64334
55598
}
64335
55599
64336
55600
-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64337
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55601
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64338
55602
/* { dg-final { cleanup-saved-temps } } */
64339
55603
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
64340
55604
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
64353
55617
}
64354
55618
64355
55619
-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64356
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55620
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64357
55621
/* { dg-final { cleanup-saved-temps } } */
64358
55622
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
64359
55623
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
64372
55636
}
64373
55637
64374
55638
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64375
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55639
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64376
55640
/* { dg-final { cleanup-saved-temps } } */
64377
55641
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
64378
55642
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
64391
55655
}
64392
55656
64393
55657
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64394
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55658
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64395
55659
/* { dg-final { cleanup-saved-temps } } */
64396
55660
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
64397
55661
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
64410
55674
}
64411
55675
64412
55676
-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64413
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55677
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64414
55678
/* { dg-final { cleanup-saved-temps } } */
64415
55679
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
64416
55680
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
64429
55693
}
64430
55694
64431
55695
-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64432
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55696
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64433
55697
/* { dg-final { cleanup-saved-temps } } */
64434
55698
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
64435
55699
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
64448
55712
}
64449
55713
64450
55714
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64451
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55715
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64452
55716
/* { dg-final { cleanup-saved-temps } } */
64453
55717
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
64454
55718
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
64467
55731
}
64468
55732
64469
55733
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64470
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55734
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64471
55735
/* { dg-final { cleanup-saved-temps } } */
64472
55736
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
64473
55737
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
64486
55750
}
64487
55751
64488
55752
-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64489
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55753
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64490
55754
/* { dg-final { cleanup-saved-temps } } */
64491
55755
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
64492
55756
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
64505
55769
}
64506
55770
64507
55771
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64508
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55772
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64509
55773
/* { dg-final { cleanup-saved-temps } } */
64510
55774
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
64511
55775
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
64524
55788
}
64525
55789
64526
55790
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64527
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55791
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64528
55792
/* { dg-final { cleanup-saved-temps } } */
64529
55793
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
64530
55794
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
64543
55807
}
64544
55808
64545
55809
-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64546
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55810
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64547
55811
/* { dg-final { cleanup-saved-temps } } */
64548
55812
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
64549
55813
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
64562
55826
}
64563
55827
64564
55828
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64565
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55829
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64566
55830
/* { dg-final { cleanup-saved-temps } } */
64567
55831
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
64568
55832
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
64581
55845
}
64582
55846
64583
55847
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64584
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55848
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64585
55849
/* { dg-final { cleanup-saved-temps } } */
64586
55850
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
64587
55851
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
64600
55864
}
64601
55865
64602
55866
-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64603
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55867
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64604
55868
/* { dg-final { cleanup-saved-temps } } */
64605
55869
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
64606
55870
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
64619
55883
}
64620
55884
64621
55885
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64622
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55886
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64623
55887
/* { dg-final { cleanup-saved-temps } } */
64624
55888
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
64625
55889
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
64638
55902
}
64639
55903
64640
55904
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64641
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55905
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64642
55906
/* { dg-final { cleanup-saved-temps } } */
64643
55907
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
64644
55908
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
64657
55921
}
64658
55922
64659
55923
-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64660
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55924
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64661
55925
/* { dg-final { cleanup-saved-temps } } */
64662
55926
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
64663
55927
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
64676
55940
}
64677
55941
64678
55942
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64679
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55943
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64680
55944
/* { dg-final { cleanup-saved-temps } } */
64681
55945
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
64682
55946
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
64695
55959
}
64696
55960
64697
55961
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64698
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55962
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64699
55963
/* { dg-final { cleanup-saved-temps } } */
64700
55964
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
64701
55965
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
64714
55978
}
64715
55979
64716
55980
-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64717
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
55981
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64718
55982
/* { dg-final { cleanup-saved-temps } } */
64719
55983
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
64720
55984
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
64733
55997
}
64734
55998
64735
55999
-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64736
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
56000
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64737
56001
/* { dg-final { cleanup-saved-temps } } */
64738
56002
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
64739
56003
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
64752
56016
}
64753
56017
64754
56018
-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64755
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
56019
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64756
56020
/* { dg-final { cleanup-saved-temps } } */
64757
56021
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
64758
56022
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
64771
56035
}
64772
56036
64773
56037
-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64774
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
56038
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64775
56039
/* { dg-final { cleanup-saved-temps } } */
64776
56040
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
64777
56041
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
64790
56054
}
64791
56055
64792
56056
-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64793
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
56057
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64794
56058
/* { dg-final { cleanup-saved-temps } } */
64795
56059
--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
64796
56060
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
64809
56073
}
64810
56074
64811
56075
-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
64812
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
56076
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
64813
56077
/* { dg-final { cleanup-saved-temps } } */
64814
56078
--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c
64815
56079
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c
80057
71321
}
80058
71322
80059
71323
-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80060
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71324
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80061
71325
/* { dg-final { cleanup-saved-temps } } */
80062
71326
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
80063
71327
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
80076
71340
}
80077
71341
80078
71342
-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80079
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71343
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80080
71344
/* { dg-final { cleanup-saved-temps } } */
80081
71345
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
80082
71346
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
80095
71359
}
80096
71360
80097
71361
-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80098
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71362
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80099
71363
/* { dg-final { cleanup-saved-temps } } */
80100
71364
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
80101
71365
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
80114
71378
}
80115
71379
80116
71380
-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80117
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71381
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80118
71382
/* { dg-final { cleanup-saved-temps } } */
80119
71383
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
80120
71384
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
80133
71397
}
80134
71398
80135
71399
-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80136
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71400
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80137
71401
/* { dg-final { cleanup-saved-temps } } */
80138
71402
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
80139
71403
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
80152
71416
}
80153
71417
80154
71418
-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80155
+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71419
+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80156
71420
/* { dg-final { cleanup-saved-temps } } */
80157
71421
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
80158
71422
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
80171
71435
}
80172
71436
80173
71437
-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80174
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71438
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80175
71439
/* { dg-final { cleanup-saved-temps } } */
80176
71440
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
80177
71441
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
80190
71454
}
80191
71455
80192
71456
-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80193
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71457
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80194
71458
/* { dg-final { cleanup-saved-temps } } */
80195
71459
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
80196
71460
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
80209
71473
}
80210
71474
80211
71475
-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80212
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71476
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80213
71477
/* { dg-final { cleanup-saved-temps } } */
80214
71478
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
80215
71479
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
80228
71492
}
80229
71493
80230
71494
-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80231
+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71495
+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80232
71496
/* { dg-final { cleanup-saved-temps } } */
80233
71497
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
80234
71498
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
80247
71511
}
80248
71512
80249
71513
-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80250
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71514
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80251
71515
/* { dg-final { cleanup-saved-temps } } */
80252
71516
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
80253
71517
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
80266
71530
}
80267
71531
80268
71532
-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80269
+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71533
+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80270
71534
/* { dg-final { cleanup-saved-temps } } */
80271
71535
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
80272
71536
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
80285
71549
}
80286
71550
80287
71551
-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80288
+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71552
+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80289
71553
/* { dg-final { cleanup-saved-temps } } */
80290
71554
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
80291
71555
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
80304
71568
}
80305
71569
80306
71570
-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80307
+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71571
+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80308
71572
/* { dg-final { cleanup-saved-temps } } */
80309
71573
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
80310
71574
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
80323
71587
}
80324
71588
80325
71589
-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80326
+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71590
+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80327
71591
/* { dg-final { cleanup-saved-temps } } */
80328
71592
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
80329
71593
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
80342
71606
}
80343
71607
80344
71608
-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80345
+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71609
+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80346
71610
/* { dg-final { cleanup-saved-temps } } */
80347
71611
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
80348
71612
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
80361
71625
}
80362
71626
80363
71627
-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80364
+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71628
+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80365
71629
/* { dg-final { cleanup-saved-temps } } */
80366
71630
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
80367
71631
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
80380
71644
}
80381
71645
80382
71646
-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80383
+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71647
+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80384
71648
/* { dg-final { cleanup-saved-temps } } */
80385
71649
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
80386
71650
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
80399
71663
}
80400
71664
80401
71665
-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80402
+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71666
+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80403
71667
/* { dg-final { cleanup-saved-temps } } */
80404
71668
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
80405
71669
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
80418
71682
}
80419
71683
80420
71684
-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80421
+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71685
+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80422
71686
/* { dg-final { cleanup-saved-temps } } */
80423
71687
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
80424
71688
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
80437
71701
}
80438
71702
80439
71703
-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80440
+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71704
+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80441
71705
/* { dg-final { cleanup-saved-temps } } */
80442
71706
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
80443
71707
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
80456
71720
}
80457
71721
80458
71722
-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80459
+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71723
+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80460
71724
/* { dg-final { cleanup-saved-temps } } */
80461
71725
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
80462
71726
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
80475
71739
}
80476
71740
80477
71741
-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80478
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71742
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80479
71743
/* { dg-final { cleanup-saved-temps } } */
80480
71744
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
80481
71745
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
80494
71758
}
80495
71759
80496
71760
-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80497
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71761
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80498
71762
/* { dg-final { cleanup-saved-temps } } */
80499
71763
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
80500
71764
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
80513
71777
}
80514
71778
80515
71779
-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80516
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71780
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80517
71781
/* { dg-final { cleanup-saved-temps } } */
80518
71782
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
80519
71783
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
80532
71796
}
80533
71797
80534
71798
-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80535
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71799
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80536
71800
/* { dg-final { cleanup-saved-temps } } */
80537
71801
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
80538
71802
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
80551
71815
}
80552
71816
80553
71817
-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80554
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71818
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80555
71819
/* { dg-final { cleanup-saved-temps } } */
80556
71820
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
80557
71821
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
80570
71834
}
80571
71835
80572
71836
-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80573
+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71837
+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80574
71838
/* { dg-final { cleanup-saved-temps } } */
80575
71839
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
80576
71840
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
80589
71853
}
80590
71854
80591
71855
-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80592
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71856
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80593
71857
/* { dg-final { cleanup-saved-temps } } */
80594
71858
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
80595
71859
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
80608
71872
}
80609
71873
80610
71874
-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80611
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71875
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80612
71876
/* { dg-final { cleanup-saved-temps } } */
80613
71877
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
80614
71878
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
80627
71891
}
80628
71892
80629
71893
-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80630
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71894
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80631
71895
/* { dg-final { cleanup-saved-temps } } */
80632
71896
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
80633
71897
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
80646
71910
}
80647
71911
80648
71912
-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80649
+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71913
+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80650
71914
/* { dg-final { cleanup-saved-temps } } */
80651
71915
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
80652
71916
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
80665
71929
}
80666
71930
80667
71931
-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80668
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71932
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80669
71933
/* { dg-final { cleanup-saved-temps } } */
80670
71934
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
80671
71935
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
80684
71948
}
80685
71949
80686
71950
-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80687
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71951
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80688
71952
/* { dg-final { cleanup-saved-temps } } */
80689
71953
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
80690
71954
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
80703
71967
}
80704
71968
80705
71969
-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80706
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71970
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80707
71971
/* { dg-final { cleanup-saved-temps } } */
80708
71972
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
80709
71973
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
80722
71986
}
80723
71987
80724
71988
-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80725
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
71989
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80726
71990
/* { dg-final { cleanup-saved-temps } } */
80727
71991
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
80728
71992
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
80741
72005
}
80742
72006
80743
72007
-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80744
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72008
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80745
72009
/* { dg-final { cleanup-saved-temps } } */
80746
72010
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
80747
72011
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
80760
72024
}
80761
72025
80762
72026
-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80763
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72027
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80764
72028
/* { dg-final { cleanup-saved-temps } } */
80765
72029
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
80766
72030
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
80779
72043
}
80780
72044
80781
72045
-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80782
+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72046
+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80783
72047
/* { dg-final { cleanup-saved-temps } } */
80784
72048
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
80785
72049
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
80798
72062
}
80799
72063
80800
72064
-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80801
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72065
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80802
72066
/* { dg-final { cleanup-saved-temps } } */
80803
72067
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
80804
72068
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
80817
72081
}
80818
72082
80819
72083
-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80820
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72084
+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80821
72085
/* { dg-final { cleanup-saved-temps } } */
80822
72086
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
80823
72087
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
80836
72100
}
80837
72101
80838
72102
-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80839
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72103
+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80840
72104
/* { dg-final { cleanup-saved-temps } } */
80841
72105
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
80842
72106
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
80855
72119
}
80856
72120
80857
72121
-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80858
+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72122
+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80859
72123
/* { dg-final { cleanup-saved-temps } } */
80860
72124
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
80861
72125
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
80874
72138
}
80875
72139
80876
72140
-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80877
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72141
+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80878
72142
/* { dg-final { cleanup-saved-temps } } */
80879
72143
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
80880
72144
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
80893
72157
}
80894
72158
80895
72159
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80896
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72160
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80897
72161
/* { dg-final { cleanup-saved-temps } } */
80898
72162
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
80899
72163
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
80912
72176
}
80913
72177
80914
72178
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80915
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72179
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80916
72180
/* { dg-final { cleanup-saved-temps } } */
80917
72181
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
80918
72182
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
80931
72195
}
80932
72196
80933
72197
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80934
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72198
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80935
72199
/* { dg-final { cleanup-saved-temps } } */
80936
72200
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
80937
72201
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
80950
72214
}
80951
72215
80952
72216
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80953
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72217
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80954
72218
/* { dg-final { cleanup-saved-temps } } */
80955
72219
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
80956
72220
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
80969
72233
}
80970
72234
80971
72235
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80972
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72236
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80973
72237
/* { dg-final { cleanup-saved-temps } } */
80974
72238
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
80975
72239
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
80988
72252
}
80989
72253
80990
72254
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
80991
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72255
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
80992
72256
/* { dg-final { cleanup-saved-temps } } */
80993
72257
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
80994
72258
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
81008
72272
81009
72273
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81010
72274
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81011
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81012
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72275
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
72276
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81013
72277
/* { dg-final { cleanup-saved-temps } } */
81014
72278
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
81015
72279
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
81029
72293
81030
72294
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81031
72295
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81032
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81033
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72296
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
72297
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81034
72298
/* { dg-final { cleanup-saved-temps } } */
81035
72299
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
81036
72300
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
81050
72314
81051
72315
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81052
72316
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81053
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81054
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72317
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
72318
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81055
72319
/* { dg-final { cleanup-saved-temps } } */
81056
72320
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
81057
72321
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
81071
72335
81072
72336
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81073
72337
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81074
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81075
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72338
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
72339
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81076
72340
/* { dg-final { cleanup-saved-temps } } */
81077
72341
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
81078
72342
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
81092
72356
81093
72357
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81094
72358
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81095
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81096
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72359
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
72360
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81097
72361
/* { dg-final { cleanup-saved-temps } } */
81098
72362
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
81099
72363
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
81113
72377
81114
72378
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81115
72379
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81116
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81117
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72380
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
72381
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81118
72382
/* { dg-final { cleanup-saved-temps } } */
81119
72383
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
81120
72384
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
81134
72398
81135
72399
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81136
72400
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81137
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81138
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72401
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
72402
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81139
72403
/* { dg-final { cleanup-saved-temps } } */
81140
72404
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
81141
72405
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
81155
72419
81156
72420
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81157
72421
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81158
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81159
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72422
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
72423
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81160
72424
/* { dg-final { cleanup-saved-temps } } */
81161
72425
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
81162
72426
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
81176
72440
81177
72441
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81178
72442
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81179
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81180
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72443
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
72444
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81181
72445
/* { dg-final { cleanup-saved-temps } } */
81182
72446
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
81183
72447
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
81196
72460
}
81197
72461
81198
72462
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81199
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72463
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81200
72464
/* { dg-final { cleanup-saved-temps } } */
81201
72465
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
81202
72466
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
81215
72479
}
81216
72480
81217
72481
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81218
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72482
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81219
72483
/* { dg-final { cleanup-saved-temps } } */
81220
72484
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
81221
72485
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
81234
72498
}
81235
72499
81236
72500
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81237
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72501
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81238
72502
/* { dg-final { cleanup-saved-temps } } */
81239
72503
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
81240
72504
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
81253
72517
}
81254
72518
81255
72519
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81256
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72520
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81257
72521
/* { dg-final { cleanup-saved-temps } } */
81258
72522
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
81259
72523
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
81272
72536
}
81273
72537
81274
72538
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81275
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72539
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81276
72540
/* { dg-final { cleanup-saved-temps } } */
81277
72541
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
81278
72542
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
81291
72555
}
81292
72556
81293
72557
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81294
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72558
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81295
72559
/* { dg-final { cleanup-saved-temps } } */
81296
72560
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
81297
72561
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
81310
72574
}
81311
72575
81312
72576
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81313
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72577
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81314
72578
/* { dg-final { cleanup-saved-temps } } */
81315
72579
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
81316
72580
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
81329
72593
}
81330
72594
81331
72595
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81332
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72596
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81333
72597
/* { dg-final { cleanup-saved-temps } } */
81334
72598
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
81335
72599
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
81348
72612
}
81349
72613
81350
72614
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81351
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72615
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81352
72616
/* { dg-final { cleanup-saved-temps } } */
81353
72617
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
81354
72618
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
81367
72631
}
81368
72632
81369
72633
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81370
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72634
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81371
72635
/* { dg-final { cleanup-saved-temps } } */
81372
72636
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
81373
72637
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
81386
72650
}
81387
72651
81388
72652
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81389
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72653
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81390
72654
/* { dg-final { cleanup-saved-temps } } */
81391
72655
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
81392
72656
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
81405
72669
}
81406
72670
81407
72671
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81408
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72672
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81409
72673
/* { dg-final { cleanup-saved-temps } } */
81410
72674
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
81411
72675
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
81424
72688
}
81425
72689
81426
72690
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81427
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72691
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81428
72692
/* { dg-final { cleanup-saved-temps } } */
81429
72693
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
81430
72694
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
81443
72707
}
81444
72708
81445
72709
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81446
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72710
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81447
72711
/* { dg-final { cleanup-saved-temps } } */
81448
72712
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
81449
72713
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
81462
72726
}
81463
72727
81464
72728
-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81465
+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72729
+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81466
72730
/* { dg-final { cleanup-saved-temps } } */
81467
72731
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
81468
72732
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
81481
72745
}
81482
72746
81483
72747
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81484
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72748
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81485
72749
/* { dg-final { cleanup-saved-temps } } */
81486
72750
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
81487
72751
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
81500
72764
}
81501
72765
81502
72766
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81503
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72767
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81504
72768
/* { dg-final { cleanup-saved-temps } } */
81505
72769
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
81506
72770
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
81519
72783
}
81520
72784
81521
72785
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81522
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72786
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81523
72787
/* { dg-final { cleanup-saved-temps } } */
81524
72788
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
81525
72789
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
81538
72802
}
81539
72803
81540
72804
-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81541
+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72805
+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81542
72806
/* { dg-final { cleanup-saved-temps } } */
81543
72807
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
81544
72808
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
81557
72821
}
81558
72822
81559
72823
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81560
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72824
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81561
72825
/* { dg-final { cleanup-saved-temps } } */
81562
72826
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
81563
72827
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
81576
72840
}
81577
72841
81578
72842
-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81579
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72843
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81580
72844
/* { dg-final { cleanup-saved-temps } } */
81581
72845
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
81582
72846
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
81595
72859
}
81596
72860
81597
72861
-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81598
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72862
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81599
72863
/* { dg-final { cleanup-saved-temps } } */
81600
72864
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
81601
72865
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
81614
72878
}
81615
72879
81616
72880
-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81617
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72881
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81618
72882
/* { dg-final { cleanup-saved-temps } } */
81619
72883
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
81620
72884
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
81633
72897
}
81634
72898
81635
72899
-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81636
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72900
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81637
72901
/* { dg-final { cleanup-saved-temps } } */
81638
72902
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
81639
72903
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
81652
72916
}
81653
72917
81654
72918
-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81655
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72919
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81656
72920
/* { dg-final { cleanup-saved-temps } } */
81657
72921
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
81658
72922
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
81671
72935
}
81672
72936
81673
72937
-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81674
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72938
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81675
72939
/* { dg-final { cleanup-saved-temps } } */
81676
72940
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
81677
72941
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
81691
72955
81692
72956
-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81693
72957
-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81694
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81695
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72958
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
72959
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81696
72960
/* { dg-final { cleanup-saved-temps } } */
81697
72961
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
81698
72962
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
81712
72976
81713
72977
-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81714
72978
-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81715
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81716
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
72979
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
72980
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81717
72981
/* { dg-final { cleanup-saved-temps } } */
81718
72982
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
81719
72983
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
81733
72997
81734
72998
-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81735
72999
-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81736
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81737
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73000
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
73001
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81738
73002
/* { dg-final { cleanup-saved-temps } } */
81739
73003
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
81740
73004
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
81754
73018
81755
73019
-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81756
73020
-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81757
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81758
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73021
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
73022
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81759
73023
/* { dg-final { cleanup-saved-temps } } */
81760
73024
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
81761
73025
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
81775
73039
81776
73040
-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81777
73041
-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81778
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81779
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73042
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
73043
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81780
73044
/* { dg-final { cleanup-saved-temps } } */
81781
73045
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
81782
73046
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
81796
73060
81797
73061
-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81798
73062
-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81799
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81800
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73063
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
73064
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81801
73065
/* { dg-final { cleanup-saved-temps } } */
81802
73066
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
81803
73067
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
81817
73081
81818
73082
-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81819
73083
-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81820
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81821
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73084
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
73085
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81822
73086
/* { dg-final { cleanup-saved-temps } } */
81823
73087
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
81824
73088
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
81838
73102
81839
73103
-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81840
73104
-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81841
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81842
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73105
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
73106
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81843
73107
/* { dg-final { cleanup-saved-temps } } */
81844
73108
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
81845
73109
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
81859
73123
81860
73124
-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81861
73125
-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81862
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
81863
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73126
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
73127
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81864
73128
/* { dg-final { cleanup-saved-temps } } */
81865
73129
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
81866
73130
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
81879
73143
}
81880
73144
81881
73145
-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81882
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73146
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81883
73147
/* { dg-final { cleanup-saved-temps } } */
81884
73148
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
81885
73149
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
81898
73162
}
81899
73163
81900
73164
-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81901
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73165
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81902
73166
/* { dg-final { cleanup-saved-temps } } */
81903
73167
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
81904
73168
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
81917
73181
}
81918
73182
81919
73183
-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81920
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73184
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81921
73185
/* { dg-final { cleanup-saved-temps } } */
81922
73186
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
81923
73187
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
81936
73200
}
81937
73201
81938
73202
-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81939
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73203
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81940
73204
/* { dg-final { cleanup-saved-temps } } */
81941
73205
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
81942
73206
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
81955
73219
}
81956
73220
81957
73221
-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81958
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73222
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81959
73223
/* { dg-final { cleanup-saved-temps } } */
81960
73224
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
81961
73225
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
81974
73238
}
81975
73239
81976
73240
-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81977
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73241
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81978
73242
/* { dg-final { cleanup-saved-temps } } */
81979
73243
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
81980
73244
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
81993
73257
}
81994
73258
81995
73259
-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
81996
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73260
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
81997
73261
/* { dg-final { cleanup-saved-temps } } */
81998
73262
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
81999
73263
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
82012
73276
}
82013
73277
82014
73278
-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82015
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73279
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82016
73280
/* { dg-final { cleanup-saved-temps } } */
82017
73281
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
82018
73282
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
82031
73295
}
82032
73296
82033
73297
-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82034
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73298
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82035
73299
/* { dg-final { cleanup-saved-temps } } */
82036
73300
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
82037
73301
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
82050
73314
}
82051
73315
82052
73316
-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82053
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73317
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82054
73318
/* { dg-final { cleanup-saved-temps } } */
82055
73319
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
82056
73320
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
82069
73333
}
82070
73334
82071
73335
-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82072
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73336
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82073
73337
/* { dg-final { cleanup-saved-temps } } */
82074
73338
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
82075
73339
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
82088
73352
}
82089
73353
82090
73354
-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82091
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73355
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82092
73356
/* { dg-final { cleanup-saved-temps } } */
82093
73357
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
82094
73358
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
82107
73371
}
82108
73372
82109
73373
-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82110
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73374
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82111
73375
/* { dg-final { cleanup-saved-temps } } */
82112
73376
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
82113
73377
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
82126
73390
}
82127
73391
82128
73392
-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82129
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73393
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82130
73394
/* { dg-final { cleanup-saved-temps } } */
82131
73395
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
82132
73396
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
82145
73409
}
82146
73410
82147
73411
-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82148
+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73412
+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82149
73413
/* { dg-final { cleanup-saved-temps } } */
82150
73414
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
82151
73415
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
82164
73428
}
82165
73429
82166
73430
-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82167
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73431
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82168
73432
/* { dg-final { cleanup-saved-temps } } */
82169
73433
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
82170
73434
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
82183
73447
}
82184
73448
82185
73449
-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82186
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73450
+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82187
73451
/* { dg-final { cleanup-saved-temps } } */
82188
73452
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
82189
73453
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
82202
73466
}
82203
73467
82204
73468
-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82205
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73469
+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82206
73470
/* { dg-final { cleanup-saved-temps } } */
82207
73471
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
82208
73472
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
82221
73485
}
82222
73486
82223
73487
-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82224
+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73488
+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82225
73489
/* { dg-final { cleanup-saved-temps } } */
82226
73490
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
82227
73491
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
82240
73504
}
82241
73505
82242
73506
-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82243
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73507
+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82244
73508
/* { dg-final { cleanup-saved-temps } } */
82245
73509
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
82246
73510
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
82259
73523
}
82260
73524
82261
73525
-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82262
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73526
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82263
73527
/* { dg-final { cleanup-saved-temps } } */
82264
73528
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
82265
73529
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
82278
73542
}
82279
73543
82280
73544
-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82281
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73545
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82282
73546
/* { dg-final { cleanup-saved-temps } } */
82283
73547
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
82284
73548
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
82297
73561
}
82298
73562
82299
73563
-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82300
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73564
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82301
73565
/* { dg-final { cleanup-saved-temps } } */
82302
73566
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
82303
73567
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
82316
73580
}
82317
73581
82318
73582
-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82319
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73583
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82320
73584
/* { dg-final { cleanup-saved-temps } } */
82321
73585
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
82322
73586
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
82335
73599
}
82336
73600
82337
73601
-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82338
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73602
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82339
73603
/* { dg-final { cleanup-saved-temps } } */
82340
73604
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
82341
73605
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
82354
73618
}
82355
73619
82356
73620
-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82357
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73621
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82358
73622
/* { dg-final { cleanup-saved-temps } } */
82359
73623
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
82360
73624
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
82374
73638
82375
73639
-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82376
73640
-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82377
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
82378
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73641
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
73642
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82379
73643
/* { dg-final { cleanup-saved-temps } } */
82380
73644
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
82381
73645
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
82395
73659
82396
73660
-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82397
73661
-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82398
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
82399
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73662
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
73663
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82400
73664
/* { dg-final { cleanup-saved-temps } } */
82401
73665
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
82402
73666
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
82416
73680
82417
73681
-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82418
73682
-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82419
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
82420
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73683
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
73684
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82421
73685
/* { dg-final { cleanup-saved-temps } } */
82422
73686
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
82423
73687
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
82437
73701
82438
73702
-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82439
73703
-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82440
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
82441
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73704
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
73705
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82442
73706
/* { dg-final { cleanup-saved-temps } } */
82443
73707
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
82444
73708
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
82458
73722
82459
73723
-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82460
73724
-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82461
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
82462
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73725
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
73726
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82463
73727
/* { dg-final { cleanup-saved-temps } } */
82464
73728
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
82465
73729
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
82479
73743
82480
73744
-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82481
73745
-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82482
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
82483
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73746
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
73747
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82484
73748
/* { dg-final { cleanup-saved-temps } } */
82485
73749
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
82486
73750
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
82500
73764
82501
73765
-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82502
73766
-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82503
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
82504
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73767
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
73768
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82505
73769
/* { dg-final { cleanup-saved-temps } } */
82506
73770
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
82507
73771
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
82521
73785
82522
73786
-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82523
73787
-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82524
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
82525
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73788
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
73789
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82526
73790
/* { dg-final { cleanup-saved-temps } } */
82527
73791
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
82528
73792
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
82542
73806
82543
73807
-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82544
73808
-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82545
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
82546
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73809
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
73810
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82547
73811
/* { dg-final { cleanup-saved-temps } } */
82548
73812
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
82549
73813
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
82562
73826
}
82563
73827
82564
73828
-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82565
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73829
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82566
73830
/* { dg-final { cleanup-saved-temps } } */
82567
73831
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
82568
73832
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
82581
73845
}
82582
73846
82583
73847
-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82584
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73848
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82585
73849
/* { dg-final { cleanup-saved-temps } } */
82586
73850
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
82587
73851
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
82600
73864
}
82601
73865
82602
73866
-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82603
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73867
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82604
73868
/* { dg-final { cleanup-saved-temps } } */
82605
73869
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
82606
73870
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
82619
73883
}
82620
73884
82621
73885
-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82622
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73886
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82623
73887
/* { dg-final { cleanup-saved-temps } } */
82624
73888
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
82625
73889
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
82638
73902
}
82639
73903
82640
73904
-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82641
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73905
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82642
73906
/* { dg-final { cleanup-saved-temps } } */
82643
73907
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
82644
73908
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
82657
73921
}
82658
73922
82659
73923
-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82660
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73924
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82661
73925
/* { dg-final { cleanup-saved-temps } } */
82662
73926
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
82663
73927
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
82676
73940
}
82677
73941
82678
73942
-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82679
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73943
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82680
73944
/* { dg-final { cleanup-saved-temps } } */
82681
73945
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
82682
73946
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
82695
73959
}
82696
73960
82697
73961
-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82698
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73962
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82699
73963
/* { dg-final { cleanup-saved-temps } } */
82700
73964
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
82701
73965
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
82714
73978
}
82715
73979
82716
73980
-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82717
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
73981
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82718
73982
/* { dg-final { cleanup-saved-temps } } */
82719
73983
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
82720
73984
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
82733
73997
}
82734
73998
82735
73999
-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82736
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
74000
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82737
74001
/* { dg-final { cleanup-saved-temps } } */
82738
74002
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
82739
74003
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
82752
74016
}
82753
74017
82754
74018
-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82755
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
74019
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82756
74020
/* { dg-final { cleanup-saved-temps } } */
82757
74021
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
82758
74022
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
82771
74035
}
82772
74036
82773
74037
-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82774
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
74038
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82775
74039
/* { dg-final { cleanup-saved-temps } } */
82776
74040
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
82777
74041
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
82790
74054
}
82791
74055
82792
74056
-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82793
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
74057
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82794
74058
/* { dg-final { cleanup-saved-temps } } */
82795
74059
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
82796
74060
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
82809
74073
}
82810
74074
82811
74075
-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82812
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
74076
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82813
74077
/* { dg-final { cleanup-saved-temps } } */
82814
74078
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
82815
74079
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
82828
74092
}
82829
74093
82830
74094
-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82831
+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
74095
+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82832
74096
/* { dg-final { cleanup-saved-temps } } */
82833
74097
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
82834
74098
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
82847
74111
}
82848
74112
82849
74113
-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82850
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
74114
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82851
74115
/* { dg-final { cleanup-saved-temps } } */
82852
74116
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
82853
74117
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
82866
74130
}
82867
74131
82868
74132
-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82869
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
74133
+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82870
74134
/* { dg-final { cleanup-saved-temps } } */
82871
74135
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
82872
74136
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
82885
74149
}
82886
74150
82887
74151
-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82888
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
74152
+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82889
74153
/* { dg-final { cleanup-saved-temps } } */
82890
74154
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
82891
74155
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
82904
74168
}
82905
74169
82906
74170
-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82907
+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
74171
+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82908
74172
/* { dg-final { cleanup-saved-temps } } */
82909
74173
--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
82910
74174
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
82923
74187
}
82924
74188
82925
74189
-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
82926
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */
74190
+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */
82927
74191
/* { dg-final { cleanup-saved-temps } } */
82928
74192
--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c
82929
74193
+++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c
86169
77433
+ abort();
86170
77434
+ return 0;
86171
77435
+}
86172
--- a/src/gcc/testsuite/gcc.target/arm/neon-vld-1.c
86173
+++ b/src/gcc/testsuite/gcc.target/arm/neon-vld-1.c
86174
@@ -0,0 +1,13 @@
86175
+/* { dg-do compile } */
86176
+/* { dg-require-effective-target arm_neon_ok } */
86177
+/* { dg-options "-O1" } */
77436
--- a/src/gcc/testsuite/gcc.target/arm/neon-vld3-1.c
77437
+++ b/src/gcc/testsuite/gcc.target/arm/neon-vld3-1.c
77438
@@ -0,0 +1,27 @@
77439
+/* { dg-do run } */
77440
+/* { dg-require-effective-target arm_neon_hw } */
77441
+/* { dg-options "-O2" } */
86178
77442
+/* { dg-add-options arm_neon } */
86179
77443
+
86180
+#include <arm_neon.h>
86181
+
86182
+uint8x16_t
86183
+foo (uint8_t *a, uint8x16_t b)
86184
+{
86185
+ vst1q_lane_u8 (a, b, 14);
86186
+ return vld1q_lane_u8 (a + 0x100, b, 15);
77444
+#include "arm_neon.h"
77445
+
77446
+uint32_t buffer[12];
77447
+
77448
+void __attribute__((noinline))
77449
+foo (uint32_t *a)
77450
+{
77451
+ uint32x4x3_t x;
77452
+
77453
+ x = vld3q_u32 (a);
77454
+ x.val[0] = vaddq_u32 (x.val[0], x.val[1]);
77455
+ vst3q_u32 (a, x);
77456
+}
77457
+
77458
+int
77459
+main (void)
77460
+{
77461
+ buffer[0] = 1;
77462
+ buffer[1] = 2;
77463
+ foo (buffer);
77464
+ return buffer[0] != 3;
86187
77465
+}
86188
77466
--- a/src/gcc/testsuite/gcc.target/arm/neon-vmla-1.c
86189
77467
+++ b/src/gcc/testsuite/gcc.target/arm/neon-vmla-1.c
86446
77724
+ abort();
86447
77725
+ return 0;
86448
77726
+}
77727
--- a/src/gcc/testsuite/gcc.target/arm/neon-vst3-1.c
77728
+++ b/src/gcc/testsuite/gcc.target/arm/neon-vst3-1.c
77729
@@ -0,0 +1,25 @@
77730
+/* { dg-do run } */
77731
+/* { dg-require-effective-target arm_neon_hw } */
77732
+/* { dg-options "-O2" } */
77733
+/* { dg-add-options arm_neon } */
77734
+
77735
+#include "arm_neon.h"
77736
+
77737
+uint32_t buffer[64];
77738
+
77739
+void __attribute__((noinline))
77740
+foo (uint32_t *a)
77741
+{
77742
+ uint32x4x3_t x;
77743
+
77744
+ x = vld3q_u32 (a);
77745
+ a[35] = 1;
77746
+ vst3q_lane_u32 (a + 32, x, 1);
77747
+}
77748
+
77749
+int
77750
+main (void)
77751
+{
77752
+ foo (buffer);
77753
+ return buffer[35] != 1;
77754
+}
86449
77755
--- a/src/gcc/testsuite/gcc.target/arm/neon-vsubs64.c
86450
77756
+++ b/src/gcc/testsuite/gcc.target/arm/neon-vsubs64.c
86451
77757
@@ -0,0 +1,21 @@
86794
78100
+
86795
78101
+ return 0;
86796
78102
+}
86797
--- a/src/gcc/testsuite/gcc.target/arm/pr45447.c
86798
+++ b/src/gcc/testsuite/gcc.target/arm/pr45447.c
86799
@@ -0,0 +1,3 @@
86800
+/* { dg-do compile } */
86801
+/* { dg-options "-g -femit-struct-debug-baseonly" } */
86802
+typedef __builtin_va_list x;
86803
78103
--- a/src/gcc/testsuite/gcc.target/arm/pr46883.c
86804
78104
+++ b/src/gcc/testsuite/gcc.target/arm/pr46883.c
86805
78105
@@ -0,0 +1,16 @@
86848
78148
+
86849
78149
+ return (dwCalcVal.u_32_value);
86850
78150
+}
78151
--- a/src/gcc/testsuite/gcc.target/arm/pr48252.c
78152
+++ b/src/gcc/testsuite/gcc.target/arm/pr48252.c
78153
@@ -0,0 +1,31 @@
78154
+/* { dg-do run } */
78155
+/* { dg-require-effective-target arm_neon_hw } */
78156
+/* { dg-options "-O2" } */
78157
+/* { dg-add-options arm_neon } */
78158
+
78159
+#include "arm_neon.h"
78160
+#include <stdlib.h>
78161
+
78162
+int main(void)
78163
+{
78164
+ uint8x8_t v1 = {1, 1, 1, 1, 1, 1, 1, 1};
78165
+ uint8x8_t v2 = {2, 2, 2, 2, 2, 2, 2, 2};
78166
+ uint8x8x2_t vd1, vd2;
78167
+ union {uint8x8_t v; uint8_t buf[8];} d1, d2, d3, d4;
78168
+ int i;
78169
+
78170
+ vd1 = vzip_u8(v1, vdup_n_u8(0));
78171
+ vd2 = vzip_u8(v2, vdup_n_u8(0));
78172
+
78173
+ vst1_u8(d1.buf, vd1.val[0]);
78174
+ vst1_u8(d2.buf, vd1.val[1]);
78175
+ vst1_u8(d3.buf, vd2.val[0]);
78176
+ vst1_u8(d4.buf, vd2.val[1]);
78177
+
78178
+ for (i = 0; i < 8; i++)
78179
+ if ((i % 2 == 0 && d4.buf[i] != 2)
78180
+ || (i % 2 == 1 && d4.buf[i] != 0))
78181
+ abort ();
78182
+
78183
+ return 0;
78184
+}
86851
78185
--- a/src/gcc/testsuite/gcc.target/arm/sync-1.c
86852
78186
+++ b/src/gcc/testsuite/gcc.target/arm/sync-1.c
86853
78187
@@ -0,0 +1,25 @@
86939
78273
+}
86940
78274
+
86941
78275
+/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp," } } */
78276
--- a/src/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c
78277
+++ b/src/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c
78278
@@ -0,0 +1,9 @@
78279
+/* { dg-do compile } */
78280
+/* { dg-options "-O2 -march=armv6" } */
78281
+
78282
+unsigned char foo (unsigned char c)
78283
+{
78284
+ return (c >= '0') && (c <= '9');
78285
+}
78286
+
78287
+/* { dg-final { scan-assembler-not "uxtb" } } */
86942
78288
--- a/src/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c
86943
78289
+++ b/src/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c
86944
78290
@@ -0,0 +1,15 @@
87211
78557
+}
87212
78558
+
87213
78559
+/* { dg-final { scan-assembler-times "smulbb" 1 } } */
78560
--- a/src/gcc/testsuite/gcc.target/arm/xor-and.c
78561
+++ b/src/gcc/testsuite/gcc.target/arm/xor-and.c
78562
@@ -0,0 +1,14 @@
78563
+/* { dg-do compile } */
78564
+/* { dg-options "-O -march=armv6" } */
78565
+
78566
+unsigned short foo (unsigned short x)
78567
+{
78568
+ x ^= 0x4002;
78569
+ x >>= 1;
78570
+ x |= 0x8000;
78571
+ return x;
78572
+}
78573
+
78574
+/* { dg-final { scan-assembler "orr" } } */
78575
+/* { dg-final { scan-assembler-not "mvn" } } */
78576
+/* { dg-final { scan-assembler-not "uxth" } } */
87214
78577
--- a/src/gcc/testsuite/gcc.target/bfin/wmul-1.c
87215
78578
+++ b/src/gcc/testsuite/gcc.target/bfin/wmul-1.c
87216
78579
@@ -0,0 +1,18 @@
87247
78610
+}
87248
78611
+
87249
78612
+/* { dg-final { scan-assembler-times "\\(IS\\)" 1 } } */
87250
--- a/src/gcc/testsuite/gcc.target/i386/avx-check.h
87251
+++ b/src/gcc/testsuite/gcc.target/i386/avx-check.h
87252
@@ -20,7 +20,7 @@
87253
return 0;
87254
87255
/* Run AVX test only if host has AVX support. */
87256
- if (ecx & bit_AVX)
87257
+ if ((ecx & (bit_AVX | bit_OSXSAVE)) == (bit_AVX | bit_OSXSAVE))
87258
{
87259
do_test ();
87260
#ifdef DEBUG
87261
--- a/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-1.c
87262
+++ b/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-1.c
87263
@@ -0,0 +1,31 @@
87264
+/* { dg-do run } */
87265
+/* { dg-require-effective-target avx } */
87266
+/* { dg-options "-O2 -mavx" } */
87267
+
87268
+#include "avx-check.h"
87269
+
87270
+#ifndef MASK
87271
+#define MASK 7
87272
+#endif
87273
+
87274
+#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63)
87275
+
87276
+void static
87277
+avx_test (void)
87278
+{
87279
+ int i;
87280
+ long long m[2] = {mask_v(0), mask_v(1)};
87281
+ double s[2] = {1.1, 2.2};
87282
+ union128d u;
87283
+ union128i_q mask;
87284
+ double e[2] = {0.0};
87285
+
87286
+ mask.x = _mm_loadu_si128 ((__m128i *)m);
87287
+ u.x = _mm_maskload_pd (s, mask.x);
87288
+
87289
+ for (i = 0 ; i < 2; i++)
87290
+ e[i] = m[i] ? s[i] : 0;
87291
+
87292
+ if (check_union128d (u, e))
87293
+ abort ();
87294
+}
87295
--- a/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-2.c
87296
+++ b/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-2.c
87297
@@ -0,0 +1,33 @@
87298
+/* { dg-do run } */
87299
+/* { dg-require-effective-target avx } */
87300
+/* { dg-options "-O2 -mavx" } */
87301
+
87302
+#include "avx-check.h"
87303
+
87304
+#ifndef MASK
87305
+#define MASK 6
87306
+#endif
87307
+
87308
+#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63)
87309
+
87310
+void static
87311
+avx_test (void)
87312
+{
87313
+ int i;
87314
+ long long m[2] = {mask_v(0), mask_v(1)};
87315
+ double s[2] = {1.1, 2.2};
87316
+ double e[2] = {0.0};
87317
+ double d[2] = {0.0};
87318
+ union128d src;
87319
+ union128i_q mask;
87320
+
87321
+ src.x = _mm_loadu_pd (s);
87322
+ mask.x = _mm_loadu_si128 ((__m128i *)m);
87323
+ _mm_maskstore_pd (d, mask.x, src.x);
87324
+
87325
+ for (i = 0 ; i < 2; i++)
87326
+ e[i] = m[i] ? s[i] : 0;
87327
+
87328
+ if (checkVd (d, e, 2))
87329
+ abort ();
87330
+}
87331
--- a/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-1.c
87332
+++ b/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-1.c
87333
@@ -14,12 +14,13 @@
87334
avx_test (void)
87335
{
87336
int i;
87337
- long long m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
87338
+ long long m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
87339
double s[4] = {1.1, 2.2, 3.3, 4.4};
87340
- union256d u, mask;
87341
+ union256d u;
87342
+ union256i_q mask;
87343
double e [4] = {0.0};
87344
87345
- mask.x = _mm256_loadu_pd ((double*)m);
87346
+ mask.x = _mm256_loadu_si256 ((__m256i *)m);
87347
u.x = _mm256_maskload_pd (s, mask.x);
87348
87349
for (i = 0 ; i < 4; i++)
87350
--- a/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-2.c
87351
+++ b/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-2.c
87352
@@ -18,10 +18,11 @@
87353
double s[4] = {1.1, 2.2, 3.3, 4.4};
87354
double e [4] = {0.0};
87355
double d [4] = {0.0};
87356
- union256d src, mask;
87357
+ union256d src;
87358
+ union256i_q mask;
87359
87360
src.x = _mm256_loadu_pd (s);
87361
- mask.x = _mm256_loadu_pd ((double*)m);
87362
+ mask.x = _mm256_loadu_si256 ((__m256i *)m);
87363
_mm256_maskstore_pd (d, mask.x, src.x);
87364
87365
for (i = 0 ; i < 4; i++)
87366
--- a/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-1.c
87367
+++ b/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-1.c
87368
@@ -0,0 +1,31 @@
87369
+/* { dg-do run } */
87370
+/* { dg-require-effective-target avx } */
87371
+/* { dg-options "-O2 -mavx" } */
87372
+
87373
+#include "avx-check.h"
87374
+
87375
+#ifndef MASK
87376
+#define MASK 134
87377
+#endif
87378
+
87379
+#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31)
87380
+
87381
+void static
87382
+avx_test (void)
87383
+{
87384
+ int i;
87385
+ int m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
87386
+ float s[4] = {1,2,3,4};
87387
+ union128 u;
87388
+ union128i_d mask;
87389
+ float e[4] = {0.0};
87390
+
87391
+ mask.x = _mm_loadu_si128 ((__m128i *)m);
87392
+ u.x = _mm_maskload_ps (s, mask.x);
87393
+
87394
+ for (i = 0 ; i < 4; i++)
87395
+ e[i] = m[i] ? s[i] : 0;
87396
+
87397
+ if (check_union128 (u, e))
87398
+ abort ();
87399
+}
87400
--- a/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-2.c
87401
+++ b/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-2.c
87402
@@ -0,0 +1,33 @@
87403
+/* { dg-do run } */
87404
+/* { dg-require-effective-target avx } */
87405
+/* { dg-options "-O2 -mavx" } */
87406
+
87407
+#include "avx-check.h"
87408
+
87409
+#ifndef MASK
87410
+#define MASK 214
87411
+#endif
87412
+
87413
+#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31)
87414
+
87415
+void static
87416
+avx_test (void)
87417
+{
87418
+ int i;
87419
+ int m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
87420
+ float s[4] = {1,2,3,4};
87421
+ union128 src;
87422
+ union128i_d mask;
87423
+ float e[4] = {0.0};
87424
+ float d[4] = {0.0};
87425
+
87426
+ src.x = _mm_loadu_ps (s);
87427
+ mask.x = _mm_loadu_si128 ((__m128i *)m);
87428
+ _mm_maskstore_ps (d, mask.x, src.x);
87429
+
87430
+ for (i = 0 ; i < 4; i++)
87431
+ e[i] = m[i] ? s[i] : 0;
87432
+
87433
+ if (checkVf (d, e, 4))
87434
+ abort ();
87435
+}
87436
--- a/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-1.c
87437
+++ b/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-1.c
87438
@@ -16,10 +16,11 @@
87439
int i;
87440
int m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3), mask_v(4), mask_v(5), mask_v(6), mask_v(7)};
87441
float s[8] = {1,2,3,4,5,6,7,8};
87442
- union256 u, mask;
87443
+ union256 u;
87444
+ union256i_d mask;
87445
float e [8] = {0.0};
87446
87447
- mask.x = _mm256_loadu_ps ((float*)m);
87448
+ mask.x = _mm256_loadu_si256 ((__m256i *)m);
87449
u.x = _mm256_maskload_ps (s, mask.x);
87450
87451
for (i = 0 ; i < 8; i++)
87452
--- a/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-2.c
87453
+++ b/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-2.c
87454
@@ -16,12 +16,13 @@
87455
int i;
87456
int m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3), mask_v(4), mask_v(5), mask_v(6), mask_v(7)};
87457
float s[8] = {1,2,3,4,5,6,7,8};
87458
- union256 src, mask;
87459
+ union256 src;
87460
+ union256i_d mask;
87461
float e [8] = {0.0};
87462
float d [8] = {0.0};
87463
87464
src.x = _mm256_loadu_ps (s);
87465
- mask.x = _mm256_loadu_ps ((float *)m);
87466
+ mask.x = _mm256_loadu_si256 ((__m256i *)m);
87467
_mm256_maskstore_ps (d, mask.x, src.x);
87468
87469
for (i = 0 ; i < 8; i++)
87470
78613
--- a/src/gcc/testsuite/gcc.target/i386/pr41442.c
87471
78614
+++ b/src/gcc/testsuite/gcc.target/i386/pr41442.c
87472
78615
@@ -0,0 +1,18 @@
87488
78631
+}
87489
78632
+
87490
78633
+/* { dg-final { scan-assembler-times "test|cmp" 2 } } */
87491
--- a/src/gcc/testsuite/gcc.target/i386/pr43653.c
87492
+++ b/src/gcc/testsuite/gcc.target/i386/pr43653.c
87493
@@ -0,0 +1,14 @@
87494
+/* { dg-do compile } */
87495
+/* { dg-options "-O1 -ftree-vectorize -msse" } */
87496
+
87497
+typedef struct {} S;
87498
+
87499
+void *foo()
87500
+{
87501
+ S a[64], *p[64];
87502
+ int i;
87503
+
87504
+ for (i = 0; i < 64; i++)
87505
+ p[i] = &a[i];
87506
+ return p[0];
87507
+}
87508
--- a/src/gcc/testsuite/gcc.target/i386/pr45852.c
87509
+++ b/src/gcc/testsuite/gcc.target/i386/pr45852.c
87510
@@ -0,0 +1,16 @@
87511
+/* PR middle-end/45852 */
87512
+/* { dg-options "-O2 -mcmodel=small" } */
87513
+/* { dg-do compile { target { { i?86-*-linux* x86_64-*-linux* } && lp64 } } } */
87514
+/* { dg-require-visibility "" } */
87515
+
87516
+struct S { int s; };
87517
+
87518
+volatile struct S globvar __attribute__((visibility ("hidden"))) = { -6 };
87519
+
87520
+void
87521
+foo (void)
87522
+{
87523
+ globvar = globvar;
87524
+}
87525
+
87526
+/* { dg-final { scan-assembler-times "globvar.%?rip" 2 } } */
87527
--- a/src/gcc/testsuite/gcc.target/i386/pr46865-1.c
87528
+++ b/src/gcc/testsuite/gcc.target/i386/pr46865-1.c
87529
@@ -0,0 +1,31 @@
87530
+/* PR rtl-optimization/46865 */
87531
+/* { dg-do compile } */
87532
+/* { dg-options "-O2" } */
87533
+
87534
+extern unsigned long f;
87535
+
87536
+#define m1(f) \
87537
+ if (f & 1) \
87538
+ asm volatile ("nop /* asmnop */\n"); \
87539
+ else \
87540
+ asm volatile ("nop /* asmnop */\n");
87541
+
87542
+#define m2(f) \
87543
+ if (f & 1) \
87544
+ asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx"); \
87545
+ else \
87546
+ asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx");
87547
+
87548
+void
87549
+foo (void)
87550
+{
87551
+ m1 (f);
87552
+}
87553
+
87554
+void
87555
+bar (void)
87556
+{
87557
+ m2 (f);
87558
+}
87559
+
87560
+/* { dg-final { scan-assembler-times "asmnop" 2 } } */
87561
--- a/src/gcc/testsuite/gcc.target/i386/pr46865-2.c
87562
+++ b/src/gcc/testsuite/gcc.target/i386/pr46865-2.c
87563
@@ -0,0 +1,32 @@
87564
+/* PR rtl-optimization/46865 */
87565
+/* { dg-do compile } */
87566
+/* { dg-options "-O2 -save-temps" } */
87567
+
87568
+extern unsigned long f;
87569
+
87570
+#define m1(f) \
87571
+ if (f & 1) \
87572
+ asm volatile ("nop /* asmnop */\n"); \
87573
+ else \
87574
+ asm volatile ("nop /* asmnop */\n");
87575
+
87576
+#define m2(f) \
87577
+ if (f & 1) \
87578
+ asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx"); \
87579
+ else \
87580
+ asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx");
87581
+
87582
+void
87583
+foo (void)
87584
+{
87585
+ m1 (f);
87586
+}
87587
+
87588
+void
87589
+bar (void)
87590
+{
87591
+ m2 (f);
87592
+}
87593
+
87594
+/* { dg-final { scan-assembler-times "asmnop" 2 } } */
87595
+/* { dg-final { cleanup-saved-temps } } */
87596
--- a/src/gcc/testsuite/gcc.target/i386/pr46880.c
87597
+++ b/src/gcc/testsuite/gcc.target/i386/pr46880.c
87598
@@ -0,0 +1,28 @@
87599
+/* PR target/46880 */
87600
+/* { dg-do run } */
87601
+/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */
87602
+/* { dg-require-effective-target sse2_runtime } */
87603
+
87604
+typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__));
87605
+typedef double (*T)[2];
87606
+
87607
+static __attribute__ ((noinline, noclone)) __m128d
87608
+foo (__m128d c, __m128d d)
87609
+{
87610
+ T cp = (T) &c;
87611
+ T dp = (T) &d;
87612
+ __m128d e = { (*cp)[1], (*dp)[1] };
87613
+ return e;
87614
+}
87615
+
87616
+int
87617
+main ()
87618
+{
87619
+ __m128d c = { 1.0, 2.0 };
87620
+ __m128d d = { 3.0, 4.0 };
87621
+ union { __m128d x; double d[2]; } u;
87622
+ u.x = foo (c, d);
87623
+ if (u.d[0] != 2.0 || u.d[1] != 4.0)
87624
+ __builtin_abort ();
87625
+ return 0;
78634
--- a/src/gcc/testsuite/gcc.target/i386/pr48708.c
78635
+++ b/src/gcc/testsuite/gcc.target/i386/pr48708.c
78636
@@ -0,0 +1,15 @@
78637
+/* { dg-do compile } */
78638
+/* { dg-options "-O2 -msse2" } */
78639
+
78640
+#include <emmintrin.h>
78641
+
78642
+typedef long long T __attribute__((may_alias));
78643
+struct S { __m128i d; };
78644
+
78645
+__m128i
78646
+foo (long long *x, struct S *y, __m128i *z)
78647
+{
78648
+ struct S s = *y;
78649
+ ((T *) &s.d)[0] = *x;
78650
+ return _mm_cmpeq_epi16 (s.d, *z);
87626
78651
+}
87627
78652
--- a/src/gcc/testsuite/gcc.target/i386/pr9771-1.c
87628
78653
+++ b/src/gcc/testsuite/gcc.target/i386/pr9771-1.c
87648
78673
+ return 0;
87649
78674
+
87650
78675
+}
78676
--- a/src/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c
78677
+++ b/src/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c
78678
@@ -1,6 +1,6 @@
78679
/* { dg-do compile } */
78680
/* { dg-require-effective-target lp64 } */
78681
-/* { dg-options "-O2 -msse4 -march=core2" } */
78682
+/* { dg-options "-O2 -msse4 -march=core2 -dp" } */
78683
78684
#include <emmintrin.h>
78685
78686
@@ -10,4 +10,4 @@
78687
return _mm_cvtsi64_si128 (b);
78688
}
78689
78690
-/* { dg-final { scan-assembler "movq" } } */
78691
+/* { dg-final { scan-assembler-times "\\*vec_concatv2di_rex64_sse4_1/3" 1 } } */
87651
78692
--- a/src/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c
87652
78693
+++ b/src/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c
87653
78694
@@ -0,0 +1,17 @@
87724
78765
+}
87725
78766
+
87726
78767
+/* { dg-final { scan-assembler-times "imull" 1 } } */
87727
--- a/src/gcc/testsuite/gcc.target/mips/save-restore-1.c
87728
+++ b/src/gcc/testsuite/gcc.target/mips/save-restore-1.c
87729
@@ -1,5 +1,6 @@
87730
/* Check that we can use the save instruction to save varargs. */
87731
/* { dg-options "(-mips16) isa_rev>=1 -mabi=32 -O2" } */
87732
+/* { dg-skip-if "PR target/46610" { mips-sgi-irix6* } } */
87733
87734
#include <stdarg.h>
87735
87736
--- a/src/gcc/testsuite/gcc.target/mips/save-restore-3.c
87737
+++ b/src/gcc/testsuite/gcc.target/mips/save-restore-3.c
87738
@@ -1,6 +1,7 @@
87739
/* Check that we can use the save instruction to save spilled arguments
87740
when the argument save area is out of range of a direct load or store. */
87741
/* { dg-options "(-mips16) isa_rev>=1 -mabi=32 -O2" } */
87742
+/* { dg-skip-if "PR target/46610" { mips-sgi-irix6* } } */
87743
87744
void bar (int *);
87745
87746
--- a/src/gcc/testsuite/gcc.target/mips/save-restore-4.c
87747
+++ b/src/gcc/testsuite/gcc.target/mips/save-restore-4.c
87748
@@ -1,5 +1,6 @@
87749
/* Check that we can use the save instruction to save $16, $17 and $31. */
87750
/* { dg-options "(-mips16) isa_rev>=1 -mabi=32 -O2" } */
87751
+/* { dg-skip-if "PR target/46610" { mips-sgi-irix6* } } */
87752
87753
void bar (void);
87754
87755
--- a/src/gcc/testsuite/gcc.target/mips/save-restore-5.c
87756
+++ b/src/gcc/testsuite/gcc.target/mips/save-restore-5.c
87757
@@ -1,5 +1,6 @@
87758
/* Check that we don't try to save the same register twice. */
87759
/* { dg-options "(-mips16) isa_rev>=1 -mgp32 -O2" } */
87760
+/* { dg-skip-if "PR target/46610" { mips-sgi-irix6* } } */
87761
87762
int bar (int, int, int, int);
87763
void frob (void);
87764
--- a/src/gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c
87765
+++ b/src/gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c
87766
@@ -1,5 +1,5 @@
87767
/* { dg-do compile { target { powerpc*-*-* } } } */
87768
-/* { dg-options "-O2 -mavoid-indexed-addresses" } */
87769
+/* { dg-options "-O2 -mavoid-indexed-addresses -mno-altivec -mno-vsx" } */
87770
87771
/* { dg-final { scan-assembler-not "lbzx" } }
87772
87773
--- a/src/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c
87774
+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c
87775
@@ -30,31 +30,6 @@
87776
87777
reg_parms_t gparms;
87778
87779
-
87780
-/* Testcase could break on future gcc's, if parameter regs
87781
- are changed before this asm. */
87782
-
87783
-#define save_parms(lparms) \
87784
- asm volatile ("lis 11,gparms@ha\n\t" \
87785
- "la 11,gparms@l(11)\n\t" \
87786
- "st 3,0(11)\n\t" \
87787
- "st 4,4(11)\n\t" \
87788
- "st 5,8(11)\n\t" \
87789
- "st 6,12(11)\n\t" \
87790
- "st 7,16(11)\n\t" \
87791
- "st 8,20(11)\n\t" \
87792
- "st 9,24(11)\n\t" \
87793
- "st 10,28(11)\n\t" \
87794
- "stfd 1,32(11)\n\t" \
87795
- "stfd 2,40(11)\n\t" \
87796
- "stfd 3,48(11)\n\t" \
87797
- "stfd 4,56(11)\n\t" \
87798
- "stfd 5,64(11)\n\t" \
87799
- "stfd 6,72(11)\n\t" \
87800
- "stfd 7,80(11)\n\t" \
87801
- "stfd 8,88(11)\n\t":::"11", "memory"); \
87802
- lparms = gparms;
87803
-
87804
typedef struct sf
87805
{
87806
struct sf *backchain;
87807
@@ -62,115 +37,159 @@
87808
unsigned int slot[200];
87809
} stack_frame_t;
87810
87811
+/* Wrapper to save the GPRs and FPRs and then jump to the real function. */
87812
+#define WRAPPER(NAME) \
87813
+__asm__ ("\t.globl\t" #NAME "_asm\n\t" \
87814
+ ".text\n\t" \
87815
+ ".type " #NAME "_asm, @function\n" \
87816
+ #NAME "_asm:\n\t" \
87817
+ "lis 11,gparms@ha\n\t" \
87818
+ "la 11,gparms@l(11)\n\t" \
87819
+ "st 3,0(11)\n\t" \
87820
+ "st 4,4(11)\n\t" \
87821
+ "st 5,8(11)\n\t" \
87822
+ "st 6,12(11)\n\t" \
87823
+ "st 7,16(11)\n\t" \
87824
+ "st 8,20(11)\n\t" \
87825
+ "st 9,24(11)\n\t" \
87826
+ "st 10,28(11)\n\t" \
87827
+ "stfd 1,32(11)\n\t" \
87828
+ "stfd 2,40(11)\n\t" \
87829
+ "stfd 3,48(11)\n\t" \
87830
+ "stfd 4,56(11)\n\t" \
87831
+ "stfd 5,64(11)\n\t" \
87832
+ "stfd 6,72(11)\n\t" \
87833
+ "stfd 7,80(11)\n\t" \
87834
+ "stfd 8,88(11)\n\t" \
87835
+ "b " #NAME "\n\t" \
87836
+ ".size " #NAME ",.-" #NAME "\n")
87837
+
87838
/* Fill up floating point registers with double arguments, forcing
87839
decimal float arguments into the parameter save area. */
87840
+extern void func0_asm (double, double, double, double, double,
87841
+ double, double, double, _Decimal64, _Decimal128);
87842
+
87843
+WRAPPER(func0);
87844
+
87845
void __attribute__ ((noinline))
87846
func0 (double a1, double a2, double a3, double a4, double a5,
87847
double a6, double a7, double a8, _Decimal64 a9, _Decimal128 a10)
87848
{
87849
- reg_parms_t lparms;
87850
stack_frame_t *sp;
87851
87852
- save_parms (lparms);
87853
sp = __builtin_frame_address (0);
87854
sp = sp->backchain;
87855
87856
- if (a1 != lparms.fprs[0]) FAILURE
87857
- if (a2 != lparms.fprs[1]) FAILURE
87858
- if (a3 != lparms.fprs[2]) FAILURE
87859
- if (a4 != lparms.fprs[3]) FAILURE
87860
- if (a5 != lparms.fprs[4]) FAILURE
87861
- if (a6 != lparms.fprs[5]) FAILURE
87862
- if (a7 != lparms.fprs[6]) FAILURE
87863
- if (a8 != lparms.fprs[7]) FAILURE
87864
+ if (a1 != gparms.fprs[0]) FAILURE
87865
+ if (a2 != gparms.fprs[1]) FAILURE
87866
+ if (a3 != gparms.fprs[2]) FAILURE
87867
+ if (a4 != gparms.fprs[3]) FAILURE
87868
+ if (a5 != gparms.fprs[4]) FAILURE
87869
+ if (a6 != gparms.fprs[5]) FAILURE
87870
+ if (a7 != gparms.fprs[6]) FAILURE
87871
+ if (a8 != gparms.fprs[7]) FAILURE
87872
if (a9 != *(_Decimal64 *)&sp->slot[0]) FAILURE
87873
if (a10 != *(_Decimal128 *)&sp->slot[2]) FAILURE
87874
}
87875
87876
/* Alternate 64-bit and 128-bit decimal float arguments, checking that
87877
_Decimal128 is always passed in even/odd register pairs. */
87878
+extern void func1_asm (_Decimal64, _Decimal128, _Decimal64, _Decimal128,
87879
+ _Decimal64, _Decimal128, _Decimal64, _Decimal128);
87880
+
87881
+WRAPPER(func1);
87882
+
87883
void __attribute__ ((noinline))
87884
func1 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4,
87885
_Decimal64 a5, _Decimal128 a6, _Decimal64 a7, _Decimal128 a8)
87886
{
87887
- reg_parms_t lparms;
87888
stack_frame_t *sp;
87889
87890
- save_parms (lparms);
87891
sp = __builtin_frame_address (0);
87892
sp = sp->backchain;
87893
87894
- if (a1 != *(_Decimal64 *)&lparms.fprs[0]) FAILURE /* f1 */
87895
- if (a2 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */
87896
- if (a3 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */
87897
- if (a4 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */
87898
- if (a5 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE /* f8 */
87899
+ if (a1 != *(_Decimal64 *)&gparms.fprs[0]) FAILURE /* f1 */
87900
+ if (a2 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */
87901
+ if (a3 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */
87902
+ if (a4 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */
87903
+ if (a5 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE /* f8 */
87904
if (a6 != *(_Decimal128 *)&sp->slot[0]) FAILURE
87905
if (a7 != *(_Decimal64 *)&sp->slot[4]) FAILURE
87906
if (a8 != *(_Decimal128 *)&sp->slot[6]) FAILURE
87907
}
87908
87909
+extern void func2_asm (_Decimal128, _Decimal64, _Decimal128, _Decimal64,
87910
+ _Decimal128, _Decimal64, _Decimal128, _Decimal64);
87911
+
87912
+WRAPPER(func2);
87913
+
87914
void __attribute__ ((noinline))
87915
func2 (_Decimal128 a1, _Decimal64 a2, _Decimal128 a3, _Decimal64 a4,
87916
_Decimal128 a5, _Decimal64 a6, _Decimal128 a7, _Decimal64 a8)
87917
{
87918
- reg_parms_t lparms;
87919
stack_frame_t *sp;
87920
87921
- save_parms (lparms);
87922
sp = __builtin_frame_address (0);
87923
sp = sp->backchain;
87924
87925
- if (a1 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */
87926
- if (a2 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */
87927
- if (a3 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */
87928
- if (a4 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE /* f8 */
87929
+ if (a1 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */
87930
+ if (a2 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */
87931
+ if (a3 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */
87932
+ if (a4 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE /* f8 */
87933
if (a5 != *(_Decimal128 *)&sp->slot[0]) FAILURE
87934
if (a6 != *(_Decimal64 *)&sp->slot[4]) FAILURE
87935
if (a7 != *(_Decimal128 *)&sp->slot[6]) FAILURE
87936
if (a8 != *(_Decimal64 *)&sp->slot[10]) FAILURE
87937
}
87938
87939
+extern void func3_asm (_Decimal64, _Decimal128, _Decimal64, _Decimal128,
87940
+ _Decimal64);
87941
+
87942
+WRAPPER(func3);
87943
+
87944
void __attribute__ ((noinline))
87945
func3 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4,
87946
_Decimal64 a5)
87947
{
87948
- reg_parms_t lparms;
87949
stack_frame_t *sp;
87950
87951
- save_parms (lparms);
87952
sp = __builtin_frame_address (0);
87953
sp = sp->backchain;
87954
87955
- if (a1 != *(_Decimal64 *)&lparms.fprs[0]) FAILURE /* f1 */
87956
- if (a2 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */
87957
- if (a3 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */
87958
- if (a4 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */
87959
+ if (a1 != *(_Decimal64 *)&gparms.fprs[0]) FAILURE /* f1 */
87960
+ if (a2 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */
87961
+ if (a3 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */
87962
+ if (a4 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */
87963
if (a5 != *(_Decimal128 *)&sp->slot[0]) FAILURE
87964
}
87965
87966
+extern void func4_asm (_Decimal32, _Decimal32, _Decimal32, _Decimal32,
87967
+ _Decimal32, _Decimal32, _Decimal32, _Decimal32,
87968
+ _Decimal32, _Decimal32, _Decimal32, _Decimal32,
87969
+ _Decimal32, _Decimal32, _Decimal32, _Decimal32);
87970
+
87971
+WRAPPER(func4);
87972
+
87973
void __attribute__ ((noinline))
87974
func4 (_Decimal32 a1, _Decimal32 a2, _Decimal32 a3, _Decimal32 a4,
87975
_Decimal32 a5, _Decimal32 a6, _Decimal32 a7, _Decimal32 a8,
87976
_Decimal32 a9, _Decimal32 a10, _Decimal32 a11, _Decimal32 a12,
87977
_Decimal32 a13, _Decimal32 a14, _Decimal32 a15, _Decimal32 a16)
87978
{
87979
- reg_parms_t lparms;
87980
stack_frame_t *sp;
87981
87982
- save_parms (lparms);
87983
sp = __builtin_frame_address (0);
87984
sp = sp->backchain;
87985
87986
/* _Decimal32 is passed in the lower half of an FPR, or in parameter slot. */
87987
- if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE /* f1 */
87988
- if (a2 != ((d32parm_t *)&lparms.fprs[1])->d) FAILURE /* f2 */
87989
- if (a3 != ((d32parm_t *)&lparms.fprs[2])->d) FAILURE /* f3 */
87990
- if (a4 != ((d32parm_t *)&lparms.fprs[3])->d) FAILURE /* f4 */
87991
- if (a5 != ((d32parm_t *)&lparms.fprs[4])->d) FAILURE /* f5 */
87992
- if (a6 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE /* f6 */
87993
- if (a7 != ((d32parm_t *)&lparms.fprs[6])->d) FAILURE /* f7 */
87994
- if (a8 != ((d32parm_t *)&lparms.fprs[7])->d) FAILURE /* f8 */
87995
+ if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE /* f1 */
87996
+ if (a2 != ((d32parm_t *)&gparms.fprs[1])->d) FAILURE /* f2 */
87997
+ if (a3 != ((d32parm_t *)&gparms.fprs[2])->d) FAILURE /* f3 */
87998
+ if (a4 != ((d32parm_t *)&gparms.fprs[3])->d) FAILURE /* f4 */
87999
+ if (a5 != ((d32parm_t *)&gparms.fprs[4])->d) FAILURE /* f5 */
88000
+ if (a6 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE /* f6 */
88001
+ if (a7 != ((d32parm_t *)&gparms.fprs[6])->d) FAILURE /* f7 */
88002
+ if (a8 != ((d32parm_t *)&gparms.fprs[7])->d) FAILURE /* f8 */
88003
if (a9 != *(_Decimal32 *)&sp->slot[0]) FAILURE
88004
if (a10 != *(_Decimal32 *)&sp->slot[1]) FAILURE
88005
if (a11 != *(_Decimal32 *)&sp->slot[2]) FAILURE
88006
@@ -181,24 +200,29 @@
88007
if (a16 != *(_Decimal32 *)&sp->slot[7]) FAILURE
88008
}
88009
88010
+extern void func5_asm (_Decimal32, _Decimal64, _Decimal128,
88011
+ _Decimal32, _Decimal64, _Decimal128,
88012
+ _Decimal32, _Decimal64, _Decimal128,
88013
+ _Decimal32, _Decimal64, _Decimal128);
88014
+
88015
+WRAPPER(func5);
88016
+
88017
void __attribute__ ((noinline))
88018
func5 (_Decimal32 a1, _Decimal64 a2, _Decimal128 a3,
88019
_Decimal32 a4, _Decimal64 a5, _Decimal128 a6,
88020
_Decimal32 a7, _Decimal64 a8, _Decimal128 a9,
88021
_Decimal32 a10, _Decimal64 a11, _Decimal128 a12)
88022
{
88023
- reg_parms_t lparms;
88024
stack_frame_t *sp;
88025
88026
- save_parms (lparms);
88027
sp = __builtin_frame_address (0);
88028
sp = sp->backchain;
88029
88030
- if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE /* f1 */
88031
- if (a2 != *(_Decimal64 *)&lparms.fprs[1]) FAILURE /* f2 */
88032
- if (a3 != *(_Decimal128 *)&lparms.fprs[3]) FAILURE /* f4 & f5 */
88033
- if (a4 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE /* f6 */
88034
- if (a5 != *(_Decimal64 *)&lparms.fprs[6]) FAILURE /* f7 */
88035
+ if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE /* f1 */
88036
+ if (a2 != *(_Decimal64 *)&gparms.fprs[1]) FAILURE /* f2 */
88037
+ if (a3 != *(_Decimal128 *)&gparms.fprs[3]) FAILURE /* f4 & f5 */
88038
+ if (a4 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE /* f6 */
88039
+ if (a5 != *(_Decimal64 *)&gparms.fprs[6]) FAILURE /* f7 */
88040
88041
if (a6 != *(_Decimal128 *)&sp->slot[0]) FAILURE
88042
if (a7 != *(_Decimal32 *)&sp->slot[4]) FAILURE
88043
@@ -212,15 +236,15 @@
88044
int
88045
main ()
88046
{
88047
- func0 (1., 2., 3., 4., 5., 6., 7., 8., 9.dd, 10.dl);
88048
- func1 (1.dd, 2.dl, 3.dd, 4.dl, 5.dd, 6.dl, 7.dd, 8.dl);
88049
- func2 (1.dl, 2.dd, 3.dl, 4.dd, 5.dl, 6.dd, 7.dl, 8.dd);
88050
- func3 (1.dd, 2.dl, 3.dd, 4.dl, 5.dl);
88051
- func4 (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df,
88052
- 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df,
88053
- 515.2df, 516.2df);
88054
- func5 (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl,
88055
- 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl);
88056
+ func0_asm (1., 2., 3., 4., 5., 6., 7., 8., 9.dd, 10.dl);
88057
+ func1_asm (1.dd, 2.dl, 3.dd, 4.dl, 5.dd, 6.dl, 7.dd, 8.dl);
88058
+ func2_asm (1.dl, 2.dd, 3.dl, 4.dd, 5.dl, 6.dd, 7.dl, 8.dd);
88059
+ func3_asm (1.dd, 2.dl, 3.dd, 4.dl, 5.dl);
88060
+ func4_asm (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df,
88061
+ 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df,
88062
+ 515.2df, 516.2df);
88063
+ func5_asm (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl,
88064
+ 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl);
88065
88066
if (failcnt != 0)
88067
abort ();
88068
--- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c
88069
+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c
88070
@@ -1,4 +1,5 @@
88071
/* { dg-do run { target { powerpc64-*-* && { lp64 && dfprt } } } } */
88072
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
88073
/* { dg-options "-std=gnu99 -O2 -fno-strict-aliasing" } */
88074
88075
/* Testcase to check for ABI compliance of parameter passing
88076
@@ -31,60 +32,42 @@
88077
reg_parms_t gparms;
88078
88079
88080
-/* Testcase could break on future gcc's, if parameter regs
88081
- are changed before this asm. */
88082
-
88083
-#ifndef __MACH__
88084
-#define save_parms(lparms) \
88085
- asm volatile ("ld 11,gparms@got(2)\n\t" \
88086
- "std 3,0(11)\n\t" \
88087
- "std 4,8(11)\n\t" \
88088
- "std 5,16(11)\n\t" \
88089
- "std 6,24(11)\n\t" \
88090
- "std 7,32(11)\n\t" \
88091
- "std 8,40(11)\n\t" \
88092
- "std 9,48(11)\n\t" \
88093
- "std 10,56(11)\n\t" \
88094
- "stfd 1,64(11)\n\t" \
88095
- "stfd 2,72(11)\n\t" \
88096
- "stfd 3,80(11)\n\t" \
88097
- "stfd 4,88(11)\n\t" \
88098
- "stfd 5,96(11)\n\t" \
88099
- "stfd 6,104(11)\n\t" \
88100
- "stfd 7,112(11)\n\t" \
88101
- "stfd 8,120(11)\n\t" \
88102
- "stfd 9,128(11)\n\t" \
88103
- "stfd 10,136(11)\n\t" \
88104
- "stfd 11,144(11)\n\t" \
88105
- "stfd 12,152(11)\n\t" \
88106
- "stfd 13,160(11)\n\t":::"11", "memory"); \
88107
- lparms = gparms;
88108
-#else
88109
-#define save_parms(lparms) \
88110
- asm volatile ("ld r11,gparms@got(r2)\n\t" \
88111
- "std r3,0(r11)\n\t" \
88112
- "std r4,8(r11)\n\t" \
88113
- "std r5,16(r11)\n\t" \
88114
- "std r6,24(r11)\n\t" \
88115
- "std r7,32(r11)\n\t" \
88116
- "std r8,40(r11)\n\t" \
88117
- "std r9,48(r11)\n\t" \
88118
- "std r10,56(r11)\n\t" \
88119
- "stfd f1,64(r11)\n\t" \
88120
- "stfd f2,72(r11)\n\t" \
88121
- "stfd f3,80(r11)\n\t" \
88122
- "stfd f4,88(r11)\n\t" \
88123
- "stfd f5,96(r11)\n\t" \
88124
- "stfd f6,104(r11)\n\t" \
88125
- "stfd f7,112(r11)\n\t" \
88126
- "stfd f8,120(r11)\n\t" \
88127
- "stfd f9,128(r11)\n\t" \
88128
- "stfd f10,136(r11)\n\t" \
88129
- "stfd f11,144(r11)\n\t" \
88130
- "stfd f12,152(r11)\n\t" \
88131
- "stfd f13,160(r11)\n\t":::"r11", "memory"); \
88132
- lparms = gparms;
88133
-#endif
88134
+/* Wrapper to save the GPRs and FPRs and then jump to the real function. */
88135
+#define WRAPPER(NAME) \
88136
+__asm__ ("\t.globl\t" #NAME "_asm\n\t" \
88137
+ ".section \".opd\",\"aw\"\n\t" \
88138
+ ".align 3\n" \
88139
+ #NAME "_asm:\n\t" \
88140
+ ".quad .L." #NAME "_asm,.TOC.@tocbase,0\n\t" \
88141
+ ".text\n\t" \
88142
+ ".type " #NAME "_asm, @function\n" \
88143
+ ".L." #NAME "_asm:\n\t" \
88144
+ "ld 11,gparms@got(2)\n\t" \
88145
+ "std 3,0(11)\n\t" \
88146
+ "std 4,8(11)\n\t" \
88147
+ "std 5,16(11)\n\t" \
88148
+ "std 6,24(11)\n\t" \
88149
+ "std 7,32(11)\n\t" \
88150
+ "std 8,40(11)\n\t" \
88151
+ "std 9,48(11)\n\t" \
88152
+ "std 10,56(11)\n\t" \
88153
+ "stfd 1,64(11)\n\t" \
88154
+ "stfd 2,72(11)\n\t" \
88155
+ "stfd 3,80(11)\n\t" \
88156
+ "stfd 4,88(11)\n\t" \
88157
+ "stfd 5,96(11)\n\t" \
88158
+ "stfd 6,104(11)\n\t" \
88159
+ "stfd 7,112(11)\n\t" \
88160
+ "stfd 8,120(11)\n\t" \
88161
+ "stfd 9,128(11)\n\t" \
88162
+ "stfd 10,136(11)\n\t" \
88163
+ "stfd 11,144(11)\n\t" \
88164
+ "stfd 12,152(11)\n\t" \
88165
+ "stfd 13,160(11)\n\t" \
88166
+ "b " #NAME "\n\t" \
88167
+ ".long 0\n\t" \
88168
+ ".byte 0,0,0,0,0,0,0,0\n\t" \
88169
+ ".size " #NAME ",.-" #NAME "\n")
88170
88171
typedef struct sf
88172
{
88173
@@ -97,6 +80,13 @@
88174
unsigned long slot[100];
88175
} stack_frame_t;
88176
88177
+extern void func0_asm (double, double, double, double, double, double,
88178
+ double, double, double, double, double, double,
88179
+ double, double,
88180
+ _Decimal64, _Decimal128, _Decimal64);
88181
+
88182
+WRAPPER(func0);
88183
+
88184
/* Fill up floating point registers with double arguments, forcing
88185
decimal float arguments into the parameter save area. */
88186
void __attribute__ ((noinline))
88187
@@ -105,186 +95,209 @@
88188
double a13, double a14,
88189
_Decimal64 a15, _Decimal128 a16, _Decimal64 a17)
88190
{
88191
- reg_parms_t lparms;
88192
stack_frame_t *sp;
88193
88194
- save_parms (lparms);
88195
sp = __builtin_frame_address (0);
88196
sp = sp->backchain;
88197
88198
- if (a1 != lparms.fprs[0]) FAILURE
88199
- if (a2 != lparms.fprs[1]) FAILURE
88200
- if (a3 != lparms.fprs[2]) FAILURE
88201
- if (a4 != lparms.fprs[3]) FAILURE
88202
- if (a5 != lparms.fprs[4]) FAILURE
88203
- if (a6 != lparms.fprs[5]) FAILURE
88204
- if (a7 != lparms.fprs[6]) FAILURE
88205
- if (a8 != lparms.fprs[7]) FAILURE
88206
- if (a9 != lparms.fprs[8]) FAILURE
88207
- if (a10 != lparms.fprs[9]) FAILURE
88208
- if (a11 != lparms.fprs[10]) FAILURE
88209
- if (a12 != lparms.fprs[11]) FAILURE
88210
- if (a13 != lparms.fprs[12]) FAILURE
88211
+ if (a1 != gparms.fprs[0]) FAILURE
88212
+ if (a2 != gparms.fprs[1]) FAILURE
88213
+ if (a3 != gparms.fprs[2]) FAILURE
88214
+ if (a4 != gparms.fprs[3]) FAILURE
88215
+ if (a5 != gparms.fprs[4]) FAILURE
88216
+ if (a6 != gparms.fprs[5]) FAILURE
88217
+ if (a7 != gparms.fprs[6]) FAILURE
88218
+ if (a8 != gparms.fprs[7]) FAILURE
88219
+ if (a9 != gparms.fprs[8]) FAILURE
88220
+ if (a10 != gparms.fprs[9]) FAILURE
88221
+ if (a11 != gparms.fprs[10]) FAILURE
88222
+ if (a12 != gparms.fprs[11]) FAILURE
88223
+ if (a13 != gparms.fprs[12]) FAILURE
88224
if (a14 != *(double *)&sp->slot[13]) FAILURE
88225
if (a15 != *(_Decimal64 *)&sp->slot[14]) FAILURE
88226
if (a16 != *(_Decimal128 *)&sp->slot[15]) FAILURE
88227
if (a17 != *(_Decimal64 *)&sp->slot[17]) FAILURE
88228
}
88229
88230
+extern void func1_asm (double, double, double, double, double, double,
88231
+ double, double, double, double, double, double,
88232
+ double, _Decimal128 );
88233
+
88234
+WRAPPER(func1);
88235
+
88236
void __attribute__ ((noinline))
88237
func1 (double a1, double a2, double a3, double a4, double a5, double a6,
88238
double a7, double a8, double a9, double a10, double a11, double a12,
88239
double a13, _Decimal128 a14)
88240
{
88241
- reg_parms_t lparms;
88242
stack_frame_t *sp;
88243
88244
- save_parms (lparms);
88245
sp = __builtin_frame_address (0);
88246
sp = sp->backchain;
88247
88248
- if (a1 != lparms.fprs[0]) FAILURE
88249
- if (a2 != lparms.fprs[1]) FAILURE
88250
- if (a3 != lparms.fprs[2]) FAILURE
88251
- if (a4 != lparms.fprs[3]) FAILURE
88252
- if (a5 != lparms.fprs[4]) FAILURE
88253
- if (a6 != lparms.fprs[5]) FAILURE
88254
- if (a7 != lparms.fprs[6]) FAILURE
88255
- if (a8 != lparms.fprs[7]) FAILURE
88256
- if (a9 != lparms.fprs[8]) FAILURE
88257
- if (a10 != lparms.fprs[9]) FAILURE
88258
- if (a11 != lparms.fprs[10]) FAILURE
88259
- if (a12 != lparms.fprs[11]) FAILURE
88260
- if (a13 != lparms.fprs[12]) FAILURE
88261
+ if (a1 != gparms.fprs[0]) FAILURE
88262
+ if (a2 != gparms.fprs[1]) FAILURE
88263
+ if (a3 != gparms.fprs[2]) FAILURE
88264
+ if (a4 != gparms.fprs[3]) FAILURE
88265
+ if (a5 != gparms.fprs[4]) FAILURE
88266
+ if (a6 != gparms.fprs[5]) FAILURE
88267
+ if (a7 != gparms.fprs[6]) FAILURE
88268
+ if (a8 != gparms.fprs[7]) FAILURE
88269
+ if (a9 != gparms.fprs[8]) FAILURE
88270
+ if (a10 != gparms.fprs[9]) FAILURE
88271
+ if (a11 != gparms.fprs[10]) FAILURE
88272
+ if (a12 != gparms.fprs[11]) FAILURE
88273
+ if (a13 != gparms.fprs[12]) FAILURE
88274
if (a14 != *(_Decimal128 *)&sp->slot[13]) FAILURE
88275
}
88276
88277
+extern void func2_asm (double, double, double, double, double, double,
88278
+ double, double, double, double, double, double,
88279
+ _Decimal128);
88280
+
88281
+WRAPPER(func2);
88282
+
88283
void __attribute__ ((noinline))
88284
func2 (double a1, double a2, double a3, double a4, double a5, double a6,
88285
double a7, double a8, double a9, double a10, double a11, double a12,
88286
_Decimal128 a13)
88287
{
88288
- reg_parms_t lparms;
88289
stack_frame_t *sp;
88290
88291
- save_parms (lparms);
88292
sp = __builtin_frame_address (0);
88293
sp = sp->backchain;
88294
88295
- if (a1 != lparms.fprs[0]) FAILURE
88296
- if (a2 != lparms.fprs[1]) FAILURE
88297
- if (a3 != lparms.fprs[2]) FAILURE
88298
- if (a4 != lparms.fprs[3]) FAILURE
88299
- if (a5 != lparms.fprs[4]) FAILURE
88300
- if (a6 != lparms.fprs[5]) FAILURE
88301
- if (a7 != lparms.fprs[6]) FAILURE
88302
- if (a8 != lparms.fprs[7]) FAILURE
88303
- if (a9 != lparms.fprs[8]) FAILURE
88304
- if (a10 != lparms.fprs[9]) FAILURE
88305
- if (a11 != lparms.fprs[10]) FAILURE
88306
- if (a12 != lparms.fprs[11]) FAILURE
88307
+ if (a1 != gparms.fprs[0]) FAILURE
88308
+ if (a2 != gparms.fprs[1]) FAILURE
88309
+ if (a3 != gparms.fprs[2]) FAILURE
88310
+ if (a4 != gparms.fprs[3]) FAILURE
88311
+ if (a5 != gparms.fprs[4]) FAILURE
88312
+ if (a6 != gparms.fprs[5]) FAILURE
88313
+ if (a7 != gparms.fprs[6]) FAILURE
88314
+ if (a8 != gparms.fprs[7]) FAILURE
88315
+ if (a9 != gparms.fprs[8]) FAILURE
88316
+ if (a10 != gparms.fprs[9]) FAILURE
88317
+ if (a11 != gparms.fprs[10]) FAILURE
88318
+ if (a12 != gparms.fprs[11]) FAILURE
88319
if (a13 != *(_Decimal128 *)&sp->slot[12]) FAILURE
88320
}
88321
88322
+extern void func3_asm (_Decimal64, _Decimal128, _Decimal64, _Decimal128,
88323
+ _Decimal64, _Decimal128, _Decimal64, _Decimal128,
88324
+ _Decimal64, _Decimal128);
88325
+
88326
+WRAPPER(func3);
88327
+
88328
void __attribute__ ((noinline))
88329
func3 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4,
88330
_Decimal64 a5, _Decimal128 a6, _Decimal64 a7, _Decimal128 a8,
88331
_Decimal64 a9, _Decimal128 a10)
88332
{
88333
- reg_parms_t lparms;
88334
stack_frame_t *sp;
88335
88336
- save_parms (lparms);
88337
sp = __builtin_frame_address (0);
88338
sp = sp->backchain;
88339
88340
- if (a1 != *(_Decimal64 *)&lparms.fprs[0]) FAILURE /* f1 */
88341
- if (a2 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */
88342
- if (a3 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */
88343
- if (a4 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */
88344
- if (a5 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE /* f8 */
88345
- if (a6 != *(_Decimal128 *)&lparms.fprs[9]) FAILURE /* f10 & f11 */
88346
- if (a7 != *(_Decimal64 *)&lparms.fprs[11]) FAILURE /* f12 */
88347
+ if (a1 != *(_Decimal64 *)&gparms.fprs[0]) FAILURE /* f1 */
88348
+ if (a2 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */
88349
+ if (a3 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */
88350
+ if (a4 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */
88351
+ if (a5 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE /* f8 */
88352
+ if (a6 != *(_Decimal128 *)&gparms.fprs[9]) FAILURE /* f10 & f11 */
88353
+ if (a7 != *(_Decimal64 *)&gparms.fprs[11]) FAILURE /* f12 */
88354
if (a8 != *(_Decimal128 *)&sp->slot[10]) FAILURE
88355
if (a9 != *(_Decimal64 *)&sp->slot[12]) FAILURE
88356
if (a10 != *(_Decimal128 *)&sp->slot[13]) FAILURE
88357
}
88358
88359
+extern void func4_asm (_Decimal128, _Decimal64, _Decimal128, _Decimal64,
88360
+ _Decimal128, _Decimal64, _Decimal128, _Decimal64);
88361
+
88362
+WRAPPER(func4);
88363
+
88364
void __attribute__ ((noinline))
88365
func4 (_Decimal128 a1, _Decimal64 a2, _Decimal128 a3, _Decimal64 a4,
88366
_Decimal128 a5, _Decimal64 a6, _Decimal128 a7, _Decimal64 a8)
88367
{
88368
- reg_parms_t lparms;
88369
stack_frame_t *sp;
88370
88371
- save_parms (lparms);
88372
sp = __builtin_frame_address (0);
88373
sp = sp->backchain;
88374
88375
- if (a1 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */
88376
- if (a2 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */
88377
- if (a3 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */
88378
- if (a4 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE /* f8 */
88379
- if (a5 != *(_Decimal128 *)&lparms.fprs[9]) FAILURE /* f10 & f11 */
88380
- if (a6 != *(_Decimal64 *)&lparms.fprs[11]) FAILURE /* f12 */
88381
+ if (a1 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */
88382
+ if (a2 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */
88383
+ if (a3 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */
88384
+ if (a4 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE /* f8 */
88385
+ if (a5 != *(_Decimal128 *)&gparms.fprs[9]) FAILURE /* f10 & f11 */
88386
+ if (a6 != *(_Decimal64 *)&gparms.fprs[11]) FAILURE /* f12 */
88387
if (a7 != *(_Decimal128 *)&sp->slot[9]) FAILURE
88388
if (a8 != *(_Decimal64 *)&sp->slot[11]) FAILURE
88389
}
88390
88391
+extern void func5_asm (_Decimal32, _Decimal32, _Decimal32, _Decimal32,
88392
+ _Decimal32, _Decimal32, _Decimal32, _Decimal32,
88393
+ _Decimal32, _Decimal32, _Decimal32, _Decimal32,
88394
+ _Decimal32, _Decimal32, _Decimal32, _Decimal32);
88395
+
88396
+WRAPPER(func5);
88397
+
88398
void __attribute__ ((noinline))
88399
func5 (_Decimal32 a1, _Decimal32 a2, _Decimal32 a3, _Decimal32 a4,
88400
_Decimal32 a5, _Decimal32 a6, _Decimal32 a7, _Decimal32 a8,
88401
_Decimal32 a9, _Decimal32 a10, _Decimal32 a11, _Decimal32 a12,
88402
_Decimal32 a13, _Decimal32 a14, _Decimal32 a15, _Decimal32 a16)
88403
{
88404
- reg_parms_t lparms;
88405
stack_frame_t *sp;
88406
88407
- save_parms (lparms);
88408
sp = __builtin_frame_address (0);
88409
sp = sp->backchain;
88410
88411
/* _Decimal32 is passed in the lower half of an FPR or parameter slot. */
88412
- if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE /* f1 */
88413
- if (a2 != ((d32parm_t *)&lparms.fprs[1])->d) FAILURE /* f2 */
88414
- if (a3 != ((d32parm_t *)&lparms.fprs[2])->d) FAILURE /* f3 */
88415
- if (a4 != ((d32parm_t *)&lparms.fprs[3])->d) FAILURE /* f4 */
88416
- if (a5 != ((d32parm_t *)&lparms.fprs[4])->d) FAILURE /* f5 */
88417
- if (a6 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE /* f6 */
88418
- if (a7 != ((d32parm_t *)&lparms.fprs[6])->d) FAILURE /* f7 */
88419
- if (a8 != ((d32parm_t *)&lparms.fprs[7])->d) FAILURE /* f8 */
88420
- if (a9 != ((d32parm_t *)&lparms.fprs[8])->d) FAILURE /* f9 */
88421
- if (a10 != ((d32parm_t *)&lparms.fprs[9])->d) FAILURE /* f10 */
88422
- if (a11 != ((d32parm_t *)&lparms.fprs[10])->d) FAILURE /* f11 */
88423
- if (a12 != ((d32parm_t *)&lparms.fprs[11])->d) FAILURE /* f12 */
88424
- if (a13 != ((d32parm_t *)&lparms.fprs[12])->d) FAILURE /* f13 */
88425
+ if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE /* f1 */
88426
+ if (a2 != ((d32parm_t *)&gparms.fprs[1])->d) FAILURE /* f2 */
88427
+ if (a3 != ((d32parm_t *)&gparms.fprs[2])->d) FAILURE /* f3 */
88428
+ if (a4 != ((d32parm_t *)&gparms.fprs[3])->d) FAILURE /* f4 */
88429
+ if (a5 != ((d32parm_t *)&gparms.fprs[4])->d) FAILURE /* f5 */
88430
+ if (a6 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE /* f6 */
88431
+ if (a7 != ((d32parm_t *)&gparms.fprs[6])->d) FAILURE /* f7 */
88432
+ if (a8 != ((d32parm_t *)&gparms.fprs[7])->d) FAILURE /* f8 */
88433
+ if (a9 != ((d32parm_t *)&gparms.fprs[8])->d) FAILURE /* f9 */
88434
+ if (a10 != ((d32parm_t *)&gparms.fprs[9])->d) FAILURE /* f10 */
88435
+ if (a11 != ((d32parm_t *)&gparms.fprs[10])->d) FAILURE /* f11 */
88436
+ if (a12 != ((d32parm_t *)&gparms.fprs[11])->d) FAILURE /* f12 */
88437
+ if (a13 != ((d32parm_t *)&gparms.fprs[12])->d) FAILURE /* f13 */
88438
if (a14 != ((d32parm_t *)&sp->slot[13])->d) FAILURE
88439
if (a15 != ((d32parm_t *)&sp->slot[14])->d) FAILURE
88440
if (a16 != ((d32parm_t *)&sp->slot[15])->d) FAILURE
88441
}
88442
88443
+extern void func6_asm (_Decimal32, _Decimal64, _Decimal128,
88444
+ _Decimal32, _Decimal64, _Decimal128,
88445
+ _Decimal32, _Decimal64, _Decimal128,
88446
+ _Decimal32, _Decimal64, _Decimal128);
88447
+
88448
+WRAPPER(func6);
88449
+
88450
void __attribute__ ((noinline))
88451
func6 (_Decimal32 a1, _Decimal64 a2, _Decimal128 a3,
88452
_Decimal32 a4, _Decimal64 a5, _Decimal128 a6,
88453
_Decimal32 a7, _Decimal64 a8, _Decimal128 a9,
88454
_Decimal32 a10, _Decimal64 a11, _Decimal128 a12)
88455
{
88456
- reg_parms_t lparms;
88457
stack_frame_t *sp;
88458
88459
- save_parms (lparms);
88460
sp = __builtin_frame_address (0);
88461
sp = sp->backchain;
88462
88463
- if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE /* f1 */
88464
- if (a2 != *(_Decimal64 *)&lparms.fprs[1]) FAILURE /* f2 */
88465
- if (a3 != *(_Decimal128 *)&lparms.fprs[3]) FAILURE /* f4 & f5 */
88466
- if (a4 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE /* f6 */
88467
- if (a5 != *(_Decimal64 *)&lparms.fprs[6]) FAILURE /* f7 */
88468
- if (a6 != *(_Decimal128 *)&lparms.fprs[7]) FAILURE /* f8 & f9 */
88469
- if (a7 != ((d32parm_t *)&lparms.fprs[9])->d) FAILURE /* f10 */
88470
- if (a8 != *(_Decimal64 *)&lparms.fprs[10]) FAILURE /* f11 */
88471
- if (a9 != *(_Decimal128 *)&lparms.fprs[11]) FAILURE /* f12 & f13 */
88472
+ if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE /* f1 */
88473
+ if (a2 != *(_Decimal64 *)&gparms.fprs[1]) FAILURE /* f2 */
88474
+ if (a3 != *(_Decimal128 *)&gparms.fprs[3]) FAILURE /* f4 & f5 */
88475
+ if (a4 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE /* f6 */
88476
+ if (a5 != *(_Decimal64 *)&gparms.fprs[6]) FAILURE /* f7 */
88477
+ if (a6 != *(_Decimal128 *)&gparms.fprs[7]) FAILURE /* f8 & f9 */
88478
+ if (a7 != ((d32parm_t *)&gparms.fprs[9])->d) FAILURE /* f10 */
88479
+ if (a8 != *(_Decimal64 *)&gparms.fprs[10]) FAILURE /* f11 */
88480
+ if (a9 != *(_Decimal128 *)&gparms.fprs[11]) FAILURE /* f12 & f13 */
88481
if (a10 != ((d32parm_t *)&sp->slot[12])->d) FAILURE
88482
if (a11 != *(_Decimal64 *)&sp->slot[13]) FAILURE
88483
}
88484
@@ -292,23 +305,23 @@
88485
int
88486
main (void)
88487
{
88488
- func0 (1.5, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, 8.5, 9.5, 10.5, 11.5, 12.5, 13.5,
88489
- 14.5, 15.2dd, 16.2dl, 17.2dd);
88490
- func1 (101.5, 102.5, 103.5, 104.5, 105.5, 106.5, 107.5, 108.5, 109.5,
88491
- 110.5, 111.5, 112.5, 113.5, 114.2dd);
88492
- func2 (201.5, 202.5, 203.5, 204.5, 205.5, 206.5, 207.5, 208.5, 209.5,
88493
- 210.5, 211.5, 212.5, 213.2dd);
88494
- func3 (301.2dd, 302.2dl, 303.2dd, 304.2dl, 305.2dd, 306.2dl, 307.2dd,
88495
- 308.2dl, 309.2dd, 310.2dl);
88496
- func4 (401.2dl, 402.2dd, 403.2dl, 404.2dd, 405.2dl, 406.2dd, 407.2dl,
88497
- 408.2dd);
88498
+ func0_asm (1.5, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, 8.5, 9.5, 10.5, 11.5, 12.5, 13.5,
88499
+ 14.5, 15.2dd, 16.2dl, 17.2dd);
88500
+ func1_asm (101.5, 102.5, 103.5, 104.5, 105.5, 106.5, 107.5, 108.5, 109.5,
88501
+ 110.5, 111.5, 112.5, 113.5, 114.2dd);
88502
+ func2_asm (201.5, 202.5, 203.5, 204.5, 205.5, 206.5, 207.5, 208.5, 209.5,
88503
+ 210.5, 211.5, 212.5, 213.2dd);
88504
+ func3_asm (301.2dd, 302.2dl, 303.2dd, 304.2dl, 305.2dd, 306.2dl, 307.2dd,
88505
+ 308.2dl, 309.2dd, 310.2dl);
88506
+ func4_asm (401.2dl, 402.2dd, 403.2dl, 404.2dd, 405.2dl, 406.2dd, 407.2dl,
88507
+ 408.2dd);
88508
#if 0
88509
/* _Decimal32 doesn't yet follow the ABI; enable this when it does. */
88510
- func5 (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df,
88511
- 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df,
88512
- 515.2df, 516.2df);
88513
- func6 (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl,
88514
- 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl);
88515
+ func5_asm (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df,
88516
+ 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df,
88517
+ 515.2df, 516.2df);
88518
+ func6_asm (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl,
88519
+ 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl);
88520
#endif
88521
88522
if (failcnt != 0)
88523
--- a/src/gcc/testsuite/gcc.target/powerpc/pr47862.c
88524
+++ b/src/gcc/testsuite/gcc.target/powerpc/pr47862.c
88525
@@ -0,0 +1,19 @@
88526
+/* { dg-do compile { target { powerpc*-*-* } } } */
88527
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
88528
+/* { dg-require-effective-target powerpc_vsx_ok } */
88529
+/* { dg-options "-O2 -mcpu=power7" } */
88530
+/* { dg-final { scan-assembler-not "stfd" } } */
88531
+
88532
+/* PR 47862: Verify caller-save spill of vectors in FP regs do not use
88533
+ legacy FP insns, which spill only half the vector. */
88534
+extern vector double dd[15];
88535
+
88536
+vector double foo() {
88537
+ vector double a,b,c,d,e,f,g,h,i,j,k,l,m,n;
88538
+
88539
+ a=dd[1]; b=dd[2]; c=dd[3]; d=dd[4]; e=dd[5]; f=dd[6]; g=dd[7]; h=dd[8]; i=dd[9];
88540
+ j=dd[10]; k=dd[11]; l=dd[12]; m=dd[13]; n=dd[14];
88541
+ bar();
88542
+ return (a+b+c+d+e+f+g+h+i+j+k+l+m+n);
88543
+}
88544
+
88545
--- a/src/gcc/testsuite/gcc.target/powerpc/pr48192.c
88546
+++ b/src/gcc/testsuite/gcc.target/powerpc/pr48192.c
88547
@@ -0,0 +1,49 @@
88548
+/* { dg-do compile } */
88549
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
88550
+/* { dg-require-effective-target powerpc_vsx_ok } */
88551
+/* { dg-options "-O3 -mcpu=power7 -std=gnu89" } */
88552
+
88553
+/* Make sure that the conditional macros vector, bool, and pixel are not
88554
+ considered as being defined. */
88555
+
88556
+#ifdef bool
88557
+#error "bool is considered defined"
88558
+#endif
88559
+
88560
+#ifdef vector
88561
+#error "vector is considered defined"
88562
+#endif
88563
+
88564
+#ifdef pixel
88565
+#error "pixel is condsidered defined"
88566
+#endif
88567
+
88568
+#if defined(bool)
88569
+#error "bool is considered defined"
88570
+#endif
88571
+
88572
+#if defined(vector)
88573
+#error "vector is considered defined"
88574
+#endif
88575
+
88576
+#if defined(pixel)
88577
+#error "pixel is condsidered defined"
88578
+#endif
88579
+
88580
+#ifndef bool
88581
+#else
88582
+#error "bool is considered defined"
88583
+#endif
88584
+
88585
+#ifndef vector
88586
+#else
88587
+#error "vector is considered defined"
88588
+#endif
88589
+
88590
+#ifndef pixel
88591
+#else
88592
+#error "pixel is condsidered defined"
88593
+#endif
88594
+
88595
+#define bool long double
88596
+bool pixel = 0;
88597
--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c
88598
+++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c
88599
@@ -0,0 +1,97 @@
88600
+/* { dg-do compile { target { powerpc*-*-* } } } */
88601
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
88602
+/* { dg-require-effective-target powerpc_vsx_ok } */
88603
+/* { dg-options "-O3 -mcpu=power7" } */
88604
+
88605
+/* Test the various load/store varients. */
88606
+
88607
+#include <altivec.h>
88608
+
88609
+#define TEST_COPY(NAME, TYPE) \
88610
+void NAME ## _copy_native (vector TYPE *a, vector TYPE *b) \
88611
+{ \
88612
+ *a = *b; \
88613
+} \
88614
+ \
88615
+void NAME ## _copy_vec (vector TYPE *a, vector TYPE *b) \
88616
+{ \
88617
+ vector TYPE x = vec_ld (0, b); \
88618
+ vec_st (x, 0, a); \
88619
+} \
88620
+
88621
+#define TEST_COPYL(NAME, TYPE) \
88622
+void NAME ## _lvxl (vector TYPE *a, vector TYPE *b) \
88623
+{ \
88624
+ vector TYPE x = vec_ldl (0, b); \
88625
+ vec_stl (x, 0, a); \
88626
+} \
88627
+
88628
+#define TEST_VSX_COPY(NAME, TYPE) \
88629
+void NAME ## _copy_vsx (vector TYPE *a, vector TYPE *b) \
88630
+{ \
88631
+ vector TYPE x = vec_vsx_ld (0, b); \
88632
+ vec_vsx_st (x, 0, a); \
88633
+} \
88634
+
88635
+#define TEST_ALIGN(NAME, TYPE) \
88636
+void NAME ## _align (vector unsigned char *a, TYPE *b) \
88637
+{ \
88638
+ vector unsigned char x = vec_lvsl (0, b); \
88639
+ vector unsigned char y = vec_lvsr (0, b); \
88640
+ vec_st (x, 0, a); \
88641
+ vec_st (y, 8, a); \
88642
+}
88643
+
88644
+#ifndef NO_COPY
88645
+TEST_COPY(uchar, unsigned char)
88646
+TEST_COPY(schar, signed char)
88647
+TEST_COPY(bchar, bool char)
88648
+TEST_COPY(ushort, unsigned short)
88649
+TEST_COPY(sshort, signed short)
88650
+TEST_COPY(bshort, bool short)
88651
+TEST_COPY(uint, unsigned int)
88652
+TEST_COPY(sint, signed int)
88653
+TEST_COPY(bint, bool int)
88654
+TEST_COPY(float, float)
88655
+TEST_COPY(double, double)
88656
+#endif /* NO_COPY */
88657
+
88658
+#ifndef NO_COPYL
88659
+TEST_COPYL(uchar, unsigned char)
88660
+TEST_COPYL(schar, signed char)
88661
+TEST_COPYL(bchar, bool char)
88662
+TEST_COPYL(ushort, unsigned short)
88663
+TEST_COPYL(sshort, signed short)
88664
+TEST_COPYL(bshort, bool short)
88665
+TEST_COPYL(uint, unsigned int)
88666
+TEST_COPYL(sint, signed int)
88667
+TEST_COPYL(bint, bool int)
88668
+TEST_COPYL(float, float)
88669
+TEST_COPYL(double, double)
88670
+#endif /* NO_COPYL */
88671
+
88672
+#ifndef NO_ALIGN
88673
+TEST_ALIGN(uchar, unsigned char)
88674
+TEST_ALIGN(schar, signed char)
88675
+TEST_ALIGN(ushort, unsigned short)
88676
+TEST_ALIGN(sshort, signed short)
88677
+TEST_ALIGN(uint, unsigned int)
88678
+TEST_ALIGN(sint, signed int)
88679
+TEST_ALIGN(float, float)
88680
+TEST_ALIGN(double, double)
88681
+#endif /* NO_ALIGN */
88682
+
88683
+
88684
+#ifndef NO_VSX_COPY
88685
+TEST_VSX_COPY(uchar, unsigned char)
88686
+TEST_VSX_COPY(schar, signed char)
88687
+TEST_VSX_COPY(bchar, bool char)
88688
+TEST_VSX_COPY(ushort, unsigned short)
88689
+TEST_VSX_COPY(sshort, signed short)
88690
+TEST_VSX_COPY(bshort, bool short)
88691
+TEST_VSX_COPY(uint, unsigned int)
88692
+TEST_VSX_COPY(sint, signed int)
88693
+TEST_VSX_COPY(bint, bool int)
88694
+TEST_VSX_COPY(float, float)
88695
+TEST_VSX_COPY(double, double)
88696
+#endif /* NO_VSX_COPY */
88697
--- a/src/gcc/testsuite/gfortran.dg/argument_checking_13.f90
88698
+++ b/src/gcc/testsuite/gfortran.dg/argument_checking_13.f90
88699
@@ -26,9 +26,9 @@
88700
real, allocatable :: deferred(:,:,:)
88701
real, pointer :: ptr(:,:,:)
88702
call rlv1(deferred(1,1,1)) ! valid since contiguous
88703
-call rlv1(ptr(1,1,1)) ! { dg-error "Element of assumed-shaped array" }
88704
-call rlv1(assumed_sh_dummy(1,1,1)) ! { dg-error "Element of assumed-shaped array" }
88705
-call rlv1(pointer_dummy(1,1,1)) ! { dg-error "Element of assumed-shaped array" }
88706
+call rlv1(ptr(1,1,1)) ! { dg-error "Element of assumed-shaped or pointer array" }
88707
+call rlv1(assumed_sh_dummy(1,1,1)) ! { dg-error "Element of assumed-shaped or pointer array" }
88708
+call rlv1(pointer_dummy(1,1,1)) ! { dg-error "Element of assumed-shaped or pointer array" }
88709
end
88710
88711
subroutine test2(assumed_sh_dummy, pointer_dummy)
88712
--- a/src/gcc/testsuite/gfortran.dg/argument_checking_17.f90
88713
+++ b/src/gcc/testsuite/gfortran.dg/argument_checking_17.f90
88714
@@ -0,0 +1,26 @@
88715
+! { dg-do compile }
88716
+!
88717
+! PR fortran/47569
88718
+!
88719
+! Contributed by Jos de Kloe
88720
+!
88721
+module teststr
88722
+ implicit none
88723
+ integer, parameter :: GRH_SIZE = 20, NMAX = 41624
88724
+ type strtype
88725
+ integer :: size
88726
+ character :: mdr(NMAX)
88727
+ end type strtype
88728
+contains
88729
+ subroutine sub2(string,str_size)
88730
+ integer,intent(in) :: str_size
88731
+ character,intent(out) :: string(str_size)
88732
+ string(:) = 'a'
88733
+ end subroutine sub2
88734
+ subroutine sub1(a)
88735
+ type(strtype),intent(inout) :: a
88736
+ call sub2(a%mdr(GRH_SIZE+1),a%size-GRH_SIZE)
88737
+ end subroutine sub1
88738
+end module teststr
88739
+
88740
+! { dg-final { cleanup-modules "teststr" } }
88741
--- a/src/gcc/testsuite/gfortran.dg/array_constructor_33.f90
88742
+++ b/src/gcc/testsuite/gfortran.dg/array_constructor_33.f90
88743
@@ -1,4 +1,5 @@
88744
! { dg-do compile }
88745
+! { dg-timeout-factor 4 }
88746
! PR20923 gfortran slow for large array constructors.
88747
! Test case prepared from PR by Jerry DeLisle <jvdelisle@gcc.gnu.org>
88748
program sel
88749
--- a/src/gcc/testsuite/gfortran.dg/array_constructor_36.f90
88750
+++ b/src/gcc/testsuite/gfortran.dg/array_constructor_36.f90
88751
@@ -0,0 +1,21 @@
88752
+! { dg-do run }
88753
+! Test the fix for PR47348, in which the substring length
88754
+! in the array constructor at line 19 would be missed and
88755
+! the length of q used instead.
88756
+!
88757
+! Contributed by Thomas Koenig <tkoenig@netcologne.de>
88758
+!
88759
+program main
88760
+ implicit none
88761
+ character(len = *), parameter :: fmt='(2(A,"|"))'
88762
+ character(len = *), parameter :: test='xyc|aec|'
88763
+ integer :: i
88764
+ character(len = 4) :: q
88765
+ character(len = 8) :: buffer
88766
+ q = 'xy'
88767
+ i = 2
88768
+ write (buffer, fmt) (/ trim(q), 'ae' /)//'c'
88769
+ if (buffer .ne. test) Call abort
88770
+ write (buffer, FMT) (/ q(1:i), 'ae' /)//'c'
88771
+ if (buffer .ne. test) Call abort
88772
+end program main
88773
--- a/src/gcc/testsuite/gfortran.dg/cray_pointers_2.f90
88774
+++ b/src/gcc/testsuite/gfortran.dg/cray_pointers_2.f90
88775
@@ -1,5 +1,8 @@
88776
-! { dg-do run }
88777
-! { dg-options "-fcray-pointer -fbounds-check" }
88778
+! Using two spaces between dg-do and run is a hack to keep gfortran-dg-runtest
88779
+! from cycling through optimization options for this expensive test.
88780
+! { dg-do run }
88781
+! { dg-options "-O3 -fcray-pointer -fbounds-check" }
88782
+! { dg-timeout-factor 4 }
88783
! Series of routines for testing a Cray pointer implementation
88784
program craytest
88785
common /errors/errors(400)
88786
--- a/src/gcc/testsuite/gfortran.dg/debug/pr46756.f
88787
+++ b/src/gcc/testsuite/gfortran.dg/debug/pr46756.f
88788
@@ -0,0 +1,29 @@
88789
+C PR debug/46756, reduced from ../20010519-1.f
88790
+C { dg-do compile }
88791
+C { dg-options "-O -fcompare-debug" }
88792
+ LOGICAL QDISK,QDW,QCMPCT
88793
+ LOGICAL LNOMA,LRAISE,LSCI,LBIG
88794
+ ASSIGN 801 TO I800 ! { dg-warning "Deleted feature: ASSIGN" "Deleted feature: ASSIGN" }
88795
+ GOTO 800
88796
+ 801 CONTINUE
88797
+ ASSIGN 761 TO I760 ! { dg-warning "Deleted feature: ASSIGN" "Deleted feature: ASSIGN" }
88798
+ 761 CONTINUE
88799
+ IF(LSCI) THEN
88800
+ DO I=1,LENCM
88801
+ ENDDO
88802
+ ENDIF
88803
+ DO WHILE((CVGMX.GT.TOLDIM).AND.(ITER.LT.ITMX))
88804
+ IF(.NOT.QDW) THEN
88805
+ ASSIGN 641 to I640 ! { dg-warning "Deleted feature: ASSIGN" "Deleted feature: ASSIGN" }
88806
+ GOTO 640
88807
+ 641 CONTINUE
88808
+ ENDIF
88809
+ ENDDO
88810
+ GOTO 700
88811
+ 640 CONTINUE
88812
+ GOTO I640 ! { dg-warning "Deleted feature: Assigned" "Assigned GO TO" }
88813
+ 700 CONTINUE
88814
+ GOTO I760 ! { dg-warning "Deleted feature: Assigned" "Assigned GO TO" }
88815
+ 800 CONTINUE
88816
+ GOTO I800 ! { dg-warning "Deleted feature: Assigned" "Assigned GO TO" }
88817
+ END
88818
--- a/src/gcc/testsuite/gfortran.dg/dependency_39.f90
88819
+++ b/src/gcc/testsuite/gfortran.dg/dependency_39.f90
88820
@@ -0,0 +1,37 @@
88821
+! { dg-do run }
88822
+! PR 45777 - component ref aliases when both are pointers
88823
+module m1
88824
+ type t1
88825
+ integer, dimension(:), allocatable :: data
88826
+ end type t1
88827
+contains
88828
+ subroutine s1(t,d)
88829
+ integer, dimension(:), pointer :: d
88830
+ type(t1), pointer :: t
88831
+ d(1:5)=t%data(3:7)
88832
+ end subroutine s1
88833
+ subroutine s2(d,t)
88834
+ integer, dimension(:), pointer :: d
88835
+ type(t1), pointer :: t
88836
+ t%data(3:7) = d(1:5)
88837
+ end subroutine s2
88838
+end module m1
88839
+
88840
+program main
88841
+ use m1
88842
+ type(t1), pointer :: t
88843
+ integer, dimension(:), pointer :: d
88844
+ allocate(t)
88845
+ allocate(t%data(10))
88846
+ t%data=(/(i,i=1,10)/)
88847
+ d=>t%data(5:9)
88848
+ call s1(t,d)
88849
+ if (any(d.ne.(/3,4,5,6,7/))) call abort()
88850
+ t%data=(/(i,i=1,10)/)
88851
+ d=>t%data(1:5)
88852
+ call s2(d,t)
88853
+ if (any(t%data.ne.(/1,2,1,2,3,4,5,8,9,10/))) call abort
88854
+ deallocate(t%data)
88855
+ deallocate(t)
88856
+end program main
88857
+! { dg-final { cleanup-modules "m1" } }
88858
--- a/src/gcc/testsuite/gfortran.dg/func_result_6.f90
88859
+++ b/src/gcc/testsuite/gfortran.dg/func_result_6.f90
88860
@@ -0,0 +1,73 @@
88861
+! { dg-do run }
88862
+!
88863
+! PR fortran/47775
88864
+!
88865
+! Contributed by Fran Martinez Fadrique
88866
+!
88867
+! Before, a temporary was missing for generic procedured (cf. test())
88868
+! as the allocatable attribute was ignored for the check whether a
88869
+! temporary is required
88870
+!
88871
+module m
88872
+type t
88873
+contains
88874
+ procedure, NOPASS :: foo => foo
88875
+ generic :: gen => foo
88876
+end type t
88877
+contains
88878
+ function foo(i)
88879
+ integer, allocatable :: foo(:)
88880
+ integer :: i
88881
+ allocate(foo(2))
88882
+ foo(1) = i
88883
+ foo(2) = i + 10
88884
+ end function foo
88885
+end module m
88886
+
88887
+use m
88888
+type(t) :: x
88889
+integer, pointer :: ptr1, ptr2
88890
+integer, target :: bar1(2)
88891
+integer, target, allocatable :: bar2(:)
88892
+
88893
+allocate(bar2(2))
88894
+ptr1 => bar1(2)
88895
+ptr2 => bar2(2)
88896
+
88897
+bar1 = x%gen(1)
88898
+if (ptr1 /= 11) call abort()
88899
+bar1 = x%foo(2)
88900
+if (ptr1 /= 12) call abort()
88901
+bar2 = x%gen(3)
88902
+if (ptr2 /= 13) call abort()
88903
+bar2 = x%foo(4)
88904
+if (ptr2 /= 14) call abort()
88905
+bar2(:) = x%gen(5)
88906
+if (ptr2 /= 15) call abort()
88907
+bar2(:) = x%foo(6)
88908
+if (ptr2 /= 16) call abort()
88909
+
88910
+call test()
88911
+end
88912
+
88913
+subroutine test
88914
+interface gen
88915
+ procedure foo
88916
+end interface gen
88917
+
88918
+integer, target :: bar(2)
88919
+integer, pointer :: ptr
88920
+bar = [1,2]
88921
+ptr => bar(2)
88922
+if (ptr /= 2) call abort()
88923
+bar = gen()
88924
+if (ptr /= 77) call abort()
88925
+contains
88926
+ function foo()
88927
+ integer, allocatable :: foo(:)
88928
+ allocate(foo(2))
88929
+ foo = [33, 77]
88930
+ end function foo
88931
+end subroutine test
88932
+
88933
+! { dg-final { cleanup-modules "m" } }
88934
--- a/src/gcc/testsuite/gfortran.dg/g77/cabs.f
88935
+++ b/src/gcc/testsuite/gfortran.dg/g77/cabs.f
88936
@@ -1,4 +1,5 @@
88937
-c { dg-do run { xfail mips-sgi-irix6* } } PR 16292
88938
+c { dg-do run }
88939
+c { dg-xfail-run-if "PR target/16292" { mips-sgi-irix6* } { -O0 } { -mabi=32 } }
88940
program cabs_1
88941
complex z0
88942
real r0
88943
--- a/src/gcc/testsuite/gfortran.dg/gomp/pr47331.f90
88944
+++ b/src/gcc/testsuite/gfortran.dg/gomp/pr47331.f90
88945
@@ -0,0 +1,24 @@
88946
+! PR fortran/47331
88947
+! { dg-do compile }
88948
+! { dg-options "-fopenmp -fwhole-file" }
88949
+
88950
+subroutine foo
88951
+ !$omp parallel
88952
+ call bar ()
88953
+ !$omp end parallel
88954
+end subroutine foo
88955
+
88956
+subroutine bar
88957
+ integer :: k
88958
+ do k=1,5
88959
+ call baz (k)
88960
+ end do
88961
+end subroutine bar
88962
+
88963
+subroutine baz (k)
88964
+ integer :: k
88965
+end subroutine
88966
+
88967
+program pr47331
88968
+ call foo
88969
+end program pr47331
88970
--- a/src/gcc/testsuite/gfortran.dg/intrinsic_ifunction_2.f90
88971
+++ b/src/gcc/testsuite/gfortran.dg/intrinsic_ifunction_2.f90
88972
@@ -0,0 +1,8 @@
88973
+! { dg-do run }
88974
+! PR 48066 - this used to segfault.
88975
+program p
88976
+ real(8) :: empty(0, 3), square(0)
88977
+ logical :: lempty(0, 3), lsquare(0)
88978
+ square = sum(empty * empty, 2)
88979
+ lsquare = any(lempty .and. lempty, 2)
88980
+end
88981
--- a/src/gcc/testsuite/gfortran.dg/ldist-1.f90
88982
+++ b/src/gcc/testsuite/gfortran.dg/ldist-1.f90
88983
@@ -29,5 +29,8 @@
88984
return
88985
end Subroutine PADEC
88986
88987
-! { dg-final { scan-tree-dump-times "distributed: split to 4 loops" 1 "ldist" } }
88988
+! There are 5 legal partitions in this code. Based on the data
88989
+! locality heuristic, this loop should not be split.
88990
+
88991
+! { dg-final { scan-tree-dump-not "distributed: split to" "ldist" } }
88992
! { dg-final { cleanup-tree-dump "ldist" } }
88993
--- a/src/gcc/testsuite/gfortran.dg/ldist-pr43023.f90
88994
+++ b/src/gcc/testsuite/gfortran.dg/ldist-pr43023.f90
88995
@@ -0,0 +1,31 @@
88996
+! { dg-do compile }
88997
+! { dg-options "-O2 -ftree-loop-distribution" }
88998
+
88999
+MODULE NFT_mod
89000
+
89001
+implicit none
89002
+integer :: Nangle
89003
+real:: Z0
89004
+real, dimension(:,:), allocatable :: Angle
89005
+real, dimension(:), allocatable :: exth, ezth, hxth, hyth, hyphi
89006
+
89007
+CONTAINS
89008
+
89009
+SUBROUTINE NFT_Init()
89010
+
89011
+real :: th, fi
89012
+integer :: n
89013
+
89014
+do n = 1,Nangle
89015
+ th = Angle(n,1)
89016
+ fi = Angle(n,2)
89017
+
89018
+ exth(n) = cos(fi)*cos(th)
89019
+ ezth(n) = -sin(th)
89020
+ hxth(n) = -sin(fi)
89021
+ hyth(n) = cos(fi)
89022
+ hyphi(n) = -sin(fi)
89023
+end do
89024
+END SUBROUTINE NFT_Init
89025
+
89026
+END MODULE NFT_mod
89027
--- a/src/gcc/testsuite/gfortran.dg/namelist_71.f90
89028
+++ b/src/gcc/testsuite/gfortran.dg/namelist_71.f90
89029
@@ -0,0 +1,36 @@
89030
+! { dg-do run }
89031
+! PR47778 Reading array of structures from namelist
89032
+! Test case derived from the reporters test case.
89033
+program test_nml
89034
+type field_descr
89035
+ integer number
89036
+end type
89037
+type fsetup
89038
+ type (field_descr), dimension(3) :: vel ! 3 velocity components
89039
+ type (field_descr), dimension(3) :: scal ! 3 scalars
89040
+end type
89041
+type (fsetup) field_setup
89042
+namelist /nl_setup/ field_setup
89043
+field_setup%vel%number = 0
89044
+field_setup%scal%number = 0
89045
+! write(*,nml=nl_setup)
89046
+open(10, status="scratch")
89047
+write(10,'(a)') "&nl_setup"
89048
+write(10,'(a)') " field_setup%vel(1)%number= 3,"
89049
+write(10,'(a)') " field_setup%vel(2)%number= 9,"
89050
+write(10,'(a)') " field_setup%vel(3)%number= 27,"
89051
+write(10,'(a)') " field_setup%scal(1)%number= 2,"
89052
+write(10,'(a)') " field_setup%scal(2)%number= 4,"
89053
+write(10,'(a)') " field_setup%scal(3)%number= 8,"
89054
+write(10,'(a)') "/"
89055
+rewind(10)
89056
+read(10,nml=nl_setup)
89057
+if (field_setup%vel(1)%number .ne. 3) call abort
89058
+if (field_setup%vel(2)%number .ne. 9) call abort
89059
+if (field_setup%vel(3)%number .ne. 27) call abort
89060
+if (field_setup%scal(1)%number .ne. 2) call abort
89061
+if (field_setup%scal(2)%number .ne. 4) call abort
89062
+if (field_setup%scal(3)%number .ne. 8) call abort
89063
+!write(*,nml=nl_setup)
89064
+end program test_nml
89065
+
89066
--- a/src/gcc/testsuite/gfortran.dg/power2.f90
89067
+++ b/src/gcc/testsuite/gfortran.dg/power2.f90
89068
@@ -13,6 +13,9 @@
89069
INTEGER(KIND=1) :: k1
89070
INTEGER(KIND=2) :: k2
89071
89072
+ k1 = 1_1
89073
+ k2 = 1_2
89074
+
89075
k1 = 1_1 + 1_1**k1
89076
k2 = 1_2 + 1_2**k2
89077
89078
--- a/src/gcc/testsuite/gfortran.dg/pr44592.f90
89079
+++ b/src/gcc/testsuite/gfortran.dg/pr44592.f90
89080
@@ -0,0 +1,20 @@
89081
+! { dg-do run }
89082
+! { dg-options "-O3" }
89083
+! From forall_12.f90
89084
+! Fails with loop reversal at -O3
89085
+!
89086
+ character(len=1) :: b(4) = (/"1","2","3","4"/), c(4)
89087
+ c = b
89088
+ i = 1
89089
+ ! This statement must be here for the abort below
89090
+ b(1:3)(i:i) = b(2:4)(i:i)
89091
+
89092
+ b = c
89093
+ b(4:2:-1)(i:i) = b(3:1:-1)(i:i)
89094
+
89095
+ ! This fails. If the condition is printed, the result is F F F F
89096
+ if (any (b .ne. (/"1","1","2","3"/))) i = 2
89097
+ print *, b
89098
+ print *, b .ne. (/"1","1","2","3"/)
89099
+ if (i == 2) call abort
89100
+end
89101
--- a/src/gcc/testsuite/gfortran.dg/pr46804.f90
89102
+++ b/src/gcc/testsuite/gfortran.dg/pr46804.f90
89103
@@ -0,0 +1,36 @@
89104
+! PR rtl-optimization/46804
89105
+! { dg-do run }
89106
+! { dg-options "-O -fPIC -fexpensive-optimizations -fgcse -foptimize-register-move -fpeel-loops -fno-tree-loop-optimize" }
89107
+
89108
+program main
89109
+ integer, parameter :: n1 = 2, n2 = 3, n3 = 4, slen = 3
89110
+ character (len = slen), dimension (n1, n2, n3) :: a
89111
+ integer (kind = 1), dimension (2, 4) :: shift1
89112
+ integer (kind = 2), dimension (2, 4) :: shift2
89113
+ integer (kind = 4), dimension (2, 4) :: shift3
89114
+ do i3 = 1, n3
89115
+ do i2 = 1, n2
89116
+ do i1 = 1, n1
89117
+ a (i1, i2, i3) = 'ab'(i1:i1) // 'cde'(i2:i2) // 'fghi'(i3:i3)
89118
+ end do
89119
+ end do
89120
+ end do
89121
+ shift1 (1, :) = (/ 4, 11, 19, 20 /)
89122
+ shift1 (2, :) = (/ 55, 5, 1, 2 /)
89123
+ shift2 = shift1
89124
+ shift3 = shift1
89125
+ call test (cshift (a, shift2, 2))
89126
+ call test (cshift (a, shift3, 2))
89127
+contains
89128
+ subroutine test (b)
89129
+ character (len = slen), dimension (n1, n2, n3) :: b
89130
+ do i3 = 1, n3
89131
+ do i2 = 1, n2
89132
+ do i1 = 1, n1
89133
+ i2p = mod (shift1 (i1, i3) + i2 - 1, n2) + 1
89134
+ if (b (i1, i2, i3) .ne. a (i1, i2p, i3)) call abort
89135
+ end do
89136
+ end do
89137
+ end do
89138
+ end subroutine test
89139
+end program main
89140
--- a/src/gcc/testsuite/gfortran.dg/pr47878.f90
89141
+++ b/src/gcc/testsuite/gfortran.dg/pr47878.f90
89142
@@ -0,0 +1,10 @@
89143
+! PR fortran/47878
89144
+! { dg-do run }
89145
+ integer :: a(5)
89146
+ open (99, recl = 40)
89147
+ write (99, '(5i3)') 1, 2, 3
89148
+ rewind (99)
89149
+ read (99, '(5i3)') a
89150
+ if (any (a.ne.(/1, 2, 3, 0, 0/))) call abort
89151
+ close (99, status = 'delete')
89152
+end
89153
--- a/src/gcc/testsuite/gfortran.dg/redefined_intrinsic_assignment_2.f90
89154
+++ b/src/gcc/testsuite/gfortran.dg/redefined_intrinsic_assignment_2.f90
89155
@@ -0,0 +1,68 @@
89156
+! { dg-do compile }
89157
+!
89158
+! PR fortran/47448
89159
+!
89160
+! ASSIGNMENT(=) checks. Defined assignment is allowed if and only if
89161
+! it does not override an intrinsic assignment.
89162
+!
89163
+
89164
+module test1
89165
+ interface assignment(=)
89166
+ module procedure valid, valid2
89167
+ end interface
89168
+contains
89169
+ ! Valid: scalar = array
89170
+ subroutine valid (lhs,rhs)
89171
+ integer, intent(out) :: lhs
89172
+ integer, intent(in) :: rhs(:)
89173
+ lhs = rhs(1)
89174
+ end subroutine valid
89175
+
89176
+ ! Valid: array of different ranks
89177
+ subroutine valid2 (lhs,rhs)
89178
+ integer, intent(out) :: lhs(:)
89179
+ integer, intent(in) :: rhs(:,:)
89180
+ lhs(:) = rhs(:,1)
89181
+ end subroutine valid2
89182
+end module test1
89183
+
89184
+module test2
89185
+ interface assignment(=)
89186
+ module procedure invalid
89187
+ end interface
89188
+contains
89189
+ ! Invalid: scalar = scalar
89190
+ subroutine invalid (lhs,rhs) ! { dg-error "must not redefine an INTRINSIC type assignment" }
89191
+ integer, intent(out) :: lhs
89192
+ integer, intent(in) :: rhs
89193
+ lhs = rhs
89194
+ end subroutine invalid
89195
+end module test2
89196
+
89197
+module test3
89198
+ interface assignment(=)
89199
+ module procedure invalid2
89200
+ end interface
89201
+contains
89202
+ ! Invalid: array = scalar
89203
+ subroutine invalid2 (lhs,rhs) ! { dg-error "must not redefine an INTRINSIC type assignment" }
89204
+ integer, intent(out) :: lhs(:)
89205
+ integer, intent(in) :: rhs
89206
+ lhs(:) = rhs
89207
+ end subroutine invalid2
89208
+end module test3
89209
+
89210
+module test4
89211
+ interface assignment(=)
89212
+ module procedure invalid3
89213
+ end interface
89214
+contains
89215
+ ! Invalid: array = array for same rank
89216
+ subroutine invalid3 (lhs,rhs) ! { dg-error "must not redefine an INTRINSIC type assignment" }
89217
+ integer, intent(out) :: lhs(:)
89218
+ integer, intent(in) :: rhs(:)
89219
+ lhs(:) = rhs(:)
89220
+ end subroutine invalid3
89221
+end module test4
89222
+
89223
+! { dg-final { cleanup-modules "test1" } }
89224
--- a/src/gcc/testsuite/gfortran.dg/userdef_operator_2.f90
89225
+++ b/src/gcc/testsuite/gfortran.dg/userdef_operator_2.f90
89226
@@ -0,0 +1,17 @@
89227
+! { dg-do compile }
89228
+! PR 45338 - no ICE when cmp is not used explicitly.
89229
+! Test case by Simon Smart
89230
+module test_mod
89231
+ implicit none
89232
+contains
89233
+ subroutine test_fn (cmp)
89234
+ interface operator(.myop.)
89235
+ pure function cmp (a, b) result(ret)
89236
+ integer, intent(in) :: a, b
89237
+ logical ret
89238
+ end function cmp
89239
+ end interface
89240
+ integer :: a, b
89241
+ print*, a .myop. b
89242
+ end subroutine test_fn
89243
+end module test_mod
89244
78768
--- a/src/gcc/testsuite/gfortran.dg/vect/vect.exp
89245
78769
+++ b/src/gcc/testsuite/gfortran.dg/vect/vect.exp
89246
78770
@@ -105,7 +105,7 @@
89252
78776
if [is-effective-target arm_neon_hw] {
89253
78777
set dg-do-what-default run
89254
78778
} else {
89255
--- a/src/gcc/testsuite/gnat.dg/opt13.adb
89256
+++ b/src/gcc/testsuite/gnat.dg/opt13.adb
89257
@@ -0,0 +1,13 @@
89258
+-- { dg-do run }
89259
+-- { dg-options "-O" }
89260
+
89261
+with Opt13_Pkg; use Opt13_Pkg;
89262
+
89263
+procedure Opt13 is
89264
+ T : My_Type;
89265
+begin
89266
+ Allocate (T);
89267
+ if N /= 1 then
89268
+ raise Program_Error;
89269
+ end if;
89270
+end;
89271
--- a/src/gcc/testsuite/gnat.dg/opt13_pkg.adb
89272
+++ b/src/gcc/testsuite/gnat.dg/opt13_pkg.adb
89273
@@ -0,0 +1,31 @@
89274
+package body Opt13_Pkg is
89275
+
89276
+ subtype Index_Type is Natural range 0 .. 16;
89277
+
89278
+ type Arr is array (Index_Type range <>) of Integer;
89279
+
89280
+ type Rec is record
89281
+ F1, F2, F3 : Float;
89282
+ N : Natural;
89283
+ B1, B2 : Boolean;
89284
+ F4 : Float;
89285
+ end record;
89286
+
89287
+ type Data (D : Index_Type) is record
89288
+ A : Arr (1 .. D);
89289
+ R : Rec;
89290
+ end record;
89291
+
89292
+ Zero : constant Rec := (0.0, 0.0, 0.0, 0, False, False, 0.0);
89293
+
89294
+ procedure Allocate (T : out My_Type) is
89295
+ begin
89296
+ T := new Data (Index_Type'last);
89297
+ T.R := Zero;
89298
+
89299
+ for I in 1 .. T.A'last loop
89300
+ N := 1;
89301
+ end loop;
89302
+ end;
89303
+
89304
+end Opt13_Pkg;
89305
--- a/src/gcc/testsuite/gnat.dg/opt13_pkg.ads
89306
+++ b/src/gcc/testsuite/gnat.dg/opt13_pkg.ads
89307
@@ -0,0 +1,15 @@
89308
+package Opt13_Pkg is
89309
+
89310
+ N : Natural := 0;
89311
+
89312
+ type My_Type is private;
89313
+
89314
+ procedure Allocate (T : out My_Type);
89315
+
89316
+private
89317
+
89318
+ type Data;
89319
+
89320
+ type My_Type is access Data;
89321
+
89322
+end Opt13_Pkg;
89323
78779
--- a/src/gcc/testsuite/lib/lto.exp
89324
78780
+++ b/src/gcc/testsuite/lib/lto.exp
89325
78781
@@ -156,6 +156,7 @@
89362
78818
89363
78819
--- a/src/gcc/testsuite/lib/target-supports.exp
89364
78820
+++ b/src/gcc/testsuite/lib/target-supports.exp
89365
@@ -1,5 +1,5 @@
89366
-# Copyright (C) 1999, 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
89367
-# Free Software Foundation, Inc.
89368
+# Copyright (C) 1999, 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
89369
+# 2011 Free Software Foundation, Inc.
89370
89371
# This program is free software; you can redistribute it and/or modify
89372
# it under the terms of the GNU General Public License as published by
89373
@@ -1005,6 +1005,30 @@
89374
}]
89375
}
89376
89377
+# Return 1 if the target supports executing AVX instructions, 0
89378
+# otherwise. Cache the result.
89379
+
89380
+proc check_avx_hw_available { } {
89381
+ return [check_cached_effective_target avx_hw_available {
89382
+ # If this is not the right target then we can skip the test.
89383
+ if { !([istarget x86_64-*-*] || [istarget i?86-*-*]) } {
89384
+ expr 0
89385
+ } else {
89386
+ check_runtime_nocache avx_hw_available {
89387
+ #include "cpuid.h"
89388
+ int main ()
89389
+ {
89390
+ unsigned int eax, ebx, ecx, edx;
89391
+ if (__get_cpuid (1, &eax, &ebx, &ecx, &edx))
89392
+ return ((ecx & (bit_AVX | bit_OSXSAVE))
89393
+ != (bit_AVX | bit_OSXSAVE));
89394
+ return 1;
89395
+ }
89396
+ } ""
89397
+ }
89398
+ }]
89399
+}
89400
+
89401
# Return 1 if the target supports running SSE executables, 0 otherwise.
89402
89403
proc check_effective_target_sse_runtime { } {
89404
@@ -1025,6 +1049,16 @@
89405
}
89406
}
89407
89408
+# Return 1 if the target supports running AVX executables, 0 otherwise.
89409
+
89410
+proc check_effective_target_avx_runtime { } {
89411
+ if { [check_effective_target_avx]
89412
+ && [check_avx_hw_available] } {
89413
+ return 1
89414
+ }
89415
+ return 0
89416
+}
89417
+
89418
# Return 1 if the target supports executing VSX instructions, 0
89419
# otherwise. Cache the result.
89420
89421
@@ -1667,6 +1701,18 @@
78821
@@ -1712,6 +1712,18 @@
89422
78822
}]
89423
78823
}
89424
78824
89437
78837
# Return 1 if this is an ARM target supporting -mfpu=vfp
89438
78838
# -mfloat-abi=softfp. Some multilibs may be incompatible with these
89439
78839
# options.
89440
@@ -1695,19 +1741,87 @@
78840
@@ -1740,19 +1752,87 @@
89441
78841
}
89442
78842
}
89443
78843
89533
78933
}
89534
78934
89535
78935
# Return 1 is this is an ARM target where -mthumb causes Thumb-1 to be
89536
@@ -1746,7 +1860,7 @@
78936
@@ -1791,7 +1871,7 @@
89537
78937
: "0" (a), "w" (b));
89538
78938
return (a != 1);
89539
78939
}
89542
78942
}
89543
78943
89544
78944
# Return 1 if this is a ARM target with NEON enabled.
89545
@@ -2025,6 +2139,26 @@
78945
@@ -2070,6 +2150,26 @@
89546
78946
return $et_vect_shift_saved
89547
78947
}
89548
78948
89569
78969
# Return 1 if the target supports hardware vectors of long, 0 otherwise.
89570
78970
#
89571
78971
# This can change for different subtargets so do not cache the result.
89572
@@ -2444,7 +2578,8 @@
78972
@@ -2489,7 +2589,8 @@
89573
78973
if { ([istarget powerpc*-*-*] && ![istarget powerpc-*paired*])
89574
78974
|| [istarget i?86-*-*]
89575
78975
|| [istarget x86_64-*-*]
89579
78979
set et_vect_unpack_saved 1
89580
78980
}
89581
78981
}
89582
@@ -2484,7 +2619,7 @@
78982
@@ -2529,7 +2630,7 @@
89583
78983
if { [istarget mipsisa64*-*-*]
89584
78984
|| [istarget sparc*-*-*]
89585
78985
|| [istarget ia64-*-*]
89588
78988
set et_vect_no_align_saved 1
89589
78989
}
89590
78990
}
89591
@@ -2619,6 +2754,25 @@
78991
@@ -2664,6 +2765,25 @@
89592
78992
return $et_vector_alignment_reachable_for_64bit_saved
89593
78993
}
89594
78994
89614
79014
# Return 1 if the target supports vector conditional operations, 0 otherwise.
89615
79015
89616
79016
proc check_effective_target_vect_condition { } {
89617
@@ -3176,6 +3330,16 @@
79017
@@ -3221,6 +3341,16 @@
89618
79018
}
89619
79019
89620
79020
return $flags
89778
79178
/* If we have a path to EXIT, then we do return. */
89779
79179
if (TREE_THIS_VOLATILE (cfun->decl)
89780
79180
&& EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0)
89781
--- a/src/gcc/tree-data-ref.c
89782
+++ b/src/gcc/tree-data-ref.c
89783
@@ -4594,7 +4594,7 @@
89784
for (e = v->succ; e; e = e->succ_next)
89785
fprintf (file, " %d", e->dest);
89786
89787
- fprintf (file, ") \n");
89788
+ fprintf (file, ")\n");
89789
print_gimple_stmt (file, RDGV_STMT (v), 0, TDF_VOPS|TDF_MEMSYMS);
89790
fprintf (file, ")\n");
89791
}
89792
@@ -4991,6 +4991,38 @@
89793
free (bbs);
89794
}
89795
89796
+/* Returns true when the statement at STMT is of the form "A[i] = 0"
89797
+ that contains a data reference on its LHS with a stride of the same
89798
+ size as its unit type. */
89799
+
89800
+bool
89801
+stmt_with_adjacent_zero_store_dr_p (gimple stmt)
89802
+{
89803
+ tree op0, op1;
89804
+ bool res;
89805
+ struct data_reference *dr;
89806
+
89807
+ if (!stmt
89808
+ || !gimple_vdef (stmt)
89809
+ || !is_gimple_assign (stmt)
89810
+ || !gimple_assign_single_p (stmt)
89811
+ || !(op1 = gimple_assign_rhs1 (stmt))
89812
+ || !(integer_zerop (op1) || real_zerop (op1)))
89813
+ return false;
89814
+
89815
+ dr = XCNEW (struct data_reference);
89816
+ op0 = gimple_assign_lhs (stmt);
89817
+
89818
+ DR_STMT (dr) = stmt;
89819
+ DR_REF (dr) = op0;
89820
+
89821
+ res = dr_analyze_innermost (dr)
89822
+ && stride_of_unit_type_p (DR_STEP (dr), TREE_TYPE (op0));
89823
+
89824
+ free_data_ref (dr);
89825
+ return res;
89826
+}
89827
+
89828
/* For a data reference REF, return the declaration of its base
89829
address or NULL_TREE if the base is not determined. */
89830
89831
--- a/src/gcc/tree-data-ref.h
89832
+++ b/src/gcc/tree-data-ref.h
89833
@@ -567,6 +567,18 @@
89834
void remove_similar_memory_refs (VEC (gimple, heap) **);
89835
bool rdg_defs_used_in_other_loops_p (struct graph *, int);
89836
bool have_similar_memory_accesses (gimple, gimple);
89837
+bool stmt_with_adjacent_zero_store_dr_p (gimple);
89838
+
89839
+/* Returns true when STRIDE is equal in absolute value to the size of
89840
+ the unit type of TYPE. */
89841
+
89842
+static inline bool
89843
+stride_of_unit_type_p (tree stride, tree type)
89844
+{
89845
+ return tree_int_cst_equal (fold_unary (ABS_EXPR, TREE_TYPE (stride),
89846
+ stride),
89847
+ TYPE_SIZE_UNIT (type));
89848
+}
89849
89850
/* Determines whether RDG vertices V1 and V2 access to similar memory
89851
locations, in which case they have to be in the same partition. */
89852
79181
--- a/src/gcc/tree-if-switch-conversion.c
89853
79182
+++ b/src/gcc/tree-if-switch-conversion.c
89854
79183
@@ -0,0 +1,643 @@
90505
79834
&& TREE_CODE (SSA_NAME_VAR (name)) != PARM_DECL
90506
79835
&& (id->entry_bb != EDGE_SUCC (ENTRY_BLOCK_PTR, 0)->dest
90507
79836
|| EDGE_COUNT (id->entry_bb->preds) != 1))
90508
@@ -3067,7 +3068,7 @@
90509
/* Don't auto-inline anything that might not be bound within
90510
this unit of translation. */
90511
else if (!DECL_DECLARED_INLINE_P (fn)
90512
- && DECL_REPLACEABLE_P (fn))
90513
+ && decl_replaceable_p (fn))
90514
inlinable = false;
90515
90516
else if (!function_attribute_inlinable_p (fn))
90517
79837
@@ -3206,6 +3207,8 @@
90518
79838
case WIDEN_SUM_EXPR:
90519
79839
case WIDEN_MULT_EXPR:
90571
79891
+extern HOST_WIDE_INT estimated_stack_frame_size (tree);
90572
79892
90573
79893
#endif /* GCC_TREE_INLINE_H */
90574
--- a/src/gcc/tree-loop-distribution.c
90575
+++ b/src/gcc/tree-loop-distribution.c
90576
@@ -251,7 +251,7 @@
90577
90578
/* Generate a call to memset. Return true when the operation succeeded. */
90579
90580
-static bool
90581
+static void
90582
generate_memset_zero (gimple stmt, tree op0, tree nb_iter,
90583
gimple_stmt_iterator bsi)
90584
{
90585
@@ -265,45 +265,27 @@
90586
90587
DR_STMT (dr) = stmt;
90588
DR_REF (dr) = op0;
90589
- if (!dr_analyze_innermost (dr))
90590
- goto end;
90591
+ res = dr_analyze_innermost (dr);
90592
+ gcc_assert (res && stride_of_unit_type_p (DR_STEP (dr), TREE_TYPE (op0)));
90593
90594
- /* Test for a positive stride, iterating over every element. */
90595
- if (integer_zerop (size_binop (MINUS_EXPR,
90596
- fold_convert (sizetype, DR_STEP (dr)),
90597
- TYPE_SIZE_UNIT (TREE_TYPE (op0)))))
90598
- {
90599
- addr_base = fold_convert_loc (loc, sizetype,
90600
- size_binop_loc (loc, PLUS_EXPR,
90601
- DR_OFFSET (dr),
90602
- DR_INIT (dr)));
90603
- addr_base = fold_build2_loc (loc, POINTER_PLUS_EXPR,
90604
- TREE_TYPE (DR_BASE_ADDRESS (dr)),
90605
- DR_BASE_ADDRESS (dr), addr_base);
90606
-
90607
- nb_bytes = build_size_arg_loc (loc, nb_iter, op0, &stmt_list);
90608
- }
90609
+ nb_bytes = build_size_arg_loc (loc, nb_iter, op0, &stmt_list);
90610
+ addr_base = size_binop_loc (loc, PLUS_EXPR, DR_OFFSET (dr), DR_INIT (dr));
90611
+ addr_base = fold_convert_loc (loc, sizetype, addr_base);
90612
90613
/* Test for a negative stride, iterating over every element. */
90614
- else if (integer_zerop (size_binop (PLUS_EXPR,
90615
- TYPE_SIZE_UNIT (TREE_TYPE (op0)),
90616
- fold_convert (sizetype, DR_STEP (dr)))))
90617
+ if (integer_zerop (size_binop (PLUS_EXPR,
90618
+ TYPE_SIZE_UNIT (TREE_TYPE (op0)),
90619
+ fold_convert (sizetype, DR_STEP (dr)))))
90620
{
90621
- nb_bytes = build_size_arg_loc (loc, nb_iter, op0, &stmt_list);
90622
-
90623
- addr_base = size_binop_loc (loc, PLUS_EXPR, DR_OFFSET (dr), DR_INIT (dr));
90624
- addr_base = fold_convert_loc (loc, sizetype, addr_base);
90625
addr_base = size_binop_loc (loc, MINUS_EXPR, addr_base,
90626
fold_convert_loc (loc, sizetype, nb_bytes));
90627
addr_base = size_binop_loc (loc, PLUS_EXPR, addr_base,
90628
TYPE_SIZE_UNIT (TREE_TYPE (op0)));
90629
- addr_base = fold_build2_loc (loc, POINTER_PLUS_EXPR,
90630
- TREE_TYPE (DR_BASE_ADDRESS (dr)),
90631
- DR_BASE_ADDRESS (dr), addr_base);
90632
}
90633
- else
90634
- goto end;
90635
90636
+ addr_base = fold_build2_loc (loc, POINTER_PLUS_EXPR,
90637
+ TREE_TYPE (DR_BASE_ADDRESS (dr)),
90638
+ DR_BASE_ADDRESS (dr), addr_base);
90639
mem = force_gimple_operand (addr_base, &stmts, true, NULL);
90640
gimple_seq_add_seq (&stmt_list, stmts);
90641
90642
@@ -311,14 +293,11 @@
90643
fn_call = gimple_build_call (fn, 3, mem, integer_zero_node, nb_bytes);
90644
gimple_seq_add_stmt (&stmt_list, fn_call);
90645
gsi_insert_seq_after (&bsi, stmt_list, GSI_CONTINUE_LINKING);
90646
- res = true;
90647
90648
if (dump_file && (dump_flags & TDF_DETAILS))
90649
fprintf (dump_file, "generated memset zero\n");
90650
90651
- end:
90652
free_data_ref (dr);
90653
- return res;
90654
}
90655
90656
/* Tries to generate a builtin function for the instructions of LOOP
90657
@@ -332,7 +311,6 @@
90658
unsigned i, x = 0;
90659
basic_block *bbs;
90660
gimple write = NULL;
90661
- tree op0, op1;
90662
gimple_stmt_iterator bsi;
90663
tree nb_iter = number_of_exit_cond_executions (loop);
90664
90665
@@ -368,26 +346,17 @@
90666
}
90667
}
90668
90669
- if (!write)
90670
- goto end;
90671
-
90672
- op0 = gimple_assign_lhs (write);
90673
- op1 = gimple_assign_rhs1 (write);
90674
-
90675
- if (!(TREE_CODE (op0) == ARRAY_REF
90676
- || TREE_CODE (op0) == INDIRECT_REF))
90677
+ if (!stmt_with_adjacent_zero_store_dr_p (write))
90678
goto end;
90679
90680
/* The new statements will be placed before LOOP. */
90681
bsi = gsi_last_bb (loop_preheader_edge (loop)->src);
90682
-
90683
- if (gimple_assign_rhs_code (write) == INTEGER_CST
90684
- && (integer_zerop (op1) || real_zerop (op1)))
90685
- res = generate_memset_zero (write, op0, nb_iter, bsi);
90686
+ generate_memset_zero (write, gimple_assign_lhs (write), nb_iter, bsi);
90687
+ res = true;
90688
90689
/* If this is the last partition for which we generate code, we have
90690
to destroy the loop. */
90691
- if (res && !copy_p)
90692
+ if (!copy_p)
90693
{
90694
unsigned nbbs = loop->num_nodes;
90695
edge exit = single_exit (loop);
90696
@@ -531,24 +500,6 @@
90697
static void rdg_flag_vertex_and_dependent (struct graph *, int, bitmap, bitmap,
90698
bitmap, bool *);
90699
90700
-/* Flag all the uses of U. */
90701
-
90702
-static void
90703
-rdg_flag_all_uses (struct graph *rdg, int u, bitmap partition, bitmap loops,
90704
- bitmap processed, bool *part_has_writes)
90705
-{
90706
- struct graph_edge *e;
90707
-
90708
- for (e = rdg->vertices[u].succ; e; e = e->succ_next)
90709
- if (!bitmap_bit_p (processed, e->dest))
90710
- {
90711
- rdg_flag_vertex_and_dependent (rdg, e->dest, partition, loops,
90712
- processed, part_has_writes);
90713
- rdg_flag_all_uses (rdg, e->dest, partition, loops, processed,
90714
- part_has_writes);
90715
- }
90716
-}
90717
-
90718
/* Flag the uses of U stopping following the information from
90719
upstream_mem_writes. */
90720
90721
@@ -720,68 +671,13 @@
90722
}
90723
}
90724
90725
-/* Flag all the nodes of RDG containing memory accesses that could
90726
- potentially belong to arrays already accessed in the current
90727
- PARTITION. */
90728
-
90729
-static void
90730
-rdg_flag_similar_memory_accesses (struct graph *rdg, bitmap partition,
90731
- bitmap loops, bitmap processed,
90732
- VEC (int, heap) **other_stores)
90733
-{
90734
- bool foo;
90735
- unsigned i, n;
90736
- int j, k, kk;
90737
- bitmap_iterator ii;
90738
- struct graph_edge *e;
90739
-
90740
- EXECUTE_IF_SET_IN_BITMAP (partition, 0, i, ii)
90741
- if (RDG_MEM_WRITE_STMT (rdg, i)
90742
- || RDG_MEM_READS_STMT (rdg, i))
90743
- {
90744
- for (j = 0; j < rdg->n_vertices; j++)
90745
- if (!bitmap_bit_p (processed, j)
90746
- && (RDG_MEM_WRITE_STMT (rdg, j)
90747
- || RDG_MEM_READS_STMT (rdg, j))
90748
- && rdg_has_similar_memory_accesses (rdg, i, j))
90749
- {
90750
- /* Flag first the node J itself, and all the nodes that
90751
- are needed to compute J. */
90752
- rdg_flag_vertex_and_dependent (rdg, j, partition, loops,
90753
- processed, &foo);
90754
-
90755
- /* When J is a read, we want to coalesce in the same
90756
- PARTITION all the nodes that are using J: this is
90757
- needed for better cache locality. */
90758
- rdg_flag_all_uses (rdg, j, partition, loops, processed, &foo);
90759
-
90760
- /* Remove from OTHER_STORES the vertex that we flagged. */
90761
- if (RDG_MEM_WRITE_STMT (rdg, j))
90762
- for (k = 0; VEC_iterate (int, *other_stores, k, kk); k++)
90763
- if (kk == j)
90764
- {
90765
- VEC_unordered_remove (int, *other_stores, k);
90766
- break;
90767
- }
90768
- }
90769
-
90770
- /* If the node I has two uses, then keep these together in the
90771
- same PARTITION. */
90772
- for (n = 0, e = rdg->vertices[i].succ; e; e = e->succ_next, n++);
90773
-
90774
- if (n > 1)
90775
- rdg_flag_all_uses (rdg, i, partition, loops, processed, &foo);
90776
- }
90777
-}
90778
-
90779
/* Returns a bitmap in which all the statements needed for computing
90780
the strongly connected component C of the RDG are flagged, also
90781
including the loop exit conditions. */
90782
90783
static bitmap
90784
build_rdg_partition_for_component (struct graph *rdg, rdgc c,
90785
- bool *part_has_writes,
90786
- VEC (int, heap) **other_stores)
90787
+ bool *part_has_writes)
90788
{
90789
int i, v;
90790
bitmap partition = BITMAP_ALLOC (NULL);
90791
@@ -793,13 +689,6 @@
90792
rdg_flag_vertex_and_dependent (rdg, v, partition, loops, processed,
90793
part_has_writes);
90794
90795
- /* Also iterate on the array of stores not in the starting vertices,
90796
- and determine those vertices that have some memory affinity with
90797
- the current nodes in the component: these are stores to the same
90798
- arrays, i.e. we're taking care of cache locality. */
90799
- rdg_flag_similar_memory_accesses (rdg, partition, loops, processed,
90800
- other_stores);
90801
-
90802
rdg_flag_loop_exits (rdg, loops, partition, processed, part_has_writes);
90803
90804
BITMAP_FREE (processed);
90805
@@ -863,6 +752,79 @@
90806
BITMAP_FREE (saved_components);
90807
}
90808
90809
+/* Returns true when it is possible to generate a builtin pattern for
90810
+ the PARTITION of RDG. For the moment we detect only the memset
90811
+ zero pattern. */
90812
+
90813
+static bool
90814
+can_generate_builtin (struct graph *rdg, bitmap partition)
90815
+{
90816
+ unsigned i;
90817
+ bitmap_iterator bi;
90818
+ int nb_reads = 0;
90819
+ int nb_writes = 0;
90820
+ int stores_zero = 0;
90821
+
90822
+ EXECUTE_IF_SET_IN_BITMAP (partition, 0, i, bi)
90823
+ if (RDG_MEM_READS_STMT (rdg, i))
90824
+ nb_reads++;
90825
+ else if (RDG_MEM_WRITE_STMT (rdg, i))
90826
+ {
90827
+ nb_writes++;
90828
+ if (stmt_with_adjacent_zero_store_dr_p (RDG_STMT (rdg, i)))
90829
+ stores_zero++;
90830
+ }
90831
+
90832
+ return stores_zero == 1 && nb_writes == 1 && nb_reads == 0;
90833
+}
90834
+
90835
+/* Returns true when PARTITION1 and PARTITION2 have similar memory
90836
+ accesses in RDG. */
90837
+
90838
+static bool
90839
+similar_memory_accesses (struct graph *rdg, bitmap partition1,
90840
+ bitmap partition2)
90841
+{
90842
+ unsigned i, j;
90843
+ bitmap_iterator bi, bj;
90844
+
90845
+ EXECUTE_IF_SET_IN_BITMAP (partition1, 0, i, bi)
90846
+ if (RDG_MEM_WRITE_STMT (rdg, i)
90847
+ || RDG_MEM_READS_STMT (rdg, i))
90848
+ EXECUTE_IF_SET_IN_BITMAP (partition2, 0, j, bj)
90849
+ if (RDG_MEM_WRITE_STMT (rdg, j)
90850
+ || RDG_MEM_READS_STMT (rdg, j))
90851
+ if (rdg_has_similar_memory_accesses (rdg, i, j))
90852
+ return true;
90853
+
90854
+ return false;
90855
+}
90856
+
90857
+/* Fuse all the partitions from PARTITIONS that contain similar memory
90858
+ references, i.e., we're taking care of cache locality. This
90859
+ function does not fuse those partitions that contain patterns that
90860
+ can be code generated with builtins. */
90861
+
90862
+static void
90863
+fuse_partitions_with_similar_memory_accesses (struct graph *rdg,
90864
+ VEC (bitmap, heap) **partitions)
90865
+{
90866
+ int p1, p2;
90867
+ bitmap partition1, partition2;
90868
+
90869
+ for (p1 = 0; VEC_iterate (bitmap, *partitions, p1, partition1); p1++)
90870
+ if (!can_generate_builtin (rdg, partition1))
90871
+ for (p2 = 0; VEC_iterate (bitmap, *partitions, p2, partition2); p2++)
90872
+ if (p1 != p2
90873
+ && !can_generate_builtin (rdg, partition2)
90874
+ && similar_memory_accesses (rdg, partition1, partition2))
90875
+ {
90876
+ bitmap_ior_into (partition1, partition2);
90877
+ VEC_ordered_remove (bitmap, *partitions, p2);
90878
+ p2--;
90879
+ }
90880
+}
90881
+
90882
/* Aggregate several components into a useful partition that is
90883
registered in the PARTITIONS vector. Partitions will be
90884
distributed in different loops. */
90885
@@ -885,8 +847,7 @@
90886
if (bitmap_bit_p (processed, v))
90887
continue;
90888
90889
- np = build_rdg_partition_for_component (rdg, x, &part_has_writes,
90890
- other_stores);
90891
+ np = build_rdg_partition_for_component (rdg, x, &part_has_writes);
90892
bitmap_ior_into (partition, np);
90893
bitmap_ior_into (processed, np);
90894
BITMAP_FREE (np);
90895
@@ -932,6 +893,8 @@
90896
VEC_safe_push (bitmap, heap, *partitions, partition);
90897
else
90898
BITMAP_FREE (partition);
90899
+
90900
+ fuse_partitions_with_similar_memory_accesses (rdg, partitions);
90901
}
90902
90903
/* Dump to FILE the PARTITIONS. */
90904
79894
--- a/src/gcc/tree-pass.h
90905
79895
+++ b/src/gcc/tree-pass.h
90906
79896
@@ -407,6 +407,7 @@
90986
79976
if (!is_gimple_reg_type (ft)
90987
79977
&& !type_consists_of_records_p (ft))
90988
79978
return false;
90989
@@ -3413,7 +3416,10 @@
90990
else if (ac2->size != access->size)
90991
return NULL;
90992
90993
- if (access_precludes_ipa_sra_p (ac2))
90994
+ if (access_precludes_ipa_sra_p (ac2)
90995
+ || (ac2->type != access->type
90996
+ && (TREE_ADDRESSABLE (ac2->type)
90997
+ || TREE_ADDRESSABLE (access->type))))
90998
return NULL;
90999
91000
modification |= ac2->write;
91001
@@ -4125,6 +4131,13 @@
79979
@@ -4128,6 +4131,13 @@
91002
79980
static bool
91003
79981
ipa_sra_preliminary_function_checks (struct cgraph_node *node)
91004
79982
{
92193
81171
/* Try to optimize out __builtin_stack_restore. Optimize it out
92194
81172
if there is another __builtin_stack_restore in the same basic
92195
81173
block and no calls or ASM_EXPRs are in between, or if this block's
92196
@@ -3355,7 +4440,9 @@
92197
is replaced. If the call is expected to produces a result, then it
92198
is replaced by an assignment of the new RHS to the result variable.
92199
If the result is to be ignored, then the call is replaced by a
92200
- GIMPLE_NOP. */
92201
+ GIMPLE_NOP. A proper VDEF chain is retained by making the first
92202
+ VUSE and the last VDEF of the whole sequence be the same as the replaced
92203
+ statement and using new SSA names for stores in between. */
92204
92205
static void
92206
gimplify_and_update_call_from_tree (gimple_stmt_iterator *si_p, tree expr)
92207
@@ -3366,17 +4453,36 @@
92208
gimple_stmt_iterator i;
92209
gimple_seq stmts = gimple_seq_alloc();
92210
struct gimplify_ctx gctx;
92211
+ gimple last = NULL;
92212
+ gimple laststore = NULL;
92213
+ tree reaching_vuse;
92214
92215
stmt = gsi_stmt (*si_p);
92216
92217
gcc_assert (is_gimple_call (stmt));
92218
92219
lhs = gimple_call_lhs (stmt);
92220
+ reaching_vuse = gimple_vuse (stmt);
92221
92222
push_gimplify_context (&gctx);
92223
92224
if (lhs == NULL_TREE)
92225
- gimplify_and_add (expr, &stmts);
92226
+ {
92227
+ gimplify_and_add (expr, &stmts);
92228
+ /* We can end up with folding a memcpy of an empty class assignment
92229
+ which gets optimized away by C++ gimplification. */
92230
+ if (gimple_seq_empty_p (stmts))
92231
+ {
92232
+ pop_gimplify_context (NULL);
92233
+ if (gimple_in_ssa_p (cfun))
92234
+ {
92235
+ unlink_stmt_vdef (stmt);
92236
+ release_defs (stmt);
92237
+ }
92238
+ gsi_remove (si_p, true);
92239
+ return;
92240
+ }
92241
+ }
92242
else
92243
tmp = get_initialized_tmp_var (expr, &stmts, NULL);
92244
92245
@@ -3387,26 +4493,95 @@
92246
92247
/* The replacement can expose previously unreferenced variables. */
92248
for (i = gsi_start (stmts); !gsi_end_p (i); gsi_next (&i))
92249
- {
92250
- new_stmt = gsi_stmt (i);
92251
- find_new_referenced_vars (new_stmt);
92252
- gsi_insert_before (si_p, new_stmt, GSI_NEW_STMT);
92253
- mark_symbols_for_renaming (new_stmt);
92254
- gsi_next (si_p);
92255
- }
92256
+ {
92257
+ if (last)
92258
+ {
92259
+ gsi_insert_before (si_p, last, GSI_NEW_STMT);
92260
+ gsi_next (si_p);
92261
+ }
92262
+ new_stmt = gsi_stmt (i);
92263
+ if (gimple_in_ssa_p (cfun))
92264
+ {
92265
+ find_new_referenced_vars (new_stmt);
92266
+ mark_symbols_for_renaming (new_stmt);
92267
+ }
92268
+ /* If the new statement has a VUSE, update it with exact SSA name we
92269
+ know will reach this one. */
92270
+ if (gimple_vuse (new_stmt))
92271
+ {
92272
+ /* If we've also seen a previous store create a new VDEF for
92273
+ the latter one, and make that the new reaching VUSE. */
92274
+ if (laststore)
92275
+ {
92276
+ reaching_vuse = make_ssa_name (gimple_vop (cfun), laststore);
92277
+ gimple_set_vdef (laststore, reaching_vuse);
92278
+ update_stmt (laststore);
92279
+ laststore = NULL;
92280
+ }
92281
+ gimple_set_vuse (new_stmt, reaching_vuse);
92282
+ gimple_set_modified (new_stmt, true);
92283
+ }
92284
+ if (gimple_assign_single_p (new_stmt)
92285
+ && !is_gimple_reg (gimple_assign_lhs (new_stmt)))
92286
+ {
92287
+ laststore = new_stmt;
92288
+ }
92289
+ last = new_stmt;
92290
+ }
92291
92292
if (lhs == NULL_TREE)
92293
{
92294
- new_stmt = gimple_build_nop ();
92295
- unlink_stmt_vdef (stmt);
92296
- release_defs (stmt);
92297
+ /* If we replace a call without LHS that has a VDEF and our new
92298
+ sequence ends with a store we must make that store have the same
92299
+ vdef in order not to break the sequencing. This can happen
92300
+ for instance when folding memcpy calls into assignments. */
92301
+ if (gimple_vdef (stmt) && laststore)
92302
+ {
92303
+ gimple_set_vdef (laststore, gimple_vdef (stmt));
92304
+ if (TREE_CODE (gimple_vdef (stmt)) == SSA_NAME)
92305
+ SSA_NAME_DEF_STMT (gimple_vdef (stmt)) = laststore;
92306
+ update_stmt (laststore);
92307
+ }
92308
+ else if (gimple_in_ssa_p (cfun))
92309
+ {
92310
+ unlink_stmt_vdef (stmt);
92311
+ release_defs (stmt);
92312
+ }
92313
+ new_stmt = last;
92314
}
92315
else
92316
{
92317
+ if (last)
92318
+ {
92319
+ gsi_insert_before (si_p, last, GSI_NEW_STMT);
92320
+ gsi_next (si_p);
92321
+ }
92322
+ if (laststore && is_gimple_reg (lhs))
92323
+ {
92324
+ gimple_set_vdef (laststore, gimple_vdef (stmt));
92325
+ update_stmt (laststore);
92326
+ if (TREE_CODE (gimple_vdef (stmt)) == SSA_NAME)
92327
+ SSA_NAME_DEF_STMT (gimple_vdef (stmt)) = laststore;
92328
+ laststore = NULL;
92329
+ }
92330
+ else if (laststore)
92331
+ {
92332
+ reaching_vuse = make_ssa_name (gimple_vop (cfun), laststore);
92333
+ gimple_set_vdef (laststore, reaching_vuse);
92334
+ update_stmt (laststore);
92335
+ laststore = NULL;
92336
+ }
92337
new_stmt = gimple_build_assign (lhs, tmp);
92338
- gimple_set_vuse (new_stmt, gimple_vuse (stmt));
92339
- gimple_set_vdef (new_stmt, gimple_vdef (stmt));
92340
- move_ssa_defining_stmt_for_defs (new_stmt, stmt);
92341
+ if (!is_gimple_reg (tmp))
92342
+ gimple_set_vuse (new_stmt, reaching_vuse);
92343
+ if (!is_gimple_reg (lhs))
92344
+ {
92345
+ gimple_set_vdef (new_stmt, gimple_vdef (stmt));
92346
+ if (TREE_CODE (gimple_vdef (stmt)) == SSA_NAME)
92347
+ SSA_NAME_DEF_STMT (gimple_vdef (stmt)) = new_stmt;
92348
+ }
92349
+ else if (reaching_vuse == gimple_vuse (stmt))
92350
+ unlink_stmt_vdef (stmt);
92351
}
92352
92353
gimple_set_location (new_stmt, gimple_location (stmt));
92354
--- a/src/gcc/tree-ssa-copyrename.c
92355
+++ b/src/gcc/tree-ssa-copyrename.c
92356
@@ -225,11 +225,16 @@
92357
ign2 = false;
92358
}
92359
92360
- /* Don't coalesce if the two variables are not of the same type. */
92361
- if (TREE_TYPE (root1) != TREE_TYPE (root2))
92362
+ /* Don't coalesce if the two variables aren't type compatible . */
92363
+ if (!types_compatible_p (TREE_TYPE (root1), TREE_TYPE (root2))
92364
+ /* There is a disconnect between the middle-end type-system and
92365
+ VRP, avoid coalescing enum types with different bounds. */
92366
+ || ((TREE_CODE (TREE_TYPE (root1)) == ENUMERAL_TYPE
92367
+ || TREE_CODE (TREE_TYPE (root2)) == ENUMERAL_TYPE)
92368
+ && TREE_TYPE (root1) != TREE_TYPE (root2)))
92369
{
92370
if (debug)
92371
- fprintf (debug, " : Different types. No coalesce.\n");
92372
+ fprintf (debug, " : Incompatible types. No coalesce.\n");
92373
return false;
92374
}
92375
92376
81174
--- a/src/gcc/tree-ssa-dom.c
92377
81175
+++ b/src/gcc/tree-ssa-dom.c
92378
81176
@@ -54,6 +54,7 @@
92603
81401
return false;
92604
81402
t = canonicalize_cond_expr_cond (t);
92605
81403
if (!t)
92606
--- a/src/gcc/tree-ssa-loop-im.c
92607
+++ b/src/gcc/tree-ssa-loop-im.c
92608
@@ -2139,7 +2139,7 @@
92609
edge ex;
92610
92611
for (i = 0; VEC_iterate (edge, exits, i, ex); i++)
92612
- if (ex->flags & EDGE_ABNORMAL)
92613
+ if (ex->flags & (EDGE_ABNORMAL | EDGE_EH))
92614
return false;
92615
92616
return true;
92617
81404
--- a/src/gcc/tree-ssa-loop-ivopts.c
92618
81405
+++ b/src/gcc/tree-ssa-loop-ivopts.c
92619
81406
@@ -257,6 +257,9 @@
93201
81988
}
93202
81989
93203
81990
case FUNCTION_DECL:
93204
--- a/src/gcc/tree-ssa-pre.c
93205
+++ b/src/gcc/tree-ssa-pre.c
93206
@@ -1701,7 +1701,7 @@
93207
tree result = vn_reference_lookup_pieces (newvuse, ref->set,
93208
ref->type,
93209
newoperands,
93210
- &newref, true);
93211
+ &newref, VN_WALK);
93212
if (newref)
93213
VEC_free (vn_reference_op_s, heap, newoperands);
93214
93215
@@ -2558,6 +2558,10 @@
93216
{
93217
if (dump_file && (dump_flags & TDF_DETAILS))
93218
fprintf (dump_file, "Starting iteration %d\n", num_iterations);
93219
+ /* ??? We need to clear our PHI translation cache here as the
93220
+ ANTIC sets shrink and we restrict valid translations to
93221
+ those having operands with leaders in ANTIC. Same below
93222
+ for PA ANTIC computation. */
93223
num_iterations++;
93224
changed = false;
93225
for (i = n_basic_blocks - NUM_FIXED_BLOCKS - 1; i >= 0; i--)
93226
@@ -3965,7 +3969,7 @@
93227
copy_reference_ops_from_call (stmt, &ops);
93228
vn_reference_lookup_pieces (gimple_vuse (stmt), 0,
93229
gimple_expr_type (stmt),
93230
- ops, &ref, false);
93231
+ ops, &ref, VN_NOWALK);
93232
VEC_free (vn_reference_op_s, heap, ops);
93233
if (!ref)
93234
continue;
93235
@@ -4035,7 +4039,7 @@
93236
93237
vn_reference_lookup (gimple_assign_rhs1 (stmt),
93238
gimple_vuse (stmt),
93239
- true, &ref);
93240
+ VN_WALK, &ref);
93241
if (!ref)
93242
continue;
93243
93244
@@ -4265,7 +4269,7 @@
93245
tree rhs = gimple_assign_rhs1 (stmt);
93246
tree val;
93247
val = vn_reference_lookup (gimple_assign_lhs (stmt),
93248
- gimple_vuse (stmt), true, NULL);
93249
+ gimple_vuse (stmt), VN_WALK, NULL);
93250
if (TREE_CODE (rhs) == SSA_NAME)
93251
rhs = VN_INFO (rhs)->valnum;
93252
if (val
93253
@@ -4755,7 +4759,7 @@
93254
if (!do_fre)
93255
loop_optimizer_init (LOOPS_NORMAL);
93256
93257
- if (!run_scc_vn (do_fre))
93258
+ if (!run_scc_vn (do_fre, do_fre ? VN_WALKREWRITE : VN_WALK))
93259
{
93260
if (!do_fre)
93261
{
93262
81991
--- a/src/gcc/tree-ssa-reassoc.c
93263
81992
+++ b/src/gcc/tree-ssa-reassoc.c
93264
81993
@@ -1159,6 +1159,117 @@
93391
82120
return;
93392
82121
--- a/src/gcc/tree-ssa-sccvn.c
93393
82122
+++ b/src/gcc/tree-ssa-sccvn.c
93394
@@ -988,6 +988,8 @@
93395
}
93396
93397
static tree *last_vuse_ptr;
93398
+static vn_lookup_kind vn_walk_kind;
93399
+static vn_lookup_kind default_vn_walk_kind;
93400
93401
/* Callback for walk_non_aliased_vuses. Adjusts the vn_reference_t VR_
93402
with the current VUSE and performs the expression lookup. */
93403
@@ -1063,6 +1065,7 @@
93404
size2 = TREE_INT_CST_LOW (gimple_call_arg (def_stmt, 2)) * 8;
93405
if ((unsigned HOST_WIDE_INT)size2 / 8
93406
== TREE_INT_CST_LOW (gimple_call_arg (def_stmt, 2))
93407
+ && maxsize2 != -1
93408
&& operand_equal_p (base, base2, 0)
93409
&& offset2 <= offset
93410
&& offset2 + size2 >= offset + maxsize)
93411
@@ -1086,7 +1089,8 @@
93412
HOST_WIDE_INT offset2, size2, maxsize2;
93413
base2 = get_ref_base_and_extent (gimple_assign_lhs (def_stmt),
93414
&offset2, &size2, &maxsize2);
93415
- if (operand_equal_p (base, base2, 0)
93416
+ if (maxsize2 != -1
93417
+ && operand_equal_p (base, base2, 0)
93418
&& offset2 <= offset
93419
&& offset2 + size2 >= offset + maxsize)
93420
{
93421
@@ -1101,7 +1105,8 @@
93422
93423
/* For aggregate copies translate the reference through them if
93424
the copy kills ref. */
93425
- else if (gimple_assign_single_p (def_stmt)
93426
+ else if (vn_walk_kind == VN_WALKREWRITE
93427
+ && gimple_assign_single_p (def_stmt)
93428
&& (DECL_P (gimple_assign_rhs1 (def_stmt))
93429
|| INDIRECT_REF_P (gimple_assign_rhs1 (def_stmt))
93430
|| handled_component_p (gimple_assign_rhs1 (def_stmt))))
93431
@@ -1116,7 +1121,8 @@
93432
/* See if the assignment kills REF. */
93433
base2 = get_ref_base_and_extent (gimple_assign_lhs (def_stmt),
93434
&offset2, &size2, &maxsize2);
93435
- if (!operand_equal_p (base, base2, 0)
93436
+ if (maxsize2 == -1
93437
+ || !operand_equal_p (base, base2, 0)
93438
|| offset2 > offset
93439
|| offset2 + size2 < offset + maxsize)
93440
return (void *)-1;
93441
@@ -1190,7 +1196,7 @@
93442
tree
93443
vn_reference_lookup_pieces (tree vuse, alias_set_type set, tree type,
93444
VEC (vn_reference_op_s, heap) *operands,
93445
- vn_reference_t *vnresult, bool maywalk)
93446
+ vn_reference_t *vnresult, vn_lookup_kind kind)
93447
{
93448
struct vn_reference_s vr1;
93449
vn_reference_t tmp;
93450
@@ -1215,10 +1221,11 @@
93451
vn_reference_lookup_1 (&vr1, vnresult);
93452
93453
if (!*vnresult
93454
- && maywalk
93455
+ && kind != VN_NOWALK
93456
&& vr1.vuse)
93457
{
93458
ao_ref r;
93459
+ vn_walk_kind = kind;
93460
if (ao_ref_init_from_vn_reference (&r, set, type, vr1.operands))
93461
*vnresult =
93462
(vn_reference_t)walk_non_aliased_vuses (&r, vr1.vuse,
93463
@@ -1241,7 +1248,7 @@
93464
stored in the hashtable if one exists. */
93465
93466
tree
93467
-vn_reference_lookup (tree op, tree vuse, bool maywalk,
93468
+vn_reference_lookup (tree op, tree vuse, vn_lookup_kind kind,
93469
vn_reference_t *vnresult)
93470
{
93471
VEC (vn_reference_op_s, heap) *operands;
93472
@@ -1256,12 +1263,13 @@
93473
vr1.set = get_alias_set (op);
93474
vr1.hashcode = vn_reference_compute_hash (&vr1);
93475
93476
- if (maywalk
93477
+ if (kind != VN_NOWALK
93478
&& vr1.vuse)
93479
{
93480
vn_reference_t wvnresult;
93481
ao_ref r;
93482
ao_ref_init (&r, op);
93483
+ vn_walk_kind = kind;
93484
wvnresult =
93485
(vn_reference_t)walk_non_aliased_vuses (&r, vr1.vuse,
93486
vn_reference_lookup_2,
93487
@@ -1980,14 +1988,15 @@
93488
93489
last_vuse = gimple_vuse (stmt);
93490
last_vuse_ptr = &last_vuse;
93491
- result = vn_reference_lookup (op, gimple_vuse (stmt), true, NULL);
93492
+ result = vn_reference_lookup (op, gimple_vuse (stmt),
93493
+ default_vn_walk_kind, NULL);
93494
last_vuse_ptr = NULL;
93495
93496
/* If we have a VCE, try looking up its operand as it might be stored in
93497
a different type. */
93498
if (!result && TREE_CODE (op) == VIEW_CONVERT_EXPR)
93499
result = vn_reference_lookup (TREE_OPERAND (op, 0), gimple_vuse (stmt),
93500
- true, NULL);
93501
+ default_vn_walk_kind, NULL);
93502
93503
/* We handle type-punning through unions by value-numbering based
93504
on offset and size of the access. Be prepared to handle a
93505
@@ -2098,7 +2107,7 @@
93506
Otherwise, the vdefs for the store are used when inserting into
93507
the table, since the store generates a new memory state. */
93508
93509
- result = vn_reference_lookup (lhs, gimple_vuse (stmt), false, NULL);
93510
+ result = vn_reference_lookup (lhs, gimple_vuse (stmt), VN_NOWALK, NULL);
93511
93512
if (result)
93513
{
93514
@@ -2277,6 +2286,10 @@
82123
@@ -2286,6 +2286,10 @@
93515
82124
case GIMPLE_BINARY_RHS:
93516
82125
return (is_gimple_min_invariant (gimple_assign_rhs1 (stmt))
93517
82126
|| is_gimple_min_invariant (gimple_assign_rhs2 (stmt)));
93522
82131
case GIMPLE_SINGLE_RHS:
93523
82132
/* Constants inside reference ops are rarely interesting, but
93524
82133
it can take a lot of looking to find them. */
93525
@@ -3186,16 +3199,18 @@
93526
}
93527
93528
/* Do SCCVN. Returns true if it finished, false if we bailed out
93529
- due to resource constraints. */
93530
+ due to resource constraints. DEFAULT_VN_WALK_KIND_ specifies
93531
+ how we use the alias oracle walking during the VN process. */
93532
93533
bool
93534
-run_scc_vn (bool may_insert_arg)
93535
+run_scc_vn (bool may_insert_arg, vn_lookup_kind default_vn_walk_kind_)
93536
{
93537
size_t i;
93538
tree param;
93539
bool changed = true;
93540
93541
may_insert = may_insert_arg;
93542
+ default_vn_walk_kind = default_vn_walk_kind_;
93543
93544
init_scc_vn ();
93545
current_info = valid_info;
93546
--- a/src/gcc/tree-ssa-sccvn.h
93547
+++ b/src/gcc/tree-ssa-sccvn.h
93548
@@ -163,11 +163,13 @@
93549
unsigned needs_insertion : 1;
93550
} *vn_ssa_aux_t;
93551
93552
+typedef enum { VN_NOWALK, VN_WALK, VN_WALKREWRITE } vn_lookup_kind;
93553
+
93554
/* Return the value numbering info for an SSA_NAME. */
93555
extern vn_ssa_aux_t VN_INFO (tree);
93556
extern vn_ssa_aux_t VN_INFO_GET (tree);
93557
tree vn_get_expr_for (tree);
93558
-bool run_scc_vn (bool);
93559
+bool run_scc_vn (bool, vn_lookup_kind);
93560
void free_scc_vn (void);
93561
tree vn_nary_op_lookup (tree, vn_nary_op_t *);
93562
tree vn_nary_op_lookup_stmt (gimple, vn_nary_op_t *);
93563
@@ -187,8 +189,8 @@
93564
VEC (vn_reference_op_s, heap) *);
93565
tree vn_reference_lookup_pieces (tree, alias_set_type, tree,
93566
VEC (vn_reference_op_s, heap) *,
93567
- vn_reference_t *, bool);
93568
-tree vn_reference_lookup (tree, tree, bool, vn_reference_t *);
93569
+ vn_reference_t *, vn_lookup_kind);
93570
+tree vn_reference_lookup (tree, tree, vn_lookup_kind, vn_reference_t *);
93571
vn_reference_t vn_reference_insert (tree, tree, tree);
93572
vn_reference_t vn_reference_insert_pieces (tree, alias_set_type, tree,
93573
VEC (vn_reference_op_s, heap) *,
93574
82134
--- a/src/gcc/tree-ssa-sink.c
93575
82135
+++ b/src/gcc/tree-ssa-sink.c
93576
82136
@@ -470,6 +470,47 @@
93621
82181
if (dump_file)
93622
82182
{
93623
82183
fprintf (dump_file, "Sinking ");
93624
--- a/src/gcc/tree-ssa-structalias.c
93625
+++ b/src/gcc/tree-ssa-structalias.c
93626
@@ -369,7 +369,11 @@
93627
ret->may_have_pointers = true;
93628
ret->is_global_var = (t == NULL_TREE);
93629
if (t && DECL_P (t))
93630
- ret->is_global_var = is_global_var (t);
93631
+ ret->is_global_var = (is_global_var (t)
93632
+ /* We have to treat even local register variables
93633
+ as escape points. */
93634
+ || (TREE_CODE (t) == VAR_DECL
93635
+ && DECL_HARD_REGISTER (t)));
93636
ret->solution = BITMAP_ALLOC (&pta_obstack);
93637
ret->oldsolution = BITMAP_ALLOC (&oldpta_obstack);
93638
ret->next = NULL;
93639
@@ -2784,33 +2788,6 @@
93640
}
93641
}
93642
93643
-/* Return true if T is a type that could contain pointers. */
93644
-
93645
-static bool
93646
-type_could_have_pointers (tree type)
93647
-{
93648
- if (POINTER_TYPE_P (type))
93649
- return true;
93650
-
93651
- if (TREE_CODE (type) == ARRAY_TYPE)
93652
- return type_could_have_pointers (TREE_TYPE (type));
93653
-
93654
- return AGGREGATE_TYPE_P (type);
93655
-}
93656
-
93657
-/* Return true if T is a variable of a type that could contain
93658
- pointers. */
93659
-
93660
-static bool
93661
-could_have_pointers (tree t)
93662
-{
93663
- return (((TREE_CODE (t) == VAR_DECL
93664
- || TREE_CODE (t) == PARM_DECL
93665
- || TREE_CODE (t) == RESULT_DECL)
93666
- && (TREE_PUBLIC (t) || DECL_EXTERNAL (t) || TREE_ADDRESSABLE (t)))
93667
- || type_could_have_pointers (TREE_TYPE (t)));
93668
-}
93669
-
93670
/* Return the position, in bits, of FIELD_DECL from the beginning of its
93671
structure. */
93672
93673
@@ -2822,7 +2799,7 @@
93674
|| !host_integerp (DECL_FIELD_BIT_OFFSET (fdecl), 0))
93675
return -1;
93676
93677
- return (TREE_INT_CST_LOW (DECL_FIELD_OFFSET (fdecl)) * 8
93678
+ return (TREE_INT_CST_LOW (DECL_FIELD_OFFSET (fdecl)) * BITS_PER_UNIT
93679
+ TREE_INT_CST_LOW (DECL_FIELD_BIT_OFFSET (fdecl)));
93680
}
93681
93682
@@ -3163,14 +3140,18 @@
93683
in that case *NULL does not fail, so it _should_ alias *anything.
93684
It is not worth adding a new option or renaming the existing one,
93685
since this case is relatively obscure. */
93686
- if (flag_delete_null_pointer_checks
93687
- && ((TREE_CODE (t) == INTEGER_CST
93688
- && integer_zerop (t))
93689
- /* The only valid CONSTRUCTORs in gimple with pointer typed
93690
- elements are zero-initializer. */
93691
- || TREE_CODE (t) == CONSTRUCTOR))
93692
+ if ((TREE_CODE (t) == INTEGER_CST
93693
+ && integer_zerop (t))
93694
+ /* The only valid CONSTRUCTORs in gimple with pointer typed
93695
+ elements are zero-initializer. But in IPA mode we also
93696
+ process global initializers, so verify at least. */
93697
+ || (TREE_CODE (t) == CONSTRUCTOR
93698
+ && CONSTRUCTOR_NELTS (t) == 0))
93699
{
93700
- temp.var = nothing_id;
93701
+ if (flag_delete_null_pointer_checks)
93702
+ temp.var = nothing_id;
93703
+ else
93704
+ temp.var = nonlocal_id;
93705
temp.type = ADDRESSOF;
93706
temp.offset = 0;
93707
VEC_safe_push (ce_s, heap, *results, &temp);
93708
@@ -3243,6 +3224,15 @@
93709
get_constraint_for_ssa_var (t, results, address_p);
93710
return;
93711
}
93712
+ case tcc_constant:
93713
+ {
93714
+ /* We cannot refer to automatic variables through constants. */
93715
+ temp.type = ADDRESSOF;
93716
+ temp.var = nonlocal_id;
93717
+ temp.offset = 0;
93718
+ VEC_safe_push (ce_s, heap, *results, &temp);
93719
+ return;
93720
+ }
93721
default:;
93722
}
93723
93724
@@ -3498,8 +3488,7 @@
93725
93726
/* Find those pointers being passed, and make sure they end up
93727
pointing to anything. */
93728
- if (could_have_pointers (arg))
93729
- make_escape_constraint (arg);
93730
+ make_escape_constraint (arg);
93731
}
93732
93733
/* The static chain escapes as well. */
93734
@@ -3599,17 +3588,13 @@
93735
for (k = 0; k < gimple_call_num_args (stmt); ++k)
93736
{
93737
tree arg = gimple_call_arg (stmt, k);
93738
-
93739
- if (could_have_pointers (arg))
93740
- {
93741
- VEC(ce_s, heap) *argc = NULL;
93742
- unsigned i;
93743
- struct constraint_expr *argp;
93744
- get_constraint_for_rhs (arg, &argc);
93745
- for (i = 0; VEC_iterate (ce_s, argc, i, argp); ++i)
93746
- VEC_safe_push (ce_s, heap, *results, argp);
93747
- VEC_free(ce_s, heap, argc);
93748
- }
93749
+ VEC(ce_s, heap) *argc = NULL;
93750
+ unsigned i;
93751
+ struct constraint_expr *argp;
93752
+ get_constraint_for_rhs (arg, &argc);
93753
+ for (i = 0; VEC_iterate (ce_s, argc, i, argp); ++i)
93754
+ VEC_safe_push (ce_s, heap, *results, argp);
93755
+ VEC_free(ce_s, heap, argc);
93756
}
93757
93758
/* May return addresses of globals. */
93759
@@ -3633,12 +3618,8 @@
93760
for (i = 0; i < gimple_call_num_args (stmt); ++i)
93761
{
93762
tree arg = gimple_call_arg (stmt, i);
93763
-
93764
- if (could_have_pointers (arg))
93765
- {
93766
- make_constraint_to (callused_id, arg);
93767
- need_callused = true;
93768
- }
93769
+ make_constraint_to (callused_id, arg);
93770
+ need_callused = true;
93771
}
93772
93773
/* The static chain is used as well. */
93774
@@ -3678,34 +3659,27 @@
93775
/* Now build constraints expressions. */
93776
if (gimple_code (t) == GIMPLE_PHI)
93777
{
93778
- gcc_assert (!AGGREGATE_TYPE_P (TREE_TYPE (gimple_phi_result (t))));
93779
+ size_t i;
93780
+ unsigned int j;
93781
93782
- /* Only care about pointers and structures containing
93783
- pointers. */
93784
- if (could_have_pointers (gimple_phi_result (t)))
93785
- {
93786
- size_t i;
93787
- unsigned int j;
93788
-
93789
- /* For a phi node, assign all the arguments to
93790
- the result. */
93791
- get_constraint_for (gimple_phi_result (t), &lhsc);
93792
- for (i = 0; i < gimple_phi_num_args (t); i++)
93793
- {
93794
- tree strippedrhs = PHI_ARG_DEF (t, i);
93795
+ /* For a phi node, assign all the arguments to
93796
+ the result. */
93797
+ get_constraint_for (gimple_phi_result (t), &lhsc);
93798
+ for (i = 0; i < gimple_phi_num_args (t); i++)
93799
+ {
93800
+ tree strippedrhs = PHI_ARG_DEF (t, i);
93801
93802
- STRIP_NOPS (strippedrhs);
93803
- get_constraint_for_rhs (gimple_phi_arg_def (t, i), &rhsc);
93804
+ STRIP_NOPS (strippedrhs);
93805
+ get_constraint_for_rhs (gimple_phi_arg_def (t, i), &rhsc);
93806
93807
- for (j = 0; VEC_iterate (ce_s, lhsc, j, c); j++)
93808
+ for (j = 0; VEC_iterate (ce_s, lhsc, j, c); j++)
93809
+ {
93810
+ struct constraint_expr *c2;
93811
+ while (VEC_length (ce_s, rhsc) > 0)
93812
{
93813
- struct constraint_expr *c2;
93814
- while (VEC_length (ce_s, rhsc) > 0)
93815
- {
93816
- c2 = VEC_last (ce_s, rhsc);
93817
- process_constraint (new_constraint (*c, *c2));
93818
- VEC_pop (ce_s, rhsc);
93819
- }
93820
+ c2 = VEC_last (ce_s, rhsc);
93821
+ process_constraint (new_constraint (*c, *c2));
93822
+ VEC_pop (ce_s, rhsc);
93823
}
93824
}
93825
}
93826
@@ -3854,16 +3828,7 @@
93827
else
93828
handle_rhs_call (t, &rhsc);
93829
if (gimple_call_lhs (t))
93830
- {
93831
- if (could_have_pointers (gimple_call_lhs (t)))
93832
- handle_lhs_call (gimple_call_lhs (t), flags, rhsc, fndecl);
93833
- /* Similar to conversions a result that is not a pointer
93834
- is an escape point for any pointer the function might
93835
- return. */
93836
- else if (flags & (ECF_CONST|ECF_PURE
93837
- |ECF_NOVOPS|ECF_LOOPING_CONST_OR_PURE))
93838
- make_constraints_to (escaped_id, rhsc);
93839
- }
93840
+ handle_lhs_call (gimple_call_lhs (t), flags, rhsc, fndecl);
93841
VEC_free (ce_s, heap, rhsc);
93842
}
93843
else
93844
@@ -3946,8 +3911,7 @@
93845
/* Otherwise, just a regular assignment statement. Only care about
93846
operations with pointer result, others are dealt with as escape
93847
points if they have pointer operands. */
93848
- else if (is_gimple_assign (t)
93849
- && type_could_have_pointers (TREE_TYPE (gimple_assign_lhs (t))))
93850
+ else if (is_gimple_assign (t))
93851
{
93852
/* Otherwise, just a regular assignment statement. */
93853
tree lhsop = gimple_assign_lhs (t);
93854
@@ -3957,23 +3921,45 @@
93855
do_structure_copy (lhsop, rhsop);
93856
else
93857
{
93858
- struct constraint_expr temp;
93859
+ enum tree_code code = gimple_assign_rhs_code (t);
93860
+
93861
get_constraint_for (lhsop, &lhsc);
93862
93863
- if (gimple_assign_rhs_code (t) == POINTER_PLUS_EXPR)
93864
+ if (code == POINTER_PLUS_EXPR)
93865
get_constraint_for_ptr_offset (gimple_assign_rhs1 (t),
93866
gimple_assign_rhs2 (t), &rhsc);
93867
- else if ((CONVERT_EXPR_CODE_P (gimple_assign_rhs_code (t))
93868
+ else if (code == BIT_AND_EXPR
93869
+ && TREE_CODE (gimple_assign_rhs2 (t)) == INTEGER_CST)
93870
+ {
93871
+ /* Aligning a pointer via a BIT_AND_EXPR is offsetting
93872
+ the pointer. Handle it by offsetting it by UNKNOWN. */
93873
+ get_constraint_for_ptr_offset (gimple_assign_rhs1 (t),
93874
+ NULL_TREE, &rhsc);
93875
+ }
93876
+ else if ((CONVERT_EXPR_CODE_P (code)
93877
&& !(POINTER_TYPE_P (gimple_expr_type (t))
93878
&& !POINTER_TYPE_P (TREE_TYPE (rhsop))))
93879
|| gimple_assign_single_p (t))
93880
get_constraint_for_rhs (rhsop, &rhsc);
93881
+ else if (truth_value_p (code))
93882
+ /* Truth value results are not pointer (parts). Or at least
93883
+ very very unreasonable obfuscation of a part. */
93884
+ ;
93885
else
93886
{
93887
- temp.type = ADDRESSOF;
93888
- temp.var = anything_id;
93889
- temp.offset = 0;
93890
- VEC_safe_push (ce_s, heap, rhsc, &temp);
93891
+ /* All other operations are merges. */
93892
+ VEC (ce_s, heap) *tmp = NULL;
93893
+ struct constraint_expr *rhsp;
93894
+ unsigned i, j;
93895
+ get_constraint_for_rhs (gimple_assign_rhs1 (t), &rhsc);
93896
+ for (i = 2; i < gimple_num_ops (t); ++i)
93897
+ {
93898
+ get_constraint_for_rhs (gimple_op (t, i), &tmp);
93899
+ for (j = 0; VEC_iterate (ce_s, tmp, j, rhsp); ++j)
93900
+ VEC_safe_push (ce_s, heap, rhsc, rhsp);
93901
+ VEC_truncate (ce_s, tmp, 0);
93902
+ }
93903
+ VEC_free (ce_s, heap, tmp);
93904
}
93905
process_all_all_constraints (lhsc, rhsc);
93906
}
93907
@@ -3992,17 +3978,9 @@
93908
make_constraint_from_restrict (get_vi_for_tree (lhsop),
93909
"CAST_RESTRICT");
93910
}
93911
- /* For conversions of pointers to non-pointers the pointer escapes. */
93912
- else if (gimple_assign_cast_p (t)
93913
- && POINTER_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (t)))
93914
- && !POINTER_TYPE_P (TREE_TYPE (gimple_assign_lhs (t))))
93915
- {
93916
- make_escape_constraint (gimple_assign_rhs1 (t));
93917
- }
93918
/* Handle escapes through return. */
93919
else if (gimple_code (t) == GIMPLE_RETURN
93920
- && gimple_return_retval (t) != NULL_TREE
93921
- && could_have_pointers (gimple_return_retval (t)))
93922
+ && gimple_return_retval (t) != NULL_TREE)
93923
{
93924
make_escape_constraint (gimple_return_retval (t));
93925
}
93926
@@ -4033,7 +4011,7 @@
93927
93928
/* The asm may read global memory, so outputs may point to
93929
any global memory. */
93930
- if (op && could_have_pointers (op))
93931
+ if (op)
93932
{
93933
VEC(ce_s, heap) *lhsc = NULL;
93934
struct constraint_expr rhsc, *lhsp;
93935
@@ -4063,7 +4041,7 @@
93936
/* Strictly we'd only need the constraint to ESCAPED if
93937
the asm clobbers memory, otherwise using CALLUSED
93938
would be enough. */
93939
- else if (op && could_have_pointers (op))
93940
+ else if (op)
93941
make_escape_constraint (op);
93942
}
93943
}
93944
@@ -4188,6 +4166,8 @@
93945
93946
unsigned has_unknown_size : 1;
93947
93948
+ unsigned must_have_pointers : 1;
93949
+
93950
unsigned may_have_pointers : 1;
93951
93952
unsigned only_restrict_pointers : 1;
93953
@@ -4252,6 +4232,33 @@
93954
return false;
93955
}
93956
93957
+/* Return true if T is a type that does contain pointers. */
93958
+
93959
+static bool
93960
+type_must_have_pointers (tree type)
93961
+{
93962
+ if (POINTER_TYPE_P (type))
93963
+ return true;
93964
+
93965
+ if (TREE_CODE (type) == ARRAY_TYPE)
93966
+ return type_must_have_pointers (TREE_TYPE (type));
93967
+
93968
+ /* A function or method can have pointers as arguments, so track
93969
+ those separately. */
93970
+ if (TREE_CODE (type) == FUNCTION_TYPE
93971
+ || TREE_CODE (type) == METHOD_TYPE)
93972
+ return true;
93973
+
93974
+ return false;
93975
+}
93976
+
93977
+static bool
93978
+field_must_have_pointers (tree t)
93979
+{
93980
+ return type_must_have_pointers (TREE_TYPE (t));
93981
+}
93982
+
93983
+
93984
/* Given a TYPE, and a vector of field offsets FIELDSTACK, push all
93985
the fields of TYPE onto fieldstack, recording their offsets along
93986
the way.
93987
@@ -4262,7 +4269,7 @@
93988
93989
static int
93990
push_fields_onto_fieldstack (tree type, VEC(fieldoff_s,heap) **fieldstack,
93991
- HOST_WIDE_INT offset, bool must_have_pointers_p)
93992
+ HOST_WIDE_INT offset)
93993
{
93994
tree field;
93995
int count = 0;
93996
@@ -4288,8 +4295,7 @@
93997
|| TREE_CODE (TREE_TYPE (field)) == UNION_TYPE)
93998
push = true;
93999
else if (!(pushed = push_fields_onto_fieldstack
94000
- (TREE_TYPE (field), fieldstack, offset + foff,
94001
- must_have_pointers_p))
94002
+ (TREE_TYPE (field), fieldstack, offset + foff))
94003
&& (DECL_SIZE (field)
94004
&& !integer_zerop (DECL_SIZE (field))))
94005
/* Empty structures may have actual size, like in C++. So
94006
@@ -4301,24 +4307,35 @@
94007
{
94008
fieldoff_s *pair = NULL;
94009
bool has_unknown_size = false;
94010
+ bool must_have_pointers_p;
94011
94012
if (!VEC_empty (fieldoff_s, *fieldstack))
94013
pair = VEC_last (fieldoff_s, *fieldstack);
94014
94015
+ if (!pair
94016
+ && offset + foff != 0)
94017
+ {
94018
+ pair = VEC_safe_push (fieldoff_s, heap, *fieldstack, NULL);
94019
+ pair->offset = 0;
94020
+ pair->size = offset + foff;
94021
+ pair->has_unknown_size = false;
94022
+ pair->may_have_pointers = false;
94023
+ pair->only_restrict_pointers = false;
94024
+ }
94025
+
94026
if (!DECL_SIZE (field)
94027
|| !host_integerp (DECL_SIZE (field), 1))
94028
has_unknown_size = true;
94029
94030
/* If adjacent fields do not contain pointers merge them. */
94031
+ must_have_pointers_p = field_must_have_pointers (field);
94032
if (pair
94033
- && !pair->may_have_pointers
94034
- && !pair->has_unknown_size
94035
&& !has_unknown_size
94036
- && pair->offset + (HOST_WIDE_INT)pair->size == offset + foff
94037
&& !must_have_pointers_p
94038
- && !could_have_pointers (field))
94039
+ && !pair->must_have_pointers
94040
+ && !pair->has_unknown_size
94041
+ && pair->offset + (HOST_WIDE_INT)pair->size == offset + foff)
94042
{
94043
- pair = VEC_last (fieldoff_s, *fieldstack);
94044
pair->size += TREE_INT_CST_LOW (DECL_SIZE (field));
94045
}
94046
else
94047
@@ -4330,8 +4347,8 @@
94048
pair->size = TREE_INT_CST_LOW (DECL_SIZE (field));
94049
else
94050
pair->size = -1;
94051
- pair->may_have_pointers
94052
- = must_have_pointers_p || could_have_pointers (field);
94053
+ pair->must_have_pointers = must_have_pointers_p;
94054
+ pair->may_have_pointers = true;
94055
pair->only_restrict_pointers
94056
= (!has_unknown_size
94057
&& POINTER_TYPE_P (TREE_TYPE (field))
94058
@@ -4497,17 +4514,14 @@
94059
VEC (fieldoff_s,heap) *fieldstack = NULL;
94060
94061
if (var_can_have_subvars (decl) && use_field_sensitive)
94062
- push_fields_onto_fieldstack (decl_type, &fieldstack, 0,
94063
- TREE_PUBLIC (decl)
94064
- || DECL_EXTERNAL (decl)
94065
- || TREE_ADDRESSABLE (decl));
94066
+ push_fields_onto_fieldstack (decl_type, &fieldstack, 0);
94067
94068
/* If the variable doesn't have subvars, we may end up needing to
94069
sort the field list and create fake variables for all the
94070
fields. */
94071
vi = new_var_info (decl, name);
94072
vi->offset = 0;
94073
- vi->may_have_pointers = could_have_pointers (decl);
94074
+ vi->may_have_pointers = true;
94075
if (!declsize
94076
|| !host_integerp (declsize, 1))
94077
{
94078
@@ -4680,9 +4694,6 @@
94079
{
94080
varinfo_t p;
94081
94082
- if (!could_have_pointers (t))
94083
- continue;
94084
-
94085
/* For restrict qualified pointers to objects passed by
94086
reference build a real representative for the pointed-to object. */
94087
if (DECL_BY_REFERENCE (t)
94088
--- a/src/gcc/tree-ssa-ter.c
94089
+++ b/src/gcc/tree-ssa-ter.c
94090
@@ -416,7 +416,9 @@
94091
return false;
94092
94093
/* Without alias info we can't move around loads. */
94094
- if (gimple_references_memory_p (stmt) && !optimize)
94095
+ if (!optimize
94096
+ && gimple_assign_single_p (stmt)
94097
+ && !is_gimple_val (gimple_assign_rhs1 (stmt)))
94098
return false;
94099
94100
/* Float expressions must go through memory if float-store is on. */
94101
82184
--- a/src/gcc/tree-ssa-threadedge.c
94102
82185
+++ b/src/gcc/tree-ssa-threadedge.c
94103
82186
@@ -247,14 +247,14 @@
94146
82229
if (xloc.file != floc.file
94147
82230
|| xloc.line < floc.line
94148
82231
|| xloc.line > LOCATION_LINE (cfun->function_end_locus))
94149
--- a/src/gcc/tree-vect-generic.c
94150
+++ b/src/gcc/tree-vect-generic.c
94151
@@ -518,8 +518,7 @@
94152
way to do it is change expand_vector_operation and its callees to
94153
return a tree_code, RHS1 and RHS2 instead of a tree. */
94154
gimple_assign_set_rhs_from_tree (gsi, new_rhs);
94155
-
94156
- gimple_set_modified (gsi_stmt (*gsi), true);
94157
+ update_stmt (gsi_stmt (*gsi));
94158
}
94159
94160
/* Use this to lower vector operations introduced by the vectorizer,
94161
@@ -536,16 +535,24 @@
82232
--- a/src/gcc/tree-switch-conversion.c
82233
+++ b/src/gcc/tree-switch-conversion.c
82234
@@ -549,7 +549,7 @@
82235
build_arrays (gimple swtch)
94162
82236
{
82237
tree arr_index_type;
82238
- tree tidx, sub, tmp;
82239
+ tree tidx, sub, tmp, utype;
82240
gimple stmt;
94163
82241
gimple_stmt_iterator gsi;
94164
basic_block bb;
94165
+ bool cfg_changed = false;
94166
94167
FOR_EACH_BB (bb)
94168
{
94169
for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
94170
{
94171
expand_vector_operations_1 (&gsi);
94172
- update_stmt_if_modified (gsi_stmt (gsi));
94173
+ /* ??? If we do not cleanup EH then we will ICE in
94174
+ verification. But in reality we have created wrong-code
94175
+ as we did not properly transition EH info and edges to
94176
+ the piecewise computations. */
94177
+ if (maybe_clean_eh_stmt (gsi_stmt (gsi))
94178
+ && gimple_purge_dead_eh_edges (bb))
94179
+ cfg_changed = true;
94180
}
94181
}
94182
- return 0;
82242
int i;
82243
@@ -557,14 +557,20 @@
82244
82245
gsi = gsi_for_stmt (swtch);
82246
82247
+ /* Make sure we do not generate arithmetics in a subrange. */
82248
+ utype = TREE_TYPE (info.index_expr);
82249
+ if (TREE_TYPE (utype))
82250
+ utype = lang_hooks.types.type_for_mode (TYPE_MODE (TREE_TYPE (utype)), 1);
82251
+ else
82252
+ utype = lang_hooks.types.type_for_mode (TYPE_MODE (utype), 1);
94183
82253
+
94184
+ return cfg_changed ? TODO_cleanup_cfg : 0;
94185
}
94186
94187
struct gimple_opt_pass pass_lower_vector =
94188
--- a/src/gcc/tree-vect-loop.c
94189
+++ b/src/gcc/tree-vect-loop.c
94190
@@ -2363,7 +2363,7 @@
94191
stmt_vec_info stmt_vinfo = vinfo_for_stmt (iv_phi);
94192
loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
94193
struct loop *loop = LOOP_VINFO_LOOP (loop_vinfo);
94194
- tree scalar_type = TREE_TYPE (gimple_phi_result (iv_phi));
94195
+ tree scalar_type;
94196
tree vectype;
94197
int nunits;
94198
edge pe = loop_preheader_edge (loop);
94199
@@ -2392,24 +2392,7 @@
94200
gimple_stmt_iterator si;
94201
basic_block bb = gimple_bb (iv_phi);
94202
tree stepvectype;
94203
-
94204
- vectype = get_vectype_for_scalar_type (scalar_type);
94205
- gcc_assert (vectype);
94206
- nunits = TYPE_VECTOR_SUBPARTS (vectype);
94207
- ncopies = vf / nunits;
94208
-
94209
- gcc_assert (phi_info);
94210
- gcc_assert (ncopies >= 1);
94211
-
94212
- /* Find the first insertion point in the BB. */
94213
- si = gsi_after_labels (bb);
94214
-
94215
- if (INTEGRAL_TYPE_P (scalar_type))
94216
- step_expr = build_int_cst (scalar_type, 0);
94217
- else if (POINTER_TYPE_P (scalar_type))
94218
- step_expr = build_int_cst (sizetype, 0);
82254
arr_index_type = build_index_type (info.range_size);
82255
- tmp = create_tmp_var (TREE_TYPE (info.index_expr), "csti");
82256
+ tmp = create_tmp_var (utype, "csui");
82257
add_referenced_var (tmp);
82258
tidx = make_ssa_name (tmp, NULL);
82259
- sub = fold_build2_loc (loc, MINUS_EXPR,
82260
- TREE_TYPE (info.index_expr), info.index_expr,
82261
- fold_convert_loc (loc, TREE_TYPE (info.index_expr),
82262
- info.range_min));
82263
+ sub = fold_build2_loc (loc, MINUS_EXPR, utype,
82264
+ fold_convert_loc (loc, utype, info.index_expr),
82265
+ fold_convert_loc (loc, utype, info.range_min));
82266
sub = force_gimple_operand_gsi (&gsi, sub,
82267
false, NULL, true, GSI_SAME_STMT);
82268
stmt = gimple_build_assign (tidx, sub);
82269
@@ -673,12 +679,7 @@
82270
tree label_decl2 = create_artificial_label (UNKNOWN_LOCATION);
82271
tree label_decl3 = create_artificial_label (UNKNOWN_LOCATION);
82272
gimple label1, label2, label3;
82273
-
82274
- tree utype;
82275
- tree tmp_u_1, tmp_u_2, tmp_u_var;
82276
- tree cast;
82277
- gimple cast_assign, minus_assign;
82278
- tree ulb, minus;
82279
+ tree utype, tidx;
82280
tree bound;
82281
82282
gimple cond_stmt;
82283
@@ -692,49 +693,24 @@
82284
gcc_assert (info.default_values);
82285
bb0 = gimple_bb (swtch);
82286
82287
- /* Make sure we do not generate arithmetics in a subrange. */
82288
- if (TREE_TYPE (TREE_TYPE (info.index_expr)))
82289
- utype = lang_hooks.types.type_for_mode
82290
- (TYPE_MODE (TREE_TYPE (TREE_TYPE (info.index_expr))), 1);
94219
82291
- else
94220
- step_expr = build_real (scalar_type, dconst0);
94221
+ tree resvectype;
94222
94223
/* Is phi in an inner-loop, while vectorizing an enclosing outer-loop? */
94224
if (nested_in_vect_loop_p (loop, iv_phi))
94225
@@ -2426,11 +2409,25 @@
94226
94227
access_fn = analyze_scalar_evolution (iv_loop, PHI_RESULT (iv_phi));
94228
gcc_assert (access_fn);
94229
+ STRIP_NOPS (access_fn);
94230
ok = vect_is_simple_iv_evolution (iv_loop->num, access_fn,
94231
&init_expr, &step_expr);
94232
gcc_assert (ok);
94233
pe = loop_preheader_edge (iv_loop);
94234
94235
+ scalar_type = TREE_TYPE (init_expr);
94236
+ vectype = get_vectype_for_scalar_type (scalar_type);
94237
+ resvectype = get_vectype_for_scalar_type (TREE_TYPE (PHI_RESULT (iv_phi)));
94238
+ gcc_assert (vectype);
94239
+ nunits = TYPE_VECTOR_SUBPARTS (vectype);
94240
+ ncopies = vf / nunits;
94241
+
94242
+ gcc_assert (phi_info);
94243
+ gcc_assert (ncopies >= 1);
94244
+
94245
+ /* Find the first insertion point in the BB. */
94246
+ si = gsi_after_labels (bb);
94247
+
94248
/* Create the vector that holds the initial_value of the induction. */
94249
if (nested_in_vect_loop)
94250
{
94251
@@ -2456,7 +2453,7 @@
94252
}
94253
94254
t = NULL_TREE;
94255
- t = tree_cons (NULL_TREE, init_expr, t);
94256
+ t = tree_cons (NULL_TREE, new_name, t);
94257
for (i = 1; i < nunits; i++)
94258
{
94259
/* Create: new_name_i = new_name + step_expr */
94260
@@ -2575,6 +2572,19 @@
94261
gimple_assign_set_lhs (new_stmt, vec_def);
94262
94263
gsi_insert_before (&si, new_stmt, GSI_SAME_STMT);
94264
+ if (!useless_type_conversion_p (resvectype, vectype))
94265
+ {
94266
+ new_stmt = gimple_build_assign_with_ops
94267
+ (VIEW_CONVERT_EXPR,
94268
+ vect_get_new_vect_var (resvectype, vect_simple_var,
94269
+ "vec_iv_"),
94270
+ build1 (VIEW_CONVERT_EXPR, resvectype,
94271
+ gimple_assign_lhs (new_stmt)), NULL_TREE);
94272
+ gimple_assign_set_lhs (new_stmt,
94273
+ make_ssa_name
94274
+ (gimple_assign_lhs (new_stmt), new_stmt));
94275
+ gsi_insert_before (&si, new_stmt, GSI_SAME_STMT);
94276
+ }
94277
set_vinfo_for_stmt (new_stmt,
94278
new_stmt_vec_info (new_stmt, loop_vinfo, NULL));
94279
STMT_VINFO_RELATED_STMT (prev_stmt_vinfo) = new_stmt;
94280
@@ -2622,6 +2632,22 @@
94281
}
94282
94283
STMT_VINFO_VEC_STMT (phi_info) = induction_phi;
94284
+ if (!useless_type_conversion_p (resvectype, vectype))
94285
+ {
94286
+ new_stmt = gimple_build_assign_with_ops
94287
+ (VIEW_CONVERT_EXPR,
94288
+ vect_get_new_vect_var (resvectype, vect_simple_var, "vec_iv_"),
94289
+ build1 (VIEW_CONVERT_EXPR, resvectype, induc_def), NULL_TREE);
94290
+ induc_def = make_ssa_name (gimple_assign_lhs (new_stmt), new_stmt);
94291
+ gimple_assign_set_lhs (new_stmt, induc_def);
94292
+ si = gsi_start_bb (bb);
94293
+ gsi_insert_before (&si, new_stmt, GSI_SAME_STMT);
94294
+ set_vinfo_for_stmt (new_stmt,
94295
+ new_stmt_vec_info (new_stmt, loop_vinfo, NULL));
94296
+ STMT_VINFO_RELATED_STMT (vinfo_for_stmt (new_stmt))
94297
+ = STMT_VINFO_RELATED_STMT (vinfo_for_stmt (induction_phi));
94298
+ }
94299
+
94300
return induc_def;
94301
}
82292
- utype = lang_hooks.types.type_for_mode
82293
- (TYPE_MODE (TREE_TYPE (info.index_expr)), 1);
82294
+ tidx = gimple_assign_lhs (info.arr_ref_first);
82295
+ utype = TREE_TYPE (tidx);
82296
82297
/* (end of) block 0 */
82298
gsi = gsi_for_stmt (info.arr_ref_first);
82299
- tmp_u_var = create_tmp_var (utype, "csui");
82300
- add_referenced_var (tmp_u_var);
82301
- tmp_u_1 = make_ssa_name (tmp_u_var, NULL);
82302
-
82303
- cast = fold_convert_loc (loc, utype, info.index_expr);
82304
- cast_assign = gimple_build_assign (tmp_u_1, cast);
82305
- SSA_NAME_DEF_STMT (tmp_u_1) = cast_assign;
82306
- gsi_insert_before (&gsi, cast_assign, GSI_SAME_STMT);
82307
- update_stmt (cast_assign);
82308
-
82309
- ulb = fold_convert_loc (loc, utype, info.range_min);
82310
- minus = fold_build2_loc (loc, MINUS_EXPR, utype, tmp_u_1, ulb);
82311
- minus = force_gimple_operand_gsi (&gsi, minus, false, NULL, true,
82312
- GSI_SAME_STMT);
82313
- tmp_u_2 = make_ssa_name (tmp_u_var, NULL);
82314
- minus_assign = gimple_build_assign (tmp_u_2, minus);
82315
- SSA_NAME_DEF_STMT (tmp_u_2) = minus_assign;
82316
- gsi_insert_before (&gsi, minus_assign, GSI_SAME_STMT);
82317
- update_stmt (minus_assign);
82318
+ gsi_next (&gsi);
82319
82320
bound = fold_convert_loc (loc, utype, info.range_size);
82321
- cond_stmt = gimple_build_cond (LE_EXPR, tmp_u_2, bound, NULL_TREE, NULL_TREE);
82322
+ cond_stmt = gimple_build_cond (LE_EXPR, tidx, bound, NULL_TREE, NULL_TREE);
82323
gsi_insert_before (&gsi, cond_stmt, GSI_SAME_STMT);
82324
update_stmt (cond_stmt);
82325
82326
/* block 2 */
82327
- gsi = gsi_for_stmt (info.arr_ref_first);
82328
label2 = gimple_build_label (label_decl2);
82329
gsi_insert_before (&gsi, label2, GSI_SAME_STMT);
82330
last_assign = gen_def_assigns (&gsi);
82331
82332
/* block 1 */
82333
- gsi = gsi_for_stmt (info.arr_ref_first);
82334
label1 = gimple_build_label (label_decl1);
82335
gsi_insert_before (&gsi, label1, GSI_SAME_STMT);
94302
82336
94303
82337
--- a/src/gcc/tree-vect-stmts.c
94304
82338
+++ b/src/gcc/tree-vect-stmts.c
94305
@@ -1014,8 +1014,10 @@
94306
/* Get the def from the vectorized stmt. */
94307
def_stmt_info = vinfo_for_stmt (def_stmt);
94308
vec_stmt = STMT_VINFO_VEC_STMT (def_stmt_info);
94309
- gcc_assert (vec_stmt && gimple_code (vec_stmt) == GIMPLE_PHI);
94310
- vec_oprnd = PHI_RESULT (vec_stmt);
94311
+ if (gimple_code (vec_stmt) == GIMPLE_PHI)
94312
+ vec_oprnd = PHI_RESULT (vec_stmt);
94313
+ else
94314
+ vec_oprnd = gimple_get_lhs (vec_stmt);
94315
return vec_oprnd;
94316
}
94317
94318
@@ -2236,7 +2238,6 @@
94319
int op_type;
94320
optab optab;
94321
int icode;
94322
- enum machine_mode optab_op2_mode;
94323
tree def;
94324
gimple def_stmt;
94325
enum vect_def_type dt[2] = {vect_unknown_def_type, vect_unknown_def_type};
94326
@@ -2249,8 +2250,6 @@
94327
int j, i;
94328
VEC(tree,heap) *vec_oprnds0 = NULL, *vec_oprnds1 = NULL;
94329
tree vop0, vop1;
94330
- unsigned int k;
94331
- bool scalar_shift_arg = false;
94332
bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info);
94333
int vf;
94334
94335
@@ -4867,6 +4866,11 @@
82339
@@ -4866,6 +4866,11 @@
94336
82340
tree wide_vectype = get_vectype_for_scalar_type (type);
94337
82341
enum tree_code c1, c2;
94338
82342
94364
82368
case GIMPLE_SINGLE_RHS:
94365
82369
return tree_single_nonzero_warnv_p (gimple_assign_rhs1 (stmt),
94366
82370
strict_overflow_p);
94367
@@ -7290,6 +7294,7 @@
94368
size_t i;
94369
prop_value_t *single_val_range;
94370
bool do_value_subst_p;
94371
+ unsigned num = num_ssa_names;
94372
94373
if (dump_file)
94374
{
94375
@@ -7301,10 +7306,10 @@
94376
/* We may have ended with ranges that have exactly one value. Those
94377
values can be substituted as any other const propagated
94378
value using substitute_and_fold. */
94379
- single_val_range = XCNEWVEC (prop_value_t, num_ssa_names);
94380
+ single_val_range = XCNEWVEC (prop_value_t, num);
94381
94382
do_value_subst_p = false;
94383
- for (i = 0; i < num_ssa_names; i++)
94384
+ for (i = 0; i < num; i++)
94385
if (vr_value[i]
94386
&& vr_value[i]->type == VR_RANGE
94387
&& vr_value[i]->min == vr_value[i]->max
94388
@@ -7332,7 +7337,7 @@
94389
identify_jump_threads ();
94390
94391
/* Free allocated memory. */
94392
- for (i = 0; i < num_ssa_names; i++)
94393
+ for (i = 0; i < num; i++)
94394
if (vr_value[i])
94395
{
94396
BITMAP_FREE (vr_value[i]->equiv);
94397
82371
--- a/src/gcc/tree.c
94398
82372
+++ b/src/gcc/tree.c
94399
@@ -5797,12 +5797,18 @@
94400
|| TREE_TYPE (a->type) != TREE_TYPE (b->type)
94401
|| !attribute_list_equal (TYPE_ATTRIBUTES (a->type),
94402
TYPE_ATTRIBUTES (b->type))
94403
- || TYPE_ALIGN (a->type) != TYPE_ALIGN (b->type)
94404
- || TYPE_MODE (a->type) != TYPE_MODE (b->type)
94405
|| (TREE_CODE (a->type) != COMPLEX_TYPE
94406
&& TYPE_NAME (a->type) != TYPE_NAME (b->type)))
94407
return 0;
94408
94409
+ /* Be careful about comparing arrays before and after the element type
94410
+ has been completed; don't compare TYPE_ALIGN unless both types are
94411
+ complete. */
94412
+ if (COMPLETE_TYPE_P (a->type) && COMPLETE_TYPE_P (b->type)
94413
+ && (TYPE_ALIGN (a->type) != TYPE_ALIGN (b->type)
94414
+ || TYPE_MODE (a->type) != TYPE_MODE (b->type)))
94415
+ return 0;
94416
+
94417
switch (TREE_CODE (a->type))
94418
{
94419
case VOID_TYPE:
94420
@@ -6538,6 +6544,23 @@
82373
@@ -6548,6 +6548,23 @@
94421
82374
return false;
94422
82375
}
94423
82376
94441
82394
/* Generate a hash value for an expression. This can be used iteratively
94442
82395
by passing a previous result as the VAL argument.
94443
82396
94444
@@ -9358,6 +9381,19 @@
82397
@@ -9368,6 +9385,19 @@
94445
82398
return true;
94446
82399
}
94447
82400
94484
82437
Operand 1 is an integer shift amount in bits. */
94485
82438
--- a/src/gcc/tree.h
94486
82439
+++ b/src/gcc/tree.h
94487
@@ -2913,26 +2913,6 @@
94488
94489
#define DECL_COMDAT_GROUP(NODE) (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.comdat_group)
94490
94491
-/* A replaceable function is one which may be replaced at link-time
94492
- with an entirely different definition, provided that the
94493
- replacement has the same type. For example, functions declared
94494
- with __attribute__((weak)) on most systems are replaceable.
94495
-
94496
- COMDAT functions are not replaceable, since all definitions of the
94497
- function must be equivalent. It is important that COMDAT functions
94498
- not be treated as replaceable so that use of C++ template
94499
- instantiations is not penalized.
94500
-
94501
- For example, DECL_REPLACEABLE is used to determine whether or not a
94502
- function (including a template instantiation) which is not
94503
- explicitly declared "inline" can be inlined. If the function is
94504
- DECL_REPLACEABLE then it is not safe to do the inlining, since the
94505
- implementation chosen at link-time may be different. However, a
94506
- function that is not DECL_REPLACEABLE can be inlined, since all
94507
- versions of the function will be functionally identical. */
94508
-#define DECL_REPLACEABLE_P(NODE) \
94509
- (!DECL_COMDAT (NODE) && !targetm.binds_local_p (NODE))
94510
-
94511
/* The name of the object as the assembler will see it (but before any
94512
translations made by ASM_OUTPUT_LABELREF). Often this is the same
94513
as DECL_NAME. It is an IDENTIFIER_NODE. */
94514
@@ -4707,6 +4687,7 @@
82440
@@ -4687,6 +4687,7 @@
94515
82441
extern int type_num_arguments (const_tree);
94516
82442
extern bool associative_tree_code (enum tree_code);
94517
82443
extern bool commutative_tree_code (enum tree_code);
94519
82445
extern tree upper_bound_in_type (tree, tree);
94520
82446
extern tree lower_bound_in_type (tree, tree);
94521
82447
extern int operand_equal_for_phi_arg_p (const_tree, const_tree);
94522
@@ -4963,6 +4944,8 @@
82448
@@ -4943,6 +4944,8 @@
94523
82449
extern bool merge_ranges (int *, tree *, tree *, int, tree, tree, int,
94524
82450
tree, tree);
94525
82451
extern void set_builtin_user_assembler_name (tree decl, const char *asmspec);
94528
82454
94529
82455
/* In convert.c */
94530
82456
extern tree strip_float_extensions (tree);
94531
@@ -5145,6 +5128,8 @@
94532
extern void finish_aliases_2 (void);
94533
extern tree emutls_decl (tree);
94534
extern void remove_unreachable_alias_pairs (void);
94535
+extern bool decl_replaceable_p (tree);
94536
+extern bool decl_binds_to_current_def_p (tree);
94537
94538
/* In stmt.c */
94539
extern void expand_computed_goto (tree);
94540
82457
--- a/src/gcc/unwind-dw2.c
94541
82458
+++ b/src/gcc/unwind-dw2.c
94542
82459
@@ -1414,16 +1414,12 @@
94714
82631
94715
82632
/* Return true if DECL's initializer is suitable for a BSS section. */
94716
82633
94717
@@ -6691,6 +6721,51 @@
94718
return local_p;
94719
}
94720
94721
+/* Return true when references to DECL must bind to current definition in
94722
+ final executable.
94723
+
94724
+ The condition is usually equivalent to whether the function binds to the
94725
+ current module (shared library or executable), that is to binds_local_p.
94726
+ We use this fact to avoid need for another target hook and implement
94727
+ the logic using binds_local_p and just special cases where
94728
+ decl_binds_to_current_def_p is stronger than binds local_p. In particular
94729
+ the weak definitions (that can be overwritten at linktime by other
94730
+ definition from different object file) and when resolution info is available
94731
+ we simply use the knowledge passed to us by linker plugin. */
94732
+bool
94733
+decl_binds_to_current_def_p (tree decl)
94734
+{
94735
+ gcc_assert (DECL_P (decl));
94736
+ if (!TREE_PUBLIC (decl))
94737
+ return true;
94738
+ if (!targetm.binds_local_p (decl))
94739
+ return false;
94740
+ /* Otherwise we have to assume the worst for DECL_WEAK (hidden weaks
94741
+ binds localy but still can be overwritten).
94742
+ This rely on fact that binds_local_p behave as decl_replaceable_p
94743
+ for all other declaration types. */
94744
+ return !DECL_WEAK (decl);
94745
+}
94746
+
94747
+/* A replaceable function or variable is one which may be replaced
94748
+ at link-time with an entirely different definition, provided that the
94749
+ replacement has the same type. For example, functions declared
94750
+ with __attribute__((weak)) on most systems are replaceable.
94751
+
94752
+ COMDAT functions are not replaceable, since all definitions of the
94753
+ function must be equivalent. It is important that COMDAT functions
94754
+ not be treated as replaceable so that use of C++ template
94755
+ instantiations is not penalized. */
94756
+
94757
+bool
94758
+decl_replaceable_p (tree decl)
94759
+{
94760
+ gcc_assert (DECL_P (decl));
94761
+ if (!TREE_PUBLIC (decl) || DECL_COMDAT (decl))
94762
+ return false;
94763
+ return !decl_binds_to_current_def_p (decl);
94764
+}
94765
+
94766
/* Default function to output code that will globalize a label. A
94767
target must define GLOBAL_ASM_OP or provide its own function to
94768
globalize a label. */
94769
82634
--- a/src/gcc/vec.h
94770
82635
+++ b/src/gcc/vec.h
94771
82636
@@ -188,6 +188,18 @@
94787
82652
/* Allocate new vector.
94788
82653
VEC(T,A) *VEC_T_A_alloc(int reserve);
94789
82654
94790
--- a/src/gcc/xcoffout.c
94791
+++ b/src/gcc/xcoffout.c
94792
@@ -81,8 +81,15 @@
94793
#define ASM_OUTPUT_LINE(FILE,LINENUM) \
94794
do \
94795
{ \
94796
+ /* Make sure we're in a function and prevent output of .line 0, as \
94797
+ line # 0 is meant for symbol addresses in xcoff. Additionally, \
94798
+ line numbers are 'unsigned short' in 32-bit mode. */ \
94799
if (xcoff_begin_function_line >= 0) \
94800
- fprintf (FILE, "\t.line\t%d\n", ABS_OR_RELATIVE_LINENO (LINENUM)); \
94801
+ { \
94802
+ int lno = ABS_OR_RELATIVE_LINENO (LINENUM); \
94803
+ if (lno > 0 && (TARGET_64BIT || lno <= (int)USHRT_MAX)) \
94804
+ fprintf (FILE, "\t.line\t%d\n", lno); \
94805
+ } \
94806
} \
94807
while (0)
94808
94809
--- a/src/libcpp/ChangeLog
94810
+++ b/src/libcpp/ChangeLog
94811
@@ -1,3 +1,19 @@
94812
+2011-03-21 Michael Meissner <meissner@linux.vnet.ibm.com>
94813
+
94814
+ PR preprocessor/48192
94815
+ Backport from trunk
94816
+ * directives.c (do_ifdef): Do not consider conditional macros as
94817
+ being defined.
94818
+ (do_ifndef): Ditto.
94819
+ * expr.c (parse_defined): Ditto.
94820
+
94821
+2011-01-04 Eric Botcazou <ebotcazou@adacore.com>
94822
+ Jakub Jelinek <jakub@redhat.com>
94823
+
94824
+ PR preprocessor/39213
94825
+ * directives.c (end_directive): Call _cpp_remove_overlay for deferred
94826
+ pragmas as well in traditional mode.
94827
+
94828
2010-12-16 Release Manager
94829
94830
* GCC 4.5.2 released.
94831
--- a/src/libcpp/directives.c
94832
+++ b/src/libcpp/directives.c
94833
@@ -280,16 +280,17 @@
94834
static void
94835
end_directive (cpp_reader *pfile, int skip_line)
94836
{
94837
- if (pfile->state.in_deferred_pragma)
94838
- ;
94839
- else if (CPP_OPTION (pfile, traditional))
94840
+ if (CPP_OPTION (pfile, traditional))
94841
{
94842
/* Revert change of prepare_directive_trad. */
94843
- pfile->state.prevent_expansion--;
94844
+ if (!pfile->state.in_deferred_pragma)
94845
+ pfile->state.prevent_expansion--;
94846
94847
if (pfile->directive != &dtable[T_DEFINE])
94848
_cpp_remove_overlay (pfile);
94849
}
94850
+ else if (pfile->state.in_deferred_pragma)
94851
+ ;
94852
/* We don't skip for an assembler #. */
94853
else if (skip_line)
94854
{
94855
@@ -1792,7 +1793,12 @@
94856
94857
if (node)
94858
{
94859
- skip = node->type != NT_MACRO;
94860
+ /* Do not treat conditional macros as being defined. This is due to
94861
+ the powerpc and spu ports using conditional macros for 'vector',
94862
+ 'bool', and 'pixel' to act as conditional keywords. This messes
94863
+ up tests like #ifndef bool. */
94864
+ skip = (node->type != NT_MACRO
94865
+ || ((node->flags & NODE_CONDITIONAL) != 0));
94866
_cpp_mark_macro_used (node);
94867
if (!(node->flags & NODE_USED))
94868
{
94869
@@ -1830,7 +1836,12 @@
94870
94871
if (node)
94872
{
94873
- skip = node->type == NT_MACRO;
94874
+ /* Do not treat conditional macros as being defined. This is due to
94875
+ the powerpc and spu ports using conditional macros for 'vector',
94876
+ 'bool', and 'pixel' to act as conditional keywords. This messes
94877
+ up tests like #ifndef bool. */
94878
+ skip = (node->type == NT_MACRO
94879
+ && ((node->flags & NODE_CONDITIONAL) == 0));
94880
_cpp_mark_macro_used (node);
94881
if (!(node->flags & NODE_USED))
94882
{
94883
--- a/src/libcpp/expr.c
94884
+++ b/src/libcpp/expr.c
94885
@@ -711,10 +711,15 @@
94886
94887
pfile->state.prevent_expansion--;
94888
94889
+ /* Do not treat conditional macros as being defined. This is due to the
94890
+ powerpc and spu ports using conditional macros for 'vector', 'bool', and
94891
+ 'pixel' to act as conditional keywords. This messes up tests like #ifndef
94892
+ bool. */
94893
result.unsignedp = false;
94894
result.high = 0;
94895
result.overflow = false;
94896
- result.low = node && node->type == NT_MACRO;
94897
+ result.low = (node && node->type == NT_MACRO
94898
+ && (node->flags & NODE_CONDITIONAL) == 0);
94899
return result;
94900
}
94901
94902
82655
--- a/src/libffi/ChangeLog
94903
82656
+++ b/src/libffi/ChangeLog
94904
@@ -1,3 +1,18 @@
94905
+2011-02-09 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
94906
+
94907
+ PR libffi/46661
94908
+ * testsuite/libffi.call/cls_pointer.c (main): Cast void * to
94909
+ uintptr_t first.
94910
+ * testsuite/libffi.call/cls_pointer_stack.c (main): Likewise.
94911
+
94912
+2010-12-17 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
94913
+
94914
+ Backport from mainline:
94915
+ 2010-12-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
94916
+
94917
+ * testsuite/libffi.call/ffitest.h [__sgi] (PRId64, PRIu64): Define.
94918
+ (PRIuPTR): Define.
94919
+
94920
2010-12-16 Release Manager
94921
94922
* GCC 4.5.2 released.
94923
--- a/src/libffi/testsuite/libffi.call/cls_pointer.c
94924
+++ b/src/libffi/testsuite/libffi.call/cls_pointer.c
94925
@@ -65,7 +65,7 @@
94926
94927
CHECK(ffi_prep_closure_loc(pcl, &cif, cls_pointer_gn, NULL, code) == FFI_OK);
94928
94929
- res = (ffi_arg)((void*(*)(void*, void*))(code))(arg1, arg2);
94930
+ res = (ffi_arg)(uintptr_t)((void*(*)(void*, void*))(code))(arg1, arg2);
94931
/* { dg-output "\n0x12345678 0x89abcdef: 0x9be02467" } */
94932
printf("res: 0x%08x\n", (unsigned int) res);
94933
/* { dg-output "\nres: 0x9be02467" } */
94934
--- a/src/libffi/testsuite/libffi.call/cls_pointer_stack.c
94935
+++ b/src/libffi/testsuite/libffi.call/cls_pointer_stack.c
94936
@@ -129,7 +129,7 @@
94937
94938
CHECK(ffi_prep_closure_loc(pcl, &cif, cls_pointer_gn, NULL, code) == FFI_OK);
94939
94940
- res = (ffi_arg)((void*(*)(void*, void*))(code))(arg1, arg2);
94941
+ res = (ffi_arg)(uintptr_t)((void*(*)(void*, void*))(code))(arg1, arg2);
94942
94943
printf("res: 0x%08x\n", (unsigned int) res);
94944
// { dg-output "\n0x01234567 0x89abcdef: 0x8acf1356" }
94945
--- a/src/libffi/testsuite/libffi.call/ffitest.h
94946
+++ b/src/libffi/testsuite/libffi.call/ffitest.h
94947
@@ -77,6 +77,26 @@
94948
#define PRIuPTR "lu"
94949
#endif
94950
94951
+/* IRIX kludge. */
94952
+#if defined(__sgi)
94953
+/* IRIX 6.5 <inttypes.h> provides all definitions, but only for C99
94954
+ compilations. */
94955
+#if (_MIPS_SZLONG == 32)
94956
+#define PRId64 "lld"
94957
+#define PRIu64 "llu"
94958
+#endif
94959
+/* This doesn't match <inttypes.h>, which always has "lld" here, but the
94960
+ arguments are uint64_t, int64_t, which are unsigned long, long for
94961
+ 64-bit in <sgidefs.h>. */
94962
+#if (_MIPS_SZLONG == 64)
94963
+#define PRId64 "ld"
94964
+#define PRIu64 "lu"
94965
+#endif
94966
+/* This doesn't match <inttypes.h>, which has "u" here, but the arguments
94967
+ are uintptr_t, which is always unsigned long. */
94968
+#define PRIuPTR "lu"
94969
+#endif
94970
+
94971
/* Solaris < 10 kludge. */
94972
#if defined(__sun__) && defined(__svr4__) && !defined(PRIuPTR)
94973
#if defined(__arch64__) || defined (__x86_64__)
94974
--- a/src/libgcc/ChangeLog
94975
+++ b/src/libgcc/ChangeLog
94976
@@ -1,3 +1,15 @@
94977
+2011-02-23 Nathan Froyd <froydnj@codesourcery.com>
94978
+
94979
+ PR target/43810
94980
+
94981
+ Backport from mainline:
94982
+ 2010-07-23 Nathan Froyd <froydnj@codesourcery.com>
94983
+
94984
+ * config.host (powerpc*-eabispe*): Set tmake_file.
94985
+ (powerpc*-eabi*): Likewise.
94986
+ * config/rs6000/t-ppccomm (EXTRA_PARTS): Add crtbegin, crtend,
94987
+ crtbeginS, crtendS, crtbeginT.
94988
+
94989
2010-12-16 Release Manager
94990
94991
* GCC 4.5.2 released.
82657
@@ -1,3 +1,13 @@
82658
+2011-05-02 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
82659
+
82660
+ Backport from mainline:
82661
+ 2011-04-29 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
82662
+
82663
+ * src/alpha/osf.S (UA_SI, FDE_ENCODING, FDE_ENCODE, FDE_ARANGE):
82664
+ Define.
82665
+ Use them to handle ELF vs. ECOFF differences.
82666
+ [__osf__] (_GLOBAL__F_ffi_call_osf): Define.
82667
+
82668
2011-04-28 Release Manager
82669
82670
* GCC 4.5.3 released.
82671
--- a/src/libffi/src/alpha/osf.S
82672
+++ b/src/libffi/src/alpha/osf.S
82673
@@ -1,5 +1,5 @@
82674
/* -----------------------------------------------------------------------
82675
- osf.S - Copyright (c) 1998, 2001, 2007, 2008 Red Hat
82676
+ osf.S - Copyright (c) 1998, 2001, 2007, 2008, 2011 Red Hat
82677
82678
Alpha/OSF Foreign Function Interface
82679
82680
@@ -299,33 +299,51 @@
82681
#endif
82682
82683
#ifdef __ELF__
82684
+# define UA_SI .4byte
82685
+# define FDE_ENCODING 0x1b /* pcrel sdata4 */
82686
+# define FDE_ENCODE(X) .4byte X-.
82687
+# define FDE_ARANGE(X) .4byte X
82688
+#elif defined __osf__
82689
+# define UA_SI .align 0; .long
82690
+# define FDE_ENCODING 0x50 /* aligned absolute */
82691
+# define FDE_ENCODE(X) .align 3; .quad X
82692
+# define FDE_ARANGE(X) .align 0; .quad X
82693
+#endif
82694
+
82695
+#ifdef __ELF__
82696
.section .eh_frame,EH_FRAME_FLAGS,@progbits
82697
+#elif defined __osf__
82698
+ .data
82699
+ .align 3
82700
+ .globl _GLOBAL__F_ffi_call_osf
82701
+_GLOBAL__F_ffi_call_osf:
82702
+#endif
82703
__FRAME_BEGIN__:
82704
- .4byte $LECIE1-$LSCIE1 # Length of Common Information Entry
82705
+ UA_SI $LECIE1-$LSCIE1 # Length of Common Information Entry
82706
$LSCIE1:
82707
- .4byte 0x0 # CIE Identifier Tag
82708
+ UA_SI 0x0 # CIE Identifier Tag
82709
.byte 0x1 # CIE Version
82710
.ascii "zR\0" # CIE Augmentation
82711
.byte 0x1 # uleb128 0x1; CIE Code Alignment Factor
82712
.byte 0x78 # sleb128 -8; CIE Data Alignment Factor
82713
.byte 26 # CIE RA Column
82714
.byte 0x1 # uleb128 0x1; Augmentation size
82715
- .byte 0x1b # FDE Encoding (pcrel sdata4)
82716
+ .byte FDE_ENCODING # FDE Encoding
82717
.byte 0xc # DW_CFA_def_cfa
82718
.byte 30 # uleb128 column 30
82719
.byte 0 # uleb128 offset 0
82720
.align 3
82721
$LECIE1:
82722
$LSFDE1:
82723
- .4byte $LEFDE1-$LASFDE1 # FDE Length
82724
+ UA_SI $LEFDE1-$LASFDE1 # FDE Length
82725
$LASFDE1:
82726
- .4byte $LASFDE1-__FRAME_BEGIN__ # FDE CIE offset
82727
- .4byte $LFB1-. # FDE initial location
82728
- .4byte $LFE1-$LFB1 # FDE address range
82729
+ UA_SI $LASFDE1-__FRAME_BEGIN__ # FDE CIE offset
82730
+ FDE_ENCODE($LFB1) # FDE initial location
82731
+ FDE_ARANGE($LFE1-$LFB1) # FDE address range
82732
.byte 0x0 # uleb128 0x0; Augmentation size
82733
82734
.byte 0x4 # DW_CFA_advance_loc4
82735
- .4byte $LCFI1-$LFB1
82736
+ UA_SI $LCFI1-$LFB1
82737
.byte 0x9a # DW_CFA_offset, column 26
82738
.byte 4 # uleb128 4*-8
82739
.byte 0x8f # DW_CFA_offset, column 15
82740
@@ -335,32 +353,35 @@
82741
.byte 32 # uleb128 offset 32
82742
82743
.byte 0x4 # DW_CFA_advance_loc4
82744
- .4byte $LCFI2-$LCFI1
82745
+ UA_SI $LCFI2-$LCFI1
82746
.byte 0xda # DW_CFA_restore, column 26
82747
.align 3
82748
$LEFDE1:
82749
82750
$LSFDE3:
82751
- .4byte $LEFDE3-$LASFDE3 # FDE Length
82752
+ UA_SI $LEFDE3-$LASFDE3 # FDE Length
82753
$LASFDE3:
82754
- .4byte $LASFDE3-__FRAME_BEGIN__ # FDE CIE offset
82755
- .4byte $LFB2-. # FDE initial location
82756
- .4byte $LFE2-$LFB2 # FDE address range
82757
+ UA_SI $LASFDE3-__FRAME_BEGIN__ # FDE CIE offset
82758
+ FDE_ENCODE($LFB2) # FDE initial location
82759
+ FDE_ARANGE($LFE2-$LFB2) # FDE address range
82760
.byte 0x0 # uleb128 0x0; Augmentation size
82761
82762
.byte 0x4 # DW_CFA_advance_loc4
82763
- .4byte $LCFI5-$LFB2
82764
+ UA_SI $LCFI5-$LFB2
82765
.byte 0xe # DW_CFA_def_cfa_offset
82766
.byte 0x80,0x1 # uleb128 128
82767
82768
.byte 0x4 # DW_CFA_advance_loc4
82769
- .4byte $LCFI6-$LCFI5
82770
+ UA_SI $LCFI6-$LCFI5
82771
.byte 0x9a # DW_CFA_offset, column 26
82772
.byte 16 # uleb128 offset 16*-8
82773
.align 3
82774
$LEFDE3:
82775
+#if defined __osf__
82776
+ .align 0
82777
+ .long 0 # End of Table
82778
+#endif
82779
82780
-#ifdef __linux__
82781
+#if defined __ELF__ && defined __linux__
82782
.section .note.GNU-stack,"",@progbits
82783
#endif
82784
-#endif
94992
82785
--- a/src/libgcc/Makefile.in
94993
82786
+++ b/src/libgcc/Makefile.in
94994
82787
@@ -400,18 +400,24 @@
95025
82818
+# the unwinder in simple programs which use 64-bit division. Omitting
95026
82819
+# the option is safe.
95027
82820
+LIB2_DIVMOD_EXCEPTION_FLAGS := -fexceptions
95028
--- a/src/libgcc/config/rs6000/t-ppccomm
95029
+++ b/src/libgcc/config/rs6000/t-ppccomm
95030
@@ -15,7 +15,9 @@
95031
e500crtsavg64gpr.S \
95032
e500crtsavg64gprctr.S
95033
95034
-EXTRA_PARTS += ecrti$(objext) ecrtn$(objext) ncrti$(objext) ncrtn$(objext)
95035
+EXTRA_PARTS += crtbegin$(objext) crtend$(objext) \
95036
+ crtbeginS$(objext) crtendS$(objext) crtbeginT$(objext) \
95037
+ ecrti$(objext) ecrtn$(objext) ncrti$(objext) ncrtn$(objext)
95038
95039
# We build {e,n}crti.o and {e,n}crtn.o, which serve to add begin and
95040
# end labels to all of the special sections used when we link using gcc.
95041
82821
--- a/src/libgcc/config.host
95042
82822
+++ b/src/libgcc/config.host
95043
82823
@@ -208,12 +208,15 @@
95056
82836
;;
95057
82837
arm*-*-rtems*)
95058
82838
;;
95059
@@ -456,6 +459,7 @@
95060
powerpc-*-netbsd*)
95061
;;
95062
powerpc-*-eabispe*)
95063
+ tmake_file="${tmake_file} rs6000/t-ppccomm"
95064
;;
95065
powerpc-*-eabisimaltivec*)
95066
;;
95067
@@ -466,6 +470,7 @@
95068
powerpc-*-eabialtivec*)
95069
;;
95070
powerpc-*-eabi*)
95071
+ tmake_file="${tmake_file} rs6000/t-ppccomm"
95072
;;
95073
powerpc-*-rtems*)
95074
;;
95075
82839
--- a/src/libgcc/shared-object.mk
95076
82840
+++ b/src/libgcc/shared-object.mk
95077
82841
@@ -8,11 +8,13 @@
95103
82867
95104
82868
else
95105
82869
95106
--- a/src/libgfortran/ChangeLog
95107
+++ b/src/libgfortran/ChangeLog
95108
@@ -1,3 +1,153 @@
95109
+2011-03-13 Thomas Koenig <tkoenig@gcc.gnu.org>
95110
+
95111
+ PR libfortran/48066
95112
+ Backport from trunk
95113
+ * m4/ifunction.m4: If return array is empty, return.
95114
+ * m4/ifunction_logical.m4: Likewise.
95115
+ * generated/all_l16.c: Regenerated.
95116
+ * generated/all_l1.c: Regenerated.
95117
+ * generated/all_l2.c: Regenerated.
95118
+ * generated/all_l4.c: Regenerated.
95119
+ * generated/all_l8.c: Regenerated.
95120
+ * generated/any_l16.c: Regenerated.
95121
+ * generated/any_l1.c: Regenerated.
95122
+ * generated/any_l2.c: Regenerated.
95123
+ * generated/any_l4.c: Regenerated.
95124
+ * generated/any_l8.c: Regenerated.
95125
+ * generated/count_16_l.c: Regenerated.
95126
+ * generated/count_1_l.c: Regenerated.
95127
+ * generated/count_2_l.c: Regenerated.
95128
+ * generated/count_4_l.c: Regenerated.
95129
+ * generated/count_8_l.c: Regenerated.
95130
+ * generated/maxloc1_16_i16.c: Regenerated.
95131
+ * generated/maxloc1_16_i1.c: Regenerated.
95132
+ * generated/maxloc1_16_i2.c: Regenerated.
95133
+ * generated/maxloc1_16_i4.c: Regenerated.
95134
+ * generated/maxloc1_16_i8.c: Regenerated.
95135
+ * generated/maxloc1_16_r10.c: Regenerated.
95136
+ * generated/maxloc1_16_r16.c: Regenerated.
95137
+ * generated/maxloc1_16_r4.c: Regenerated.
95138
+ * generated/maxloc1_16_r8.c: Regenerated.
95139
+ * generated/maxloc1_4_i16.c: Regenerated.
95140
+ * generated/maxloc1_4_i1.c: Regenerated.
95141
+ * generated/maxloc1_4_i2.c: Regenerated.
95142
+ * generated/maxloc1_4_i4.c: Regenerated.
95143
+ * generated/maxloc1_4_i8.c: Regenerated.
95144
+ * generated/maxloc1_4_r10.c: Regenerated.
95145
+ * generated/maxloc1_4_r16.c: Regenerated.
95146
+ * generated/maxloc1_4_r4.c: Regenerated.
95147
+ * generated/maxloc1_4_r8.c: Regenerated.
95148
+ * generated/maxloc1_8_i16.c: Regenerated.
95149
+ * generated/maxloc1_8_i1.c: Regenerated.
95150
+ * generated/maxloc1_8_i2.c: Regenerated.
95151
+ * generated/maxloc1_8_i4.c: Regenerated.
95152
+ * generated/maxloc1_8_i8.c: Regenerated.
95153
+ * generated/maxloc1_8_r10.c: Regenerated.
95154
+ * generated/maxloc1_8_r16.c: Regenerated.
95155
+ * generated/maxloc1_8_r4.c: Regenerated.
95156
+ * generated/maxloc1_8_r8.c: Regenerated.
95157
+ * generated/maxval_i16.c: Regenerated.
95158
+ * generated/maxval_i1.c: Regenerated.
95159
+ * generated/maxval_i2.c: Regenerated.
95160
+ * generated/maxval_i4.c: Regenerated.
95161
+ * generated/maxval_i8.c: Regenerated.
95162
+ * generated/maxval_r10.c: Regenerated.
95163
+ * generated/maxval_r16.c: Regenerated.
95164
+ * generated/maxval_r4.c: Regenerated.
95165
+ * generated/maxval_r8.c: Regenerated.
95166
+ * generated/minloc1_16_i16.c: Regenerated.
95167
+ * generated/minloc1_16_i1.c: Regenerated.
95168
+ * generated/minloc1_16_i2.c: Regenerated.
95169
+ * generated/minloc1_16_i4.c: Regenerated.
95170
+ * generated/minloc1_16_i8.c: Regenerated.
95171
+ * generated/minloc1_16_r10.c: Regenerated.
95172
+ * generated/minloc1_16_r16.c: Regenerated.
95173
+ * generated/minloc1_16_r4.c: Regenerated.
95174
+ * generated/minloc1_16_r8.c: Regenerated.
95175
+ * generated/minloc1_4_i16.c: Regenerated.
95176
+ * generated/minloc1_4_i1.c: Regenerated.
95177
+ * generated/minloc1_4_i2.c: Regenerated.
95178
+ * generated/minloc1_4_i4.c: Regenerated.
95179
+ * generated/minloc1_4_i8.c: Regenerated.
95180
+ * generated/minloc1_4_r10.c: Regenerated.
95181
+ * generated/minloc1_4_r16.c: Regenerated.
95182
+ * generated/minloc1_4_r4.c: Regenerated.
95183
+ * generated/minloc1_4_r8.c: Regenerated.
95184
+ * generated/minloc1_8_i16.c: Regenerated.
95185
+ * generated/minloc1_8_i1.c: Regenerated.
95186
+ * generated/minloc1_8_i2.c: Regenerated.
95187
+ * generated/minloc1_8_i4.c: Regenerated.
95188
+ * generated/minloc1_8_i8.c: Regenerated.
95189
+ * generated/minloc1_8_r10.c: Regenerated.
95190
+ * generated/minloc1_8_r16.c: Regenerated.
95191
+ * generated/minloc1_8_r4.c: Regenerated.
95192
+ * generated/minloc1_8_r8.c: Regenerated.
95193
+ * generated/minval_i16.c: Regenerated.
95194
+ * generated/minval_i1.c: Regenerated.
95195
+ * generated/minval_i2.c: Regenerated.
95196
+ * generated/minval_i4.c: Regenerated.
95197
+ * generated/minval_i8.c: Regenerated.
95198
+ * generated/minval_r10.c: Regenerated.
95199
+ * generated/minval_r16.c: Regenerated.
95200
+ * generated/minval_r4.c: Regenerated.
95201
+ * generated/minval_r8.c: Regenerated.
95202
+ * generated/product_c10.c: Regenerated.
95203
+ * generated/product_c16.c: Regenerated.
95204
+ * generated/product_c4.c: Regenerated.
95205
+ * generated/product_c8.c: Regenerated.
95206
+ * generated/product_i16.c: Regenerated.
95207
+ * generated/product_i1.c: Regenerated.
95208
+ * generated/product_i2.c: Regenerated.
95209
+ * generated/product_i4.c: Regenerated.
95210
+ * generated/product_i8.c: Regenerated.
95211
+ * generated/product_r10.c: Regenerated.
95212
+ * generated/product_r16.c: Regenerated.
95213
+ * generated/product_r4.c: Regenerated.
95214
+ * generated/product_r8.c: Regenerated.
95215
+ * generated/sum_c10.c: Regenerated.
95216
+ * generated/sum_c16.c: Regenerated.
95217
+ * generated/sum_c4.c: Regenerated.
95218
+ * generated/sum_c8.c: Regenerated.
95219
+ * generated/sum_i16.c: Regenerated.
95220
+ * generated/sum_i1.c: Regenerated.
95221
+ * generated/sum_i2.c: Regenerated.
95222
+ * generated/sum_i4.c: Regenerated.
95223
+ * generated/sum_i8.c: Regenerated.
95224
+ * generated/sum_r10.c: Regenerated.
95225
+ * generated/sum_r16.c: Regenerated.
95226
+ * generated/sum_r4.c: Regenerated.
95227
+ * generated/sum_r8.c: Regenerated.
95228
+
95229
+2011-03-06 Jerry DeLisle <jvdelisle@gcc.gnu.org>
95230
+
95231
+ PR libgfortran/47778
95232
+ * io/list_read.c (namelist_read): Intialize the error string buffere.
95233
+ If pprev_nl was used during the previous namelist read and the rank
95234
+ was zero, reset the pointer to NULL for the next namelist read.
95235
+
95236
+2011-03-04 Jakub Jelinek <jakub@redhat.com>
95237
+
95238
+ Backport from mainline
95239
+ PR fortran/47878
95240
+ * io/transfer.c (read_sf): Call fbuf_getptr only at the end,
95241
+ and subtract n, dtp->u.p.sf_seen_eor and seen_comma from it.
95242
+
95243
+2011-03-04 Janne Blomqvist <jb@gcc.gnu.org>
95244
+ Jerry DeLisle <jvdelisle@gcc.gnu.org>
95245
+
95246
+ Backport from mainline
95247
+ PR libfortran/47694
95248
+ * io/fbuf.h (fbuf_getptr): New inline function.
95249
+ * io/transfer.c (read_sf): Use fbuf_getptr and fbuf_getc to scan
95250
+ through the string instead of fbuf_read.
95251
+
95252
+2011-02-22 Tobias Burnus <burnus@net-b.de>
95253
+ Kai-Uwe Eckhardt <kuehro@gmx.de>
95254
+
95255
+ PR libfortran/47830
95256
+ * intrinsics/c99_functions.c (roundl): Make C valid for
95257
+ HAVE_NEXTAFTERL.
95258
+
95259
2010-12-16 Release Manager
95260
95261
* GCC 4.5.2 released.
95262
--- a/src/libgfortran/generated/all_l1.c
95263
+++ b/src/libgfortran/generated/all_l1.c
95264
@@ -142,7 +142,7 @@
95265
count[n] = 0;
95266
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95267
if (extent[n] <= 0)
95268
- len = 0;
95269
+ return;
95270
}
95271
95272
base = array->data;
95273
--- a/src/libgfortran/generated/all_l16.c
95274
+++ b/src/libgfortran/generated/all_l16.c
95275
@@ -142,7 +142,7 @@
95276
count[n] = 0;
95277
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95278
if (extent[n] <= 0)
95279
- len = 0;
95280
+ return;
95281
}
95282
95283
base = array->data;
95284
--- a/src/libgfortran/generated/all_l2.c
95285
+++ b/src/libgfortran/generated/all_l2.c
95286
@@ -142,7 +142,7 @@
95287
count[n] = 0;
95288
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95289
if (extent[n] <= 0)
95290
- len = 0;
95291
+ return;
95292
}
95293
95294
base = array->data;
95295
--- a/src/libgfortran/generated/all_l4.c
95296
+++ b/src/libgfortran/generated/all_l4.c
95297
@@ -142,7 +142,7 @@
95298
count[n] = 0;
95299
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95300
if (extent[n] <= 0)
95301
- len = 0;
95302
+ return;
95303
}
95304
95305
base = array->data;
95306
--- a/src/libgfortran/generated/all_l8.c
95307
+++ b/src/libgfortran/generated/all_l8.c
95308
@@ -142,7 +142,7 @@
95309
count[n] = 0;
95310
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95311
if (extent[n] <= 0)
95312
- len = 0;
95313
+ return;
95314
}
95315
95316
base = array->data;
95317
--- a/src/libgfortran/generated/any_l1.c
95318
+++ b/src/libgfortran/generated/any_l1.c
95319
@@ -142,7 +142,7 @@
95320
count[n] = 0;
95321
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95322
if (extent[n] <= 0)
95323
- len = 0;
95324
+ return;
95325
}
95326
95327
base = array->data;
95328
--- a/src/libgfortran/generated/any_l16.c
95329
+++ b/src/libgfortran/generated/any_l16.c
95330
@@ -142,7 +142,7 @@
95331
count[n] = 0;
95332
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95333
if (extent[n] <= 0)
95334
- len = 0;
95335
+ return;
95336
}
95337
95338
base = array->data;
95339
--- a/src/libgfortran/generated/any_l2.c
95340
+++ b/src/libgfortran/generated/any_l2.c
95341
@@ -142,7 +142,7 @@
95342
count[n] = 0;
95343
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95344
if (extent[n] <= 0)
95345
- len = 0;
95346
+ return;
95347
}
95348
95349
base = array->data;
95350
--- a/src/libgfortran/generated/any_l4.c
95351
+++ b/src/libgfortran/generated/any_l4.c
95352
@@ -142,7 +142,7 @@
95353
count[n] = 0;
95354
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95355
if (extent[n] <= 0)
95356
- len = 0;
95357
+ return;
95358
}
95359
95360
base = array->data;
95361
--- a/src/libgfortran/generated/any_l8.c
95362
+++ b/src/libgfortran/generated/any_l8.c
95363
@@ -142,7 +142,7 @@
95364
count[n] = 0;
95365
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95366
if (extent[n] <= 0)
95367
- len = 0;
95368
+ return;
95369
}
95370
95371
base = array->data;
95372
--- a/src/libgfortran/generated/count_16_l.c
95373
+++ b/src/libgfortran/generated/count_16_l.c
95374
@@ -142,7 +142,7 @@
95375
count[n] = 0;
95376
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95377
if (extent[n] <= 0)
95378
- len = 0;
95379
+ return;
95380
}
95381
95382
base = array->data;
95383
--- a/src/libgfortran/generated/count_1_l.c
95384
+++ b/src/libgfortran/generated/count_1_l.c
95385
@@ -142,7 +142,7 @@
95386
count[n] = 0;
95387
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95388
if (extent[n] <= 0)
95389
- len = 0;
95390
+ return;
95391
}
95392
95393
base = array->data;
95394
--- a/src/libgfortran/generated/count_2_l.c
95395
+++ b/src/libgfortran/generated/count_2_l.c
95396
@@ -142,7 +142,7 @@
95397
count[n] = 0;
95398
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95399
if (extent[n] <= 0)
95400
- len = 0;
95401
+ return;
95402
}
95403
95404
base = array->data;
95405
--- a/src/libgfortran/generated/count_4_l.c
95406
+++ b/src/libgfortran/generated/count_4_l.c
95407
@@ -142,7 +142,7 @@
95408
count[n] = 0;
95409
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95410
if (extent[n] <= 0)
95411
- len = 0;
95412
+ return;
95413
}
95414
95415
base = array->data;
95416
--- a/src/libgfortran/generated/count_8_l.c
95417
+++ b/src/libgfortran/generated/count_8_l.c
95418
@@ -142,7 +142,7 @@
95419
count[n] = 0;
95420
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95421
if (extent[n] <= 0)
95422
- len = 0;
95423
+ return;
95424
}
95425
95426
base = array->data;
95427
--- a/src/libgfortran/generated/maxloc1_16_i1.c
95428
+++ b/src/libgfortran/generated/maxloc1_16_i1.c
95429
@@ -129,7 +129,7 @@
95430
count[n] = 0;
95431
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95432
if (extent[n] <= 0)
95433
- len = 0;
95434
+ return;
95435
}
95436
95437
base = array->data;
95438
--- a/src/libgfortran/generated/maxloc1_16_i16.c
95439
+++ b/src/libgfortran/generated/maxloc1_16_i16.c
95440
@@ -129,7 +129,7 @@
95441
count[n] = 0;
95442
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95443
if (extent[n] <= 0)
95444
- len = 0;
95445
+ return;
95446
}
95447
95448
base = array->data;
95449
--- a/src/libgfortran/generated/maxloc1_16_i2.c
95450
+++ b/src/libgfortran/generated/maxloc1_16_i2.c
95451
@@ -129,7 +129,7 @@
95452
count[n] = 0;
95453
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95454
if (extent[n] <= 0)
95455
- len = 0;
95456
+ return;
95457
}
95458
95459
base = array->data;
95460
--- a/src/libgfortran/generated/maxloc1_16_i4.c
95461
+++ b/src/libgfortran/generated/maxloc1_16_i4.c
95462
@@ -129,7 +129,7 @@
95463
count[n] = 0;
95464
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95465
if (extent[n] <= 0)
95466
- len = 0;
95467
+ return;
95468
}
95469
95470
base = array->data;
95471
--- a/src/libgfortran/generated/maxloc1_16_i8.c
95472
+++ b/src/libgfortran/generated/maxloc1_16_i8.c
95473
@@ -129,7 +129,7 @@
95474
count[n] = 0;
95475
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95476
if (extent[n] <= 0)
95477
- len = 0;
95478
+ return;
95479
}
95480
95481
base = array->data;
95482
--- a/src/libgfortran/generated/maxloc1_16_r10.c
95483
+++ b/src/libgfortran/generated/maxloc1_16_r10.c
95484
@@ -129,7 +129,7 @@
95485
count[n] = 0;
95486
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95487
if (extent[n] <= 0)
95488
- len = 0;
95489
+ return;
95490
}
95491
95492
base = array->data;
95493
--- a/src/libgfortran/generated/maxloc1_16_r16.c
95494
+++ b/src/libgfortran/generated/maxloc1_16_r16.c
95495
@@ -129,7 +129,7 @@
95496
count[n] = 0;
95497
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95498
if (extent[n] <= 0)
95499
- len = 0;
95500
+ return;
95501
}
95502
95503
base = array->data;
95504
--- a/src/libgfortran/generated/maxloc1_16_r4.c
95505
+++ b/src/libgfortran/generated/maxloc1_16_r4.c
95506
@@ -129,7 +129,7 @@
95507
count[n] = 0;
95508
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95509
if (extent[n] <= 0)
95510
- len = 0;
95511
+ return;
95512
}
95513
95514
base = array->data;
95515
--- a/src/libgfortran/generated/maxloc1_16_r8.c
95516
+++ b/src/libgfortran/generated/maxloc1_16_r8.c
95517
@@ -129,7 +129,7 @@
95518
count[n] = 0;
95519
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95520
if (extent[n] <= 0)
95521
- len = 0;
95522
+ return;
95523
}
95524
95525
base = array->data;
95526
--- a/src/libgfortran/generated/maxloc1_4_i1.c
95527
+++ b/src/libgfortran/generated/maxloc1_4_i1.c
95528
@@ -129,7 +129,7 @@
95529
count[n] = 0;
95530
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95531
if (extent[n] <= 0)
95532
- len = 0;
95533
+ return;
95534
}
95535
95536
base = array->data;
95537
--- a/src/libgfortran/generated/maxloc1_4_i16.c
95538
+++ b/src/libgfortran/generated/maxloc1_4_i16.c
95539
@@ -129,7 +129,7 @@
95540
count[n] = 0;
95541
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95542
if (extent[n] <= 0)
95543
- len = 0;
95544
+ return;
95545
}
95546
95547
base = array->data;
95548
--- a/src/libgfortran/generated/maxloc1_4_i2.c
95549
+++ b/src/libgfortran/generated/maxloc1_4_i2.c
95550
@@ -129,7 +129,7 @@
95551
count[n] = 0;
95552
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95553
if (extent[n] <= 0)
95554
- len = 0;
95555
+ return;
95556
}
95557
95558
base = array->data;
95559
--- a/src/libgfortran/generated/maxloc1_4_i4.c
95560
+++ b/src/libgfortran/generated/maxloc1_4_i4.c
95561
@@ -129,7 +129,7 @@
95562
count[n] = 0;
95563
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95564
if (extent[n] <= 0)
95565
- len = 0;
95566
+ return;
95567
}
95568
95569
base = array->data;
95570
--- a/src/libgfortran/generated/maxloc1_4_i8.c
95571
+++ b/src/libgfortran/generated/maxloc1_4_i8.c
95572
@@ -129,7 +129,7 @@
95573
count[n] = 0;
95574
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95575
if (extent[n] <= 0)
95576
- len = 0;
95577
+ return;
95578
}
95579
95580
base = array->data;
95581
--- a/src/libgfortran/generated/maxloc1_4_r10.c
95582
+++ b/src/libgfortran/generated/maxloc1_4_r10.c
95583
@@ -129,7 +129,7 @@
95584
count[n] = 0;
95585
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95586
if (extent[n] <= 0)
95587
- len = 0;
95588
+ return;
95589
}
95590
95591
base = array->data;
95592
--- a/src/libgfortran/generated/maxloc1_4_r16.c
95593
+++ b/src/libgfortran/generated/maxloc1_4_r16.c
95594
@@ -129,7 +129,7 @@
95595
count[n] = 0;
95596
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95597
if (extent[n] <= 0)
95598
- len = 0;
95599
+ return;
95600
}
95601
95602
base = array->data;
95603
--- a/src/libgfortran/generated/maxloc1_4_r4.c
95604
+++ b/src/libgfortran/generated/maxloc1_4_r4.c
95605
@@ -129,7 +129,7 @@
95606
count[n] = 0;
95607
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95608
if (extent[n] <= 0)
95609
- len = 0;
95610
+ return;
95611
}
95612
95613
base = array->data;
95614
--- a/src/libgfortran/generated/maxloc1_4_r8.c
95615
+++ b/src/libgfortran/generated/maxloc1_4_r8.c
95616
@@ -129,7 +129,7 @@
95617
count[n] = 0;
95618
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95619
if (extent[n] <= 0)
95620
- len = 0;
95621
+ return;
95622
}
95623
95624
base = array->data;
95625
--- a/src/libgfortran/generated/maxloc1_8_i1.c
95626
+++ b/src/libgfortran/generated/maxloc1_8_i1.c
95627
@@ -129,7 +129,7 @@
95628
count[n] = 0;
95629
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95630
if (extent[n] <= 0)
95631
- len = 0;
95632
+ return;
95633
}
95634
95635
base = array->data;
95636
--- a/src/libgfortran/generated/maxloc1_8_i16.c
95637
+++ b/src/libgfortran/generated/maxloc1_8_i16.c
95638
@@ -129,7 +129,7 @@
95639
count[n] = 0;
95640
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95641
if (extent[n] <= 0)
95642
- len = 0;
95643
+ return;
95644
}
95645
95646
base = array->data;
95647
--- a/src/libgfortran/generated/maxloc1_8_i2.c
95648
+++ b/src/libgfortran/generated/maxloc1_8_i2.c
95649
@@ -129,7 +129,7 @@
95650
count[n] = 0;
95651
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95652
if (extent[n] <= 0)
95653
- len = 0;
95654
+ return;
95655
}
95656
95657
base = array->data;
95658
--- a/src/libgfortran/generated/maxloc1_8_i4.c
95659
+++ b/src/libgfortran/generated/maxloc1_8_i4.c
95660
@@ -129,7 +129,7 @@
95661
count[n] = 0;
95662
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95663
if (extent[n] <= 0)
95664
- len = 0;
95665
+ return;
95666
}
95667
95668
base = array->data;
95669
--- a/src/libgfortran/generated/maxloc1_8_i8.c
95670
+++ b/src/libgfortran/generated/maxloc1_8_i8.c
95671
@@ -129,7 +129,7 @@
95672
count[n] = 0;
95673
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95674
if (extent[n] <= 0)
95675
- len = 0;
95676
+ return;
95677
}
95678
95679
base = array->data;
95680
--- a/src/libgfortran/generated/maxloc1_8_r10.c
95681
+++ b/src/libgfortran/generated/maxloc1_8_r10.c
95682
@@ -129,7 +129,7 @@
95683
count[n] = 0;
95684
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95685
if (extent[n] <= 0)
95686
- len = 0;
95687
+ return;
95688
}
95689
95690
base = array->data;
95691
--- a/src/libgfortran/generated/maxloc1_8_r16.c
95692
+++ b/src/libgfortran/generated/maxloc1_8_r16.c
95693
@@ -129,7 +129,7 @@
95694
count[n] = 0;
95695
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95696
if (extent[n] <= 0)
95697
- len = 0;
95698
+ return;
95699
}
95700
95701
base = array->data;
95702
--- a/src/libgfortran/generated/maxloc1_8_r4.c
95703
+++ b/src/libgfortran/generated/maxloc1_8_r4.c
95704
@@ -129,7 +129,7 @@
95705
count[n] = 0;
95706
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95707
if (extent[n] <= 0)
95708
- len = 0;
95709
+ return;
95710
}
95711
95712
base = array->data;
95713
--- a/src/libgfortran/generated/maxloc1_8_r8.c
95714
+++ b/src/libgfortran/generated/maxloc1_8_r8.c
95715
@@ -129,7 +129,7 @@
95716
count[n] = 0;
95717
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95718
if (extent[n] <= 0)
95719
- len = 0;
95720
+ return;
95721
}
95722
95723
base = array->data;
95724
--- a/src/libgfortran/generated/maxval_i1.c
95725
+++ b/src/libgfortran/generated/maxval_i1.c
95726
@@ -128,7 +128,7 @@
95727
count[n] = 0;
95728
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95729
if (extent[n] <= 0)
95730
- len = 0;
95731
+ return;
95732
}
95733
95734
base = array->data;
95735
--- a/src/libgfortran/generated/maxval_i16.c
95736
+++ b/src/libgfortran/generated/maxval_i16.c
95737
@@ -128,7 +128,7 @@
95738
count[n] = 0;
95739
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95740
if (extent[n] <= 0)
95741
- len = 0;
95742
+ return;
95743
}
95744
95745
base = array->data;
95746
--- a/src/libgfortran/generated/maxval_i2.c
95747
+++ b/src/libgfortran/generated/maxval_i2.c
95748
@@ -128,7 +128,7 @@
95749
count[n] = 0;
95750
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95751
if (extent[n] <= 0)
95752
- len = 0;
95753
+ return;
95754
}
95755
95756
base = array->data;
95757
--- a/src/libgfortran/generated/maxval_i4.c
95758
+++ b/src/libgfortran/generated/maxval_i4.c
95759
@@ -128,7 +128,7 @@
95760
count[n] = 0;
95761
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95762
if (extent[n] <= 0)
95763
- len = 0;
95764
+ return;
95765
}
95766
95767
base = array->data;
95768
--- a/src/libgfortran/generated/maxval_i8.c
95769
+++ b/src/libgfortran/generated/maxval_i8.c
95770
@@ -128,7 +128,7 @@
95771
count[n] = 0;
95772
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95773
if (extent[n] <= 0)
95774
- len = 0;
95775
+ return;
95776
}
95777
95778
base = array->data;
95779
--- a/src/libgfortran/generated/maxval_r10.c
95780
+++ b/src/libgfortran/generated/maxval_r10.c
95781
@@ -128,7 +128,7 @@
95782
count[n] = 0;
95783
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95784
if (extent[n] <= 0)
95785
- len = 0;
95786
+ return;
95787
}
95788
95789
base = array->data;
95790
--- a/src/libgfortran/generated/maxval_r16.c
95791
+++ b/src/libgfortran/generated/maxval_r16.c
95792
@@ -128,7 +128,7 @@
95793
count[n] = 0;
95794
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95795
if (extent[n] <= 0)
95796
- len = 0;
95797
+ return;
95798
}
95799
95800
base = array->data;
95801
--- a/src/libgfortran/generated/maxval_r4.c
95802
+++ b/src/libgfortran/generated/maxval_r4.c
95803
@@ -128,7 +128,7 @@
95804
count[n] = 0;
95805
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95806
if (extent[n] <= 0)
95807
- len = 0;
95808
+ return;
95809
}
95810
95811
base = array->data;
95812
--- a/src/libgfortran/generated/maxval_r8.c
95813
+++ b/src/libgfortran/generated/maxval_r8.c
95814
@@ -128,7 +128,7 @@
95815
count[n] = 0;
95816
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95817
if (extent[n] <= 0)
95818
- len = 0;
95819
+ return;
95820
}
95821
95822
base = array->data;
95823
--- a/src/libgfortran/generated/minloc1_16_i1.c
95824
+++ b/src/libgfortran/generated/minloc1_16_i1.c
95825
@@ -129,7 +129,7 @@
95826
count[n] = 0;
95827
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95828
if (extent[n] <= 0)
95829
- len = 0;
95830
+ return;
95831
}
95832
95833
base = array->data;
95834
--- a/src/libgfortran/generated/minloc1_16_i16.c
95835
+++ b/src/libgfortran/generated/minloc1_16_i16.c
95836
@@ -129,7 +129,7 @@
95837
count[n] = 0;
95838
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95839
if (extent[n] <= 0)
95840
- len = 0;
95841
+ return;
95842
}
95843
95844
base = array->data;
95845
--- a/src/libgfortran/generated/minloc1_16_i2.c
95846
+++ b/src/libgfortran/generated/minloc1_16_i2.c
95847
@@ -129,7 +129,7 @@
95848
count[n] = 0;
95849
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95850
if (extent[n] <= 0)
95851
- len = 0;
95852
+ return;
95853
}
95854
95855
base = array->data;
95856
--- a/src/libgfortran/generated/minloc1_16_i4.c
95857
+++ b/src/libgfortran/generated/minloc1_16_i4.c
95858
@@ -129,7 +129,7 @@
95859
count[n] = 0;
95860
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95861
if (extent[n] <= 0)
95862
- len = 0;
95863
+ return;
95864
}
95865
95866
base = array->data;
95867
--- a/src/libgfortran/generated/minloc1_16_i8.c
95868
+++ b/src/libgfortran/generated/minloc1_16_i8.c
95869
@@ -129,7 +129,7 @@
95870
count[n] = 0;
95871
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95872
if (extent[n] <= 0)
95873
- len = 0;
95874
+ return;
95875
}
95876
95877
base = array->data;
95878
--- a/src/libgfortran/generated/minloc1_16_r10.c
95879
+++ b/src/libgfortran/generated/minloc1_16_r10.c
95880
@@ -129,7 +129,7 @@
95881
count[n] = 0;
95882
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95883
if (extent[n] <= 0)
95884
- len = 0;
95885
+ return;
95886
}
95887
95888
base = array->data;
95889
--- a/src/libgfortran/generated/minloc1_16_r16.c
95890
+++ b/src/libgfortran/generated/minloc1_16_r16.c
95891
@@ -129,7 +129,7 @@
95892
count[n] = 0;
95893
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95894
if (extent[n] <= 0)
95895
- len = 0;
95896
+ return;
95897
}
95898
95899
base = array->data;
95900
--- a/src/libgfortran/generated/minloc1_16_r4.c
95901
+++ b/src/libgfortran/generated/minloc1_16_r4.c
95902
@@ -129,7 +129,7 @@
95903
count[n] = 0;
95904
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95905
if (extent[n] <= 0)
95906
- len = 0;
95907
+ return;
95908
}
95909
95910
base = array->data;
95911
--- a/src/libgfortran/generated/minloc1_16_r8.c
95912
+++ b/src/libgfortran/generated/minloc1_16_r8.c
95913
@@ -129,7 +129,7 @@
95914
count[n] = 0;
95915
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95916
if (extent[n] <= 0)
95917
- len = 0;
95918
+ return;
95919
}
95920
95921
base = array->data;
95922
--- a/src/libgfortran/generated/minloc1_4_i1.c
95923
+++ b/src/libgfortran/generated/minloc1_4_i1.c
95924
@@ -129,7 +129,7 @@
95925
count[n] = 0;
95926
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95927
if (extent[n] <= 0)
95928
- len = 0;
95929
+ return;
95930
}
95931
95932
base = array->data;
95933
--- a/src/libgfortran/generated/minloc1_4_i16.c
95934
+++ b/src/libgfortran/generated/minloc1_4_i16.c
95935
@@ -129,7 +129,7 @@
95936
count[n] = 0;
95937
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95938
if (extent[n] <= 0)
95939
- len = 0;
95940
+ return;
95941
}
95942
95943
base = array->data;
95944
--- a/src/libgfortran/generated/minloc1_4_i2.c
95945
+++ b/src/libgfortran/generated/minloc1_4_i2.c
95946
@@ -129,7 +129,7 @@
95947
count[n] = 0;
95948
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95949
if (extent[n] <= 0)
95950
- len = 0;
95951
+ return;
95952
}
95953
95954
base = array->data;
95955
--- a/src/libgfortran/generated/minloc1_4_i4.c
95956
+++ b/src/libgfortran/generated/minloc1_4_i4.c
95957
@@ -129,7 +129,7 @@
95958
count[n] = 0;
95959
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95960
if (extent[n] <= 0)
95961
- len = 0;
95962
+ return;
95963
}
95964
95965
base = array->data;
95966
--- a/src/libgfortran/generated/minloc1_4_i8.c
95967
+++ b/src/libgfortran/generated/minloc1_4_i8.c
95968
@@ -129,7 +129,7 @@
95969
count[n] = 0;
95970
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95971
if (extent[n] <= 0)
95972
- len = 0;
95973
+ return;
95974
}
95975
95976
base = array->data;
95977
--- a/src/libgfortran/generated/minloc1_4_r10.c
95978
+++ b/src/libgfortran/generated/minloc1_4_r10.c
95979
@@ -129,7 +129,7 @@
95980
count[n] = 0;
95981
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95982
if (extent[n] <= 0)
95983
- len = 0;
95984
+ return;
95985
}
95986
95987
base = array->data;
95988
--- a/src/libgfortran/generated/minloc1_4_r16.c
95989
+++ b/src/libgfortran/generated/minloc1_4_r16.c
95990
@@ -129,7 +129,7 @@
95991
count[n] = 0;
95992
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
95993
if (extent[n] <= 0)
95994
- len = 0;
95995
+ return;
95996
}
95997
95998
base = array->data;
95999
--- a/src/libgfortran/generated/minloc1_4_r4.c
96000
+++ b/src/libgfortran/generated/minloc1_4_r4.c
96001
@@ -129,7 +129,7 @@
96002
count[n] = 0;
96003
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96004
if (extent[n] <= 0)
96005
- len = 0;
96006
+ return;
96007
}
96008
96009
base = array->data;
96010
--- a/src/libgfortran/generated/minloc1_4_r8.c
96011
+++ b/src/libgfortran/generated/minloc1_4_r8.c
96012
@@ -129,7 +129,7 @@
96013
count[n] = 0;
96014
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96015
if (extent[n] <= 0)
96016
- len = 0;
96017
+ return;
96018
}
96019
96020
base = array->data;
96021
--- a/src/libgfortran/generated/minloc1_8_i1.c
96022
+++ b/src/libgfortran/generated/minloc1_8_i1.c
96023
@@ -129,7 +129,7 @@
96024
count[n] = 0;
96025
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96026
if (extent[n] <= 0)
96027
- len = 0;
96028
+ return;
96029
}
96030
96031
base = array->data;
96032
--- a/src/libgfortran/generated/minloc1_8_i16.c
96033
+++ b/src/libgfortran/generated/minloc1_8_i16.c
96034
@@ -129,7 +129,7 @@
96035
count[n] = 0;
96036
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96037
if (extent[n] <= 0)
96038
- len = 0;
96039
+ return;
96040
}
96041
96042
base = array->data;
96043
--- a/src/libgfortran/generated/minloc1_8_i2.c
96044
+++ b/src/libgfortran/generated/minloc1_8_i2.c
96045
@@ -129,7 +129,7 @@
96046
count[n] = 0;
96047
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96048
if (extent[n] <= 0)
96049
- len = 0;
96050
+ return;
96051
}
96052
96053
base = array->data;
96054
--- a/src/libgfortran/generated/minloc1_8_i4.c
96055
+++ b/src/libgfortran/generated/minloc1_8_i4.c
96056
@@ -129,7 +129,7 @@
96057
count[n] = 0;
96058
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96059
if (extent[n] <= 0)
96060
- len = 0;
96061
+ return;
96062
}
96063
96064
base = array->data;
96065
--- a/src/libgfortran/generated/minloc1_8_i8.c
96066
+++ b/src/libgfortran/generated/minloc1_8_i8.c
96067
@@ -129,7 +129,7 @@
96068
count[n] = 0;
96069
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96070
if (extent[n] <= 0)
96071
- len = 0;
96072
+ return;
96073
}
96074
96075
base = array->data;
96076
--- a/src/libgfortran/generated/minloc1_8_r10.c
96077
+++ b/src/libgfortran/generated/minloc1_8_r10.c
96078
@@ -129,7 +129,7 @@
96079
count[n] = 0;
96080
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96081
if (extent[n] <= 0)
96082
- len = 0;
96083
+ return;
96084
}
96085
96086
base = array->data;
96087
--- a/src/libgfortran/generated/minloc1_8_r16.c
96088
+++ b/src/libgfortran/generated/minloc1_8_r16.c
96089
@@ -129,7 +129,7 @@
96090
count[n] = 0;
96091
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96092
if (extent[n] <= 0)
96093
- len = 0;
96094
+ return;
96095
}
96096
96097
base = array->data;
96098
--- a/src/libgfortran/generated/minloc1_8_r4.c
96099
+++ b/src/libgfortran/generated/minloc1_8_r4.c
96100
@@ -129,7 +129,7 @@
96101
count[n] = 0;
96102
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96103
if (extent[n] <= 0)
96104
- len = 0;
96105
+ return;
96106
}
96107
96108
base = array->data;
96109
--- a/src/libgfortran/generated/minloc1_8_r8.c
96110
+++ b/src/libgfortran/generated/minloc1_8_r8.c
96111
@@ -129,7 +129,7 @@
96112
count[n] = 0;
96113
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96114
if (extent[n] <= 0)
96115
- len = 0;
96116
+ return;
96117
}
96118
96119
base = array->data;
96120
--- a/src/libgfortran/generated/minval_i1.c
96121
+++ b/src/libgfortran/generated/minval_i1.c
96122
@@ -128,7 +128,7 @@
96123
count[n] = 0;
96124
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96125
if (extent[n] <= 0)
96126
- len = 0;
96127
+ return;
96128
}
96129
96130
base = array->data;
96131
--- a/src/libgfortran/generated/minval_i16.c
96132
+++ b/src/libgfortran/generated/minval_i16.c
96133
@@ -128,7 +128,7 @@
96134
count[n] = 0;
96135
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96136
if (extent[n] <= 0)
96137
- len = 0;
96138
+ return;
96139
}
96140
96141
base = array->data;
96142
--- a/src/libgfortran/generated/minval_i2.c
96143
+++ b/src/libgfortran/generated/minval_i2.c
96144
@@ -128,7 +128,7 @@
96145
count[n] = 0;
96146
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96147
if (extent[n] <= 0)
96148
- len = 0;
96149
+ return;
96150
}
96151
96152
base = array->data;
96153
--- a/src/libgfortran/generated/minval_i4.c
96154
+++ b/src/libgfortran/generated/minval_i4.c
96155
@@ -128,7 +128,7 @@
96156
count[n] = 0;
96157
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96158
if (extent[n] <= 0)
96159
- len = 0;
96160
+ return;
96161
}
96162
96163
base = array->data;
96164
--- a/src/libgfortran/generated/minval_i8.c
96165
+++ b/src/libgfortran/generated/minval_i8.c
96166
@@ -128,7 +128,7 @@
96167
count[n] = 0;
96168
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96169
if (extent[n] <= 0)
96170
- len = 0;
96171
+ return;
96172
}
96173
96174
base = array->data;
96175
--- a/src/libgfortran/generated/minval_r10.c
96176
+++ b/src/libgfortran/generated/minval_r10.c
96177
@@ -128,7 +128,7 @@
96178
count[n] = 0;
96179
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96180
if (extent[n] <= 0)
96181
- len = 0;
96182
+ return;
96183
}
96184
96185
base = array->data;
96186
--- a/src/libgfortran/generated/minval_r16.c
96187
+++ b/src/libgfortran/generated/minval_r16.c
96188
@@ -128,7 +128,7 @@
96189
count[n] = 0;
96190
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96191
if (extent[n] <= 0)
96192
- len = 0;
96193
+ return;
96194
}
96195
96196
base = array->data;
96197
--- a/src/libgfortran/generated/minval_r4.c
96198
+++ b/src/libgfortran/generated/minval_r4.c
96199
@@ -128,7 +128,7 @@
96200
count[n] = 0;
96201
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96202
if (extent[n] <= 0)
96203
- len = 0;
96204
+ return;
96205
}
96206
96207
base = array->data;
96208
--- a/src/libgfortran/generated/minval_r8.c
96209
+++ b/src/libgfortran/generated/minval_r8.c
96210
@@ -128,7 +128,7 @@
96211
count[n] = 0;
96212
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96213
if (extent[n] <= 0)
96214
- len = 0;
96215
+ return;
96216
}
96217
96218
base = array->data;
96219
--- a/src/libgfortran/generated/product_c10.c
96220
+++ b/src/libgfortran/generated/product_c10.c
96221
@@ -128,7 +128,7 @@
96222
count[n] = 0;
96223
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96224
if (extent[n] <= 0)
96225
- len = 0;
96226
+ return;
96227
}
96228
96229
base = array->data;
96230
--- a/src/libgfortran/generated/product_c16.c
96231
+++ b/src/libgfortran/generated/product_c16.c
96232
@@ -128,7 +128,7 @@
96233
count[n] = 0;
96234
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96235
if (extent[n] <= 0)
96236
- len = 0;
96237
+ return;
96238
}
96239
96240
base = array->data;
96241
--- a/src/libgfortran/generated/product_c4.c
96242
+++ b/src/libgfortran/generated/product_c4.c
96243
@@ -128,7 +128,7 @@
96244
count[n] = 0;
96245
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96246
if (extent[n] <= 0)
96247
- len = 0;
96248
+ return;
96249
}
96250
96251
base = array->data;
96252
--- a/src/libgfortran/generated/product_c8.c
96253
+++ b/src/libgfortran/generated/product_c8.c
96254
@@ -128,7 +128,7 @@
96255
count[n] = 0;
96256
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96257
if (extent[n] <= 0)
96258
- len = 0;
96259
+ return;
96260
}
96261
96262
base = array->data;
96263
--- a/src/libgfortran/generated/product_i1.c
96264
+++ b/src/libgfortran/generated/product_i1.c
96265
@@ -128,7 +128,7 @@
96266
count[n] = 0;
96267
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96268
if (extent[n] <= 0)
96269
- len = 0;
96270
+ return;
96271
}
96272
96273
base = array->data;
96274
--- a/src/libgfortran/generated/product_i16.c
96275
+++ b/src/libgfortran/generated/product_i16.c
96276
@@ -128,7 +128,7 @@
96277
count[n] = 0;
96278
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96279
if (extent[n] <= 0)
96280
- len = 0;
96281
+ return;
96282
}
96283
96284
base = array->data;
96285
--- a/src/libgfortran/generated/product_i2.c
96286
+++ b/src/libgfortran/generated/product_i2.c
96287
@@ -128,7 +128,7 @@
96288
count[n] = 0;
96289
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96290
if (extent[n] <= 0)
96291
- len = 0;
96292
+ return;
96293
}
96294
96295
base = array->data;
96296
--- a/src/libgfortran/generated/product_i4.c
96297
+++ b/src/libgfortran/generated/product_i4.c
96298
@@ -128,7 +128,7 @@
96299
count[n] = 0;
96300
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96301
if (extent[n] <= 0)
96302
- len = 0;
96303
+ return;
96304
}
96305
96306
base = array->data;
96307
--- a/src/libgfortran/generated/product_i8.c
96308
+++ b/src/libgfortran/generated/product_i8.c
96309
@@ -128,7 +128,7 @@
96310
count[n] = 0;
96311
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96312
if (extent[n] <= 0)
96313
- len = 0;
96314
+ return;
96315
}
96316
96317
base = array->data;
96318
--- a/src/libgfortran/generated/product_r10.c
96319
+++ b/src/libgfortran/generated/product_r10.c
96320
@@ -128,7 +128,7 @@
96321
count[n] = 0;
96322
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96323
if (extent[n] <= 0)
96324
- len = 0;
96325
+ return;
96326
}
96327
96328
base = array->data;
96329
--- a/src/libgfortran/generated/product_r16.c
96330
+++ b/src/libgfortran/generated/product_r16.c
96331
@@ -128,7 +128,7 @@
96332
count[n] = 0;
96333
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96334
if (extent[n] <= 0)
96335
- len = 0;
96336
+ return;
96337
}
96338
96339
base = array->data;
96340
--- a/src/libgfortran/generated/product_r4.c
96341
+++ b/src/libgfortran/generated/product_r4.c
96342
@@ -128,7 +128,7 @@
96343
count[n] = 0;
96344
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96345
if (extent[n] <= 0)
96346
- len = 0;
96347
+ return;
96348
}
96349
96350
base = array->data;
96351
--- a/src/libgfortran/generated/product_r8.c
96352
+++ b/src/libgfortran/generated/product_r8.c
96353
@@ -128,7 +128,7 @@
96354
count[n] = 0;
96355
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96356
if (extent[n] <= 0)
96357
- len = 0;
96358
+ return;
96359
}
96360
96361
base = array->data;
96362
--- a/src/libgfortran/generated/sum_c10.c
96363
+++ b/src/libgfortran/generated/sum_c10.c
96364
@@ -128,7 +128,7 @@
96365
count[n] = 0;
96366
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96367
if (extent[n] <= 0)
96368
- len = 0;
96369
+ return;
96370
}
96371
96372
base = array->data;
96373
--- a/src/libgfortran/generated/sum_c16.c
96374
+++ b/src/libgfortran/generated/sum_c16.c
96375
@@ -128,7 +128,7 @@
96376
count[n] = 0;
96377
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96378
if (extent[n] <= 0)
96379
- len = 0;
96380
+ return;
96381
}
96382
96383
base = array->data;
96384
--- a/src/libgfortran/generated/sum_c4.c
96385
+++ b/src/libgfortran/generated/sum_c4.c
96386
@@ -128,7 +128,7 @@
96387
count[n] = 0;
96388
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96389
if (extent[n] <= 0)
96390
- len = 0;
96391
+ return;
96392
}
96393
96394
base = array->data;
96395
--- a/src/libgfortran/generated/sum_c8.c
96396
+++ b/src/libgfortran/generated/sum_c8.c
96397
@@ -128,7 +128,7 @@
96398
count[n] = 0;
96399
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96400
if (extent[n] <= 0)
96401
- len = 0;
96402
+ return;
96403
}
96404
96405
base = array->data;
96406
--- a/src/libgfortran/generated/sum_i1.c
96407
+++ b/src/libgfortran/generated/sum_i1.c
96408
@@ -128,7 +128,7 @@
96409
count[n] = 0;
96410
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96411
if (extent[n] <= 0)
96412
- len = 0;
96413
+ return;
96414
}
96415
96416
base = array->data;
96417
--- a/src/libgfortran/generated/sum_i16.c
96418
+++ b/src/libgfortran/generated/sum_i16.c
96419
@@ -128,7 +128,7 @@
96420
count[n] = 0;
96421
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96422
if (extent[n] <= 0)
96423
- len = 0;
96424
+ return;
96425
}
96426
96427
base = array->data;
96428
--- a/src/libgfortran/generated/sum_i2.c
96429
+++ b/src/libgfortran/generated/sum_i2.c
96430
@@ -128,7 +128,7 @@
96431
count[n] = 0;
96432
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96433
if (extent[n] <= 0)
96434
- len = 0;
96435
+ return;
96436
}
96437
96438
base = array->data;
96439
--- a/src/libgfortran/generated/sum_i4.c
96440
+++ b/src/libgfortran/generated/sum_i4.c
96441
@@ -128,7 +128,7 @@
96442
count[n] = 0;
96443
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96444
if (extent[n] <= 0)
96445
- len = 0;
96446
+ return;
96447
}
96448
96449
base = array->data;
96450
--- a/src/libgfortran/generated/sum_i8.c
96451
+++ b/src/libgfortran/generated/sum_i8.c
96452
@@ -128,7 +128,7 @@
96453
count[n] = 0;
96454
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96455
if (extent[n] <= 0)
96456
- len = 0;
96457
+ return;
96458
}
96459
96460
base = array->data;
96461
--- a/src/libgfortran/generated/sum_r10.c
96462
+++ b/src/libgfortran/generated/sum_r10.c
96463
@@ -128,7 +128,7 @@
96464
count[n] = 0;
96465
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96466
if (extent[n] <= 0)
96467
- len = 0;
96468
+ return;
96469
}
96470
96471
base = array->data;
96472
--- a/src/libgfortran/generated/sum_r16.c
96473
+++ b/src/libgfortran/generated/sum_r16.c
96474
@@ -128,7 +128,7 @@
96475
count[n] = 0;
96476
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96477
if (extent[n] <= 0)
96478
- len = 0;
96479
+ return;
96480
}
96481
96482
base = array->data;
96483
--- a/src/libgfortran/generated/sum_r4.c
96484
+++ b/src/libgfortran/generated/sum_r4.c
96485
@@ -128,7 +128,7 @@
96486
count[n] = 0;
96487
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96488
if (extent[n] <= 0)
96489
- len = 0;
96490
+ return;
96491
}
96492
96493
base = array->data;
96494
--- a/src/libgfortran/generated/sum_r8.c
96495
+++ b/src/libgfortran/generated/sum_r8.c
96496
@@ -128,7 +128,7 @@
96497
count[n] = 0;
96498
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96499
if (extent[n] <= 0)
96500
- len = 0;
96501
+ return;
96502
}
96503
96504
base = array->data;
96505
--- a/src/libgfortran/intrinsics/c99_functions.c
96506
+++ b/src/libgfortran/intrinsics/c99_functions.c
96507
@@ -601,7 +601,7 @@
96508
if (x > DBL_MAX || x < -DBL_MAX)
96509
{
96510
#ifdef HAVE_NEXTAFTERL
96511
- static long double prechalf = nexafterl (0.5L, LDBL_MAX);
96512
+ long double prechalf = nextafterl (0.5L, LDBL_MAX);
96513
#else
96514
static long double prechalf = 0.5L;
96515
#endif
96516
--- a/src/libgfortran/io/fbuf.h
96517
+++ b/src/libgfortran/io/fbuf.h
96518
@@ -78,4 +78,10 @@
96519
return fbuf_getc_refill (u);
96520
}
96521
96522
+static inline char *
96523
+fbuf_getptr (gfc_unit * u)
96524
+{
96525
+ return (char*) (u->fbuf->buf + u->fbuf->pos);
96526
+}
96527
+
96528
#endif
96529
--- a/src/libgfortran/io/list_read.c
96530
+++ b/src/libgfortran/io/list_read.c
96531
@@ -2863,6 +2863,11 @@
96532
char c;
96533
jmp_buf eof_jump;
96534
char nml_err_msg[200];
96535
+
96536
+ /* Initialize the error string buffer just in case we get an unexpected fail
96537
+ somewhere and end up at nml_err_ret. */
96538
+ strcpy (nml_err_msg, "Internal namelist read error");
96539
+
96540
/* Pointer to the previously read object, in case attempt is made to read
96541
new object name. Should this fail, error message can give previous
96542
name. */
96543
@@ -2950,7 +2955,11 @@
96544
}
96545
}
96546
96547
- }
96548
+ /* Reset the previous namelist pointer if we know we are not going
96549
+ to be doing multiple reads within a single namelist object. */
96550
+ if (prev_nl && prev_nl->var_rank == 0)
96551
+ prev_nl = NULL;
96552
+ }
96553
96554
dtp->u.p.eof_jump = NULL;
96555
free_saved (dtp);
96556
--- a/src/libgfortran/io/transfer.c
96557
+++ b/src/libgfortran/io/transfer.c
96558
@@ -236,16 +236,16 @@
96559
read_sf (st_parameter_dt *dtp, int * length)
96560
{
96561
static char *empty_string[0];
96562
- char *base, *p, q;
96563
+ int q, q2;
96564
int n, lorig, seen_comma;
96565
96566
/* If we have seen an eor previously, return a length of 0. The
96567
- caller is responsible for correctly padding the input field. */
96568
+ * caller is responsible for correctly padding the input field. */
96569
if (dtp->u.p.sf_seen_eor)
96570
{
96571
*length = 0;
96572
/* Just return something that isn't a NULL pointer, otherwise the
96573
- caller thinks an error occured. */
96574
+ * caller thinks an error occured. */
96575
return (char*) empty_string;
96576
}
96577
96578
@@ -253,42 +253,36 @@
96579
96580
/* Read data into format buffer and scan through it. */
96581
lorig = *length;
96582
- base = p = fbuf_read (dtp->u.p.current_unit, length);
96583
- if (base == NULL)
96584
- return NULL;
96585
96586
while (n < *length)
96587
{
96588
- q = *p;
96589
-
96590
- if (q == '\n' || q == '\r')
96591
+ q = fbuf_getc (dtp->u.p.current_unit);
96592
+ if (q == EOF)
96593
+ break;
96594
+ else if (q == '\n' || q == '\r')
96595
{
96596
/* Unexpected end of line. Set the position. */
96597
- fbuf_seek (dtp->u.p.current_unit, n + 1 ,SEEK_CUR);
96598
dtp->u.p.sf_seen_eor = 1;
96599
96600
/* If we see an EOR during non-advancing I/O, we need to skip
96601
- the rest of the I/O statement. Set the corresponding flag. */
96602
+ * the rest of the I/O statement. Set the corresponding flag. */
96603
if (dtp->u.p.advance_status == ADVANCE_NO || dtp->u.p.seen_dollar)
96604
dtp->u.p.eor_condition = 1;
96605
96606
/* If we encounter a CR, it might be a CRLF. */
96607
if (q == '\r') /* Probably a CRLF */
96608
{
96609
- /* See if there is an LF. Use fbuf_read rather then fbuf_getc so
96610
- the position is not advanced unless it really is an LF. */
96611
- int readlen = 1;
96612
- p = fbuf_read (dtp->u.p.current_unit, &readlen);
96613
- if (*p == '\n' && readlen == 1)
96614
- {
96615
- dtp->u.p.sf_seen_eor = 2;
96616
- fbuf_seek (dtp->u.p.current_unit, 1 ,SEEK_CUR);
96617
- }
96618
+ /* See if there is an LF. */
96619
+ q2 = fbuf_getc (dtp->u.p.current_unit);
96620
+ if (q2 == '\n')
96621
+ dtp->u.p.sf_seen_eor = 2;
96622
+ else if (q2 != EOF) /* Oops, seek back. */
96623
+ fbuf_seek (dtp->u.p.current_unit, -1, SEEK_CUR);
96624
}
96625
96626
/* Without padding, terminate the I/O statement without assigning
96627
- the value. With padding, the value still needs to be assigned,
96628
- so we can just continue with a short read. */
96629
+ * the value. With padding, the value still needs to be assigned,
96630
+ * so we can just continue with a short read. */
96631
if (dtp->u.p.current_unit->pad_status == PAD_NO)
96632
{
96633
generate_error (&dtp->common, LIBERROR_EOR, NULL);
96634
@@ -299,25 +293,23 @@
96635
goto done;
96636
}
96637
/* Short circuit the read if a comma is found during numeric input.
96638
- The flag is set to zero during character reads so that commas in
96639
- strings are not ignored */
96640
- if (q == ',')
96641
+ * The flag is set to zero during character reads so that commas in
96642
+ * strings are not ignored */
96643
+ else if (q == ',')
96644
if (dtp->u.p.sf_read_comma == 1)
96645
{
96646
seen_comma = 1;
96647
notify_std (&dtp->common, GFC_STD_GNU,
96648
"Comma in formatted numeric read.");
96649
- *length = n;
96650
break;
96651
}
96652
n++;
96653
- p++;
96654
- }
96655
+ }
96656
96657
- fbuf_seek (dtp->u.p.current_unit, n + seen_comma, SEEK_CUR);
96658
+ *length = n;
96659
96660
/* A short read implies we hit EOF, unless we hit EOR, a comma, or
96661
- some other stuff. Set the relevant flags. */
96662
+ * some other stuff. Set the relevant flags. */
96663
if (lorig > *length && !dtp->u.p.sf_seen_eor && !seen_comma)
96664
{
96665
if (n > 0)
96666
@@ -352,7 +344,12 @@
96667
if ((dtp->common.flags & IOPARM_DT_HAS_SIZE) != 0)
96668
dtp->u.p.size_used += (GFC_IO_INT) n;
96669
96670
- return base;
96671
+ /* We can't call fbuf_getptr before the loop doing fbuf_getc, because
96672
+ * fbuf_getc might reallocate the buffer. So return current pointer
96673
+ * minus all the advances, which is n plus up to two characters
96674
+ * of newline or comma. */
96675
+ return fbuf_getptr (dtp->u.p.current_unit)
96676
+ - n - dtp->u.p.sf_seen_eor - seen_comma;
96677
}
96678
96679
96680
--- a/src/libgfortran/m4/ifunction.m4
96681
+++ b/src/libgfortran/m4/ifunction.m4
96682
@@ -116,7 +116,7 @@
96683
count[n] = 0;
96684
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96685
if (extent[n] <= 0)
96686
- len = 0;
96687
+ return;
96688
}
96689
96690
base = array->data;
96691
--- a/src/libgfortran/m4/ifunction_logical.m4
96692
+++ b/src/libgfortran/m4/ifunction_logical.m4
96693
@@ -130,7 +130,7 @@
96694
count[n] = 0;
96695
dstride[n] = GFC_DESCRIPTOR_STRIDE(retarray,n);
96696
if (extent[n] <= 0)
96697
- len = 0;
96698
+ return;
96699
}
96700
96701
base = array->data;
96702
--- a/src/libgomp/ChangeLog
96703
+++ b/src/libgomp/ChangeLog
96704
@@ -1,3 +1,27 @@
96705
+2011-02-27 Tobias Burnus <burnus@net-b.de>
96706
+
96707
+ Backport from mainline
96708
+ 2011-02-27 Jakub Jelinek <jakub@redhat.com>
96709
+
96710
+ PR fortran/47886
96711
+ * testsuite/libgomp.fortran/task3.f90: New test.
96712
+
96713
+
96714
+2011-01-16 Jakub Jelinek <jakub@redhat.com>
96715
+
96716
+ Backport from mainline
96717
+ 2010-12-14 Jakub Jelinek <jakub@redhat.com>
96718
+
96719
+ PR fortran/46874
96720
+ * libgomp.fortran/allocatable6.f90: New test.
96721
+
96722
+2010-12-17 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
96723
+
96724
+ Backport from mainline:
96725
+ 2010-12-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
96726
+
96727
+ * configure.tgt (mips-sgi-irix6*): Add -lpthread to XLDFLAGS.
96728
+
96729
2010-12-16 Release Manager
96730
96731
* GCC 4.5.2 released.
96732
--- a/src/libgomp/configure.tgt
96733
+++ b/src/libgomp/configure.tgt
96734
@@ -125,6 +125,10 @@
96735
config_path="bsd posix"
96736
;;
96737
96738
+ mips-sgi-irix6*)
96739
+ # Need to link with -lpthread so libgomp.so is self-contained.
96740
+ XLDFLAGS="${XLDFLAGS} -lpthread"
96741
+ ;;
96742
*)
96743
;;
96744
96745
--- a/src/libgomp/testsuite/libgomp.fortran/allocatable6.f90
96746
+++ b/src/libgomp/testsuite/libgomp.fortran/allocatable6.f90
96747
@@ -0,0 +1,45 @@
96748
+! PR fortran/46874
96749
+! { dg-do run }
96750
+
96751
+ interface
96752
+ subroutine sub (a, b, c, d, n)
96753
+ integer :: n
96754
+ integer, allocatable :: a(:), b(:), c(:), d(:)
96755
+ end subroutine
96756
+ end interface
96757
+
96758
+ integer, allocatable :: a(:), b(:), c(:), d(:)
96759
+ integer :: i, j
96760
+ allocate (a(50), b(50), c(50), d(50))
96761
+ do i = 1, 50
96762
+ a(i) = 2 + modulo (i, 7)
96763
+ b(i) = 179 - modulo (i, 11)
96764
+ end do
96765
+ c = 0
96766
+ d = 2147483647
96767
+ call sub (a, b, c, d, 50)
96768
+ do i = 1, 50
96769
+ j = 0
96770
+ if (i .eq. 3) then
96771
+ j = 8
96772
+ else if (i .gt. 1 .and. i .lt. 9) then
96773
+ j = 7
96774
+ end if
96775
+ if (c(i) .ne. j) call abort
96776
+ j = 179 - modulo (i, 11)
96777
+ if (i .gt. 1 .and. i .lt. 9) j = i
96778
+ if (d(i) .ne. j) call abort
96779
+ end do
96780
+ deallocate (a, b, c, d)
96781
+end
96782
+
96783
+subroutine sub (a, b, c, d, n)
96784
+ integer :: n
96785
+ integer, allocatable :: a(:), b(:), c(:), d(:)
96786
+!$omp parallel do shared(a, b) reduction(+:c) reduction(min:d)
96787
+ do i = 1, n
96788
+ c(a(i)) = c(a(i)) + 1
96789
+ d(i) = min(d(i), b(i))
96790
+ d(a(i)) = min(d(a(i)), a(i))
96791
+ end do
96792
+end
96793
--- a/src/libgomp/testsuite/libgomp.fortran/task3.f90
96794
+++ b/src/libgomp/testsuite/libgomp.fortran/task3.f90
96795
@@ -0,0 +1,27 @@
96796
+! { dg-do run }
96797
+! { dg-options "-fopenmp" }
96798
+!
96799
+! PR fortran/47886
96800
+!
96801
+! Test case contributed by Bill Long
96802
+
96803
+! derived from OpenMP test OMP3f/F03_2_7_1d.F90
96804
+program F03_2_7_1d
96805
+ use omp_lib
96806
+ implicit none
96807
+ integer, parameter :: NT = 4
96808
+ integer :: sum = 0
96809
+
96810
+ call omp_set_num_threads(NT);
96811
+
96812
+ !$omp parallel
96813
+ !$omp task if(omp_get_num_threads() > 0)
96814
+ !$omp atomic
96815
+ sum = sum + 1
96816
+ !$omp end task
96817
+ !$omp end parallel
96818
+ if (sum /= NT) then
96819
+ print *, "FAIL - sum == ", sum, " (expected ", NT, ")"
96820
+ call abort
96821
+ end if
96822
+end program F03_2_7_1d
96823
--- a/src/libjava/ChangeLog
96824
+++ b/src/libjava/ChangeLog
96825
@@ -1,3 +1,24 @@
96826
+2011-01-07 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
96827
+
96828
+ Backport from mainline:
96829
+ 2011-01-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
96830
+
96831
+ * testsuite/libjava.jni/jni.exp (gcj_jni_get_cxxflags_invocation):
96832
+ Add -shared-libgcc to cxxflags for *-*-solaris*.
96833
+ Remove -lsocket.
96834
+
96835
+2010-12-13 Andrew John Hughes <ahughes@redhat.com>
96836
+
96837
+ PR libgcj/46774
96838
+ * libjava/java/security/VMAccessController.java:
96839
+ (DEFAULT_CONTEXT): Create ProtectionDomain with
96840
+ four argument constructor (arguments are the same
96841
+ as those implied by the two argument constructor).
96842
+ (getContext()): Create ProtectionDomain instances
96843
+ with four argument constructor using a null Principal
96844
+ array (as before) but including the classloader, which
96845
+ was always null before.
96846
+
96847
2010-12-16 Release Manager
96848
96849
* GCC 4.5.2 released.
96850
--- a/src/libjava/java/security/VMAccessController.java
96851
+++ b/src/libjava/java/security/VMAccessController.java
96852
@@ -56,7 +56,7 @@
96853
Permissions permissions = new Permissions();
96854
permissions.add(new AllPermission());
96855
ProtectionDomain[] domain = new ProtectionDomain[] {
96856
- new ProtectionDomain(source, permissions)
96857
+ new ProtectionDomain(source, permissions, null, null)
96858
};
96859
DEFAULT_CONTEXT = new AccessControlContext(domain);
96860
}
96861
@@ -178,12 +178,13 @@
96862
for (int i = 3; i < classes.length; i++)
96863
{
96864
Class clazz = classes[i];
96865
+ ClassLoader loader = clazz.getClassLoader();
96866
96867
if (DEBUG)
96868
{
96869
debug("checking " + clazz);
96870
// subject to getClassLoader RuntimePermission
96871
- debug("loader = " + clazz.getClassLoader());
96872
+ debug("loader = " + loader);
96873
}
96874
96875
if (privileged && i == classes.length - 2)
96876
@@ -208,7 +209,8 @@
96877
// Create a static snapshot of this domain, which may change over time
96878
// if the current policy changes.
96879
domains.add(new ProtectionDomain(domain.getCodeSource(),
96880
- domain.getPermissions()));
96881
+ domain.getPermissions(),
96882
+ loader, null));
96883
}
96884
96885
if (DEBUG)
96886
--- a/src/libjava/testsuite/libjava.jni/jni.exp
96887
+++ b/src/libjava/testsuite/libjava.jni/jni.exp
96888
@@ -274,8 +274,10 @@
96889
eval lappend cxxflags "-shared-libgcc -lgcj $libiconv"
96890
}
96891
96892
+ # Make sure libgcc unwinder is used on 64-bit Solaris 10+/x86 rather than
96893
+ # the libc one.
96894
if { [istarget "*-*-solaris*"] } {
96895
- lappend cxxflags "-lsocket"
96896
+ lappend cxxflags "-shared-libgcc"
96897
}
96898
96899
return $cxxflags
96900
--- a/src/libstdc++-v3/ChangeLog
96901
+++ b/src/libstdc++-v3/ChangeLog
96902
@@ -1,3 +1,96 @@
96903
+2011-03-21 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
96904
+
96905
+ * testsuite/22_locale/num_put/put/char/14220.cc: Don't xfail on
96906
+ sparc*-sun-solaris2.10 && lp64.
96907
+
96908
+2011-03-14 Andrey Zholos <aaz@althenia.net>
96909
+
96910
+ PR libstdc++/48114
96911
+ * include/bits/random.tcc (binomial_distribution<>::operator()):
96912
+ Fix thinko in computation, __param.p() is a double.
96913
+
96914
+2011-02-25 Johannes Singler <singler@kit.edu>
96915
+
96916
+ PR libstdc++/47433
96917
+ * include/parallel/losertree.h
96918
+ (_LoserTree<>::__delete_min_insert):
96919
+ Do not qualify swap with std:: for value type,
96920
+ but include a using directive instead.
96921
+ (_LoserTreeUnguarded<>::__delete_min_insert): Likewise.
96922
+ * include/parallel/balanced_quicksort.h (__qsb_divide):
96923
+ Use std::iter_swap instead of std::swap.
96924
+ (__qsb_local_sort_with_helping): Likewise.
96925
+ * include/parallel/partition.h (__parallel_partition):
96926
+ Likewise. (__parallel_nth_element): Likewise.
96927
+
96928
+2011-02-25 Johannes Singler <singler@kit.edu>
96929
+
96930
+ * include/parallel/numeric (inner_product, partial_sum):
96931
+ Qualify subsequent call with __gnu_parallel instead of
96932
+ _GLIBCXX_STD_P to reenable parallel execution without ambiguity.
96933
+ * include/parallel/algobase.h (equal): Likewise.
96934
+ * include/parallel/algo.h (find_first_of, search_n, merge,
96935
+ nth_element, partial_sort, max_element, min_element): Likewise.
96936
+ * testsuite/25_algorithms/headers/algorithm/
96937
+ parallel_algorithm_mixed1.cc (main): Add respective test cases.
96938
+ * testsuite/25_algorithms/headers/algorithm/
96939
+ parallel_algorithm_mixed2.cc (main): Likewise.
96940
+ * testsuite/26_numerics/headers/numeric/
96941
+ parallel_numeric_mixed1.cc (main): Likewise.
96942
+ * testsuite/26_numerics/headers/numeric/
96943
+ parallel_numeric_mixed2.cc (main): Likewise.
96944
+
96945
+2011-02-13 Gerald Pfeifer <gerald@pfeifer.com>
96946
+
96947
+ * doc/xml/faq.xml: Adjust link to bug database.
96948
+ Remove old item on broken header files.
96949
+
96950
+2011-02-12 Paolo Carlini <paolo.carlini@oracle.com>
96951
+
96952
+ PR libstdc++/47709
96953
+ * include/ext/algorithm (is_heap): In C++0x mode import from
96954
+ namespace std.
96955
+ * testsuite/ext/is_heap/47709.cc: New.
96956
+
96957
+2011-02-08 Jonathan Wakely <jwakely.gcc@gmail.com>
96958
+
96959
+ * doc/xml/gnu/gpl-2.0.xml: Remove.
96960
+ * doc/Makefile.am: Update.
96961
+ * doc/Makefile.in: Regenerate.
96962
+
96963
+2011-02-06 Gerald Pfeifer <gerald@pfeifer.com>
96964
+
96965
+ * doc/xml/manual/debug.xml: Use GDB instead of gdb.
96966
+ Adjust link to GDB manual.
96967
+
96968
+2011-02-01 Paolo Carlini <paolo.carlini@oracle.com>
96969
+
96970
+ PR libstdc++/46914
96971
+ * include/bits/atomic_0.h (_ATOMIC_STORE_, _ATOMIC_MODIFY_,
96972
+ _ATOMIC_CMPEXCHNG_): Rename __v -> __w, and __m -> __n, to
96973
+ avoid name conflicts.
96974
+
96975
+2011-01-30 Gerald Pfeifer <gerald@pfeifer.com>
96976
+
96977
+ * doc/xml/manual/codecvt.xml: Fix link to The Austin Common
96978
+ Standards Revision Group.
96979
+ * doc/xml/manual/locale.xml: Ditto.
96980
+ * doc/xml/manual/messages.xml: Ditto.
96981
+ * doc/xml/manual/using_exceptions.xml: Ditto.
96982
+
96983
+2011-01-19 Graham Reed <greed@pobox.com>
96984
+
96985
+ PR libstdc++/47354
96986
+ * src/bitmap_allocator.cc (free_list::_M_get): Lock mutex.
96987
+
96988
+2010-12-17 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
96989
+
96990
+ Backport from mainline:
96991
+ 2010-12-10 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
96992
+
96993
+ * testsuite/lib/libstdc++.exp (v3-build_support): Delete
96994
+ libtestc++.a before creation.
96995
+
96996
2010-12-16 Release Manager
96997
96998
* GCC 4.5.2 released.
96999
82870
--- a/src/libstdc++-v3/acinclude.m4
97000
82871
+++ b/src/libstdc++-v3/acinclude.m4
97001
82872
@@ -95,7 +95,7 @@
97462
83333
else
97463
83334
os_include_dir="os/gnu-linux"
97464
83335
fi
97465
--- a/src/libstdc++-v3/doc/Makefile.am
97466
+++ b/src/libstdc++-v3/doc/Makefile.am
97467
@@ -204,7 +204,6 @@
97468
97469
xml_sources_extra = \
97470
${xml_dir}/gnu/fdl-1.2.xml \
97471
- ${xml_dir}/gnu/gpl-2.0.xml \
97472
${xml_dir}/gnu/gpl-3.0.xml
97473
97474
xml_sources = \
97475
--- a/src/libstdc++-v3/doc/Makefile.in
97476
+++ b/src/libstdc++-v3/doc/Makefile.in
97477
@@ -343,7 +343,6 @@
97478
97479
xml_sources_extra = \
97480
${xml_dir}/gnu/fdl-1.2.xml \
97481
- ${xml_dir}/gnu/gpl-2.0.xml \
97482
${xml_dir}/gnu/gpl-3.0.xml
97483
97484
xml_sources = \
97485
83336
--- a/src/libstdc++-v3/doc/xml/faq.xml
97486
83337
+++ b/src/libstdc++-v3/doc/xml/faq.xml
97487
83338
@@ -636,6 +636,8 @@
97493
83344
</para>
97494
83345
<para>The guideline is simple: the more recent the C++ library, the
97495
83346
more recent the C library. (This is also documented in the main
97496
@@ -745,7 +747,7 @@
97497
</para>
97498
<para>
97499
Before reporting a bug, please examine the
97500
- <ulink url="http://gcc.gnu.org/bugs.html">bugs database</ulink> with the
97501
+ <ulink url="http://gcc.gnu.org/bugs/">bugs database</ulink> with the
97502
category set to <quote>g++</quote>.
97503
</para>
97504
</answer>
97505
@@ -848,17 +850,9 @@
97506
</question>
97507
<answer id="a-v2_headers">
97508
<para>
97509
- If you have found an extremely broken header file which is
97510
- causing problems for you, look carefully before submitting a
97511
- "high" priority bug report (which you probably
97512
- shouldn't do anyhow; see the last paragraph of the page
97513
- describing <ulink url="http://gcc.gnu.org/bugs.html">the GCC
97514
- bug database</ulink>).
97515
- </para>
97516
- <para>
97517
- If the headers are in <filename>${prefix}/include/g++-3</filename>, or
97518
- if the installed library's name looks like
97519
- <filename>libstdc++-2.10.a</filename> or
97520
+ If you are using headers in
97521
+ <filename>${prefix}/include/g++-3</filename>, or if the installed
97522
+ library's name looks like <filename>libstdc++-2.10.a</filename> or
97523
<filename>libstdc++-libc6-2.10.so</filename>, then you are using the
97524
old libstdc++-v2 library, which is nonstandard and
97525
unmaintained. Do not report problems with -v2 to the -v3
97526
--- a/src/libstdc++-v3/doc/xml/gnu/gpl-2.0.xml
97527
+++ b/src/libstdc++-v3/doc/xml/gnu/gpl-2.0.xml
97528
@@ -1,366 +0,0 @@
97529
-<?xml version='1.0' encoding='ISO-8859-1'?>
97530
-<!DOCTYPE appendix PUBLIC "-//OASIS//DTD DocBook XML V4.5//EN"
97531
- "http://www.oasis-open.org/docbook/xml/4.5/docbookx.dtd">
97532
-<appendix id="appendix.gpl-2.0">
97533
- <appendixinfo>
97534
- <title>GNU General Public License</title>
97535
- <pubdate>Version 2, June 1991</pubdate>
97536
- <copyright>
97537
- <year>1989, 1991</year>
97538
- <holder>Free Software Foundation, Inc.</holder>
97539
- </copyright>
97540
- <legalnotice id="gpl-legalnotice">
97541
- <para>
97542
- <address>Free Software Foundation, Inc.
97543
- <street>51 Franklin Street, Fifth Floor</street>,
97544
- <city>Boston</city>, <state>MA</state> <postcode>02110-1301</postcode>
97545
- <country>USA</country>
97546
- </address>
97547
- </para>
97548
- <para>Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.</para>
97549
- </legalnotice>
97550
- <releaseinfo>Version 2, June 1991</releaseinfo>
97551
- </appendixinfo>
97552
- <title>GNU General Public License</title>
97553
- <section id="gpl-1">
97554
- <title>Preamble</title>
97555
- <para>The licenses for most software are designed to take away your
97556
- freedom to share and change it. By contrast, the GNU General Public License is
97557
- intended to guarantee your freedom to share and change
97558
- free software - to make sure the software is free for all its users.
97559
- This General Public License applies to most of the Free Software
97560
- Foundation's software and to any other program whose authors commit
97561
- to using it. (Some other Free Software Foundation software is covered
97562
- by the GNU Library General Public License instead.) You can apply it
97563
- to your programs, too.</para>
97564
-
97565
- <para>When we speak of free software, we are referring to freedom, not price.
97566
- Our General Public Licenses are designed to make sure that you have the
97567
- freedom to distribute copies of free software (and charge for this
97568
- service if you wish), that you receive source code or can get it if you
97569
- want it, that you can change the software or use pieces of it in new free
97570
- programs; and that you know you can do these things.</para>
97571
-
97572
- <para>To protect your rights, we need to make restrictions that forbid anyone
97573
- to deny you these rights or to ask you to surrender the rights. These
97574
- restrictions translate to certain responsibilities for you if you distribute
97575
- copies of the software, or if you modify it.</para>
97576
-
97577
- <para>For example, if you distribute copies of such a program, whether gratis or
97578
- for a fee, you must give the recipients all the rights that you have. You
97579
- must make sure that they, too, receive or can get the source code. And you
97580
- must show them these terms so they know their rights.</para>
97581
-
97582
- <para>We protect your rights with two steps:
97583
- <orderedlist>
97584
- <listitem>
97585
- <para>copyright the software, and</para>
97586
- </listitem>
97587
- <listitem>
97588
- <para>offer you this license which gives you legal permission to copy,
97589
- distribute and/or modify the software.</para>
97590
- </listitem>
97591
- </orderedlist>
97592
- </para>
97593
-
97594
- <para>Also, for each author's protection and ours, we want to make certain that
97595
- everyone understands that there is no warranty for this free software. If
97596
- the software is modified by someone else and passed on, we want its
97597
- recipients to know that what they have is not the original, so that any
97598
- problems introduced by others will not reflect on the original authors'
97599
- reputations.</para>
97600
-
97601
- <para>Finally, any free program is threatened constantly by software patents.
97602
- We wish to avoid the danger that redistributors of a free program will
97603
- individually obtain patent licenses, in effect making the program
97604
- proprietary. To prevent this, we have made it clear that any patent must be
97605
- licensed for everyone's free use or not licensed at all.</para>
97606
-
97607
- <para>The precise terms and conditions for copying, distribution and modification
97608
- follow.</para>
97609
- </section>
97610
- <section id="gpl-2">
97611
- <title>TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION</title>
97612
- <section id="gpl-2-0">
97613
- <title>Section 0</title>
97614
- <para>This License applies to any program or other work which contains a notice
97615
- placed by the copyright holder saying it may be distributed under the terms
97616
- of this General Public License. The <quote>Program</quote>, below, refers to any such
97617
- program or work, and a
97618
- <quote>work based on the Program</quote> means either
97619
- the Program or any derivative work under copyright law: that is to say, a
97620
- work containing the Program or a portion of it, either verbatim or with
97621
- modifications and/or translated into another language. (Hereinafter, translation
97622
- is included without limitation in the term
97623
- <quote>modification</quote>.) Each licensee is addressed as <quote>you</quote>.</para>
97624
-
97625
- <para>Activities other than copying, distribution and modification are not covered by
97626
- this License; they are outside its scope. The act of running the Program is not
97627
- restricted, and the output from the Program is covered only if its contents
97628
- constitute a work based on the Program (independent of having been made by running
97629
- the Program). Whether that is true depends on what the Program does.</para>
97630
- </section>
97631
- <section id="gpl-2-1">
97632
- <title>Section 1</title>
97633
- <para>You may copy and distribute verbatim copies of the Program's source code as you
97634
- receive it, in any medium, provided that you conspicuously and appropriately
97635
- publish on each copy an appropriate copyright notice and disclaimer of warranty;
97636
- keep intact all the notices that refer to this License and to the absence of any
97637
- warranty; and give any other recipients of the Program a copy of this License
97638
- along with the Program.</para>
97639
-
97640
- <para>You may charge a fee for the physical act of transferring a copy, and you may at
97641
- your option offer warranty protection in exchange for a fee.</para>
97642
- </section>
97643
- <section id="gpl-2-2">
97644
- <title>Section 2</title>
97645
- <para>You may modify your copy or copies of the Program or any portion of it, thus
97646
- forming a work based on the Program, and copy and distribute such modifications
97647
- or work under the terms of
97648
- <link linkend="gpl-2-1">Section 1</link> above, provided
97649
- that you also meet all of these conditions:
97650
- <orderedlist numeration="loweralpha">
97651
- <listitem>
97652
- <para>You must cause the modified files to carry prominent notices stating that
97653
- you changed the files and the date of any change.</para>
97654
- </listitem>
97655
- <listitem>
97656
- <para>You must cause any work that you distribute or publish, that in whole or
97657
- in part contains or is derived from the Program or any part thereof, to be
97658
- licensed as a whole at no charge to all third parties under the terms of
97659
- this License.</para>
97660
- </listitem>
97661
- <listitem>
97662
- <para>If the modified program normally reads commands interactively when run, you
97663
- must cause it, when started running for such interactive use in the most
97664
- ordinary way, to print or display an announcement including an appropriate
97665
- copyright notice and a notice that there is no warranty (or else, saying
97666
- that you provide a warranty) and that users may redistribute the program
97667
- under these conditions, and telling the user how to view a copy of this
97668
- License. (Exception: If the Program itself is interactive but does not
97669
- normally print such an announcement, your work based on the Program is not
97670
- required to print an announcement.)</para>
97671
- </listitem>
97672
- </orderedlist>
97673
- </para>
97674
-
97675
- <para>These requirements apply to the modified work as a whole. If identifiable sections
97676
- of that work are not derived from the Program, and can be reasonably considered
97677
- independent and separate works in themselves, then this License, and its terms,
97678
- do not apply to those sections when you distribute them as separate works. But when
97679
- you distribute the same sections as part of a whole which is a work based on the
97680
- Program, the distribution of the whole must be on the terms of this License, whose
97681
- permissions for other licensees extend to the entire whole, and thus to each and
97682
- every part regardless of who wrote it.</para>
97683
-
97684
- <para>Thus, it is not the intent of this section to claim rights or contest your rights
97685
- to work written entirely by you; rather, the intent is to exercise the right to control
97686
- the distribution of derivative or collective works based on the Program.</para>
97687
-
97688
- <para>In addition, mere aggregation of another work not based on the Program with the Program
97689
- (or with a work based on the Program) on a volume of a storage or distribution medium
97690
- does not bring the other work under the scope of this License.</para>
97691
- </section>
97692
- <section id="gpl-2-3">
97693
- <title>Section 3</title>
97694
- <para>You may copy and distribute the Program (or a work based on it, under
97695
- <link linkend="gpl-2-2">Section 2</link> in object code or executable form under the terms of
97696
- <link linkend="gpl-2-1">Sections 1</link> and
97697
- <link linkend="gpl-2-2">2</link> above provided that you also do one of the following:
97698
- <orderedlist numeration="loweralpha">
97699
- <listitem>
97700
- <para>Accompany it with the complete corresponding machine-readable source code, which
97701
- must be distributed under the terms of Sections 1 and 2 above on a medium
97702
- customarily used for software interchange; or,</para>
97703
- </listitem>
97704
- <listitem>
97705
- <para>Accompany it with a written offer, valid for at least three years, to give any
97706
- third party, for a charge no more than your cost of physically performing source
97707
- distribution, a complete machine-readable copy of the corresponding source code,
97708
- to be distributed under the terms of Sections 1 and 2 above on a medium customarily
97709
- used for software interchange; or,</para>
97710
- </listitem>
97711
- <listitem>
97712
- <para>Accompany it with the information you received as to the offer to distribute
97713
- corresponding source code. (This alternative is allowed only for noncommercial
97714
- distribution and only if you received the program in object code or executable form
97715
- with such an offer, in accord with Subsection b above.)</para>
97716
- </listitem>
97717
- </orderedlist>
97718
- </para>
97719
-
97720
- <para>The source code for a work means the preferred form of the work for making modifications
97721
- to it. For an executable work, complete source code means all the source code for all modules
97722
- it contains, plus any associated interface definition files, plus the scripts used to control
97723
- compilation and installation of the executable. However, as a special exception, the source
97724
- code distributed need not include anything that is normally distributed (in either source or
97725
- binary form) with the major components (compiler, kernel, and so on) of the operating system
97726
- on which the executable runs, unless that component itself accompanies the executable.</para>
97727
-
97728
- <para>If distribution of executable or object code is made by offering access to copy from a
97729
- designated place, then offering equivalent access to copy the source code from the same place
97730
- counts as distribution of the source code, even though third parties are not compelled to
97731
- copy the source along with the object code.</para>
97732
- </section>
97733
- <section id="gpl-2-4">
97734
- <title>Section 4</title>
97735
- <para>You may not copy, modify, sublicense, or distribute the Program except as expressly provided
97736
- under this License. Any attempt otherwise to copy, modify, sublicense or distribute the
97737
- Program is void, and will automatically terminate your rights under this License. However,
97738
- parties who have received copies, or rights, from you under this License will not have their
97739
- licenses terminated so long as such parties remain in full compliance.</para>
97740
- </section>
97741
- <section id="gpl-2-5">
97742
- <title>Section 5</title>
97743
- <para>You are not required to accept this License, since you have not signed it. However, nothing
97744
- else grants you permission to modify or distribute the Program or its derivative works.
97745
- These actions are prohibited by law if you do not accept this License. Therefore, by modifying
97746
- or distributing the Program (or any work based on the Program), you indicate your acceptance
97747
- of this License to do so, and all its terms and conditions for copying, distributing or
97748
- modifying the Program or works based on it.</para>
97749
- </section>
97750
- <section id="gpl-2-6">
97751
- <title>Section 6</title>
97752
- <para>Each time you redistribute the Program (or any work based on the Program), the recipient
97753
- automatically receives a license from the original licensor to copy, distribute or modify
97754
- the Program subject to these terms and conditions. You may not impose any further restrictions
97755
- on the recipients' exercise of the rights granted herein. You are not responsible for enforcing
97756
- compliance by third parties to this License.</para>
97757
- </section>
97758
- <section id="gpl-2-7">
97759
- <title>Section 7</title>
97760
- <para>If, as a consequence of a court judgment or allegation of patent infringement or for any other
97761
- reason (not limited to patent issues), conditions are imposed on you (whether by court order,
97762
- agreement or otherwise) that contradict the conditions of this License, they do not excuse you
97763
- from the conditions of this License. If you cannot distribute so as to satisfy simultaneously
97764
- your obligations under this License and any other pertinent obligations, then as a consequence
97765
- you may not distribute the Program at all. For example, if a patent license would not permit
97766
- royalty-free redistribution of the Program by all those who receive copies directly or
97767
- indirectly through you, then the only way you could satisfy both it and this License would be
97768
- to refrain entirely from distribution of the Program.</para>
97769
-
97770
- <para>If any portion of this section is held invalid or unenforceable under any particular circumstance,
97771
- the balance of the section is intended to apply and the section as a whole is intended to apply
97772
- in other circumstances.</para>
97773
-
97774
- <para>It is not the purpose of this section to induce you to infringe any patents or other property
97775
- right claims or to contest validity of any such claims; this section has the sole purpose of
97776
- protecting the integrity of the free software distribution system, which is implemented by public
97777
- license practices. Many people have made generous contributions to the wide range of software
97778
- distributed through that system in reliance on consistent application of that system; it is up
97779
- to the author/donor to decide if he or she is willing to distribute software through any other
97780
- system and a licensee cannot impose that choice.</para>
97781
-
97782
- <para>This section is intended to make thoroughly clear what is believed to be a consequence of the
97783
- rest of this License.</para>
97784
- </section>
97785
- <section id="gpl-2-8">
97786
- <title>Section 8</title>
97787
- <para>If the distribution and/or use of the Program is restricted in certain countries either by patents
97788
- or by copyrighted interfaces, the original copyright holder who places the Program under this License
97789
- may add an explicit geographical distribution limitation excluding those countries, so that
97790
- distribution is permitted only in or among countries not thus excluded. In such case, this License
97791
- incorporates the limitation as if written in the body of this License.</para>
97792
- </section>
97793
- <section id="gpl-2-9">
97794
- <title>Section 9</title>
97795
- <para>The Free Software Foundation may publish revised and/or new versions of the General Public License
97796
- from time to time. Such new versions will be similar in spirit to the present version, but may differ
97797
- in detail to address new problems or concerns.</para>
97798
-
97799
- <para>Each version is given a distinguishing version number. If the Program specifies a version number of
97800
- this License which applies to it and <quote>any later version</quote>, you have the option of following the terms
97801
- and conditions either of that version or of any later version published by the Free Software
97802
- Foundation. If the Program does not specify a version number of this License, you may choose any
97803
- version ever published by the Free Software Foundation.</para>
97804
- </section>
97805
- <section id="gpl-2-10">
97806
- <title>Section 10</title>
97807
- <para>If you wish to incorporate parts of the Program into other free programs whose distribution
97808
- conditions are different, write to the author to ask for permission. For software which is copyrighted
97809
- by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions
97810
- for this. Our decision will be guided by the two goals of preserving the free status of all
97811
- derivatives of our free software and of promoting the sharing and reuse of software generally.</para>
97812
- </section>
97813
- <section id="gpl-2-11">
97814
- <title>NO WARRANTY Section 11</title>
97815
- <para>BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT
97816
- PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR
97817
- OTHER PARTIES PROVIDE THE PROGRAM <quote>AS IS</quote> WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED,
97818
- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
97819
- PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
97820
- PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.</para>
97821
- </section>
97822
- <section id="gpl-2-12">
97823
- <title>Section 12</title>
97824
- <para>IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR
97825
- ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU
97826
- FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
97827
- USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED
97828
- INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH
97829
- ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
97830
- DAMAGES.</para>
97831
-
97832
- <para>END OF TERMS AND CONDITIONS</para>
97833
- </section>
97834
- </section>
97835
- <section id="gpl-3">
97836
- <title>How to Apply These Terms to Your New Programs</title>
97837
- <para>If you develop a new program, and you want it to be of the greatest
97838
- possible use to the public, the best way to achieve this is to make it
97839
- free software which everyone can redistribute and change under these terms.</para>
97840
-
97841
- <para>To do so, attach the following notices to the program. It is safest
97842
- to attach them to the start of each source file to most effectively
97843
- convey the exclusion of warranty; and each file should have at least
97844
- the <quote>copyright</quote> line and a pointer to where the full notice is found.</para>
97845
-
97846
- <para><one line to give the program's name and a brief idea of what it does.>
97847
- Copyright (C) <year> <name of author></para>
97848
-
97849
- <para>This program is free software; you can redistribute it and/or modify
97850
- it under the terms of the GNU General Public License as published by
97851
- the Free Software Foundation; either version 2 of the License, or
97852
- (at your option) any later version.</para>
97853
-
97854
- <para>This program is distributed in the hope that it will be useful,
97855
- but WITHOUT ANY WARRANTY; without even the implied warranty of
97856
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
97857
- GNU General Public License for more details.</para>
97858
-
97859
- <para>You should have received a copy of the GNU General Public License
97860
- along with this program; if not, write to the Free Software
97861
- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA</para>
97862
-
97863
- <para>Also add information on how to contact you by electronic and paper mail.</para>
97864
-
97865
- <para>If the program is interactive, make it output a short notice like this
97866
- when it starts in an interactive mode:</para>
97867
-
97868
- <para>Gnomovision version 69, Copyright (C) year name of author
97869
- Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type <quote>show w</quote>.
97870
- This is free software, and you are welcome to redistribute it
97871
- under certain conditions; type <quote>show c</quote> for details.</para>
97872
-
97873
- <para>The hypothetical commands <quote>show w</quote> and <quote>show c</quote> should
97874
- show the appropriate parts of the General Public License. Of course, the commands you
97875
- use may be called something other than <quote>show w</quote> and <quote>show c</quote>;
97876
- they could even be mouse-clicks or menu items--whatever suits your program.</para>
97877
-
97878
- <para>You should also get your employer (if you work as a programmer) or your
97879
- school, if any, to sign a <quote>copyright disclaimer</quote> for the program, if
97880
- necessary. Here is a sample; alter the names:</para>
97881
-
97882
- <para>Yoyodyne, Inc., hereby disclaims all copyright interest in the program
97883
- <quote>Gnomovision</quote> (which makes passes at compilers) written by James Hacker.</para>
97884
-
97885
- <para><signature of Ty Coon>, 1 April 1989
97886
- Ty Coon, President of Vice</para>
97887
-
97888
- <para>This General Public License does not permit incorporating your program into
97889
- proprietary programs. If your program is a subroutine library, you may
97890
- consider it more useful to permit linking proprietary applications with the
97891
- library. If this is what you want to do, use the GNU Library General
97892
- Public License instead of this License.</para>
97893
- </section>
97894
-</appendix>
97895
--- a/src/libstdc++-v3/doc/xml/manual/codecvt.xml
97896
+++ b/src/libstdc++-v3/doc/xml/manual/codecvt.xml
97897
@@ -595,7 +595,7 @@
97898
97899
<biblioentry>
97900
<biblioid class="uri">
97901
- <ulink url="http://www.opengroup.org/austin">
97902
+ <ulink url="http://www.opengroup.org/austin/">
97903
<citetitle>
97904
System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)
97905
</citetitle>
97906
83347
--- a/src/libstdc++-v3/doc/xml/manual/configure.xml
97907
83348
+++ b/src/libstdc++-v3/doc/xml/manual/configure.xml
97908
83349
@@ -113,8 +113,7 @@
97915
83356
can change the library ABI.
97916
83357
</para>
97917
83358
</listitem></varlistentry>
97918
--- a/src/libstdc++-v3/doc/xml/manual/debug.xml
97919
+++ b/src/libstdc++-v3/doc/xml/manual/debug.xml
97920
@@ -45,7 +45,7 @@
97921
communicate information about source constructs can be changed via
97922
<code>-gdwarf-2</code> or <code>-gstabs</code> flags: some debugging
97923
formats permit more expressive type and scope information to be
97924
- shown in gdb. Expressiveness can be enhanced by flags like
97925
+ shown in GDB. Expressiveness can be enhanced by flags like
97926
<code>-g3</code>. The default debug information for a particular
97927
platform can be identified via the value set by the
97928
PREFERRED_DEBUGGING_TYPE macro in the gcc sources.
97929
@@ -197,14 +197,14 @@
97930
</para>
97931
97932
<para>
97933
- Many options are available for gdb itself: please see <ulink
97934
- url="http://sources.redhat.com/gdb/current/onlinedocs/gdb_13.html#SEC125">
97935
- "GDB features for C++" </ulink> in the gdb documentation. Also
97936
+ Many options are available for GDB itself: please see <ulink
97937
+ url="http://sources.redhat.com/gdb/current/onlinedocs/gdb/">
97938
+ "GDB features for C++" </ulink> in the GDB documentation. Also
97939
recommended: the other parts of this manual.
97940
</para>
97941
97942
<para>
97943
- These settings can either be switched on in at the gdb command line,
97944
+ These settings can either be switched on in at the GDB command line,
97945
or put into a .gdbint file to establish default debugging
97946
characteristics, like so:
97947
</para>
97948
--- a/src/libstdc++-v3/doc/xml/manual/locale.xml
97949
+++ b/src/libstdc++-v3/doc/xml/manual/locale.xml
97950
@@ -571,7 +571,7 @@
97951
97952
<biblioentry>
97953
<biblioid class="uri">
97954
- <ulink url="http://www.opengroup.org/austin">
97955
+ <ulink url="http://www.opengroup.org/austin/">
97956
<citetitle>
97957
System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)
97958
</citetitle>
97959
--- a/src/libstdc++-v3/doc/xml/manual/messages.xml
97960
+++ b/src/libstdc++-v3/doc/xml/manual/messages.xml
97961
@@ -498,7 +498,7 @@
97962
97963
<biblioentry>
97964
<biblioid class="uri">
97965
- <ulink url="http://www.opengroup.org/austin">
97966
+ <ulink url="http://www.opengroup.org/austin/">
97967
<citetitle>
97968
System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)
97969
</citetitle>
97970
83359
--- a/src/libstdc++-v3/doc/xml/manual/prerequisites.xml
97971
83360
+++ b/src/libstdc++-v3/doc/xml/manual/prerequisites.xml
97972
83361
@@ -52,16 +52,8 @@
97988
83377
</para>
97989
83378
97990
83379
<para>
97991
--- a/src/libstdc++-v3/doc/xml/manual/using_exceptions.xml
97992
+++ b/src/libstdc++-v3/doc/xml/manual/using_exceptions.xml
97993
@@ -440,7 +440,7 @@
97994
97995
<biblioentry>
97996
<biblioid class="uri">
97997
- <ulink url="http://www.opengroup.org/austin">
97998
+ <ulink url="http://www.opengroup.org/austin/">
97999
<citetitle>
98000
System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)
98001
</citetitle>
98002
--- a/src/libstdc++-v3/include/bits/atomic_0.h
98003
+++ b/src/libstdc++-v3/include/bits/atomic_0.h
98004
@@ -1,6 +1,6 @@
98005
// -*- C++ -*- header.
98006
98007
-// Copyright (C) 2008, 2009
98008
+// Copyright (C) 2008, 2009, 2010, 2011
98009
// Free Software Foundation, Inc.
98010
//
98011
// This file is part of the GNU ISO C++ Library. This library is free
98012
@@ -49,34 +49,34 @@
98013
atomic_flag_clear_explicit(__g, __x); \
98014
__r; })
98015
98016
-#define _ATOMIC_STORE_(__a, __m, __x) \
98017
+#define _ATOMIC_STORE_(__a, __n, __x) \
98018
({__typeof__ _ATOMIC_MEMBER_* __p = &_ATOMIC_MEMBER_; \
98019
- __typeof__(__m) __v = (__m); \
98020
+ __typeof__(__n) __w = (__n); \
98021
__atomic_flag_base* __g = __atomic_flag_for_address(__p); \
98022
__atomic_flag_wait_explicit(__g, __x); \
98023
- *__p = __v; \
98024
+ *__p = __w; \
98025
atomic_flag_clear_explicit(__g, __x); \
98026
- __v; })
98027
+ __w; })
98028
98029
-#define _ATOMIC_MODIFY_(__a, __o, __m, __x) \
98030
+#define _ATOMIC_MODIFY_(__a, __o, __n, __x) \
98031
({__typeof__ _ATOMIC_MEMBER_* __p = &_ATOMIC_MEMBER_; \
98032
- __typeof__(__m) __v = (__m); \
98033
+ __typeof__(__n) __w = (__n); \
98034
__atomic_flag_base* __g = __atomic_flag_for_address(__p); \
98035
__atomic_flag_wait_explicit(__g, __x); \
98036
__typeof__ _ATOMIC_MEMBER_ __r = *__p; \
98037
- *__p __o __v; \
98038
+ *__p __o __w; \
98039
atomic_flag_clear_explicit(__g, __x); \
98040
__r; })
98041
98042
-#define _ATOMIC_CMPEXCHNG_(__a, __e, __m, __x) \
98043
+#define _ATOMIC_CMPEXCHNG_(__a, __e, __n, __x) \
98044
({__typeof__ _ATOMIC_MEMBER_* __p = &_ATOMIC_MEMBER_; \
98045
__typeof__(__e) __q = (__e); \
98046
- __typeof__(__m) __v = (__m); \
98047
+ __typeof__(__n) __w = (__n); \
98048
bool __r; \
98049
__atomic_flag_base* __g = __atomic_flag_for_address(__p); \
98050
__atomic_flag_wait_explicit(__g, __x); \
98051
__typeof__ _ATOMIC_MEMBER_ __t__ = *__p; \
98052
- if (__t__ == *__q) { *__p = __v; __r = true; } \
98053
+ if (__t__ == *__q) { *__p = __w; __r = true; } \
98054
else { *__q = __t__; __r = false; } \
98055
atomic_flag_clear_explicit(__g, __x); \
98056
__r; })
98057
--- a/src/libstdc++-v3/include/bits/random.tcc
98058
+++ b/src/libstdc++-v3/include/bits/random.tcc
98059
@@ -1,6 +1,6 @@
98060
// random number generation (out of line) -*- C++ -*-
98061
98062
-// Copyright (C) 2009, 2010 Free Software Foundation, Inc.
98063
+// Copyright (C) 2009, 2010, 2011 Free Software Foundation, Inc.
98064
//
98065
// This file is part of the GNU ISO C++ Library. This library is free
98066
// software; you can redistribute it and/or modify it under the
98067
@@ -1392,7 +1392,7 @@
98068
{
98069
result_type __ret;
98070
const _IntType __t = __param.t();
98071
- const _IntType __p = __param.p();
98072
+ const double __p = __param.p();
98073
const double __p12 = __p <= 0.5 ? __p : 1.0 - __p;
98074
__detail::_Adaptor<_UniformRandomNumberGenerator, double>
98075
__aurng(__urng);
98076
--- a/src/libstdc++-v3/include/ext/algorithm
98077
+++ b/src/libstdc++-v3/include/ext/algorithm
98078
@@ -1,6 +1,7 @@
98079
// Algorithm extensions -*- C++ -*-
98080
98081
-// Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
98082
+// Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
98083
+// 2009, 2010, 2011
98084
// Free Software Foundation, Inc.
98085
//
98086
// This file is part of the GNU ISO C++ Library. This library is free
98087
@@ -424,6 +425,9 @@
98088
__out_last - __out_first);
98089
}
98090
98091
+#ifdef __GXX_EXPERIMENTAL_CXX0X__
98092
+ using std::is_heap;
98093
+#else
98094
/**
98095
* This is an SGI extension.
98096
* @ingroup SGIextensions
98097
@@ -463,6 +467,7 @@
98098
98099
return std::__is_heap(__first, __comp, __last - __first);
98100
}
98101
+#endif
98102
98103
// is_sorted, a predicated testing whether a range is sorted in
98104
// nondescending order. This is an extension, not part of the C++
98105
--- a/src/libstdc++-v3/include/parallel/algo.h
98106
+++ b/src/libstdc++-v3/include/parallel/algo.h
98107
@@ -292,7 +292,7 @@
98108
typedef typename _IIterTraits::value_type _IValueType;
98109
typedef typename iteratorf_traits::value_type _FValueType;
98110
98111
- return _GLIBCXX_STD_P::find_first_of(__begin1, __end1, __begin2, __end2,
98112
+ return __gnu_parallel::find_first_of(__begin1, __end1, __begin2, __end2,
98113
__gnu_parallel::_EqualTo<_IValueType, _FValueType>());
98114
}
98115
98116
@@ -1160,7 +1160,7 @@
98117
const _Tp& __val)
98118
{
98119
typedef typename iterator_traits<_FIterator>::value_type _ValueType;
98120
- return _GLIBCXX_STD_P::search_n(__begin, __end, __count, __val,
98121
+ return __gnu_parallel::search_n(__begin, __end, __count, __val,
98122
__gnu_parallel::_EqualTo<_ValueType, _Tp>());
98123
}
98124
98125
@@ -2086,7 +2086,7 @@
98126
typedef typename _Iterator1Traits::value_type _ValueType1;
98127
typedef typename _Iterator2Traits::value_type _ValueType2;
98128
98129
- return _GLIBCXX_STD_P::merge(__begin1, __end1, __begin2, __end2,
98130
+ return __gnu_parallel::merge(__begin1, __end1, __begin2, __end2,
98131
__result, __gnu_parallel::_Less<_ValueType1, _ValueType2>());
98132
}
98133
98134
@@ -2128,7 +2128,7 @@
98135
{
98136
typedef iterator_traits<_RAIter> _TraitsType;
98137
typedef typename _TraitsType::value_type _ValueType;
98138
- _GLIBCXX_STD_P::nth_element(__begin, __nth, __end,
98139
+ __gnu_parallel::nth_element(__begin, __nth, __end,
98140
std::less<_ValueType>());
98141
}
98142
98143
@@ -2171,7 +2171,7 @@
98144
{
98145
typedef iterator_traits<_RAIter> _TraitsType;
98146
typedef typename _TraitsType::value_type _ValueType;
98147
- _GLIBCXX_STD_P::partial_sort(__begin, __middle, __end,
98148
+ __gnu_parallel::partial_sort(__begin, __middle, __end,
98149
std::less<_ValueType>());
98150
}
98151
98152
@@ -2241,7 +2241,7 @@
98153
max_element(_FIterator __begin, _FIterator __end)
98154
{
98155
typedef typename iterator_traits<_FIterator>::value_type _ValueType;
98156
- return _GLIBCXX_STD_P::max_element(__begin, __end,
98157
+ return __gnu_parallel::max_element(__begin, __end,
98158
std::less<_ValueType>());
98159
}
98160
98161
@@ -2333,7 +2333,7 @@
98162
min_element(_FIterator __begin, _FIterator __end)
98163
{
98164
typedef typename iterator_traits<_FIterator>::value_type _ValueType;
98165
- return _GLIBCXX_STD_P::min_element(__begin, __end,
98166
+ return __gnu_parallel::min_element(__begin, __end,
98167
std::less<_ValueType>());
98168
}
98169
98170
--- a/src/libstdc++-v3/include/parallel/algobase.h
98171
+++ b/src/libstdc++-v3/include/parallel/algobase.h
98172
@@ -142,7 +142,7 @@
98173
inline bool
98174
equal(_IIter1 __begin1, _IIter1 __end1, _IIter2 __begin2)
98175
{
98176
- return _GLIBCXX_STD_P::mismatch(__begin1, __end1, __begin2).first
98177
+ return __gnu_parallel::mismatch(__begin1, __end1, __begin2).first
98178
== __end1;
98179
}
98180
98181
@@ -152,7 +152,7 @@
98182
equal(_IIter1 __begin1, _IIter1 __end1, _IIter2 __begin2,
98183
_Predicate __pred)
98184
{
98185
- return _GLIBCXX_STD_P::mismatch(__begin1, __end1, __begin2, __pred).first
98186
+ return __gnu_parallel::mismatch(__begin1, __end1, __begin2, __pred).first
98187
== __end1;
98188
}
98189
98190
--- a/src/libstdc++-v3/include/parallel/balanced_quicksort.h
98191
+++ b/src/libstdc++-v3/include/parallel/balanced_quicksort.h
98192
@@ -132,7 +132,7 @@
98193
98194
// Swap pivot value to end.
98195
if (__pivot_pos != (__end - 1))
98196
- std::swap(*__pivot_pos, *(__end - 1));
98197
+ std::iter_swap(__pivot_pos, __end - 1);
98198
__pivot_pos = __end - 1;
98199
98200
__gnu_parallel::__binder2nd<_Compare, _ValueType, _ValueType, bool>
98201
@@ -144,7 +144,7 @@
98202
__num_threads);
98203
98204
// Swap back pivot to middle.
98205
- std::swap(*(__begin + __split_pos), *__pivot_pos);
98206
+ std::iter_swap(__begin + __split_pos, __pivot_pos);
98207
__pivot_pos = __begin + __split_pos;
98208
98209
#if _GLIBCXX_ASSERTIONS
98210
@@ -284,7 +284,7 @@
98211
98212
// Swap __pivot_pos value to end.
98213
if (__pivot_pos != (__end - 1))
98214
- std::swap(*__pivot_pos, *(__end - 1));
98215
+ std::iter_swap(__pivot_pos, __end - 1);
98216
__pivot_pos = __end - 1;
98217
98218
__gnu_parallel::__binder2nd
98219
@@ -303,7 +303,7 @@
98220
#endif
98221
// Swap pivot back to middle.
98222
if (__split_pos1 != __pivot_pos)
98223
- std::swap(*__split_pos1, *__pivot_pos);
98224
+ std::iter_swap(__split_pos1, __pivot_pos);
98225
__pivot_pos = __split_pos1;
98226
98227
// In case all elements are equal, __split_pos1 == 0.
98228
--- a/src/libstdc++-v3/include/parallel/losertree.h
98229
+++ b/src/libstdc++-v3/include/parallel/losertree.h
98230
@@ -216,6 +216,7 @@
98231
void
98232
__delete_min_insert(_Tp __key, bool __sup)
98233
{
98234
+ using std::swap;
98235
#if _GLIBCXX_ASSERTIONS
98236
// no dummy sequence can ever be at the top!
98237
_GLIBCXX_PARALLEL_ASSERT(_M_losers[0]._M_source != -1);
98238
@@ -236,7 +237,7 @@
98239
// The other one is smaller.
98240
std::swap(_M_losers[__pos]._M_sup, __sup);
98241
std::swap(_M_losers[__pos]._M_source, __source);
98242
- std::swap(_M_losers[__pos]._M_key, __key);
98243
+ swap(_M_losers[__pos]._M_key, __key);
98244
}
98245
}
98246
98247
@@ -316,6 +317,7 @@
98248
void
98249
__delete_min_insert(_Tp __key, bool __sup)
98250
{
98251
+ using std::swap;
98252
#if _GLIBCXX_ASSERTIONS
98253
// no dummy sequence can ever be at the top!
98254
_GLIBCXX_PARALLEL_ASSERT(_M_losers[0]._M_source != -1);
98255
@@ -332,7 +334,7 @@
98256
// The other one is smaller.
98257
std::swap(_M_losers[__pos]._M_sup, __sup);
98258
std::swap(_M_losers[__pos]._M_source, __source);
98259
- std::swap(_M_losers[__pos]._M_key, __key);
98260
+ swap(_M_losers[__pos]._M_key, __key);
98261
}
98262
}
98263
98264
@@ -679,6 +681,7 @@
98265
void
98266
__delete_min_insert(_Tp __key, bool)
98267
{
98268
+ using std::swap;
98269
#if _GLIBCXX_ASSERTIONS
98270
// no dummy sequence can ever be at the top!
98271
_GLIBCXX_PARALLEL_ASSERT(_M_losers[0]._M_source != -1);
98272
@@ -695,7 +698,7 @@
98273
{
98274
// The other one is smaller.
98275
std::swap(_M_losers[__pos]._M_source, __source);
98276
- std::swap(_M_losers[__pos]._M_key, __key);
98277
+ swap(_M_losers[__pos]._M_key, __key);
98278
}
98279
}
98280
98281
@@ -772,6 +775,7 @@
98282
void
98283
__delete_min_insert(_Tp __key, bool)
98284
{
98285
+ using std::swap;
98286
#if _GLIBCXX_ASSERTIONS
98287
// no dummy sequence can ever be at the top!
98288
_GLIBCXX_PARALLEL_ASSERT(_M_losers[0]._M_source != -1);
98289
@@ -786,7 +790,7 @@
98290
{
98291
// The other one is smaller.
98292
std::swap(_M_losers[__pos]._M_source, __source);
98293
- std::swap(_M_losers[__pos]._M_key, __key);
98294
+ swap(_M_losers[__pos]._M_key, __key);
98295
}
98296
}
98297
98298
--- a/src/libstdc++-v3/include/parallel/numeric
98299
+++ b/src/libstdc++-v3/include/parallel/numeric
98300
@@ -283,7 +283,7 @@
98301
typedef typename
98302
__gnu_parallel::_Multiplies<_ValueType1, _ValueType2>::result_type
98303
_MultipliesResultType;
98304
- return _GLIBCXX_STD_P::inner_product(__first1, __last1, __first2, __init,
98305
+ return __gnu_parallel::inner_product(__first1, __last1, __first2, __init,
98306
__gnu_parallel::_Plus<_Tp, _MultipliesResultType>(),
98307
__gnu_parallel::
98308
_Multiplies<_ValueType1, _ValueType2>(),
98309
@@ -303,7 +303,7 @@
98310
typedef typename
98311
__gnu_parallel::_Multiplies<_ValueType1, _ValueType2>::result_type
98312
_MultipliesResultType;
98313
- return _GLIBCXX_STD_P::inner_product(__first1, __last1, __first2, __init,
98314
+ return __gnu_parallel::inner_product(__first1, __last1, __first2, __init,
98315
__gnu_parallel::_Plus<_Tp, _MultipliesResultType>(),
98316
__gnu_parallel::
98317
_Multiplies<_ValueType1, _ValueType2>());
98318
@@ -359,7 +359,7 @@
98319
partial_sum(_IIter __begin, _IIter __end, _OutputIterator __result)
98320
{
98321
typedef typename iterator_traits<_IIter>::value_type _ValueType;
98322
- return _GLIBCXX_STD_P::partial_sum(__begin, __end,
98323
+ return __gnu_parallel::partial_sum(__begin, __end,
98324
__result, std::plus<_ValueType>());
98325
}
98326
98327
--- a/src/libstdc++-v3/include/parallel/partition.h
98328
+++ b/src/libstdc++-v3/include/parallel/partition.h
98329
@@ -171,8 +171,8 @@
98330
// Fetch new chunk(__s).
98331
break;
98332
98333
- std::swap(__begin[__thread_left],
98334
- __begin[__thread_right]);
98335
+ std::iter_swap(__begin + __thread_left,
98336
+ __begin + __thread_right);
98337
++__thread_left;
98338
--__thread_right;
98339
}
98340
@@ -303,7 +303,7 @@
98341
98342
if (__final_left == __final_right)
98343
break;
98344
- std::swap(__begin[__final_left], __begin[__final_right]);
98345
+ std::iter_swap(__begin + __final_left, __begin + __final_right);
98346
++__final_left;
98347
--__final_right;
98348
}
98349
@@ -358,7 +358,7 @@
98350
98351
// Swap __pivot_pos value to end.
98352
if (__pivot_pos != (__end - 1))
98353
- std::swap(*__pivot_pos, *(__end - 1));
98354
+ std::iter_swap(__pivot_pos, __end - 1);
98355
__pivot_pos = __end - 1;
98356
98357
// _Compare must have first_value_type, second_value_type,
98358
@@ -380,7 +380,7 @@
98359
98360
// Swap pivot back to middle.
98361
if (__split_pos1 != __pivot_pos)
98362
- std::swap(*__split_pos1, *__pivot_pos);
98363
+ std::iter_swap(__split_pos1, __pivot_pos);
98364
__pivot_pos = __split_pos1;
98365
98366
// In case all elements are equal, __split_pos1 == 0
98367
83380
--- a/src/libstdc++-v3/libsupc++/eh_arm.cc
98368
83381
+++ b/src/libstdc++-v3/libsupc++/eh_arm.cc
98369
83382
@@ -30,10 +30,11 @@
98471
83484
actions = _UA_SEARCH_PHASE;
98472
83485
break;
98473
83486
98474
--- a/src/libstdc++-v3/src/bitmap_allocator.cc
98475
+++ b/src/libstdc++-v3/src/bitmap_allocator.cc
98476
@@ -49,6 +49,7 @@
98477
{
98478
#if defined __GTHREADS
98479
__mutex_type& __bfl_mutex = _M_get_mutex();
98480
+ __bfl_mutex.lock();
98481
#endif
98482
const vector_type& __free_list = _M_get_free_list();
98483
using __gnu_cxx::__detail::__lower_bound;
98484
--- a/src/libstdc++-v3/testsuite/22_locale/num_put/put/char/14220.cc
98485
+++ b/src/libstdc++-v3/testsuite/22_locale/num_put/put/char/14220.cc
98486
@@ -1,6 +1,6 @@
98487
// 2004-04-30 Paolo Carlini <pcarlini@suse.de>
98488
98489
-// Copyright (C) 2004, 2009, 2010 Free Software Foundation
98490
+// Copyright (C) 2004, 2009, 2010, 2011 Free Software Foundation
98491
//
98492
// This file is part of the GNU ISO C++ Library. This library is free
98493
// software; you can redistribute it and/or modify it under the
98494
@@ -19,13 +19,12 @@
98495
98496
// 22.2.2.2.1 num_put members
98497
98498
-// On Solaris 9/x86, 32-bit Solaris 10/x86 and 64-bit Solaris 10/SPARC, this
98499
-// test crashes in libc. Inside libstdc++, we call sprintf like so:
98500
+// On Solaris 9/x86 and 32-bit Solaris 10/x86, this test crashes in libc.
98501
+// Inside libstdc++, we call sprintf like so:
98502
// sprintf (buffer, "%.*f", 1000, 1.0)
98503
// which crashes.
98504
// { dg-xfail-run-if "" i?86-*-solaris2.9 }
98505
// { dg-xfail-run-if "" { i?86-*-solaris2.10 && ilp32 } }
98506
-// { dg-xfail-run-if "" { sparc*-sun-solaris2.10 && lp64 } }
98507
98508
#include <locale>
98509
#include <sstream>
98510
--- a/src/libstdc++-v3/testsuite/25_algorithms/headers/algorithm/parallel_algorithm_mixed1.cc
98511
+++ b/src/libstdc++-v3/testsuite/25_algorithms/headers/algorithm/parallel_algorithm_mixed1.cc
98512
@@ -30,7 +30,59 @@
98513
98514
const value_type c(0);
98515
98516
- vector_type v(10);
98517
+ vector_type v(10), result(20);
98518
+
98519
+ std::equal(v.begin(), v.end(), v.begin());
98520
+ std::equal(v.begin(), v.end(), v.begin(), std::equal_to<value_type>());
98521
+ __gnu_parallel::equal(v.begin(), v.end(), v.begin());
98522
+ __gnu_parallel::equal(v.begin(), v.end(), v.begin(),
98523
+ std::equal_to<value_type>());
98524
+
98525
std::find(v.begin(), v.end(), c);
98526
__gnu_parallel::find(v.begin(), v.end(), c);
98527
+
98528
+ std::find_first_of(v.begin(), v.end(), v.begin(), v.end());
98529
+ std::find_first_of(v.begin(), v.end(), v.begin(), v.end(),
98530
+ std::equal_to<value_type>());
98531
+ __gnu_parallel::find_first_of(v.begin(), v.end(), v.begin(), v.end());
98532
+ __gnu_parallel::find_first_of(v.begin(), v.end(), v.begin(), v.end(),
98533
+ std::equal_to<value_type>());
98534
+
98535
+ std::search_n(v.begin(), v.end(), 5, value_type(1));
98536
+ std::search_n(v.begin(), v.end(), 5, value_type(1),
98537
+ std::equal_to<value_type>());
98538
+ __gnu_parallel::search_n(v.begin(), v.end(), 5, value_type(1));
98539
+ __gnu_parallel::search_n(v.begin(), v.end(), 5, value_type(1),
98540
+ std::equal_to<value_type>());
98541
+
98542
+ std::merge(v.begin(), v.end(), v.begin(), v.end(), result.begin());
98543
+ std::merge(v.begin(), v.end(), v.begin(), v.end(), result.begin(),
98544
+ std::less<value_type>());
98545
+ __gnu_parallel::merge(v.begin(), v.end(), v.begin(), v.end(),
98546
+ result.begin());
98547
+ __gnu_parallel::merge(v.begin(), v.end(), v.begin(), v.end(),
98548
+ result.begin(), std::less<value_type>());
98549
+
98550
+ std::nth_element(v.begin(), v.begin() + 5, v.end());
98551
+ std::nth_element(v.begin(), v.begin() + 5, v.end(), std::less<value_type>());
98552
+ __gnu_parallel::nth_element(v.begin(), v.begin() + 5, v.end());
98553
+ __gnu_parallel::nth_element(v.begin(), v.begin() + 5, v.end(),
98554
+ std::less<value_type>());
98555
+
98556
+ std::partial_sort(v.begin(), v.begin() + 5, v.end());
98557
+ std::partial_sort(v.begin(), v.begin() + 5, v.end(),
98558
+ std::less<value_type>());
98559
+ __gnu_parallel::partial_sort(v.begin(), v.begin() + 5, v.end());
98560
+ __gnu_parallel::partial_sort(v.begin(), v.begin() + 5, v.end(),
98561
+ std::less<value_type>());
98562
+
98563
+ std::min_element(v.begin(), v.end());
98564
+ std::min_element(v.begin(), v.end(), std::less<value_type>());
98565
+ __gnu_parallel::min_element(v.begin(), v.end());
98566
+ __gnu_parallel::min_element(v.begin(), v.end(), std::less<value_type>());
98567
+
98568
+ std::max_element(v.begin(), v.end());
98569
+ std::max_element(v.begin(), v.end(), std::less<value_type>());
98570
+ __gnu_parallel::max_element(v.begin(), v.end());
98571
+ __gnu_parallel::max_element(v.begin(), v.end(), std::less<value_type>());
98572
}
98573
--- a/src/libstdc++-v3/testsuite/25_algorithms/headers/algorithm/parallel_algorithm_mixed2.cc
98574
+++ b/src/libstdc++-v3/testsuite/25_algorithms/headers/algorithm/parallel_algorithm_mixed2.cc
98575
@@ -35,7 +35,59 @@
98576
98577
const value_type c(0);
98578
98579
- vector_type v(10);
98580
+ vector_type v(10), result(20);
98581
+
98582
+ std::equal(v.begin(), v.end(), v.begin());
98583
+ std::equal(v.begin(), v.end(), v.begin(), std::equal_to<value_type>());
98584
+ __gnu_parallel::equal(v.begin(), v.end(), v.begin());
98585
+ __gnu_parallel::equal(v.begin(), v.end(), v.begin(),
98586
+ std::equal_to<value_type>());
98587
+
98588
std::find(v.begin(), v.end(), c);
98589
__gnu_parallel::find(v.begin(), v.end(), c);
98590
+
98591
+ std::find_first_of(v.begin(), v.end(), v.begin(), v.end());
98592
+ std::find_first_of(v.begin(), v.end(), v.begin(), v.end(),
98593
+ std::equal_to<value_type>());
98594
+ __gnu_parallel::find_first_of(v.begin(), v.end(), v.begin(), v.end());
98595
+ __gnu_parallel::find_first_of(v.begin(), v.end(), v.begin(), v.end(),
98596
+ std::equal_to<value_type>());
98597
+
98598
+ std::search_n(v.begin(), v.end(), 5, value_type(1));
98599
+ std::search_n(v.begin(), v.end(), 5, value_type(1),
98600
+ std::equal_to<value_type>());
98601
+ __gnu_parallel::search_n(v.begin(), v.end(), 5, value_type(1));
98602
+ __gnu_parallel::search_n(v.begin(), v.end(), 5, value_type(1),
98603
+ std::equal_to<value_type>());
98604
+
98605
+ std::merge(v.begin(), v.end(), v.begin(), v.end(), result.begin());
98606
+ std::merge(v.begin(), v.end(), v.begin(), v.end(), result.begin(),
98607
+ std::less<value_type>());
98608
+ __gnu_parallel::merge(v.begin(), v.end(), v.begin(), v.end(),
98609
+ result.begin());
98610
+ __gnu_parallel::merge(v.begin(), v.end(), v.begin(), v.end(),
98611
+ result.begin(), std::less<value_type>());
98612
+
98613
+ std::nth_element(v.begin(), v.begin() + 5, v.end());
98614
+ std::nth_element(v.begin(), v.begin() + 5, v.end(), std::less<value_type>());
98615
+ __gnu_parallel::nth_element(v.begin(), v.begin() + 5, v.end());
98616
+ __gnu_parallel::nth_element(v.begin(), v.begin() + 5, v.end(),
98617
+ std::less<value_type>());
98618
+
98619
+ std::partial_sort(v.begin(), v.begin() + 5, v.end());
98620
+ std::partial_sort(v.begin(), v.begin() + 5, v.end(),
98621
+ std::less<value_type>());
98622
+ __gnu_parallel::partial_sort(v.begin(), v.begin() + 5, v.end());
98623
+ __gnu_parallel::partial_sort(v.begin(), v.begin() + 5, v.end(),
98624
+ std::less<value_type>());
98625
+
98626
+ std::min_element(v.begin(), v.end());
98627
+ std::min_element(v.begin(), v.end(), std::less<value_type>());
98628
+ __gnu_parallel::min_element(v.begin(), v.end());
98629
+ __gnu_parallel::min_element(v.begin(), v.end(), std::less<value_type>());
98630
+
98631
+ std::max_element(v.begin(), v.end());
98632
+ std::max_element(v.begin(), v.end(), std::less<value_type>());
98633
+ __gnu_parallel::max_element(v.begin(), v.end());
98634
+ __gnu_parallel::max_element(v.begin(), v.end(), std::less<value_type>());
98635
}
98636
--- a/src/libstdc++-v3/testsuite/26_numerics/headers/numeric/parallel_numeric_mixed1.cc
98637
+++ b/src/libstdc++-v3/testsuite/26_numerics/headers/numeric/parallel_numeric_mixed1.cc
98638
@@ -32,6 +32,17 @@
98639
const value_type c(0);
98640
98641
vector_type v(10);
98642
+
98643
std::accumulate(v.begin(), v.end(), value_type(1));
98644
+ std::accumulate(v.begin(), v.end(), value_type(1), std::plus<value_type>());
98645
__gnu_parallel::accumulate(v.begin(), v.end(), value_type(1));
98646
+ __gnu_parallel::accumulate(v.begin(), v.end(), value_type(1),
98647
+ std::plus<value_type>());
98648
+
98649
+ std::inner_product(v.begin(), v.end(), v.begin(), value_type(1));
98650
+ std::inner_product(v.begin(), v.end(), v.begin(), value_type(1),
98651
+ std::multiplies<value_type>(), std::plus<value_type>());
98652
+ __gnu_parallel::inner_product(v.begin(), v.end(), v.begin(), value_type(1));
98653
+ __gnu_parallel::inner_product(v.begin(), v.end(), v.begin(), value_type(1),
98654
+ std::multiplies<value_type>(), std::plus<value_type>());
98655
}
98656
--- a/src/libstdc++-v3/testsuite/26_numerics/headers/numeric/parallel_numeric_mixed2.cc
98657
+++ b/src/libstdc++-v3/testsuite/26_numerics/headers/numeric/parallel_numeric_mixed2.cc
98658
@@ -37,6 +37,17 @@
98659
const value_type c(0);
98660
98661
vector_type v(10);
98662
+
98663
std::accumulate(v.begin(), v.end(), value_type(1));
98664
+ std::accumulate(v.begin(), v.end(), value_type(1), std::plus<value_type>());
98665
__gnu_parallel::accumulate(v.begin(), v.end(), value_type(1));
98666
+ __gnu_parallel::accumulate(v.begin(), v.end(), value_type(1),
98667
+ std::plus<value_type>());
98668
+
98669
+ std::inner_product(v.begin(), v.end(), v.begin(), value_type(1));
98670
+ std::inner_product(v.begin(), v.end(), v.begin(), value_type(1),
98671
+ std::multiplies<value_type>(), std::plus<value_type>());
98672
+ __gnu_parallel::inner_product(v.begin(), v.end(), v.begin(), value_type(1));
98673
+ __gnu_parallel::inner_product(v.begin(), v.end(), v.begin(), value_type(1),
98674
+ std::multiplies<value_type>(), std::plus<value_type>());
98675
}
98676
--- a/src/libstdc++-v3/testsuite/ext/is_heap/47709.cc
98677
+++ b/src/libstdc++-v3/testsuite/ext/is_heap/47709.cc
98678
@@ -0,0 +1,29 @@
98679
+// { dg-do compile }
98680
+// { dg-options "-std=gnu++0x" }
98681
+
98682
+// Copyright (C) 2011 Free Software Foundation, Inc.
98683
+//
98684
+// This file is part of the GNU ISO C++ Library. This library is free
98685
+// software; you can redistribute it and/or modify it under the
98686
+// terms of the GNU General Public License as published by the
98687
+// Free Software Foundation; either version 3, or (at your option)
98688
+// any later version.
98689
+
98690
+// This library is distributed in the hope that it will be useful,
98691
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
98692
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
98693
+// GNU General Public License for more details.
98694
+
98695
+// You should have received a copy of the GNU General Public License along
98696
+// with this library; see the file COPYING3. If not see
98697
+// <http://www.gnu.org/licenses/>.
98698
+
98699
+#include <ext/algorithm>
98700
+#include <vector>
98701
+
98702
+// libstdc++/47709
98703
+void foo()
98704
+{
98705
+ std::vector<int> v;
98706
+ is_heap(v.begin(), v.end());
98707
+}
98708
--- a/src/libstdc++-v3/testsuite/lib/libstdc++.exp
98709
+++ b/src/libstdc++-v3/testsuite/lib/libstdc++.exp
98710
@@ -586,6 +586,15 @@
98711
}
98712
98713
# Collect into libtestc++.a
98714
+ # Delete libtestc++.a first. Mixed 32 and 64-bit archives cannot be
98715
+ # linked on IRIX 6.
98716
+ # Use same procedure as gcc-dg.exp (remove-build-file).
98717
+ if [is_remote host] {
98718
+ # Ensure the host knows the file is gone by deleting there
98719
+ # first.
98720
+ remote_file host delete "./libtestc++.a"
98721
+ }
98722
+ remote_file build delete "./libtestc++.a"
98723
if [info exists env(AR)] {
98724
set ar $env(AR)
98725
} else {
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