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//Original:/proj/frio/dv/testcases/core/c_interr_timer_reload/c_interr_timer_reload.dsp
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// Spec Reference: interrupt on HW TIMER auto-reload
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# sim: --environment operating
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.include "testutils.inc"
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include(selfcheck.inc)
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#define TCNTL 0xFFE03000
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#define TPERIOD 0xFFE03004
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#define TSCALE 0xFFE03008
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#define TCOUNT 0xFFE0300c
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#define EVT 0xFFE02000
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#define EVT15 0xFFE0203c
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#define EVT_OVERRIDE 0xFFE02100
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#define ITABLE 0x000FF000
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#define PROGRAM_STACK 0x000FF100
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#define STACKSIZE 0x00000300
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INIT_R_REGS(0); // Initialize Dregs
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INIT_P_REGS(0); // Initialize Pregs
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// CHECK_INIT(p5, 0x00BFFFFC);
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// CHECK_INIT(p5, 0xE0000000);
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LD32(p0, EVT); // Setup Event Vectors and Handlers
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LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
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LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
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LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
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LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
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[ P0 ++ ] = R0; // IVT4 not used
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LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
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LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
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LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
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LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
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LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
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LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
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LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
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LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
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LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
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LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
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LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
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LD32(p0, EVT_OVERRIDE);
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R0 = -1; // Change this to mask interrupts (*)
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[ P0 ] = R0; // IMASK
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LD32_LABEL(p1, START);
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[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
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RAISE 15; // after we RTI, INT 15 should be taken
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LD32_LABEL(r7, START);
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NOP; // Workaround for Bug 217
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[ -- SP ] = RETI; // Enable Nested Interrupts
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WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state)
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WR_MMR(TPERIOD, 0x00000020, p0, r0);
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WR_MMR(TCOUNT, 0x00000002, p0, r0);
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WR_MMR(TSCALE, 0x00000005, p0, r0);
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// Read the contents of the Timer
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RD_MMR(TPERIOD, p0, r2);
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CHECKREG(r2, 0x00000020);
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RD_MMR(TCOUNT, p0, r3);
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CHECKREG(r3, 0x00000002);// fsim -ro useChecker=regtrace
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WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN)
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NOP; NOP; NOP; NOP; NOP;
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NOP; NOP; NOP; NOP; NOP;
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NOP; NOP; NOP; NOP; NOP;
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RD_MMR(TCOUNT, p0, r4);
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CHECKREG(r4, 0x00000000);
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RD_MMR(TCNTL, p0, r5);
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CHECKREG(r5, 0x0000000B);
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WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
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CHECKREG(r7, 0x00000001);
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WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power
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WR_MMR(TPERIOD, 0x00000020, p0, r0);
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WR_MMR(TCOUNT, 0x00000003, p0, r0);
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WR_MMR(TSCALE, 0x00000002, p0, r0);
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WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auo-reload
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NOP; NOP; NOP; NOP; NOP;
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NOP; NOP; NOP; NOP; NOP;
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NOP; NOP; NOP; NOP; NOP;
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NOP; NOP; NOP; NOP; NOP;
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// Read the contents of the Timer
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// CHECKREG(r7, 0x00000002);
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WR_MMR(TPERIOD, 0x00000030, p0, r0); // SHOULD NOT EXECUTE
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RD_MMR(TPERIOD, p0, r2);
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CHECKREG(r2, 0x00000020);
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RD_MMR(TCNTL , p0, r3);
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CHECKREG(r3, 0x0000000F);
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WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer but not auto-reload
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RD_MMR(TCOUNT, p0, r4);
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CHECKREG(r4, 0x00000000);
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RD_MMR(TCNTL, p0, r5);
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CHECKREG(r5, 0x0000000B);
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WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
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dbg_pass; // Call Endtest Macro
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//*********************************************************************
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// Handlers for Events
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EHANDLE: // Emulation Handler 0
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RHANDLE: // Reset Handler 1
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NHANDLE: // NMI Handler 2
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XHANDLE: // Exception Handler 3
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HWHANDLE: // HW Error Handler 5
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THANDLE: // Timer Handler 6
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I7HANDLE: // IVG 7 Handler
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I8HANDLE: // IVG 8 Handler
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I9HANDLE: // IVG 9 Handler
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I10HANDLE: // IVG 10 Handler
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I11HANDLE: // IVG 11 Handler
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I12HANDLE: // IVG 12 Handler
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I13HANDLE: // IVG 13 Handler
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I14HANDLE: // IVG 14 Handler
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I15HANDLE: // IVG 15 Handler
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.section MEM_DATA_ADDR_1,"aw"
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NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug