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//Original:testcases/core/c_ldstidxl_ld_dr_xh/c_ldstidxl_ld_dr_xh.dsp
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// Spec Reference: c_ldstidxl load dreg XH (ld with indexed addressing)
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.include "testutils.inc"
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I1 = P3; P3 = I0; I3 = SP; SP = I2;
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loadsym p1, DATA_ADDR_1, 0x00;
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loadsym p2, DATA_ADDR_2, 0xA0;
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loadsym i1, DATA_ADDR_1, 0x70;
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loadsym p4, DATA_ADDR_2, 0x70;
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loadsym p5, DATA_ADDR_1, 0x70;
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loadsym fp, DATA_ADDR_2, 0x70;
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loadsym i3, DATA_ADDR_1, 0x70;
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R0 = W [ P1 + 154 ] (X);
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R1 = W [ P1 + 84 ] (X);
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R2 = W [ P1 + 48 ] (X);
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R3 = W [ P1 + 10 ] (X);
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R4 = W [ P1 + 34 ] (X);
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R5 = W [ P1 + 20 ] (X);
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R6 = W [ P1 + 126 ] (X);
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R7 = W [ P1 + 154 ] (X);
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CHECKREG r0, 0x00000405;
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CHECKREG r1, 0x00002425;
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CHECKREG r2, 0xFFFF8485;
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CHECKREG r3, 0x00000809;
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CHECKREG r4, 0x00001122;
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CHECKREG r5, 0x00001617;
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CHECKREG r6, 0x00006263;
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CHECKREG r7, 0x00000405;
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R0 = W [ P2 + -120 ] (X);
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R1 = W [ P2 + -114 ] (X);
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R2 = W [ P2 + -36 ] (X);
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R3 = W [ P2 + -22 ] (X);
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R4 = W [ P2 + -44 ] (X);
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R5 = W [ P2 + -6 ] (X);
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R6 = W [ P2 + -52 ] (X);
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R7 = W [ P2 + -146 ] (X);
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CHECKREG r0, 0xFFFFD5D6;
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CHECKREG r1, 0xFFFFD7D8;
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CHECKREG r2, 0x0000565A;
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CHECKREG r3, 0xFFFFA667;
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CHECKREG r4, 0xFFFF99EA;
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CHECKREG r5, 0x00004C4D;
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CHECKREG r6, 0xFFFF99EA;
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CHECKREG r7, 0x00004C4D;
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R0 = W [ P3 + 56 ] (X);
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R1 = W [ P3 + 62 ] (X);
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R2 = W [ P3 + -64 ] (X);
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R3 = W [ P3 + 60 ] (X);
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R4 = W [ P3 + -56 ] (X);
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R5 = W [ P3 + 10 ] (X);
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R6 = W [ P3 + -28 ] (X);
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R7 = W [ P3 + -110 ] (X);
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CHECKREG r0, 0x00001617;
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CHECKREG r1, 0x00001819;
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CHECKREG r2, 0xFFFF8485;
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CHECKREG r3, 0x00001A1B;
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CHECKREG r4, 0xFFFF8283;
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CHECKREG r5, 0x00005859;
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CHECKREG r6, 0x00002425;
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CHECKREG r7, 0x00000001;
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R0 = W [ P4 + 42 ] (X);
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R1 = W [ P4 + -40 ] (X);
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R2 = W [ P4 + 38 ] (X);
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R3 = W [ P4 + -32 ] (X);
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R4 = W [ P4 + 28 ] (X);
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R5 = W [ P4 + 26 ] (X);
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R6 = W [ P4 + -22 ] (X);
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R7 = W [ P4 + 106 ] (X);
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CHECKREG r0, 0x00004C4D;
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CHECKREG r1, 0xFFFF99EA;
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CHECKREG r2, 0x00004849;
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CHECKREG r3, 0xFFFF99EA;
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CHECKREG r4, 0x00004243;
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CHECKREG r5, 0xFFFFA667;
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CHECKREG r6, 0xFFFF98E8;
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CHECKREG r7, 0xFFFF95E8;
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R0 = W [ P5 + -14 ] (X);
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R1 = W [ P5 + 12 ] (X);
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R2 = W [ P5 + -6 ] (X);
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R3 = W [ P5 + 4 ] (X);
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R4 = W [ P5 + 0 ] (X);
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R5 = W [ P5 + -2 ] (X);
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R6 = W [ P5 + 8 ] (X);
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R7 = W [ P5 + -108 ] (X);
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CHECKREG r0, 0x00003435;
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CHECKREG r1, 0x00006465;
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CHECKREG r2, 0x00004243;
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CHECKREG r3, 0x00005657;
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CHECKREG r4, 0x00005253;
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CHECKREG r5, 0x00004647;
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CHECKREG r6, 0x00006061;
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CHECKREG r7, 0x00000607;
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R0 = W [ FP + 90 ] (X);
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R1 = W [ FP + -14 ] (X);
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R2 = W [ FP + 42 ] (X);
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R3 = W [ FP + -66 ] (X);
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R4 = W [ FP + 26 ] (X);
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R5 = W [ FP + -34 ] (X);
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R6 = W [ FP + 38 ] (X);
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R7 = W [ FP + -98 ] (X);
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CHECKREG r0, 0xFFFF91E8;
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CHECKREG r1, 0xFFFF91E8;
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CHECKREG r2, 0x00004C4D;
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CHECKREG r3, 0xFFFFD7D8;
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CHECKREG r4, 0xFFFFA667;
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CHECKREG r5, 0xFFFF95E8;
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CHECKREG r6, 0x00004849;
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CHECKREG r7, 0x00004C4D;
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R0 = W [ SP + 46 ] (X);
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R1 = W [ SP + -42 ] (X);
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R2 = W [ SP + 48 ] (X);
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R3 = W [ SP + 50 ] (X);
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R4 = W [ SP + -102 ] (X);
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R5 = W [ SP + 82 ] (X);
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R6 = W [ SP + 62 ] (X);
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R7 = W [ SP + 46 ] (X);
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CHECKREG r0, 0x00000809;
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CHECKREG r1, 0x00000506;
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CHECKREG r2, 0x00000E0F;
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CHECKREG r3, 0x00000C0D;
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CHECKREG r4, 0x00000809;
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CHECKREG r5, 0x00007475;
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CHECKREG r6, 0x00001819;
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CHECKREG r7, 0x00000809;
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// Pre-load memory with known data
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// More data is defined than will actually be used
added
removed
sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xh.s
