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// See the file "License.txt" for information on usage and redistribution of
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// this file, and for a DISCLAIMER OF ALL WARRANTIES.
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// $Id: M6532.cxx 2412 2012-03-14 01:19:23Z stephena $
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// $Id: M6532.cxx 2499 2012-05-25 12:41:19Z stephena $
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//============================================================================
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if(DDR bit is input) set output as 1
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else if(DDR bit is output) set output as bit in ORA
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uInt8 a = myOutA | ~myDDRA;
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Controller& port0 = myConsole.controller(Controller::Left);
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port0.write(Controller::One, a & 0x10);
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port0.write(Controller::Two, a & 0x20);
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port0.write(Controller::Three, a & 0x40);
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port0.write(Controller::Four, a & 0x80);
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Controller& port1 = myConsole.controller(Controller::Right);
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port1.write(Controller::One, a & 0x01);
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port1.write(Controller::Two, a & 0x02);
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port1.write(Controller::Three, a & 0x04);
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port1.write(Controller::Four, a & 0x08);
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uInt8 ioport = myOutA | ~myDDRA;
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port0.write(Controller::One, ioport & 0x10);
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port0.write(Controller::Two, ioport & 0x20);
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port0.write(Controller::Three, ioport & 0x40);
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port0.write(Controller::Four, ioport & 0x80);
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port1.write(Controller::One, ioport & 0x01);
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port1.write(Controller::Two, ioport & 0x02);
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port1.write(Controller::Three, ioport & 0x04);
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port1.write(Controller::Four, ioport & 0x08);
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port0.controlWrite();
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port1.controlWrite();
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port0.controlWrite(ioport);
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port1.controlWrite(ioport);
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out.putString(name());
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// Output the RAM
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for(uInt32 t = 0; t < 128; ++t)
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out.putByte((char)myRAM[t]);
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out.putByteArray(myRAM, 128);
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out.putInt(myTimer);
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out.putInt(myIntervalShift);
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out.putBool(myInterruptEnabled);
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out.putBool(myInterruptTriggered);
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out.putByte((char)myDDRA);
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out.putByte((char)myDDRB);
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out.putByte((char)myOutA);
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out.putByte((char)myOutB);
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out.putByte((char)myOutTimer[0]);
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out.putByte((char)myOutTimer[1]);
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out.putByte((char)myOutTimer[2]);
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out.putByte((char)myOutTimer[3]);
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out.putByteArray(myOutTimer, 4);
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catch(const char* msg)
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cerr << "ERROR: M6532::save" << endl << " " << msg << endl;
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cerr << "ERROR: M6532::save" << endl;
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uInt32 limit = (uInt32) in.getInt();
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for(uInt32 t = 0; t < limit; ++t)
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myRAM[t] = (uInt8) in.getByte();
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in.getByteArray(myRAM, 128);
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myTimer = (uInt32) in.getInt();
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myIntervalShift = (uInt32) in.getInt();
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myCyclesWhenTimerSet = (uInt32) in.getInt();
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myTimer = in.getInt();
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myIntervalShift = in.getInt();
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myCyclesWhenTimerSet = in.getInt();
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myInterruptEnabled = in.getBool();
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myInterruptTriggered = in.getBool();
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myDDRA = (uInt8) in.getByte();
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myDDRB = (uInt8) in.getByte();
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myOutA = (uInt8) in.getByte();
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myOutB = (uInt8) in.getByte();
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myOutTimer[0] = (uInt8) in.getByte();
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myOutTimer[1] = (uInt8) in.getByte();
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myOutTimer[2] = (uInt8) in.getByte();
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myOutTimer[3] = (uInt8) in.getByte();
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myDDRA = in.getByte();
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myDDRB = in.getByte();
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myOutA = in.getByte();
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myOutB = in.getByte();
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in.getByteArray(myOutTimer, 4);
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catch(const char* msg)
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cerr << "ERROR: M6532::load" << endl << " " << msg << endl;
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cerr << "ERROR: M6532::load" << endl;