200
#define EEDR _SFR_IO8(0X20)
208
#define EEDR _SFR_IO8 (0x20)
209
#define EEAR _SFR_IO16 (0x21)
210
#define EEARL _SFR_IO8 (0x21)
211
#define EEARH _SFR_IO8 (0x22)
202
/* Combine EEARL and EEARH */
203
#define EEAR _SFR_IO16(0x21)
204
#define EEARL _SFR_IO8(0x21)
205
#define EEARH _SFR_IO8(0X22)
213
207
Even though EEARH is not used by the mega48, the EEAR8 bit in the register
214
208
must be written to 0, according to the datasheet, hence the EEARH register
215
209
must be defined for the mega48.
211
/* 6-char sequence denoting where to find the EEPROM registers in memory space.
212
Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
214
First two letters: EECR address.
215
Second two letters: EEDR address.
216
Last two letters: EEAR address. */
217
#define __EEPROM_REG_LOCATIONS__ 1F2021
218
220
#define GTCCR _SFR_IO8 (0x23)
618
620
/* Interrupt vectors */
620
#define SIG_INTERRUPT0 _VECTOR(1)
621
#define SIG_INTERRUPT1 _VECTOR(2)
622
#define SIG_PIN_CHANGE0 _VECTOR(3)
623
#define SIG_PIN_CHANGE1 _VECTOR(4)
624
#define SIG_PIN_CHANGE2 _VECTOR(5)
625
#define SIG_WATCHDOG_TIMEOUT _VECTOR(6)
626
#define SIG_OUTPUT_COMPARE2A _VECTOR(7)
627
#define SIG_OUTPUT_COMPARE2B _VECTOR(8)
628
#define SIG_OVERFLOW2 _VECTOR(9)
629
#define SIG_INPUT_CAPTURE1 _VECTOR(10)
630
#define SIG_OUTPUT_COMPARE1A _VECTOR(11)
631
#define SIG_OUTPUT_COMPARE1B _VECTOR(12)
632
#define SIG_OVERFLOW1 _VECTOR(13)
633
#define SIG_OUTPUT_COMPARE0A _VECTOR(14)
634
#define SIG_OUTPUT_COMPARE0B _VECTOR(15)
635
#define SIG_OVERFLOW0 _VECTOR(16)
636
#define SIG_SPI _VECTOR(17)
637
#define SIG_USART_RECV _VECTOR(18)
638
#define SIG_USART_DATA _VECTOR(19)
639
#define SIG_USART_TRANS _VECTOR(20)
640
#define SIG_ADC _VECTOR(21)
641
#define SIG_EEPROM_READY _VECTOR(22)
642
#define SIG_COMPARATOR _VECTOR(23)
643
#define SIG_TWI _VECTOR(24)
644
#define SIG_SPM_READY _VECTOR(25)
622
/* External Interrupt Request 0 */
623
#define INT0_vect _VECTOR(1)
624
#define SIG_INTERRUPT0 _VECTOR(1)
626
/* External Interrupt Request 1 */
627
#define INT1_vect _VECTOR(2)
628
#define SIG_INTERRUPT1 _VECTOR(2)
630
/* Pin Change Interrupt Request 0 */
631
#define PCINT0_vect _VECTOR(3)
632
#define SIG_PIN_CHANGE0 _VECTOR(3)
634
/* Pin Change Interrupt Request 0 */
635
#define PCINT1_vect _VECTOR(4)
636
#define SIG_PIN_CHANGE1 _VECTOR(4)
638
/* Pin Change Interrupt Request 1 */
639
#define PCINT2_vect _VECTOR(5)
640
#define SIG_PIN_CHANGE2 _VECTOR(5)
642
/* Watchdog Time-out Interrupt */
643
#define WDT_vect _VECTOR(6)
644
#define SIG_WATCHDOG_TIMEOUT _VECTOR(6)
646
/* Timer/Counter2 Compare Match A */
647
#define TIMER2_COMPA_vect _VECTOR(7)
648
#define SIG_OUTPUT_COMPARE2A _VECTOR(7)
650
/* Timer/Counter2 Compare Match A */
651
#define TIMER2_COMPB_vect _VECTOR(8)
652
#define SIG_OUTPUT_COMPARE2B _VECTOR(8)
654
/* Timer/Counter2 Overflow */
655
#define TIMER2_OVF_vect _VECTOR(9)
656
#define SIG_OVERFLOW2 _VECTOR(9)
658
/* Timer/Counter1 Capture Event */
659
#define TIMER1_CAPT_vect _VECTOR(10)
660
#define SIG_INPUT_CAPTURE1 _VECTOR(10)
662
/* Timer/Counter1 Compare Match A */
663
#define TIMER1_COMPA_vect _VECTOR(11)
664
#define SIG_OUTPUT_COMPARE1A _VECTOR(11)
666
/* Timer/Counter1 Compare Match B */
667
#define TIMER1_COMPB_vect _VECTOR(12)
668
#define SIG_OUTPUT_COMPARE1B _VECTOR(12)
670
/* Timer/Counter1 Overflow */
671
#define TIMER1_OVF_vect _VECTOR(13)
672
#define SIG_OVERFLOW1 _VECTOR(13)
674
/* TimerCounter0 Compare Match A */
675
#define TIMER0_COMPA_vect _VECTOR(14)
676
#define SIG_OUTPUT_COMPARE0A _VECTOR(14)
678
/* TimerCounter0 Compare Match B */
679
#define TIMER0_COMPB_vect _VECTOR(15)
680
#define SIG_OUTPUT_COMPARE0B _VECTOR(15)
682
/* Timer/Couner0 Overflow */
683
#define TIMER0_OVF_vect _VECTOR(16)
684
#define SIG_OVERFLOW0 _VECTOR(16)
686
/* SPI Serial Transfer Complete */
687
#define SPI_STC_vect _VECTOR(17)
688
#define SIG_SPI _VECTOR(17)
690
/* USART Rx Complete */
691
#define USART_RX_vect _VECTOR(18)
692
#define SIG_USART_RECV _VECTOR(18)
694
/* USART, Data Register Empty */
695
#define USART_UDRE_vect _VECTOR(19)
696
#define SIG_USART_DATA _VECTOR(19)
698
/* USART Tx Complete */
699
#define USART_TX_vect _VECTOR(20)
700
#define SIG_USART_TRANS _VECTOR(20)
702
/* ADC Conversion Complete */
703
#define ADC_vect _VECTOR(21)
704
#define SIG_ADC _VECTOR(21)
707
#define EE_READY_vect _VECTOR(22)
708
#define SIG_EEPROM_READY _VECTOR(22)
710
/* Analog Comparator */
711
#define ANALOG_COMP_vect _VECTOR(23)
712
#define SIG_COMPARATOR _VECTOR(23)
714
/* Two-wire Serial Interface */
715
#define TWI_vect _VECTOR(24)
716
#define SIG_TWI _VECTOR(24)
717
#define SIG_2WIRE_SERIAL _VECTOR(24)
719
/* Store Program Memory Read */
720
#define SPM_READY_vect _VECTOR(25)
721
#define SIG_SPM_READY _VECTOR(25)
646
723
/* The mega48 and mega88 vector tables are single instruction entries (16 bits
647
724
per entry for an RJMP) while the mega168 table has double instruction