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Viewing changes to src/sdk/resources/lexers/lexer_verilog.sample

  • Committer: Bazaar Package Importer
  • Author(s): Michael Casadevall
  • Date: 2008-07-17 04:39:23 UTC
  • Revision ID: james.westby@ubuntu.com-20080717043923-gmsy5cwkdjswghkm
Tags: upstream-8.02
Import upstream version 8.02

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src/sdk/resources/lexers/lexer_verilog.sample
 
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// D flip-flop
 
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module d_ff ( d, clk, q, q_bar);
 
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input d ,clk;
 
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output q, q_bar;
 
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wire d ,clk;
 
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reg q, q_bar;
 
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always @ (posedge clk)
 
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begin
 
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    q <= d;
 
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    q_bar <=  ! d;
 
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end
 
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endmodule
 
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// D flip-flop
 
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module d_ff ( d, clk, q, q_bar);
 
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input d ,clk;
 
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output q, q_bar;
 
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wire d ,clk;
 
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reg q, q_bar;
 
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always @ (posedge clk)
 
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begin
 
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    q <= d;
 
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    q_bar <=  ! d;
 
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end
 
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endmodule