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V1.01 08/31/99 teeny fix
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V1.00 08/31/99 Complete Version
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VRCVI (VRC6) (48 pin standard 600mil wide DIP)
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This chip is used in such games as Konami's CV3j and Madara. It's unique
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because it has some extra sound channels on it that get piped through the
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Famicom (note this is a fami-only chip and you will not find one in any
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NES game). "VI" of "VRCVI" is "6" for the roman numeral challenged.
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This chip generates its audio via a 6 bit R2R ladder. This is contained
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inside a 9 pin resistor network like so:
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/------*-\/\/-*-\/\/-*-\/\/-*-\/\/-*-\/\/-*------*-\/\/-\
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\ 6K \ 6K \ 6K \ 6K \ 6K \ 6K \ 6K | |
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GND D0 D1 D2 D3 D4 D5 Aud In Aud Out
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(s) means this pin connects to the System
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(r) this only connects to the ROM
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(w) this is a SRAM/WRAM connection only
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AUD : these pass to the resistor network
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CHR : these connect to the CHR ROM and/or fami's CHR pins
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PRG : these connect to the PRG ROM and/or fami's PRG pins
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WRAM : this hooks to the WRAM
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CIRAM : the RAM chip which is on the fami board
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AUD D1 - |02 47| - AUD D0
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AUD D3 - |03 46| - AUD D2
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AUD D5 - |04 45| - AUD D4
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(s) PRG A12 - |05 44| - PRG A16 (r)
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(s) PRG A14 - |06 43| - PRG A13 (s)
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(s) M2 - |07 42| - PRG A17 (r)
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(r) PRG A14 - |08 41| - PRG A15 (r)
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*1 (s) PRG A1 - |09 40| - PRG A13 (r)
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*1 (s) PRG A0 - |10 39| - PRG D7 (s)
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(s) PRG D0 - |11 38| - PRG D6 (s)
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(s) PRG D1 - |12 37| - PRG D5 (s)
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(s) PRG D2 - |13 36| - PRG D4 (s)
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(r) PRG /CE - |14 35| - PRG D3 (s)
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(s) R/W - |15 34| - PRG /CE (s)
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*2 (w) WRAM /CE - |16 33| - /IRQ (s)
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(r) CHR /CE - |17 32| - CIRAM /CE (s)
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(s) CHR /RD - |18 31| - CHR A10 (s)
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(s) CHR /A13 - |19 30| - CHR A11 (s)
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(r) CHR A16 - |20 29| - CHR A12 (s)
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(r) CHR A15 - |21 28| - CHR A17 (r)
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(r) CHR A12 - |22 27| - CHR A14 (r)
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(r) CHR A11 - |23 26| - CHR A13 (r)
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GND - |24 25| - CHR A10 (r)
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*1: On some VRCVI carts, these are reversed. This affects some registers.
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*2: This passes through a small pulse shaping network consisting of a
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resistor, diode, and cap.
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Registers: (sound related only)
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regs 9000-9002 are for pulse channel #1
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regs a000-a002 are for pulse channel #2
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regs b000-b002 are for the phase accumulator channel (sawtooth)
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(bits listed 7 through 0)
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000 - 1/16th ( 6.25%)
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001 - 2/16ths (12.50%)
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010 - 3/16ths (18.75%)
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011 - 4/16ths (25.00%)
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100 - 5/16ths (31.25%)
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101 - 6/16ths (37.50%)
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110 - 7/16ths (43.75%)
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111 - 8/16ths (50.00%)
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V - Volume bits. 0000b is silence, 1111b is loudest. Volume is
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linear. When in "normal" mode (see G bit), this acts as a general
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volume control register. When in "digitized" mode, these act as a
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G - Gate bit. 0=normal operation, 1=digitized. In digi operation,
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registers 9001h and 9002h are totally disabled. Only bits 0-3 of
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9000h are used. Whatever binary word is present here is passed on
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as a 4 bit digitized output.
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F - Lower 8 bits of frequency data
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X - Channel disable. 0=channel disabled, 1=channel enabled.
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F - Upper 4 bits of frequency data
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A000h-A002h are identical in operation to 9000h-9002h. One note: this chip
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will mix both digitized outputs (if the G bits are both set) into one
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added output. (see in-depth chip operation below)
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P - Phase accumulator input bits
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F - Lower 8 bits of frequency data
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X - Channel disable. 0=channel disabled, 1=channel enabled.
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F - Upper 4 bits of frequency data
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How the sounds are formed:
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--------------------------
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This chip is pretty cool. It outputs a 6 bit binary word for the sound
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which is passed through a DAC and finally to the NES/Fami. Because of this,
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the sound can be emulated *very* close to the original.
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I used my scope to figure all this out as well as my meter and logic probe
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so it should be 100% accurate.
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Block diagrams of the VRCVI: (as reverse engineered by me)
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----------------------------
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| F bits | | D bits| | V bits |
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| (12) | | (3) | | (4) |
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\___________/ \_______/ \________/
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+-----+ +----------------+ +-----------+ +------------+
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| OSC |-->|Divider (12 bit)|-->| Duty Cycle|-->| AND array |(4)> chan out
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|(M2) | | | | Generator | | |--/
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+-----+ +----------------+ +-----------+ +------------+
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One Pulse channel (both are identical)
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--------------------------------------
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How it works: The oscillator (in the NES, the clock arrives on the M2 line
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and is about 1.78Mhz) generates our starting frequency. This is passed
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first into a divide by 1 to 4096 divider to generate a base frequency.
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This is then passed to the duty cycle generator. The duty cycle generator
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generates the desired duty cycle for the output waveform. The "D" input
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controls the duty cycle generator's duty cycle. If the "G" bit is
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a "1", it forces the output of the duty cycle generator to a "1" also. If
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the "X" bit is "0", it forces the output of the duty cycle generator to "0",
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which effectively disables the channel. Note that this input has precidence
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The AND array is just that- an array of 4 AND gates. If the output of
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the duty cycle generator is a "0", then the "chan out" outputs will all be
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forced to "0". If the output of the duty cycle generator is a "1", then
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the chan out outputs will follow the V bit inputs.
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Note that the output of this generator is a 4 bit binary word.
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\___________/ \_______/
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+-----+ +----------------+ +-----------+
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| OSC |-->|Divider (12 bit)|-->| Phase |(5)> chan out
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|(M2) | | | |Accumulator|--/
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+-----+ +----------------+ +-----------+
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The Sawtooth (ramp) channel
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---------------------------
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This one is pretty similar to the above when it comes to frequency selection.
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The output frequency will be the same relative to the square wave channels.
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OK, the tough part will be explaining the phase accumulator. :-) What it is
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is just an adder tied to a latch. Every clock it adds a constant to the
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latch. In the case of the VRCVI, what you do is this:
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The ramp is generated over the course of 7 evenly spaced cycles, generated
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from the divider. Every clock from the divider causes the phase accumulator
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to add once. So... let's say we have 03h in the P bits. Every 7 cycles
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the phase accumulator (which is 8 bits) is reset to 00h.
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cycle: accumulator: chan out: notes:
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-----------------------------------------
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0 00h 00h On the first cycle, the acc. is reset to 0
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1 03h 00h We add 3 to 0 to get 3
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2 06h 00h We add 3 to 3 to get 6
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7 00h 00h Reset the acc. back to 0 and do it again
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This will look like so: (as viewed on an oscilloscope)
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012345601234560123456-+
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Note: if you enter a value that is too large (i.e. 30h) the accumulator
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*WILL WRAP*. Yes, this doesn't sound very good at all and you no longer
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The upper 5 bits of said accumulator are run to the "chan out" outputs.
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The lower 3 bits are not run anywhere.
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"X" disables the phase accumulator and forces all outputs to "0".
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Note that the output of this generator is a 5 bit word.
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Now that the actual sound generation is out of the way, here's how the
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channels are combined into the final 6 bit binary output:
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+---------+ +---------+ +---------+
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| 4 Bit |--\ | 5 Bit | /--|Sawtooth |
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| Binary |(5)>| Binary |<(5)|Generator|
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| Adder |--/ | Adder | \--| |
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+---------+ +---------+ +---------+
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The three channels are finally added together through a series of adders
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to produce the final output word. The two pulse chans are most likely added
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first since they are 4 bit words, and that 5 bit result is most likely
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added to the sawtooth's output. (The actual adding order is not known,
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but I can make a *very* good guess. The above illustrated way uses the least
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amount of transistors). In the end it does not matter the order in which
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the words are added; the final word will always be the same.
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The final 6 bit output word is run through an "R2R" resistor ladder which
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turns the digital bits into a 64 level analog representation. The ladder
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is binarally weighted and works like the DAC on your soundcard. :-)
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(so take heart emulator authours: just run the finished 6 bit word to
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your soundcard and it will sound right ;-).
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Frequency Generation:
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---------------------
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The chip generates all its output frequencies based on M2, which is
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colourburst divided by two (1789772.7272Hz). This signal is passed
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directly into the programmable dividers (the 12 bit frequency regs).
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These take the output of the programmable divider and then run it through
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the duty cycle generator, which in the process of generating the duty cycle,
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divides the frequency by 16.
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To calculate output frequency:
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Fout = ----------------
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This will tell you the exact frequency in Hz. (note that the * 16 is to
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compensate for the divide by 16 duty cycle generator.)
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This is similar to the above, however the duty cycle generator is replaced
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with a phase accumulator which divides the output frequency by 14.
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To calculate output frequency:
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Fout = ----------------
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This will tell you the exact frequency in Hz. (note that the * 14 is to
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compensate for the phase accumulator.)
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So how accurate is this info, anyways?
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--------------------------------------
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I believe the info to be 100% accurate. I have extensively tested the
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output of the actual VRCVI chip to this spec and everything fits perfectly.
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I did this by using a register dump and a QBASIC program I wrote which
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takes the register dump and produces a WAV file. All frequency and
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duty cycle measurements were taken with a Fluke 83 multimeter, and all
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waveform data was culled from my oscilloscope measuring the real chip.
added
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fceu/documentation/tech/exp/vrcvi.txt
