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skyeye_mach_s3c44b0.c - define machine s3c44b0 for skyeye
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Copyright (C) 2003 Skyeye Develop Group
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for help please send mail to <skyeye-developer@lists.gro.clinux.org>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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* 7/19/2003 init this file.
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* should be completed. who can do it?
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* walimis <wlm@student.dlut.edu.cn>
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//teawater add DBCT_TEST_SPEED 2005.10.04---------------------------------------
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//AJ2D--------------------------------------------------------------------------
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/* 2007-01-18 added by Anthony Lee : for new uart device frame */
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#include "skyeye_uart.h"
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void s3c44b0_io_write_word (ARMul_State * state, ARMword addr, ARMword data);
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ARMword s3c44b0_io_read_word (ARMul_State * state, ARMword addr);
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/* s3c44b0 Internal IO Registers
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typedef struct s3c44b0_io
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/*System Manager control */
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/*Interrupt Controller Registers */
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int tcmpb[TIMER_NUM]; /*timer5 has no tcmpb register. */
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int tcmp[TIMER_NUM]; /*timer5 has no tcmpb register. */
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int tcnto[TIMER_NUM];
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static s3c44b0_io_t s3c44b0_io;
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#define io s3c44b0_io
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#define ENABLE_IRQ ~io.intcon & 0x2
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#define ENABLE_FIQ ~io.intcon & 0x1
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s3c44b0_update_int (ARMul_State * state)
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ARMword requests = io.intpnd & (~io.intmsk & INT_MASK_INIT);
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state->NfiqSig = (requests & io.intmod) ? LOW : HIGH;
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state->NirqSig = (requests & ~io.intmod) ? LOW : HIGH;
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s3c44b0_set_interrupt (unsigned int irq)
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io.i_ispr = (1 << interrupt);
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if (ENABLE_IRQ | ENABLE_FIQ) {
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io.intpnd |= (1 << irq);
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s3c44b0_io_reset (ARMul_State * state)
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memset (&s3c44b0_io, 0, sizeof (s3c44b0_io));
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/*Interrupt register reset */
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io.intmsk = INT_MASK_INIT;
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io.i_pslv = 0x1b1b1b1b;
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io.i_pmst = 0x00001f1b;
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io.i_cslv = 0x1b1b1b1b;
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io.i_cmst = 0x0000001b;
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/*UART*/ io.utrstat0 = io.utrstat1 = 0x6;
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/* test timer register tcon's bit.
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timer_op (int n, int op)
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return TIMER_OP (io.tcon, n, op);
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if (n == 5 && op == TIMER_OP_RELOAD)
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return TIMER_OP (io.tcon, n + 1, op - 1);
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return TIMER_OP (io.tcon, n + 1, op);
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/* get timer interrupt num.
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get_timer_int (int i)
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return TIMER_INT (0);
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return TIMER_INT (1);
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return TIMER_INT (2);
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return TIMER_INT (3);
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return TIMER_INT (4);
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return TIMER_INT (5);
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/*s3c44b0 io_do_cycle*/
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s3c44b0_io_do_cycle (ARMul_State * state)
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for (i = 0; i < TIMER_NUM; i++) {
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if (timer_op (i, TIMER_OP_START)) {
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if (io.tcnt[i] > 0) {
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if (io.tcnt[i] == 0) {
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if (timer_op (i, TIMER_OP_RELOAD)) {
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io.tcnt[i] = io.tcntb[i];
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io.tcmp[i] = io.tcmpb[i];
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io.tcnto[i] = io.tcntb[i];
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s3c44b0_set_interrupt (get_timer_int
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s3c44b0_update_int (state);
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//s3c44b0_set_interrupt(get_timer_int(i));
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//s3c44b0_update_int(state);
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/*UART*/ if (!(io.intpnd & INT_URXD0) || !(io.intpnd & INT_URXD1)) {
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/* 2007-01-18 modified by Anthony Lee : for new uart device frame */
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if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0)
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io.urxh0 = io.urxh1 = (int) buf;
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io.utrstat0 |= UART_LSR_DR;
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io.utrstat1 |= UART_LSR_DR;
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if ((io.ucon0 & 0x3) == 0x1) {
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s3c44b0_set_interrupt (INT_URXD0);
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s3c44b0_update_int (state);
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if ((io.ucon1 & 0x3) == 0x1) {
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s3c44b0_set_interrupt (INT_URXD1);
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s3c44b0_update_int (state);
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// s3c44b0_update_int(state);
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s3c44b0_io_read_byte (ARMul_State * state, ARMword addr)
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s3c44b0_io_read_word (state, addr);
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/*printf("SKYEYE: s3c44b0_io_read_byte error\n");
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s3c44b0_io_read_halfword (ARMul_State * state, ARMword addr)
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s3c44b0_io_read_word (state, addr);
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/*printf("SKYEYE: s3c44b0_io_read_halfword error\n");
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s3c44b0_io_read_word (ARMul_State * state, ARMword addr)
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printf ("%s (addr = 0x%08x), pc:%x, NumInstrs:%x\n",
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__FUNCTION__, addr, state->pc, state->NumInstrs);
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//printf("instr:%x\n",state->loaded);
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/*find which interrupt is pending */
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for (i = 0; i < 26; i++) {
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if (io.intpnd & (1 << i))
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/*UART*/ case ULCON0:
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io.utrstat0 &= ~UART_LSR_DR;
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io.utrstat1 &= ~UART_LSR_DR;
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SKYEYE_DBG ("%s (addr = 0x%08x)\n", __FUNCTION__, addr);
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s3c44b0_io_write_byte (ARMul_State * state, ARMword addr, ARMword data)
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s3c44b0_io_write_word (state, addr, data);
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/*printf("SKYEYE: s3c44b0_io_write_byte error\n");
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s3c44b0_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data)
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s3c44b0_io_write_word (state, addr, data);
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printf ("SKYEYE: s3c44b0_io_write_halfword error\n");
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s3c44b0_io_write_word (ARMul_State * state, ARMword addr, ARMword data)
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io.intpnd &= (~data & INT_MASK_INIT);
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//s3c44b0_update_int(state);
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io.intpnd &= (~data & INT_MASK_INIT);
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//s3c44b0_update_int(state);
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/*UART*/ case ULCON0:
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/* 2007-01-18 modified by Anthony Lee : for new uart device frame */
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skyeye_uart_write(-1, &c, 1, NULL);
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io.utrstat0 |= UART_LSR_THRE | UART_LSR_TEMT;
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if ((io.ucon0 & 0xc) == 0x04) {
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s3c44b0_set_interrupt (INT_UTXD0);
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s3c44b0_update_int (state);
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for (i = 0; i < TIMER_NUM; i++) {
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rel = timer_op (i, TIMER_OP_MANUAL);
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//if(timer_op(i, TIMER_OP_MANUAL)){
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io.tcnt[i] = io.tcntb[i];
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io.tcmp[i] = io.tcmpb[i];
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io.tcnto[i] = io.tcntb[i];
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int n = (addr - TCNTB0) / 12;
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io.tcntb[n] = data * 480;
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int n = (addr - TCNTB0) / 12;
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io.tcntb[5] = data; //* 480;
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SKYEYE_DBG ("%s(0x%08x) = 0x%08x\n", __FUNCTION__, addr,
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s3c44b0_mach_init (ARMul_State * state, machine_config_t * this_mach)
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ARMul_SelectProcessor (state, ARM_v4_Prop);
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state->lateabtSig = HIGH;
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this_mach->mach_io_do_cycle = s3c44b0_io_do_cycle;
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this_mach->mach_io_reset = s3c44b0_io_reset;
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this_mach->mach_io_read_word = s3c44b0_io_read_word;
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this_mach->mach_io_read_halfword = s3c44b0_io_read_halfword;
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this_mach->mach_io_read_byte = s3c44b0_io_read_byte;
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this_mach->mach_io_write_word = s3c44b0_io_write_word;
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this_mach->mach_io_write_halfword = s3c44b0_io_write_halfword;
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this_mach->mach_io_write_byte = s3c44b0_io_write_byte;
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this_mach->mach_update_int = s3c44b0_update_int;
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/* 2007-01-28 : added by Anthony Lee */
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this_mach->state = (void *) state;
added
removed
arch/arm/mach/skyeye_mach_s3c44b0.c
