570
/* As a rule processors have APIC timer running in deep C states */
571
if (c->x86 > 0xf && !cpu_has_amd_erratum(amd_erratum_400))
572
set_cpu_cap(c, X86_FEATURE_ARAT);
575
* Disable GART TLB Walk Errors on Fam10h. We do this here
576
* because this is always needed when GART is enabled, even in a
577
* kernel which has no MCE support built in.
579
if (c->x86 == 0x10) {
581
* BIOS should disable GartTlbWlk Errors themself. If
582
* it doesn't do it here as suggested by the BKDG.
584
* Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
588
rdmsrl(MSR_AMD64_MCx_MASK(4), mask);
590
wrmsrl(MSR_AMD64_MCx_MASK(4), mask);
571
594
#ifdef CONFIG_X86_32
612
635
cpu_dev_register(amd_cpu_dev);
638
* AMD errata checking
640
* Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
641
* AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
642
* have an OSVW id assigned, which it takes as first argument. Both take a
643
* variable number of family-specific model-stepping ranges created by
644
* AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const
645
* int[] in arch/x86/include/asm/processor.h.
649
* const int amd_erratum_319[] =
650
* AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
651
* AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
652
* AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
655
const int amd_erratum_400[] =
656
AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
657
AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
660
bool cpu_has_amd_erratum(const int *erratum)
662
struct cpuinfo_x86 *cpu = ¤t_cpu_data;
663
int osvw_id = *erratum++;
668
* If called early enough that current_cpu_data hasn't been initialized
669
* yet, fall back to boot_cpu_data.
672
cpu = &boot_cpu_data;
674
if (cpu->x86_vendor != X86_VENDOR_AMD)
677
if (osvw_id >= 0 && osvw_id < 65536 &&
678
cpu_has(cpu, X86_FEATURE_OSVW)) {
681
rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
682
if (osvw_id < osvw_len) {
685
rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
687
return osvw_bits & (1ULL << (osvw_id & 0x3f));
691
/* OSVW unavailable or ID unknown, match family-model-stepping range */
692
ms = (cpu->x86_model << 4) | cpu->x86_mask;
693
while ((range = *erratum++))
694
if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
695
(ms >= AMD_MODEL_RANGE_START(range)) &&
696
(ms <= AMD_MODEL_RANGE_END(range)))