506
506
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
507
507
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
509
#define ICH_PMBASE 0x40
510
#define ICH_ACPI_CNTL 0x44
511
#define ICH4_ACPI_EN 0x10
512
#define ICH6_ACPI_EN 0x80
513
#define ICH4_GPIOBASE 0x58
514
#define ICH4_GPIO_CNTL 0x5c
515
#define ICH4_GPIO_EN 0x10
516
#define ICH6_GPIOBASE 0x48
517
#define ICH6_GPIO_CNTL 0x4c
518
#define ICH6_GPIO_EN 0x10
510
521
* ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
511
522
* 0x40 (128 bytes of ACPI, GPIO & TCO registers)
514
525
static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
518
pci_read_config_dword(dev, 0x40, ®ion);
519
quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
521
pci_read_config_dword(dev, 0x58, ®ion);
522
quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
531
* The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
532
* with low legacy (and fixed) ports. We don't know the decoding
533
* priority and can't tell whether the legacy device or the one created
534
* here is really at that address. This happens on boards with broken
538
pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
539
if (enable & ICH4_ACPI_EN) {
540
pci_read_config_dword(dev, ICH_PMBASE, ®ion);
541
region &= PCI_BASE_ADDRESS_IO_MASK;
542
if (region >= PCIBIOS_MIN_IO)
543
quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
544
"ICH4 ACPI/GPIO/TCO");
547
pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
548
if (enable & ICH4_GPIO_EN) {
549
pci_read_config_dword(dev, ICH4_GPIOBASE, ®ion);
550
region &= PCI_BASE_ADDRESS_IO_MASK;
551
if (region >= PCIBIOS_MIN_IO)
552
quirk_io_region(dev, region, 64,
553
PCI_BRIDGE_RESOURCES + 1, "ICH4 GPIO");
524
556
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
525
557
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
535
567
static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
539
pci_read_config_dword(dev, 0x40, ®ion);
540
quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
542
pci_read_config_dword(dev, 0x48, ®ion);
543
quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
572
pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
573
if (enable & ICH6_ACPI_EN) {
574
pci_read_config_dword(dev, ICH_PMBASE, ®ion);
575
region &= PCI_BASE_ADDRESS_IO_MASK;
576
if (region >= PCIBIOS_MIN_IO)
577
quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
578
"ICH6 ACPI/GPIO/TCO");
581
pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
582
if (enable & ICH4_GPIO_EN) {
583
pci_read_config_dword(dev, ICH6_GPIOBASE, ®ion);
584
region &= PCI_BASE_ADDRESS_IO_MASK;
585
if (region >= PCIBIOS_MIN_IO)
586
quirk_io_region(dev, region, 64,
587
PCI_BRIDGE_RESOURCES + 1, "ICH6 GPIO");
546
591
static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
2496
2541
#endif /* CONFIG_PCI_MSI */
2498
#ifdef CONFIG_PCI_IOV
2501
* For Intel 82576 SR-IOV NIC, if BIOS doesn't allocate resources for the
2502
* SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the
2503
* old Flash Memory Space.
2505
static void __devinit quirk_i82576_sriov(struct pci_dev *dev)
2508
u32 bar, start, size;
2510
if (PAGE_SIZE > 0x10000)
2513
flags = pci_resource_flags(dev, 0);
2514
if ((flags & PCI_BASE_ADDRESS_SPACE) !=
2515
PCI_BASE_ADDRESS_SPACE_MEMORY ||
2516
(flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) !=
2517
PCI_BASE_ADDRESS_MEM_TYPE_32)
2520
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
2524
pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar);
2525
if (bar & PCI_BASE_ADDRESS_MEM_MASK)
2528
start = pci_resource_start(dev, 1);
2529
size = pci_resource_len(dev, 1);
2530
if (!start || size != 0x400000 || start & (size - 1))
2533
pci_resource_flags(dev, 1) = 0;
2534
pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
2535
pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start);
2536
pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2);
2538
dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n");
2540
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov);
2541
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov);
2542
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov);
2543
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e8, quirk_i82576_sriov);
2544
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150a, quirk_i82576_sriov);
2545
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150d, quirk_i82576_sriov);
2546
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1518, quirk_i82576_sriov);
2548
#endif /* CONFIG_PCI_IOV */
2550
2543
static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2551
2544
struct pci_fixup *end)