2
* (C) Copyright 2007-2009 DENX Software Engineering
4
* See file CREDITS for list of people who contributed to this
7
* This program is free software; you can redistribute it and/or
8
* modify it under the terms of the GNU General Public License as
9
* published by the Free Software Foundation; either version 2 of
10
* the License, or (at your option) any later version.
12
* This program is distributed in the hope that it will be useful,
13
* but WITHOUT ANY WARRANTY; without even the implied warranty of
14
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15
* GNU General Public License for more details.
17
* You should have received a copy of the GNU General Public License
18
* along with this program; if not, write to the Free Software
19
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24
* MPC5121ADS board configuration file
30
#define CONFIG_MPC5121ADS 1
32
* Memory map for the MPC5121ADS board:
34
* 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
35
* 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
36
* 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
37
* 0x8200_0000 - 0x8200_001F CPLD (32 B)
38
* 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB)
39
* 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB)
40
* 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
41
* 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
45
* High Level Configuration Options
47
#define CONFIG_E300 1 /* E300 Family */
48
#define CONFIG_MPC512X 1 /* MPC512X family */
49
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
50
#undef CONFIG_FSL_DIU_LOGO_BMP /* Don't include FSL DIU binary bmp */
55
#if defined(CONFIG_VIDEO)
56
#define CONFIG_CFB_CONSOLE
57
#define CONFIG_VGA_AS_SINGLE_DEVICE
60
/* CONFIG_PCI is defined at config time */
62
#ifdef CONFIG_MPC5121ADS_REV2
63
#define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */
65
#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
69
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
70
#define CONFIG_MISC_INIT_R
72
#define CONFIG_SYS_IMMR 0x80000000
73
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
75
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
76
#define CONFIG_SYS_MEMTEST_END 0x00400000
79
* DDR Setup - manually set all parameters as there's no SPD etc.
81
#ifdef CONFIG_MPC5121ADS_REV2
82
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
84
#define CONFIG_SYS_DDR_SIZE 512 /* MB */
86
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
87
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
89
/* DDR Controller Configuration
92
* [31:31] MDDRC Soft Reset: Diabled
93
* [30:30] DRAM CKE pin: Enabled
94
* [29:29] DRAM CLK: Enabled
95
* [28:28] Command Mode: Enabled (For initialization only)
96
* [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
97
* [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
98
* [20:19] Read Test: DON'T USE
99
* [18:18] Self Refresh: Enabled
100
* [17:17] 16bit Mode: Disabled
101
* [16:13] Ready Delay: 2
102
* [12:12] Half DQS Delay: Disabled
103
* [11:11] Quarter DQS Delay: Disabled
104
* [10:08] Write Delay: 2
105
* [07:07] Early ODT: Disabled
106
* [06:06] On DIE Termination: Disabled
107
* [05:05] FIFO Overflow Clear: DON'T USE here
108
* [04:04] FIFO Underflow Clear: DON'T USE here
109
* [03:03] FIFO Overflow Pending: DON'T USE here
110
* [02:02] FIFO Underlfow Pending: DON'T USE here
111
* [01:01] FIFO Overlfow Enabled: Enabled
112
* [00:00] FIFO Underflow Enabled: Enabled
114
* [31:16] DRAM Refresh Time: 0 CSB clocks
115
* [15:8] DRAM Command Time: 0 CSB clocks
116
* [07:00] DRAM Precharge Time: 0 CSB clocks
120
* [20:17] DRAM tWRT1:
127
* [22:19] DRAM tRTW1:
133
#ifdef CONFIG_MPC5121ADS_REV2
134
#define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00
135
#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00
136
#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168
137
#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864
139
#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00
140
#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00
141
#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
142
#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
144
#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
145
#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E
146
#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E
148
#define CONFIG_SYS_MICRON_NOP 0x01380000
149
#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400
150
#define CONFIG_SYS_MICRON_EM2 0x01020000
151
#define CONFIG_SYS_MICRON_EM3 0x01030000
152
#define CONFIG_SYS_MICRON_EN_DLL 0x01010000
153
#define CONFIG_SYS_MICRON_RFSH 0x01080000
154
#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
155
#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780
157
/* DDR Priority Manager Configuration */
158
#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
159
#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
160
#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
161
#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
162
#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
163
#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
164
#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
165
#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
166
#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
167
#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
168
#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
169
#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
170
#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
171
#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
172
#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
173
#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
174
#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
175
#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
176
#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
177
#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
178
#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
179
#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
180
#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
183
* NOR FLASH on the Local Bus
185
#undef CONFIG_BKUP_FLASH
186
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
187
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
188
#ifdef CONFIG_BKUP_FLASH
189
#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
190
#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* max flash size in bytes */
192
#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */
193
#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size in bytes */
195
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
196
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
197
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
198
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
200
#undef CONFIG_SYS_FLASH_CHECKSUM
204
* drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
206
#define CONFIG_CMD_NAND /* enable NAND support */
207
#define CONFIG_JFFS2_NAND /* with JFFS2 on it */
208
#define CONFIG_NAND_MPC5121_NFC
209
#define CONFIG_SYS_NAND_BASE 0x40000000
211
#define CONFIG_SYS_MAX_NAND_DEVICE 2
212
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
213
#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
215
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
218
* Configuration parameters for MPC5121 NAND driver
220
#define CONFIG_FSL_NFC_WIDTH 1
221
#define CONFIG_FSL_NFC_WRITE_SIZE 2048
222
#define CONFIG_FSL_NFC_SPARE_SIZE 64
223
#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
226
* CPLD registers area is really only 32 bytes in size, but the smallest possible LP
229
#define CONFIG_SYS_CPLD_BASE 0x82000000
230
#define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */
232
#define CONFIG_SYS_SRAM_BASE 0x30000000
233
#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
235
#define CONFIG_SYS_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
236
#define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
237
#define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */
239
/* Use SRAM for initial stack */
240
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */
241
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE /* End of used area in RAM */
243
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
244
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
245
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
247
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */
248
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
249
#ifdef CONFIG_FSL_DIU_FB
250
#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
252
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
258
#define CONFIG_CONS_INDEX 1
259
#undef CONFIG_SERIAL_SOFTWARE_FIFO
262
* Serial console configuration
264
#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
265
#if CONFIG_PSC_CONSOLE != 3
266
#error CONFIG_PSC_CONSOLE must be 3
268
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
269
#define CONFIG_SYS_BAUDRATE_TABLE \
270
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
272
#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
273
#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
274
#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
275
#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
277
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
278
/* Use the HUSH parser */
279
#define CONFIG_SYS_HUSH_PARSER
280
#ifdef CONFIG_SYS_HUSH_PARSER
281
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
292
#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
293
#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
294
#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
295
#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
296
#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
297
#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
298
#define CONFIG_SYS_PCI_IO_BASE 0x00000000
299
#define CONFIG_SYS_PCI_IO_PHYS 0x84000000
300
#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
303
#define CONFIG_PCI_PNP /* do pci plug-and-play */
305
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
310
#define CONFIG_HARD_I2C /* I2C with hardware support */
311
#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
312
#define CONFIG_I2C_MULTI_BUS
313
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
314
#define CONFIG_SYS_I2C_SLAVE 0x7F
316
#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
320
* IIM - IC Identification Module
325
* EEPROM configuration
327
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
328
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
329
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
330
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
333
* Ethernet configuration
335
#define CONFIG_MPC512x_FEC 1
336
#define CONFIG_NET_MULTI
337
#define CONFIG_PHY_ADDR 0x1
338
#define CONFIG_MII 1 /* MII PHY management */
339
#define CONFIG_FEC_AN_TIMEOUT 1
340
#define CONFIG_HAS_ETH0
343
* Configure on-board RTC
345
#define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */
346
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
351
#define CONFIG_ENV_IS_IN_FLASH 1
352
/* This has to be a multiple of the Flash sector size */
353
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
354
#define CONFIG_ENV_SIZE 0x2000
355
#ifdef CONFIG_BKUP_FLASH
356
#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */
358
#define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
361
/* Address and size of Redundant Environment Sector */
362
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
363
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
365
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
366
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
368
#include <config_cmd_default.h>
370
#define CONFIG_CMD_ASKENV
371
#define CONFIG_CMD_DATE
372
#define CONFIG_CMD_DHCP
373
#define CONFIG_CMD_EEPROM
374
#define CONFIG_CMD_EXT2
375
#define CONFIG_CMD_I2C
376
#define CONFIG_CMD_IDE
377
#define CONFIG_CMD_JFFS2
378
#define CONFIG_CMD_MII
379
#define CONFIG_CMD_NFS
380
#define CONFIG_CMD_PING
381
#define CONFIG_CMD_REGINFO
383
#undef CONFIG_CMD_FUSE
385
#if defined(CONFIG_PCI)
386
#define CONFIG_CMD_PCI
390
* Dynamic MTD partition support
392
#define CONFIG_CMD_MTDPARTS
393
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
394
#define CONFIG_FLASH_CFI_MTD
395
#define MTDIDS_DEFAULT "nor0=fc000000.flash,nand0=mpc5121.nand"
400
* FC000000 - FEABFFFF 42.75 MiB User Data
401
* FEAC0000 - FFABFFFF 16 MiB Root File System
402
* FFAC0000 - FFEBFFFF 4 MiB Linux Kernel
403
* FFEC0000 - FFEFFFFF 256 KiB Device Tree
404
* FFF00000 - FFFFFFFF 1 MiB U-Boot (up to 512 KiB) and 2 x * env
406
* NAND flash layout: one big partition
408
#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:43776k(user)," \
413
"mpc5121.nand:-(data)"
416
#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
417
#define CONFIG_DOS_PARTITION
418
#define CONFIG_MAC_PARTITION
419
#define CONFIG_ISO_PARTITION
420
#endif /* defined(CONFIG_CMD_IDE) */
423
* Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
424
* For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
425
* to 0xFFFF, watchdog timeouts after about 64s. For details refer
426
* to chapter 36 of the MPC5121e Reference Manual.
428
/* #define CONFIG_WATCHDOG */ /* enable watchdog */
429
#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
432
* Miscellaneous configurable options
434
#define CONFIG_SYS_LONGHELP /* undef to save memory */
435
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
436
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
438
#ifdef CONFIG_CMD_KGDB
439
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
441
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
445
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
446
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
447
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
448
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
451
* For booting Linux, the board info and command line data
452
* have to be in the first 8 MB of memory, since this is
453
* the maximum mapped by the Linux kernel during initialization.
455
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
457
/* Cache Configuration */
458
#define CONFIG_SYS_DCACHE_SIZE 32768
459
#define CONFIG_SYS_CACHELINE_SIZE 32
460
#ifdef CONFIG_CMD_KGDB
461
#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
464
#define CONFIG_SYS_HID0_INIT 0x000000000
465
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
466
#define CONFIG_SYS_HID2 HID2_HBE
468
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
471
* Internal Definitions
475
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
476
#define BOOTFLAG_WARM 0x02 /* Software reboot */
478
#ifdef CONFIG_CMD_KGDB
479
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
480
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
484
* Environment Configuration
486
#define CONFIG_TIMESTAMP
488
#define CONFIG_HOSTNAME mpc5121ads
489
#define CONFIG_BOOTFILE mpc5121ads/uImage
490
#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
492
#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
494
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
495
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
497
#define CONFIG_BAUDRATE 115200
499
#define CONFIG_PREBOOT "echo;" \
500
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
503
#define CONFIG_EXTRA_ENV_SETTINGS \
504
"u-boot_addr_r=200000\0" \
505
"kernel_addr_r=600000\0" \
506
"fdt_addr_r=880000\0" \
507
"ramdisk_addr_r=900000\0" \
508
"u-boot_addr=FFF00000\0" \
509
"kernel_addr=FFAC0000\0" \
510
"fdt_addr=FFEC0000\0" \
511
"ramdisk_addr=FEAC0000\0" \
512
"ramdiskfile=mpc5121ads/uRamdisk\0" \
513
"u-boot=mpc5121ads/u-boot.bin\0" \
514
"bootfile=mpc5121ads/uImage\0" \
515
"fdtfile=mpc5121ads/mpc5121ads.dtb\0" \
516
"rootpath=/opt/eldk/ppc_6xx\n" \
518
"consdev=ttyPSC0\0" \
519
"nfsargs=setenv bootargs root=/dev/nfs rw " \
520
"nfsroot=${serverip}:${rootpath}\0" \
521
"ramargs=setenv bootargs root=/dev/ram rw\0" \
522
"addip=setenv bootargs ${bootargs} " \
523
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
524
":${hostname}:${netdev}:off panic=1\0" \
525
"addtty=setenv bootargs ${bootargs} " \
526
"console=${consdev},${baudrate}\0" \
527
"flash_nfs=run nfsargs addip addtty;" \
528
"bootm ${kernel_addr} - ${fdt_addr}\0" \
529
"flash_self=run ramargs addip addtty;" \
530
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
531
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
532
"tftp ${fdt_addr_r} ${fdtfile};" \
533
"run nfsargs addip addtty;" \
534
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
535
"net_self=tftp ${kernel_addr_r} ${bootfile};" \
536
"tftp ${ramdisk_addr_r} ${ramdiskfile};" \
537
"tftp ${fdt_addr_r} ${fdtfile};" \
538
"run ramargs addip addtty;" \
539
"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
540
"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
541
"update=protect off ${u-boot_addr} +${filesize};" \
542
"era ${u-boot_addr} +${filesize};" \
543
"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
544
"upd=run load update\0" \
547
#define CONFIG_BOOTCOMMAND "run flash_self"
549
#define CONFIG_OF_LIBFDT 1
550
#define CONFIG_OF_BOARD_SETUP 1
551
#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
553
#define OF_CPU "PowerPC,5121@0"
554
#define OF_SOC_COMPAT "fsl,mpc5121-immr"
555
#define OF_TBCLK (bd->bi_busfreq / 4)
556
#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
558
/*-----------------------------------------------------------------------
560
*-----------------------------------------------------------------------
563
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
564
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
565
#undef CONFIG_IDE_LED /* LED for IDE not supported */
567
#define CONFIG_IDE_RESET /* reset for IDE supported */
568
#define CONFIG_IDE_PREINIT
570
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
571
#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
573
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
574
#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base()
576
/* Offset for data I/O RefMan MPC5121EE Table 28-10 */
577
#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
579
/* Offset for normal register accesses */
580
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
582
/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
583
#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
585
/* Interval between registers */
586
#define CONFIG_SYS_ATA_STRIDE 4
588
#define ATA_BASE_ADDR get_pata_base()
591
* Control register bit definitions
593
#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
594
#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
595
#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
596
#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
597
#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
598
#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
599
#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
600
#define FSL_ATA_CTRL_IORDY_EN 0x01000000
602
#endif /* __CONFIG_H */
added
removed
include/configs/mpc5121ads.h
