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// ------------------------------------------------------------------
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// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice appear in all copies.
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// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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// ------------------------------------------------------------------
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//===================================================================
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// Author(s): ="Atheros"
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//===================================================================
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#ifndef _MBOX_WLAN_HOST_REG_REG_H_
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#define _MBOX_WLAN_HOST_REG_REG_H_
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#define HOST_INT_STATUS_ADDRESS 0x00000400
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#define HOST_INT_STATUS_OFFSET 0x00000400
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#define HOST_INT_STATUS_ERROR_MSB 7
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#define HOST_INT_STATUS_ERROR_LSB 7
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#define HOST_INT_STATUS_ERROR_MASK 0x00000080
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#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
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#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
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#define HOST_INT_STATUS_CPU_MSB 6
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#define HOST_INT_STATUS_CPU_LSB 6
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#define HOST_INT_STATUS_CPU_MASK 0x00000040
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#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
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#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
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#define HOST_INT_STATUS_INT_MSB 5
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#define HOST_INT_STATUS_INT_LSB 5
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#define HOST_INT_STATUS_INT_MASK 0x00000020
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#define HOST_INT_STATUS_INT_GET(x) (((x) & HOST_INT_STATUS_INT_MASK) >> HOST_INT_STATUS_INT_LSB)
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#define HOST_INT_STATUS_INT_SET(x) (((x) << HOST_INT_STATUS_INT_LSB) & HOST_INT_STATUS_INT_MASK)
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#define HOST_INT_STATUS_COUNTER_MSB 4
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#define HOST_INT_STATUS_COUNTER_LSB 4
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#define HOST_INT_STATUS_COUNTER_MASK 0x00000010
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#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
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#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
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#define HOST_INT_STATUS_MBOX_DATA_MSB 3
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#define HOST_INT_STATUS_MBOX_DATA_LSB 0
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#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f
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#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
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#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
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#define CPU_INT_STATUS_ADDRESS 0x00000401
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#define CPU_INT_STATUS_OFFSET 0x00000401
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#define CPU_INT_STATUS_BIT_MSB 7
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#define CPU_INT_STATUS_BIT_LSB 0
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#define CPU_INT_STATUS_BIT_MASK 0x000000ff
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#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
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#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
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#define ERROR_INT_STATUS_ADDRESS 0x00000402
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#define ERROR_INT_STATUS_OFFSET 0x00000402
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#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MSB 6
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#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB 6
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#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040
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#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB)
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#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK)
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#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MSB 5
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#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB 5
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#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020
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#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB)
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#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK)
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#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MSB 4
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#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB 4
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#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010
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#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB)
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#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK)
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#define ERROR_INT_STATUS_SPI_MSB 3
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#define ERROR_INT_STATUS_SPI_LSB 3
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#define ERROR_INT_STATUS_SPI_MASK 0x00000008
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#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
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#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
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#define ERROR_INT_STATUS_WAKEUP_MSB 2
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#define ERROR_INT_STATUS_WAKEUP_LSB 2
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#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
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#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
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#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
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#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1
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#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
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#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
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#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
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#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
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#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0
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#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
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#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
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#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
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#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
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#define COUNTER_INT_STATUS_ADDRESS 0x00000403
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#define COUNTER_INT_STATUS_OFFSET 0x00000403
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#define COUNTER_INT_STATUS_COUNTER_MSB 7
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#define COUNTER_INT_STATUS_COUNTER_LSB 0
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#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
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#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
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#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
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#define MBOX_FRAME_ADDRESS 0x00000404
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#define MBOX_FRAME_OFFSET 0x00000404
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#define MBOX_FRAME_RX_EOM_MSB 7
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#define MBOX_FRAME_RX_EOM_LSB 4
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#define MBOX_FRAME_RX_EOM_MASK 0x000000f0
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#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
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#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
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#define MBOX_FRAME_RX_SOM_MSB 3
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#define MBOX_FRAME_RX_SOM_LSB 0
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#define MBOX_FRAME_RX_SOM_MASK 0x0000000f
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#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
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#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
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#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405
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#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405
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#define RX_LOOKAHEAD_VALID_MBOX_MSB 3
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#define RX_LOOKAHEAD_VALID_MBOX_LSB 0
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#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f
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#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
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#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
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#define HOST_INT_STATUS2_ADDRESS 0x00000406
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#define HOST_INT_STATUS2_OFFSET 0x00000406
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#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MSB 2
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#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB 2
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#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK 0x00000004
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#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB)
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#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK)
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#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MSB 1
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#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB 1
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#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK 0x00000002
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#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB)
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#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK)
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#define HOST_INT_STATUS2_GMBOX_DATA_MSB 0
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#define HOST_INT_STATUS2_GMBOX_DATA_LSB 0
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#define HOST_INT_STATUS2_GMBOX_DATA_MASK 0x00000001
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#define HOST_INT_STATUS2_GMBOX_DATA_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_DATA_MASK) >> HOST_INT_STATUS2_GMBOX_DATA_LSB)
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#define HOST_INT_STATUS2_GMBOX_DATA_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_DATA_LSB) & HOST_INT_STATUS2_GMBOX_DATA_MASK)
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#define GMBOX_RX_AVAIL_ADDRESS 0x00000407
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#define GMBOX_RX_AVAIL_OFFSET 0x00000407
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#define GMBOX_RX_AVAIL_BYTE_MSB 6
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#define GMBOX_RX_AVAIL_BYTE_LSB 0
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#define GMBOX_RX_AVAIL_BYTE_MASK 0x0000007f
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#define GMBOX_RX_AVAIL_BYTE_GET(x) (((x) & GMBOX_RX_AVAIL_BYTE_MASK) >> GMBOX_RX_AVAIL_BYTE_LSB)
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#define GMBOX_RX_AVAIL_BYTE_SET(x) (((x) << GMBOX_RX_AVAIL_BYTE_LSB) & GMBOX_RX_AVAIL_BYTE_MASK)
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#define RX_LOOKAHEAD0_ADDRESS 0x00000408
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#define RX_LOOKAHEAD0_OFFSET 0x00000408
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#define RX_LOOKAHEAD0_DATA_MSB 7
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#define RX_LOOKAHEAD0_DATA_LSB 0
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#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff
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#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
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#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
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#define RX_LOOKAHEAD1_ADDRESS 0x0000040c
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#define RX_LOOKAHEAD1_OFFSET 0x0000040c
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#define RX_LOOKAHEAD1_DATA_MSB 7
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#define RX_LOOKAHEAD1_DATA_LSB 0
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#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff
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#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
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#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
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#define RX_LOOKAHEAD2_ADDRESS 0x00000410
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#define RX_LOOKAHEAD2_OFFSET 0x00000410
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#define RX_LOOKAHEAD2_DATA_MSB 7
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#define RX_LOOKAHEAD2_DATA_LSB 0
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#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff
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#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
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#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
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#define RX_LOOKAHEAD3_ADDRESS 0x00000414
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#define RX_LOOKAHEAD3_OFFSET 0x00000414
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#define RX_LOOKAHEAD3_DATA_MSB 7
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#define RX_LOOKAHEAD3_DATA_LSB 0
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#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff
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#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
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#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
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#define INT_STATUS_ENABLE_ADDRESS 0x00000418
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#define INT_STATUS_ENABLE_OFFSET 0x00000418
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#define INT_STATUS_ENABLE_ERROR_MSB 7
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#define INT_STATUS_ENABLE_ERROR_LSB 7
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#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080
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#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
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#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
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#define INT_STATUS_ENABLE_CPU_MSB 6
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#define INT_STATUS_ENABLE_CPU_LSB 6
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#define INT_STATUS_ENABLE_CPU_MASK 0x00000040
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#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
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#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
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#define INT_STATUS_ENABLE_INT_MSB 5
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#define INT_STATUS_ENABLE_INT_LSB 5
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#define INT_STATUS_ENABLE_INT_MASK 0x00000020
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#define INT_STATUS_ENABLE_INT_GET(x) (((x) & INT_STATUS_ENABLE_INT_MASK) >> INT_STATUS_ENABLE_INT_LSB)
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#define INT_STATUS_ENABLE_INT_SET(x) (((x) << INT_STATUS_ENABLE_INT_LSB) & INT_STATUS_ENABLE_INT_MASK)
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#define INT_STATUS_ENABLE_COUNTER_MSB 4
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#define INT_STATUS_ENABLE_COUNTER_LSB 4
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#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
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#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
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#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
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#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3
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#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0
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#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
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#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
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#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
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#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419
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#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419
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#define CPU_INT_STATUS_ENABLE_BIT_MSB 7
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#define CPU_INT_STATUS_ENABLE_BIT_LSB 0
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#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
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#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
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#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
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#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a
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#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a
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#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MSB 6
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#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB 6
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#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040
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#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB)
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#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK)
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#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MSB 5
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#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB 5
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#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020
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#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB)
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#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK)
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#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MSB 4
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#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB 4
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#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010
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#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB)
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#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK)
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#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2
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#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2
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#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004
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#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
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#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
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#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1
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#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
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#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
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#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
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#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
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#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0
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#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
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#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
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#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
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#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
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#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b
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#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b
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#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7
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#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
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#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
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#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
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#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
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#define COUNT_ADDRESS 0x00000420
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#define COUNT_OFFSET 0x00000420
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#define COUNT_VALUE_MSB 7
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#define COUNT_VALUE_LSB 0
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#define COUNT_VALUE_MASK 0x000000ff
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#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
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#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
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#define COUNT_DEC_ADDRESS 0x00000440
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#define COUNT_DEC_OFFSET 0x00000440
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#define COUNT_DEC_VALUE_MSB 7
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#define COUNT_DEC_VALUE_LSB 0
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#define COUNT_DEC_VALUE_MASK 0x000000ff
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#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
279
#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
281
#define SCRATCH_ADDRESS 0x00000460
282
#define SCRATCH_OFFSET 0x00000460
283
#define SCRATCH_VALUE_MSB 7
284
#define SCRATCH_VALUE_LSB 0
285
#define SCRATCH_VALUE_MASK 0x000000ff
286
#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
287
#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
289
#define FIFO_TIMEOUT_ADDRESS 0x00000468
290
#define FIFO_TIMEOUT_OFFSET 0x00000468
291
#define FIFO_TIMEOUT_VALUE_MSB 7
292
#define FIFO_TIMEOUT_VALUE_LSB 0
293
#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff
294
#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
295
#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
297
#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469
298
#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469
299
#define FIFO_TIMEOUT_ENABLE_SET_MSB 0
300
#define FIFO_TIMEOUT_ENABLE_SET_LSB 0
301
#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001
302
#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
303
#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
305
#define DISABLE_SLEEP_ADDRESS 0x0000046a
306
#define DISABLE_SLEEP_OFFSET 0x0000046a
307
#define DISABLE_SLEEP_FOR_INT_MSB 1
308
#define DISABLE_SLEEP_FOR_INT_LSB 1
309
#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002
310
#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
311
#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
312
#define DISABLE_SLEEP_ON_MSB 0
313
#define DISABLE_SLEEP_ON_LSB 0
314
#define DISABLE_SLEEP_ON_MASK 0x00000001
315
#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
316
#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
318
#define LOCAL_BUS_ADDRESS 0x00000470
319
#define LOCAL_BUS_OFFSET 0x00000470
320
#define LOCAL_BUS_STATE_MSB 1
321
#define LOCAL_BUS_STATE_LSB 0
322
#define LOCAL_BUS_STATE_MASK 0x00000003
323
#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
324
#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
326
#define INT_WLAN_ADDRESS 0x00000472
327
#define INT_WLAN_OFFSET 0x00000472
328
#define INT_WLAN_VECTOR_MSB 7
329
#define INT_WLAN_VECTOR_LSB 0
330
#define INT_WLAN_VECTOR_MASK 0x000000ff
331
#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
332
#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
334
#define WINDOW_DATA_ADDRESS 0x00000474
335
#define WINDOW_DATA_OFFSET 0x00000474
336
#define WINDOW_DATA_DATA_MSB 7
337
#define WINDOW_DATA_DATA_LSB 0
338
#define WINDOW_DATA_DATA_MASK 0x000000ff
339
#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
340
#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
342
#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478
343
#define WINDOW_WRITE_ADDR_OFFSET 0x00000478
344
#define WINDOW_WRITE_ADDR_ADDR_MSB 7
345
#define WINDOW_WRITE_ADDR_ADDR_LSB 0
346
#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff
347
#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
348
#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
350
#define WINDOW_READ_ADDR_ADDRESS 0x0000047c
351
#define WINDOW_READ_ADDR_OFFSET 0x0000047c
352
#define WINDOW_READ_ADDR_ADDR_MSB 7
353
#define WINDOW_READ_ADDR_ADDR_LSB 0
354
#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff
355
#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
356
#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
358
#define HOST_CTRL_SPI_CONFIG_ADDRESS 0x00000480
359
#define HOST_CTRL_SPI_CONFIG_OFFSET 0x00000480
360
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MSB 4
361
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB 4
362
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK 0x00000010
363
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK) >> HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB)
364
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK)
365
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MSB 3
366
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB 3
367
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008
368
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB)
369
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK)
370
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MSB 2
371
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB 2
372
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK 0x00000004
373
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK) >> HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB)
374
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK)
375
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MSB 1
376
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB 0
377
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK 0x00000003
378
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK) >> HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB)
379
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK)
381
#define HOST_CTRL_SPI_STATUS_ADDRESS 0x00000481
382
#define HOST_CTRL_SPI_STATUS_OFFSET 0x00000481
383
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MSB 3
384
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB 3
385
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK 0x00000008
386
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB)
387
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK)
388
#define HOST_CTRL_SPI_STATUS_RD_ERR_MSB 2
389
#define HOST_CTRL_SPI_STATUS_RD_ERR_LSB 2
390
#define HOST_CTRL_SPI_STATUS_RD_ERR_MASK 0x00000004
391
#define HOST_CTRL_SPI_STATUS_RD_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK) >> HOST_CTRL_SPI_STATUS_RD_ERR_LSB)
392
#define HOST_CTRL_SPI_STATUS_RD_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_RD_ERR_LSB) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK)
393
#define HOST_CTRL_SPI_STATUS_WR_ERR_MSB 1
394
#define HOST_CTRL_SPI_STATUS_WR_ERR_LSB 1
395
#define HOST_CTRL_SPI_STATUS_WR_ERR_MASK 0x00000002
396
#define HOST_CTRL_SPI_STATUS_WR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_WR_ERR_LSB)
397
#define HOST_CTRL_SPI_STATUS_WR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_WR_ERR_LSB) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK)
398
#define HOST_CTRL_SPI_STATUS_READY_MSB 0
399
#define HOST_CTRL_SPI_STATUS_READY_LSB 0
400
#define HOST_CTRL_SPI_STATUS_READY_MASK 0x00000001
401
#define HOST_CTRL_SPI_STATUS_READY_GET(x) (((x) & HOST_CTRL_SPI_STATUS_READY_MASK) >> HOST_CTRL_SPI_STATUS_READY_LSB)
402
#define HOST_CTRL_SPI_STATUS_READY_SET(x) (((x) << HOST_CTRL_SPI_STATUS_READY_LSB) & HOST_CTRL_SPI_STATUS_READY_MASK)
404
#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482
405
#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482
406
#define NON_ASSOC_SLEEP_EN_BIT_MSB 0
407
#define NON_ASSOC_SLEEP_EN_BIT_LSB 0
408
#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001
409
#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB)
410
#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK)
412
#define CPU_DBG_SEL_ADDRESS 0x00000483
413
#define CPU_DBG_SEL_OFFSET 0x00000483
414
#define CPU_DBG_SEL_BIT_MSB 5
415
#define CPU_DBG_SEL_BIT_LSB 0
416
#define CPU_DBG_SEL_BIT_MASK 0x0000003f
417
#define CPU_DBG_SEL_BIT_GET(x) (((x) & CPU_DBG_SEL_BIT_MASK) >> CPU_DBG_SEL_BIT_LSB)
418
#define CPU_DBG_SEL_BIT_SET(x) (((x) << CPU_DBG_SEL_BIT_LSB) & CPU_DBG_SEL_BIT_MASK)
420
#define CPU_DBG_ADDRESS 0x00000484
421
#define CPU_DBG_OFFSET 0x00000484
422
#define CPU_DBG_DATA_MSB 7
423
#define CPU_DBG_DATA_LSB 0
424
#define CPU_DBG_DATA_MASK 0x000000ff
425
#define CPU_DBG_DATA_GET(x) (((x) & CPU_DBG_DATA_MASK) >> CPU_DBG_DATA_LSB)
426
#define CPU_DBG_DATA_SET(x) (((x) << CPU_DBG_DATA_LSB) & CPU_DBG_DATA_MASK)
428
#define INT_STATUS2_ENABLE_ADDRESS 0x00000488
429
#define INT_STATUS2_ENABLE_OFFSET 0x00000488
430
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MSB 2
431
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB 2
432
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK 0x00000004
433
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB)
434
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK)
435
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MSB 1
436
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB 1
437
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK 0x00000002
438
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB)
439
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK)
440
#define INT_STATUS2_ENABLE_GMBOX_DATA_MSB 0
441
#define INT_STATUS2_ENABLE_GMBOX_DATA_LSB 0
442
#define INT_STATUS2_ENABLE_GMBOX_DATA_MASK 0x00000001
443
#define INT_STATUS2_ENABLE_GMBOX_DATA_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK) >> INT_STATUS2_ENABLE_GMBOX_DATA_LSB)
444
#define INT_STATUS2_ENABLE_GMBOX_DATA_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_DATA_LSB) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK)
446
#define GMBOX_RX_LOOKAHEAD_ADDRESS 0x00000490
447
#define GMBOX_RX_LOOKAHEAD_OFFSET 0x00000490
448
#define GMBOX_RX_LOOKAHEAD_DATA_MSB 7
449
#define GMBOX_RX_LOOKAHEAD_DATA_LSB 0
450
#define GMBOX_RX_LOOKAHEAD_DATA_MASK 0x000000ff
451
#define GMBOX_RX_LOOKAHEAD_DATA_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_DATA_MASK) >> GMBOX_RX_LOOKAHEAD_DATA_LSB)
452
#define GMBOX_RX_LOOKAHEAD_DATA_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_DATA_LSB) & GMBOX_RX_LOOKAHEAD_DATA_MASK)
454
#define GMBOX_RX_LOOKAHEAD_MUX_ADDRESS 0x00000498
455
#define GMBOX_RX_LOOKAHEAD_MUX_OFFSET 0x00000498
456
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MSB 0
457
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB 0
458
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK 0x00000001
459
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK) >> GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB)
460
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK)
462
#define CIS_WINDOW_ADDRESS 0x00000600
463
#define CIS_WINDOW_OFFSET 0x00000600
464
#define CIS_WINDOW_DATA_MSB 7
465
#define CIS_WINDOW_DATA_LSB 0
466
#define CIS_WINDOW_DATA_MASK 0x000000ff
467
#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
468
#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
471
#ifndef __ASSEMBLER__
473
typedef struct mbox_wlan_host_reg_reg_s {
474
unsigned char pad0[1024]; /* pad to 0x400 */
475
volatile unsigned char host_int_status;
476
volatile unsigned char cpu_int_status;
477
volatile unsigned char error_int_status;
478
volatile unsigned char counter_int_status;
479
volatile unsigned char mbox_frame;
480
volatile unsigned char rx_lookahead_valid;
481
volatile unsigned char host_int_status2;
482
volatile unsigned char gmbox_rx_avail;
483
volatile unsigned char rx_lookahead0[4];
484
volatile unsigned char rx_lookahead1[4];
485
volatile unsigned char rx_lookahead2[4];
486
volatile unsigned char rx_lookahead3[4];
487
volatile unsigned char int_status_enable;
488
volatile unsigned char cpu_int_status_enable;
489
volatile unsigned char error_status_enable;
490
volatile unsigned char counter_int_status_enable;
491
unsigned char pad1[4]; /* pad to 0x420 */
492
volatile unsigned char count[8];
493
unsigned char pad2[24]; /* pad to 0x440 */
494
volatile unsigned char count_dec[32];
495
volatile unsigned char scratch[8];
496
volatile unsigned char fifo_timeout;
497
volatile unsigned char fifo_timeout_enable;
498
volatile unsigned char disable_sleep;
499
unsigned char pad3[5]; /* pad to 0x470 */
500
volatile unsigned char local_bus;
501
unsigned char pad4[1]; /* pad to 0x472 */
502
volatile unsigned char int_wlan;
503
unsigned char pad5[1]; /* pad to 0x474 */
504
volatile unsigned char window_data[4];
505
volatile unsigned char window_write_addr[4];
506
volatile unsigned char window_read_addr[4];
507
volatile unsigned char host_ctrl_spi_config;
508
volatile unsigned char host_ctrl_spi_status;
509
volatile unsigned char non_assoc_sleep_en;
510
volatile unsigned char cpu_dbg_sel;
511
volatile unsigned char cpu_dbg[4];
512
volatile unsigned char int_status2_enable;
513
unsigned char pad6[7]; /* pad to 0x490 */
514
volatile unsigned char gmbox_rx_lookahead[8];
515
volatile unsigned char gmbox_rx_lookahead_mux;
516
unsigned char pad7[359]; /* pad to 0x600 */
517
volatile unsigned char cis_window[512];
518
} mbox_wlan_host_reg_reg_t;
520
#endif /* __ASSEMBLER__ */
522
#endif /* _MBOX_WLAN_HOST_REG_H_ */
added
removed
updates/cw-2.6.39/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h
