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Viewing changes to src/r6xx_accel.c

  • Committer: Bazaar Package Importer
  • Author(s): Robert Hooker
  • Date: 2010-07-08 16:45:59 UTC
  • mfrom: (1.1.34 upstream) (0.2.8 sid)
  • Revision ID: james.westby@ubuntu.com-20100708164559-t1gwcpobj4n39lhf
Tags: 1:6.13.1-1ubuntu1
* Merge from Debian Unstable. Remainning Ubuntu changes:
  + debian/control:
    - Add quilt to build-depends for Ubuntu patches
  + debian/patches/100_radeon-6.9.0-bgnr-enable.patch:
    - Smooth plymouth transition enablement patch
  + debian/rules:
    - Add xsfbs patchsys
    - Drop /etc/modprobe.d/radeon-kms.conf install.
  + debian/xserver-xorg-video-ati.{pre,post}inst.in:
    - Clean existing /etc/modprobe.d/radeon-kms.conf on install.
      At best this does nothing (KMS is the default for our kernel)
      and at worst it makes it harder to disable KMS.
* Add debian/gbp.conf pointing to Ubuntu branch to make git-buildpackage
  less narky.
* Drop 102-no-xv-rn50.patch and 103_new_pci_ids.patch from previous
  Ubuntu releases, they are upstream now.

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Lines of Context:
src/r6xx_accel.c
661
661
{
662
662
    RADEONInfoPtr info = RADEONPTR(pScrn);
663
663
 
664
 
    BEGIN_BATCH(6);
665
 
    EREG(ib, PA_SC_SCREEN_SCISSOR_TL,              ((x1 << PA_SC_SCREEN_SCISSOR_TL__TL_X_shift) |
666
 
                                                    (y1 << PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift)));
667
 
    EREG(ib, PA_SC_SCREEN_SCISSOR_BR,              ((x2 << PA_SC_SCREEN_SCISSOR_BR__BR_X_shift) |
668
 
                                                    (y2 << PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift)));
 
664
    BEGIN_BATCH(4);
 
665
    PACK0(ib, PA_SC_SCREEN_SCISSOR_TL, 2);
 
666
    E32(ib, ((x1 << PA_SC_SCREEN_SCISSOR_TL__TL_X_shift) |
 
667
             (y1 << PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift)));
 
668
    E32(ib, ((x2 << PA_SC_SCREEN_SCISSOR_BR__BR_X_shift) |
 
669
             (y2 << PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift)));
669
670
    END_BATCH();
670
671
}
671
672
 
674
675
{
675
676
    RADEONInfoPtr info = RADEONPTR(pScrn);
676
677
 
677
 
    BEGIN_BATCH(6);
678
 
    EREG(ib, PA_SC_VPORT_SCISSOR_0_TL +
679
 
         id * PA_SC_VPORT_SCISSOR_0_TL_offset, ((x1 << PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift) |
680
 
                                                (y1 << PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift) |
681
 
                                                WINDOW_OFFSET_DISABLE_bit));
682
 
    EREG(ib, PA_SC_VPORT_SCISSOR_0_BR +
683
 
         id * PA_SC_VPORT_SCISSOR_0_BR_offset, ((x2 << PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift) |
684
 
                                                (y2 << PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift)));
 
678
    BEGIN_BATCH(4);
 
679
    PACK0(ib, PA_SC_VPORT_SCISSOR_0_TL + id * PA_SC_VPORT_SCISSOR_0_TL_offset, 2);
 
680
    E32(ib, ((x1 << PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift) |
 
681
             (y1 << PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift) |
 
682
             WINDOW_OFFSET_DISABLE_bit));
 
683
    E32(ib, ((x2 << PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift) |
 
684
             (y2 << PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift)));
685
685
    END_BATCH();
686
686
}
687
687
 
690
690
{
691
691
    RADEONInfoPtr info = RADEONPTR(pScrn);
692
692
 
693
 
    BEGIN_BATCH(6);
694
 
    EREG(ib, PA_SC_GENERIC_SCISSOR_TL,            ((x1 << PA_SC_GENERIC_SCISSOR_TL__TL_X_shift) |
695
 
                                                   (y1 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift) |
696
 
                                                   WINDOW_OFFSET_DISABLE_bit));
697
 
    EREG(ib, PA_SC_GENERIC_SCISSOR_BR,            ((x2 << PA_SC_GENERIC_SCISSOR_BR__BR_X_shift) |
698
 
                                                   (y2 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift)));
 
693
    BEGIN_BATCH(4);
 
694
    PACK0(ib, PA_SC_GENERIC_SCISSOR_TL, 2);
 
695
    E32(ib, ((x1 << PA_SC_GENERIC_SCISSOR_TL__TL_X_shift) |
 
696
             (y1 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift) |
 
697
             WINDOW_OFFSET_DISABLE_bit));
 
698
    E32(ib, ((x2 << PA_SC_GENERIC_SCISSOR_BR__BR_X_shift) |
 
699
             (y2 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift)));
699
700
    END_BATCH();
700
701
}
701
702
 
704
705
{
705
706
    RADEONInfoPtr info = RADEONPTR(pScrn);
706
707
 
707
 
    BEGIN_BATCH(6);
708
 
    EREG(ib, PA_SC_WINDOW_SCISSOR_TL,             ((x1 << PA_SC_WINDOW_SCISSOR_TL__TL_X_shift) |
709
 
                                                   (y1 << PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift) |
710
 
                                                   WINDOW_OFFSET_DISABLE_bit));
711
 
    EREG(ib, PA_SC_WINDOW_SCISSOR_BR,             ((x2 << PA_SC_WINDOW_SCISSOR_BR__BR_X_shift) |
712
 
                                                   (y2 << PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift)));
 
708
    BEGIN_BATCH(4);
 
709
    PACK0(ib, PA_SC_WINDOW_SCISSOR_TL, 2);
 
710
    E32(ib, ((x1 << PA_SC_WINDOW_SCISSOR_TL__TL_X_shift) |
 
711
             (y1 << PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift) |
 
712
             WINDOW_OFFSET_DISABLE_bit));
 
713
    E32(ib, ((x2 << PA_SC_WINDOW_SCISSOR_BR__BR_X_shift) |
 
714
              (y2 << PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift)));
713
715
    END_BATCH();
714
716
}
715
717
 
718
720
{
719
721
    RADEONInfoPtr info = RADEONPTR(pScrn);
720
722
 
721
 
    BEGIN_BATCH(6);
722
 
    EREG(ib, PA_SC_CLIPRECT_0_TL +
723
 
         id * PA_SC_CLIPRECT_0_TL_offset,     ((x1 << PA_SC_CLIPRECT_0_TL__TL_X_shift) |
724
 
                                               (y1 << PA_SC_CLIPRECT_0_TL__TL_Y_shift)));
725
 
    EREG(ib, PA_SC_CLIPRECT_0_BR +
726
 
         id * PA_SC_CLIPRECT_0_BR_offset,     ((x2 << PA_SC_CLIPRECT_0_BR__BR_X_shift) |
727
 
                                               (y2 << PA_SC_CLIPRECT_0_BR__BR_Y_shift)));
 
723
    BEGIN_BATCH(4);
 
724
    PACK0(ib, PA_SC_CLIPRECT_0_TL + id * PA_SC_CLIPRECT_0_TL_offset, 2);
 
725
    E32(ib, ((x1 << PA_SC_CLIPRECT_0_TL__TL_X_shift) |
 
726
             (y1 << PA_SC_CLIPRECT_0_TL__TL_Y_shift)));
 
727
    E32(ib, ((x2 << PA_SC_CLIPRECT_0_BR__BR_X_shift) |
 
728
             (y2 << PA_SC_CLIPRECT_0_BR__BR_Y_shift)));
728
729
    END_BATCH();
729
730
}
730
731
 
752
753
 
753
754
    start_3d(pScrn, accel_state->ib);
754
755
 
755
 
    // ASIC specific setup, see drm
756
 
    BEGIN_BATCH(15);
757
 
    if (info->ChipFamily < CHIP_FAMILY_RV770) {
758
 
        EREG(ib, TA_CNTL_AUX,                     (( 3 << GRADIENT_CREDIT_shift)                |
759
 
                                                   (28 << TD_FIFO_CREDIT_shift)));
760
 
        EREG(ib, VC_ENHANCE,                      0);
761
 
        EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
762
 
        EREG(ib, DB_DEBUG,                        0x82000000); /* ? */
763
 
        EREG(ib, DB_WATERMARKS,                 ((4  << DEPTH_FREE_shift)               |
764
 
                                                 (16 << DEPTH_FLUSH_shift)              |
765
 
                                                 (0  << FORCE_SUMMARIZE_shift)          |
766
 
                                                 (4  << DEPTH_PENDING_FREE_shift)       |
767
 
                                                 (16 << DEPTH_CACHELINE_FREE_shift)     |
768
 
                                                 0));
769
 
    } else {
770
 
        EREG(ib, TA_CNTL_AUX,                      (( 2 << GRADIENT_CREDIT_shift)               |
771
 
                                                    (28 << TD_FIFO_CREDIT_shift)));
772
 
        EREG(ib, VC_ENHANCE,                       0);
773
 
        EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, VS_PC_LIMIT_ENABLE_bit);
774
 
        EREG(ib, DB_DEBUG,                         0);
775
 
        EREG(ib, DB_WATERMARKS,                    ((4  << DEPTH_FREE_shift)            |
776
 
                                                    (16 << DEPTH_FLUSH_shift)           |
777
 
                                                    (0  << FORCE_SUMMARIZE_shift)               |
778
 
                                                    (4  << DEPTH_PENDING_FREE_shift)    |
779
 
                                                    (4  << DEPTH_CACHELINE_FREE_shift)  |
780
 
                                                    0));
781
 
    }
782
 
    END_BATCH();
783
 
 
784
756
    // SQ
785
757
    sq_conf.ps_prio = 0;
786
758
    sq_conf.vs_prio = 1;
905
877
 
906
878
    sq_setup(pScrn, ib, &sq_conf);
907
879
 
908
 
    BEGIN_BATCH(59);
909
 
    EREG(ib, SQ_VTX_BASE_VTX_LOC,                 0);
910
 
    EREG(ib, SQ_VTX_START_INST_LOC,               0);
 
880
    BEGIN_BATCH(83);
 
881
    if (info->ChipFamily < CHIP_FAMILY_RV770) {
 
882
        EREG(ib, TA_CNTL_AUX, (( 3 << GRADIENT_CREDIT_shift) |
 
883
                                 - (28 << TD_FIFO_CREDIT_shift)));
 
884
        EREG(ib, VC_ENHANCE, 0);
 
885
        EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
 
886
        EREG(ib, DB_DEBUG, 0x82000000); /* ? */
 
887
        EREG(ib, DB_WATERMARKS, ((4 << DEPTH_FREE_shift) |
 
888
                                 (16 << DEPTH_FLUSH_shift) |
 
889
                                 (0 << FORCE_SUMMARIZE_shift) |
 
890
                                 (4 << DEPTH_PENDING_FREE_shift) |
 
891
                                 (16 << DEPTH_CACHELINE_FREE_shift) |
 
892
                                 0));
 
893
    } else {
 
894
        EREG(ib, TA_CNTL_AUX, (( 2 << GRADIENT_CREDIT_shift) |
 
895
                               - (28 << TD_FIFO_CREDIT_shift)));
 
896
        EREG(ib, VC_ENHANCE, 0);
 
897
        EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, VS_PC_LIMIT_ENABLE_bit);
 
898
        EREG(ib, DB_DEBUG, 0);
 
899
        EREG(ib, DB_WATERMARKS, ((4 << DEPTH_FREE_shift) |
 
900
                                 (16 << DEPTH_FLUSH_shift) |
 
901
                                 (0 << FORCE_SUMMARIZE_shift) |
 
902
                                 (4 << DEPTH_PENDING_FREE_shift) |
 
903
                                 (4 << DEPTH_CACHELINE_FREE_shift) |
 
904
                                 0));
 
905
    }
 
906
 
 
907
    PACK0(ib, SQ_VTX_BASE_VTX_LOC, 2);
 
908
    E32(ib, 0);
 
909
    E32(ib, 0);
911
910
 
912
911
    PACK0(ib, SQ_ESGS_RING_ITEMSIZE, 9);
913
 
    E32(ib, 0);                                                 // SQ_ESGS_RING_ITEMSIZE
914
 
    E32(ib, 0);                                                 // SQ_GSVS_RING_ITEMSIZE
915
 
    E32(ib, 0);                                                 // SQ_ESTMP_RING_ITEMSIZE
916
 
    E32(ib, 0);                                                 // SQ_GSTMP_RING_ITEMSIZE
917
 
    E32(ib, 0);                                                 // SQ_VSTMP_RING_ITEMSIZE
918
 
    E32(ib, 0);                                                 // SQ_PSTMP_RING_ITEMSIZE
919
 
    E32(ib, 0);                                                 // SQ_FBUF_RING_ITEMSIZE
920
 
    E32(ib, 0);                                                 // SQ_REDUC_RING_ITEMSIZE
921
 
    E32(ib, 0);                                                 // SQ_GS_VERT_ITEMSIZE
 
912
    E32(ib, 0); // SQ_ESGS_RING_ITEMSIZE
 
913
    E32(ib, 0); // SQ_GSVS_RING_ITEMSIZE
 
914
    E32(ib, 0); // SQ_ESTMP_RING_ITEMSIZE
 
915
    E32(ib, 0); // SQ_GSTMP_RING_ITEMSIZE
 
916
    E32(ib, 0); // SQ_VSTMP_RING_ITEMSIZE
 
917
    E32(ib, 0); // SQ_PSTMP_RING_ITEMSIZE
 
918
    E32(ib, 0); // SQ_FBUF_RING_ITEMSIZE
 
919
    E32(ib, 0); // SQ_REDUC_RING_ITEMSIZE
 
920
    E32(ib, 0); // SQ_GS_VERT_ITEMSIZE
922
921
 
923
922
    // DB
924
923
    EREG(ib, DB_DEPTH_INFO,                       0);
925
 
    EREG(ib, DB_STENCIL_CLEAR,                    0);
926
 
    EREG(ib, DB_DEPTH_CLEAR,                      0);
927
 
    EREG(ib, DB_STENCILREFMASK,                   0);
928
 
    EREG(ib, DB_STENCILREFMASK_BF,                0);
929
924
    EREG(ib, DB_DEPTH_CONTROL,                    0);
930
 
    EREG(ib, DB_RENDER_CONTROL,                   STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit);
 
925
    PACK0(ib, DB_RENDER_CONTROL, 2);
 
926
    E32(ib, STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit);
931
927
    if (info->ChipFamily < CHIP_FAMILY_RV770)
932
 
        EREG(ib, DB_RENDER_OVERRIDE,              FORCE_SHADER_Z_ORDER_bit);
 
928
        E32(ib, FORCE_SHADER_Z_ORDER_bit);
933
929
    else
934
 
        EREG(ib, DB_RENDER_OVERRIDE,              0);
 
930
        E32(ib, 0);
935
931
    EREG(ib, DB_ALPHA_TO_MASK,                    ((2 << ALPHA_TO_MASK_OFFSET0_shift)   |
936
932
                                                   (2 << ALPHA_TO_MASK_OFFSET1_shift)   |
937
933
                                                   (2 << ALPHA_TO_MASK_OFFSET2_shift)   |
938
934
                                                   (2 << ALPHA_TO_MASK_OFFSET3_shift)));
939
 
 
940
 
 
941
935
    EREG(ib, DB_SHADER_CONTROL, ((1 << Z_ORDER_shift) | /* EARLY_Z_THEN_LATE_Z */
942
936
                                 DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */
943
937
 
944
 
 
945
 
    // SX
946
 
    EREG(ib, SX_ALPHA_TEST_CONTROL,               0);
947
 
    EREG(ib, SX_ALPHA_REF,                        0);
948
 
 
949
 
    // CB
950
 
    PACK0(ib, CB_BLEND_RED, 4);
951
 
    E32(ib, 0x00000000);
952
 
    E32(ib, 0x00000000);
953
 
    E32(ib, 0x00000000);
954
 
    E32(ib, 0x00000000);
955
 
    END_BATCH();
956
 
 
957
 
    if (info->ChipFamily < CHIP_FAMILY_RV770) {
958
 
        BEGIN_BATCH(11);
959
 
        PACK0(ib, CB_FOG_RED, 3);
960
 
        E32(ib, 0x00000000);
961
 
        E32(ib, 0x00000000);
962
 
        E32(ib, 0x00000000);
963
 
        PACK0(ib, CB_CLEAR_RED, 4);
964
 
        EFLOAT(ib, 1.0);                                                /* WTF? */
965
 
        EFLOAT(ib, 0.0);
966
 
        EFLOAT(ib, 1.0);
967
 
        EFLOAT(ib, 1.0);
968
 
        END_BATCH();
969
 
    }
970
 
 
971
 
    BEGIN_BATCH(18);
 
938
    PACK0(ib, DB_STENCIL_CLEAR, 2);
 
939
    E32(ib, 0); // DB_STENCIL_CLEAR
 
940
    E32(ib, 0); // DB_DEPTH_CLEAR
 
941
 
 
942
    PACK0(ib, DB_STENCILREFMASK, 3);
 
943
    E32(ib, 0); // DB_STENCILREFMASK
 
944
    E32(ib, 0); // DB_STENCILREFMASK_BF
 
945
    E32(ib, 0); // SX_ALPHA_REF
 
946
 
972
947
    PACK0(ib, CB_CLRCMP_CONTROL, 4);
973
948
    E32(ib, 1 << CLRCMP_FCN_SEL_shift);                         // CB_CLRCMP_CONTROL: use CLRCMP_FCN_SRC
974
949
    E32(ib, 0);                                                 // CB_CLRCMP_SRC
975
950
    E32(ib, 0);                                                 // CB_CLRCMP_DST
976
951
    E32(ib, 0);                                                 // CB_CLRCMP_MSK
977
952
 
978
 
    EREG(ib, CB_SHADER_MASK,                      (0xf << OUTPUT0_ENABLE_shift));
 
953
    EREG(ib, CB_SHADER_MASK,                      OUTPUT0_ENABLE_mask);
979
954
    EREG(ib, R7xx_CB_SHADER_CONTROL,              (RT0_ENABLE_bit));
980
955
 
 
956
    PACK0(ib, SX_ALPHA_TEST_CONTROL, 5);
 
957
    E32(ib, 0); // SX_ALPHA_TEST_CONTROL
 
958
    E32(ib, 0x00000000); // CB_BLEND_RED
 
959
    E32(ib, 0x00000000); // CB_BLEND_GREEN
 
960
    E32(ib, 0x00000000); // CB_BLEND_BLUE
 
961
    E32(ib, 0x00000000); // CB_BLEND_ALPHA
981
962
 
982
 
    // SC
983
963
    EREG(ib, PA_SC_WINDOW_OFFSET,                 ((0 << WINDOW_X_OFFSET_shift) |
984
964
                                                   (0 << WINDOW_Y_OFFSET_shift)));
985
965
 
 
966
    if (info->ChipFamily < CHIP_FAMILY_RV770)
 
967
        EREG(ib, R7xx_PA_SC_EDGERULE,             0x00000000);
 
968
    else
 
969
        EREG(ib, R7xx_PA_SC_EDGERULE,             0xAAAAAAAA);
 
970
 
986
971
    EREG(ib, PA_SC_CLIPRECT_RULE,                 CLIP_RULE_mask);
 
972
 
987
973
    END_BATCH();
988
974
 
989
975
    /* clip boolean is set to always visible -> doesn't matter */
990
976
    for (i = 0; i < PA_SC_CLIPRECT_0_TL_num; i++)
991
977
        set_clip_rect (pScrn, ib, i, 0, 0, 8192, 8192);
992
978
 
993
 
    BEGIN_BATCH(3);
994
 
    if (info->ChipFamily < CHIP_FAMILY_RV770)
995
 
        EREG(ib, R7xx_PA_SC_EDGERULE,             0x00000000);
996
 
    else
997
 
        EREG(ib, R7xx_PA_SC_EDGERULE,             0xAAAAAAAA);
998
 
    END_BATCH();
999
 
 
1000
 
    for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++) {
 
979
    for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++)
1001
980
        set_vport_scissor (pScrn, ib, i, 0, 0, 8192, 8192);
1002
 
        BEGIN_BATCH(4);
1003
 
        PACK0(ib, PA_SC_VPORT_ZMIN_0 + i * PA_SC_VPORT_ZMIN_0_offset, 2);
1004
 
        EFLOAT(ib, 0.0);
1005
 
        EFLOAT(ib, 1.0);
1006
 
        END_BATCH();
1007
 
    }
1008
981
 
1009
 
    BEGIN_BATCH(15);
 
982
    BEGIN_BATCH(42);
 
983
    PACK0(ib, PA_SC_MPASS_PS_CNTL, 2);
 
984
    E32(ib, 0);
1010
985
    if (info->ChipFamily < CHIP_FAMILY_RV770)
1011
 
        EREG(ib, PA_SC_MODE_CNTL,                 (WALK_ORDER_ENABLE_bit | FORCE_EOV_CNTDWN_ENABLE_bit));
 
986
        E32(ib, (WALK_ORDER_ENABLE_bit | FORCE_EOV_CNTDWN_ENABLE_bit));
1012
987
    else
1013
 
        EREG(ib, PA_SC_MODE_CNTL,                 (FORCE_EOV_CNTDWN_ENABLE_bit | FORCE_EOV_REZ_ENABLE_bit |
1014
 
                                                   0x00500000)); /* ? */
1015
 
 
1016
 
    EREG(ib, PA_SU_SC_MODE_CNTL, (FACE_bit |
1017
 
                                  (POLYMODE_PTYPE__TRIANGLES << POLYMODE_FRONT_PTYPE_shift) |
1018
 
                                  (POLYMODE_PTYPE__TRIANGLES << POLYMODE_BACK_PTYPE_shift)));
1019
 
 
1020
 
 
1021
 
    EREG(ib, PA_SC_LINE_CNTL,                     0);
1022
 
    EREG(ib, PA_SC_AA_CONFIG,                     0);
1023
 
    EREG(ib, PA_SC_AA_MASK,                       0xFFFFFFFF);
1024
 
    END_BATCH();
1025
 
 
1026
 
    //XXX: double check this
1027
 
    if (info->ChipFamily > CHIP_FAMILY_R600) {
1028
 
        BEGIN_BATCH(6);
1029
 
        EREG(ib, PA_SC_AA_SAMPLE_LOCS_MCTX,       0);
1030
 
        EREG(ib, PA_SC_AA_SAMPLE_LOCS_8S_WD1_M,   0);
1031
 
        END_BATCH();
1032
 
    }
1033
 
 
1034
 
    BEGIN_BATCH(83);
1035
 
    EREG(ib, PA_SC_LINE_STIPPLE,                  0);
1036
 
    EREG(ib, PA_SC_MPASS_PS_CNTL,                 0);
1037
 
 
1038
 
    // CL
1039
 
    PACK0(ib, PA_CL_VPORT_XSCALE_0, 6);
1040
 
    EFLOAT(ib, 0.0f);                                           // PA_CL_VPORT_XSCALE
1041
 
    EFLOAT(ib, 0.0f);                                           // PA_CL_VPORT_XOFFSET
1042
 
    EFLOAT(ib, 0.0f);                                           // PA_CL_VPORT_YSCALE
1043
 
    EFLOAT(ib, 0.0f);                                           // PA_CL_VPORT_YOFFSET
1044
 
    EFLOAT(ib, 0.0f);                                           // PA_CL_VPORT_ZSCALE
1045
 
    EFLOAT(ib, 0.0f);                                           // PA_CL_VPORT_ZOFFSET
1046
 
    EREG(ib, PA_CL_VTE_CNTL,                      0);
1047
 
    EREG(ib, PA_CL_VS_OUT_CNTL,                   0);
1048
 
    EREG(ib, PA_CL_NANINF_CNTL,                   0);
1049
 
    PACK0(ib, PA_CL_GB_VERT_CLIP_ADJ, 4);
 
988
        E32(ib, (FORCE_EOV_CNTDWN_ENABLE_bit | FORCE_EOV_REZ_ENABLE_bit |
 
989
                 0x00500000)); /* ? */
 
990
 
 
991
    PACK0(ib, PA_SC_LINE_CNTL, 9);
 
992
    E32(ib, 0); // PA_SC_LINE_CNTL
 
993
    E32(ib, 0); // PA_SC_AA_CONFIG
 
994
    E32(ib, ((2 << PA_SU_VTX_CNTL__ROUND_MODE_shift) | PIX_CENTER_bit | // PA_SU_VTX_CNTL
 
995
             (5 << QUANT_MODE_shift))); /* Round to Even, fixed point 1/256 */
1050
996
    EFLOAT(ib, 1.0);                                            // PA_CL_GB_VERT_CLIP_ADJ
1051
997
    EFLOAT(ib, 1.0);                                            // PA_CL_GB_VERT_DISC_ADJ
1052
998
    EFLOAT(ib, 1.0);                                            // PA_CL_GB_HORZ_CLIP_ADJ
1053
999
    EFLOAT(ib, 1.0);                                            // PA_CL_GB_HORZ_DISC_ADJ
1054
 
 
1055
 
    /* Scissor / viewport */
1056
 
    EREG(ib, PA_CL_VTE_CNTL,                      VTX_XY_FMT_bit);
1057
 
    EREG(ib, PA_CL_CLIP_CNTL,                     CLIP_DISABLE_bit);
1058
 
 
1059
 
    // SU
1060
 
    EREG(ib, PA_SU_SC_MODE_CNTL,                  FACE_bit);
1061
 
    EREG(ib, PA_SU_POINT_SIZE,                    0);
1062
 
    EREG(ib, PA_SU_POINT_MINMAX,                  0);
1063
 
    EREG(ib, PA_SU_POLY_OFFSET_DB_FMT_CNTL,       0);
1064
 
    EREG(ib, PA_SU_POLY_OFFSET_BACK_SCALE,        0);
1065
 
    EREG(ib, PA_SU_POLY_OFFSET_FRONT_SCALE,       0);
1066
 
    EREG(ib, PA_SU_POLY_OFFSET_BACK_OFFSET,       0);
1067
 
    EREG(ib, PA_SU_POLY_OFFSET_FRONT_OFFSET,      0);
1068
 
 
1069
 
    EREG(ib, PA_SU_LINE_CNTL,                     (8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */
1070
 
    EREG(ib, PA_SU_VTX_CNTL,                      ((2 << PA_SU_VTX_CNTL__ROUND_MODE_shift) | PIX_CENTER_bit |
1071
 
                                                   (5 << QUANT_MODE_shift))); /* Round to Even, fixed point 1/256 */
1072
 
    EREG(ib, PA_SU_POLY_OFFSET_CLAMP,             0);
 
1000
    E32(ib, 0);                                                 // PA_SC_AA_SAMPLE_LOCS_MCTX
 
1001
    E32(ib, 0);                                                 // PA_SC_AA_SAMPLE_LOCS_8S_WD1_M
 
1002
 
 
1003
    EREG(ib, PA_SC_AA_MASK,                       0xFFFFFFFF);
 
1004
 
 
1005
    PACK0(ib, PA_CL_CLIP_CNTL, 5);
 
1006
    E32(ib, CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL
 
1007
    E32(ib, FACE_bit);         // PA_SU_SC_MODE_CNTL
 
1008
    E32(ib, VTX_XY_FMT_bit);   // PA_CL_VTE_CNTL
 
1009
    E32(ib, 0);                // PA_CL_VS_OUT_CNTL
 
1010
    E32(ib, 0);                // PA_CL_NANINF_CNTL
 
1011
 
 
1012
    PACK0(ib, PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
 
1013
    E32(ib, 0); // PA_SU_POLY_OFFSET_DB_FMT_CNTL
 
1014
    E32(ib, 0); // PA_SU_POLY_OFFSET_CLAMP
 
1015
    E32(ib, 0); // PA_SU_POLY_OFFSET_FRONT_SCALE
 
1016
    E32(ib, 0); // PA_SU_POLY_OFFSET_FRONT_OFFSET
 
1017
    E32(ib, 0); // PA_SU_POLY_OFFSET_BACK_SCALE
 
1018
    E32(ib, 0); // PA_SU_POLY_OFFSET_BACK_OFFSET
1073
1019
 
1074
1020
    // SPI
1075
1021
    if (info->ChipFamily < CHIP_FAMILY_RV770)
1077
1023
    else
1078
1024
        EREG(ib, R7xx_SPI_THREAD_GROUPING,        (1 << PS_GROUPING_shift));
1079
1025
 
1080
 
    EREG(ib, SPI_INPUT_Z,                         0);
1081
 
    EREG(ib, SPI_FOG_CNTL,                        0);
1082
 
    EREG(ib, SPI_FOG_FUNC_SCALE,                  0);
1083
 
    EREG(ib, SPI_FOG_FUNC_BIAS,                   0);
 
1026
    PACK0(ib, SPI_INPUT_Z, 4);
 
1027
    E32(ib, 0); // SPI_INPUT_Z
 
1028
    E32(ib, 0); // SPI_FOG_CNTL
 
1029
    E32(ib, 0); // SPI_FOG_FUNC_SCALE
 
1030
    E32(ib, 0); // SPI_FOG_FUNC_BIAS
 
1031
 
1084
1032
    END_BATCH();
1085
1033
 
1086
1034
    // clear FS
1088
1036
    fs_setup(pScrn, ib, &fs_conf, RADEON_GEM_DOMAIN_VRAM);
1089
1037
 
1090
1038
    // VGT
1091
 
    BEGIN_BATCH(75);
1092
 
    EREG(ib, VGT_MAX_VTX_INDX,                    2048); /* XXX set to a reasonably large number of indices */
1093
 
    EREG(ib, VGT_MIN_VTX_INDX,                    0);
1094
 
    EREG(ib, VGT_INDX_OFFSET,                     0);
1095
 
    EREG(ib, VGT_INSTANCE_STEP_RATE_0,            0);
1096
 
    EREG(ib, VGT_INSTANCE_STEP_RATE_1,            0);
1097
 
    EREG(ib, VGT_MULTI_PRIM_IB_RESET_INDX,        0);
1098
 
    EREG(ib, VGT_OUTPUT_PATH_CNTL,                0);
1099
 
    EREG(ib, VGT_GS_MODE,                         0);
1100
 
    EREG(ib, VGT_HOS_CNTL,                        0);
1101
 
    EREG(ib, VGT_HOS_MAX_TESS_LEVEL,              0);
1102
 
    EREG(ib, VGT_HOS_MIN_TESS_LEVEL,              0);
1103
 
    EREG(ib, VGT_HOS_REUSE_DEPTH,                 0);
1104
 
    EREG(ib, VGT_GROUP_PRIM_TYPE,                 0);
1105
 
    EREG(ib, VGT_GROUP_FIRST_DECR,                0);
1106
 
    EREG(ib, VGT_GROUP_DECR,                      0);
1107
 
    EREG(ib, VGT_GROUP_VECT_0_CNTL,               0);
1108
 
    EREG(ib, VGT_GROUP_VECT_1_CNTL,               0);
1109
 
    EREG(ib, VGT_GROUP_VECT_0_FMT_CNTL,           0);
1110
 
    EREG(ib, VGT_GROUP_VECT_1_FMT_CNTL,           0);
 
1039
    BEGIN_BATCH(43);
 
1040
    PACK0(ib, VGT_MAX_VTX_INDX, 4);
 
1041
    E32(ib, 2048); /* XXX set to a reasonably large number of indices */ // VGT_MAX_VTX_INDX
 
1042
    E32(ib, 0); // VGT_MIN_VTX_INDX
 
1043
    E32(ib, 0); // VGT_INDX_OFFSET
 
1044
    E32(ib, 0); // VGT_MULTI_PRIM_IB_RESET_INDX
 
1045
 
1111
1046
    EREG(ib, VGT_PRIMITIVEID_EN,                  0);
1112
1047
    EREG(ib, VGT_MULTI_PRIM_IB_RESET_EN,          0);
1113
 
    EREG(ib, VGT_STRMOUT_EN,                      0);
1114
 
    EREG(ib, VGT_REUSE_OFF,                       0);
1115
 
    EREG(ib, VGT_VTX_CNT_EN,                      0);
 
1048
 
 
1049
    PACK0(ib, VGT_INSTANCE_STEP_RATE_0, 2);
 
1050
    E32(ib, 0); // VGT_INSTANCE_STEP_RATE_0
 
1051
    E32(ib, 0); // VGT_INSTANCE_STEP_RATE_1
 
1052
 
 
1053
    PACK0(ib, PA_SU_POINT_SIZE, 17);
 
1054
    E32(ib, 0); // PA_SU_POINT_SIZE
 
1055
    E32(ib, 0); // PA_SU_POINT_MINMAX
 
1056
    E32(ib, (8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL
 
1057
    E32(ib, 0); // PA_SC_LINE_STIPPLE
 
1058
    E32(ib, 0); // VGT_OUTPUT_PATH_CNTL
 
1059
    E32(ib, 0); // VGT_HOS_CNTL
 
1060
    E32(ib, 0); // VGT_HOS_MAX_TESS_LEVEL
 
1061
    E32(ib, 0); // VGT_HOS_MIN_TESS_LEVEL
 
1062
    E32(ib, 0); // VGT_HOS_REUSE_DEPTH
 
1063
    E32(ib, 0); // VGT_GROUP_PRIM_TYPE
 
1064
    E32(ib, 0); // VGT_GROUP_FIRST_DECR
 
1065
    E32(ib, 0); // VGT_GROUP_DECR
 
1066
    E32(ib, 0); // VGT_GROUP_VECT_0_CNTL
 
1067
    E32(ib, 0); // VGT_GROUP_VECT_1_CNTL
 
1068
    E32(ib, 0); // VGT_GROUP_VECT_0_FMT_CNTL
 
1069
    E32(ib, 0); // VGT_GROUP_VECT_1_FMT_CNTL
 
1070
    E32(ib, 0); // VGT_GS_MODE
 
1071
 
 
1072
    PACK0(ib, VGT_STRMOUT_EN, 3);
 
1073
    E32(ib, 0); // VGT_STRMOUT_EN
 
1074
    E32(ib, 0); // VGT_REUSE_OFF
 
1075
    E32(ib, 0); // VGT_VTX_CNT_EN
 
1076
 
1116
1077
    EREG(ib, VGT_STRMOUT_BUFFER_EN,               0);
1117
1078
    END_BATCH();
1118
1079
}
1322
1283
    }
1323
1284
#endif 
1324
1285
 
1325
 
    r600_finish_op(pScrn, vert_size);
1326
 
    r600_cp_start(pScrn);
 
1286
    if (accel_state->vb_start_op != -1) {
 
1287
        r600_finish_op(pScrn, vert_size);
 
1288
        r600_cp_start(pScrn);
 
1289
    }
1327
1290
}