2
* Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
4
* This source file is released under GPL v2 license (no other versions).
5
* See the COPYING file included in the main directory of this source
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* distribution for the license terms and conditions.
11
* This file contains the implementation of hardware access methord for 20k1.
18
#include <linux/types.h>
19
#include <linux/slab.h>
20
#include <linux/pci.h>
22
#include <linux/string.h>
23
#include <linux/spinlock.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
26
#include <linux/delay.h>
28
#include "ct20k1reg.h"
30
#if BITS_PER_LONG == 32
31
#define CT_XFI_DMA_MASK DMA_BIT_MASK(32) /* 32 bit PTE */
33
#define CT_XFI_DMA_MASK DMA_BIT_MASK(64) /* 64 bit PTE */
38
spinlock_t reg_20k1_lock;
39
spinlock_t reg_pci_lock;
42
static u32 hw_read_20kx(struct hw *hw, u32 reg);
43
static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
44
static u32 hw_read_pci(struct hw *hw, u32 reg);
45
static void hw_write_pci(struct hw *hw, u32 reg, u32 data);
48
* Type definition block.
49
* The layout of control structures can be directly applied on 20k2 chip.
53
* SRC control block definitions.
56
/* SRC resource control block */
57
#define SRCCTL_STATE 0x00000007
58
#define SRCCTL_BM 0x00000008
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#define SRCCTL_RSR 0x00000030
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#define SRCCTL_SF 0x000001C0
61
#define SRCCTL_WR 0x00000200
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#define SRCCTL_PM 0x00000400
63
#define SRCCTL_ROM 0x00001800
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#define SRCCTL_VO 0x00002000
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#define SRCCTL_ST 0x00004000
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#define SRCCTL_IE 0x00008000
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#define SRCCTL_ILSZ 0x000F0000
68
#define SRCCTL_BP 0x00100000
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#define SRCCCR_CISZ 0x000007FF
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#define SRCCCR_CWA 0x001FF800
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#define SRCCCR_D 0x00200000
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#define SRCCCR_RS 0x01C00000
74
#define SRCCCR_NAL 0x3E000000
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#define SRCCCR_RA 0xC0000000
77
#define SRCCA_CA 0x03FFFFFF
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#define SRCCA_RS 0x1C000000
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#define SRCCA_NAL 0xE0000000
81
#define SRCSA_SA 0x03FFFFFF
83
#define SRCLA_LA 0x03FFFFFF
85
/* Mixer Parameter Ring ram Low and Hight register.
86
* Fixed-point value in 8.24 format for parameter channel */
87
#define MPRLH_PITCH 0xFFFFFFFF
89
/* SRC resource register dirty flags */
98
u16 czbfs:1; /* Clear Z-Buffers */
104
struct src_rsc_ctrl_blk {
111
union src_dirty dirty;
114
/* SRC manager control block */
115
union src_mgr_dirty {
131
struct src_mgr_ctrl_blk {
134
union src_mgr_dirty dirty;
137
/* SRCIMP manager control block */
138
#define SRCAIM_ARC 0x00000FFF
139
#define SRCAIM_NXT 0x00FF0000
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#define SRCAIM_SRC 0xFF000000
147
/* SRCIMP manager register dirty flags */
148
union srcimp_mgr_dirty {
156
struct srcimp_mgr_ctrl_blk {
157
struct srcimap srcimap;
158
union srcimp_mgr_dirty dirty;
162
* Function implementation block.
165
static int src_get_rsc_ctrl_blk(void **rblk)
167
struct src_rsc_ctrl_blk *blk;
170
blk = kzalloc(sizeof(*blk), GFP_KERNEL);
179
static int src_put_rsc_ctrl_blk(void *blk)
181
kfree((struct src_rsc_ctrl_blk *)blk);
186
static int src_set_state(void *blk, unsigned int state)
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struct src_rsc_ctrl_blk *ctl = blk;
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set_field(&ctl->ctl, SRCCTL_STATE, state);
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ctl->dirty.bf.ctl = 1;
195
static int src_set_bm(void *blk, unsigned int bm)
197
struct src_rsc_ctrl_blk *ctl = blk;
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set_field(&ctl->ctl, SRCCTL_BM, bm);
200
ctl->dirty.bf.ctl = 1;
204
static int src_set_rsr(void *blk, unsigned int rsr)
206
struct src_rsc_ctrl_blk *ctl = blk;
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set_field(&ctl->ctl, SRCCTL_RSR, rsr);
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ctl->dirty.bf.ctl = 1;
213
static int src_set_sf(void *blk, unsigned int sf)
215
struct src_rsc_ctrl_blk *ctl = blk;
217
set_field(&ctl->ctl, SRCCTL_SF, sf);
218
ctl->dirty.bf.ctl = 1;
222
static int src_set_wr(void *blk, unsigned int wr)
224
struct src_rsc_ctrl_blk *ctl = blk;
226
set_field(&ctl->ctl, SRCCTL_WR, wr);
227
ctl->dirty.bf.ctl = 1;
231
static int src_set_pm(void *blk, unsigned int pm)
233
struct src_rsc_ctrl_blk *ctl = blk;
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set_field(&ctl->ctl, SRCCTL_PM, pm);
236
ctl->dirty.bf.ctl = 1;
240
static int src_set_rom(void *blk, unsigned int rom)
242
struct src_rsc_ctrl_blk *ctl = blk;
244
set_field(&ctl->ctl, SRCCTL_ROM, rom);
245
ctl->dirty.bf.ctl = 1;
249
static int src_set_vo(void *blk, unsigned int vo)
251
struct src_rsc_ctrl_blk *ctl = blk;
253
set_field(&ctl->ctl, SRCCTL_VO, vo);
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ctl->dirty.bf.ctl = 1;
258
static int src_set_st(void *blk, unsigned int st)
260
struct src_rsc_ctrl_blk *ctl = blk;
262
set_field(&ctl->ctl, SRCCTL_ST, st);
263
ctl->dirty.bf.ctl = 1;
267
static int src_set_ie(void *blk, unsigned int ie)
269
struct src_rsc_ctrl_blk *ctl = blk;
271
set_field(&ctl->ctl, SRCCTL_IE, ie);
272
ctl->dirty.bf.ctl = 1;
276
static int src_set_ilsz(void *blk, unsigned int ilsz)
278
struct src_rsc_ctrl_blk *ctl = blk;
280
set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
281
ctl->dirty.bf.ctl = 1;
285
static int src_set_bp(void *blk, unsigned int bp)
287
struct src_rsc_ctrl_blk *ctl = blk;
289
set_field(&ctl->ctl, SRCCTL_BP, bp);
290
ctl->dirty.bf.ctl = 1;
294
static int src_set_cisz(void *blk, unsigned int cisz)
296
struct src_rsc_ctrl_blk *ctl = blk;
298
set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
299
ctl->dirty.bf.ccr = 1;
303
static int src_set_ca(void *blk, unsigned int ca)
305
struct src_rsc_ctrl_blk *ctl = blk;
307
set_field(&ctl->ca, SRCCA_CA, ca);
308
ctl->dirty.bf.ca = 1;
312
static int src_set_sa(void *blk, unsigned int sa)
314
struct src_rsc_ctrl_blk *ctl = blk;
316
set_field(&ctl->sa, SRCSA_SA, sa);
317
ctl->dirty.bf.sa = 1;
321
static int src_set_la(void *blk, unsigned int la)
323
struct src_rsc_ctrl_blk *ctl = blk;
325
set_field(&ctl->la, SRCLA_LA, la);
326
ctl->dirty.bf.la = 1;
330
static int src_set_pitch(void *blk, unsigned int pitch)
332
struct src_rsc_ctrl_blk *ctl = blk;
334
set_field(&ctl->mpr, MPRLH_PITCH, pitch);
335
ctl->dirty.bf.mpr = 1;
339
static int src_set_clear_zbufs(void *blk, unsigned int clear)
341
((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
345
static int src_set_dirty(void *blk, unsigned int flags)
347
((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
351
static int src_set_dirty_all(void *blk)
353
((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
357
#define AR_SLOT_SIZE 4096
358
#define AR_SLOT_BLOCK_SIZE 16
359
#define AR_PTS_PITCH 6
360
#define AR_PARAM_SRC_OFFSET 0x60
362
static unsigned int src_param_pitch_mixer(unsigned int src_idx)
364
return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
365
- AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
369
static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
371
struct src_rsc_ctrl_blk *ctl = blk;
374
if (ctl->dirty.bf.czbfs) {
375
/* Clear Z-Buffer registers */
376
for (i = 0; i < 8; i++)
377
hw_write_20kx(hw, SRCUPZ+idx*0x100+i*0x4, 0);
379
for (i = 0; i < 4; i++)
380
hw_write_20kx(hw, SRCDN0Z+idx*0x100+i*0x4, 0);
382
for (i = 0; i < 8; i++)
383
hw_write_20kx(hw, SRCDN1Z+idx*0x100+i*0x4, 0);
385
ctl->dirty.bf.czbfs = 0;
387
if (ctl->dirty.bf.mpr) {
388
/* Take the parameter mixer resource in the same group as that
389
* the idx src is in for simplicity. Unlike src, all conjugate
390
* parameter mixer resources must be programmed for
391
* corresponding conjugate src resources. */
392
unsigned int pm_idx = src_param_pitch_mixer(idx);
393
hw_write_20kx(hw, PRING_LO_HI+4*pm_idx, ctl->mpr);
394
hw_write_20kx(hw, PMOPLO+8*pm_idx, 0x3);
395
hw_write_20kx(hw, PMOPHI+8*pm_idx, 0x0);
396
ctl->dirty.bf.mpr = 0;
398
if (ctl->dirty.bf.sa) {
399
hw_write_20kx(hw, SRCSA+idx*0x100, ctl->sa);
400
ctl->dirty.bf.sa = 0;
402
if (ctl->dirty.bf.la) {
403
hw_write_20kx(hw, SRCLA+idx*0x100, ctl->la);
404
ctl->dirty.bf.la = 0;
406
if (ctl->dirty.bf.ca) {
407
hw_write_20kx(hw, SRCCA+idx*0x100, ctl->ca);
408
ctl->dirty.bf.ca = 0;
411
/* Write srccf register */
412
hw_write_20kx(hw, SRCCF+idx*0x100, 0x0);
414
if (ctl->dirty.bf.ccr) {
415
hw_write_20kx(hw, SRCCCR+idx*0x100, ctl->ccr);
416
ctl->dirty.bf.ccr = 0;
418
if (ctl->dirty.bf.ctl) {
419
hw_write_20kx(hw, SRCCTL+idx*0x100, ctl->ctl);
420
ctl->dirty.bf.ctl = 0;
426
static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
428
struct src_rsc_ctrl_blk *ctl = blk;
430
ctl->ca = hw_read_20kx(hw, SRCCA+idx*0x100);
431
ctl->dirty.bf.ca = 0;
433
return get_field(ctl->ca, SRCCA_CA);
436
static unsigned int src_get_dirty(void *blk)
438
return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
441
static unsigned int src_dirty_conj_mask(void)
446
static int src_mgr_enbs_src(void *blk, unsigned int idx)
448
((struct src_mgr_ctrl_blk *)blk)->enbsa = ~(0x0);
449
((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
450
((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
454
static int src_mgr_enb_src(void *blk, unsigned int idx)
456
((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
457
((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
461
static int src_mgr_dsb_src(void *blk, unsigned int idx)
463
((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
464
((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
468
static int src_mgr_commit_write(struct hw *hw, void *blk)
470
struct src_mgr_ctrl_blk *ctl = blk;
474
if (ctl->dirty.bf.enbsa) {
476
ret = hw_read_20kx(hw, SRCENBSTAT);
478
hw_write_20kx(hw, SRCENBS, ctl->enbsa);
479
ctl->dirty.bf.enbsa = 0;
481
for (i = 0; i < 8; i++) {
482
if ((ctl->dirty.data & (0x1 << i))) {
483
hw_write_20kx(hw, SRCENB+(i*0x100), ctl->enb[i]);
484
ctl->dirty.data &= ~(0x1 << i);
491
static int src_mgr_get_ctrl_blk(void **rblk)
493
struct src_mgr_ctrl_blk *blk;
496
blk = kzalloc(sizeof(*blk), GFP_KERNEL);
505
static int src_mgr_put_ctrl_blk(void *blk)
507
kfree((struct src_mgr_ctrl_blk *)blk);
512
static int srcimp_mgr_get_ctrl_blk(void **rblk)
514
struct srcimp_mgr_ctrl_blk *blk;
517
blk = kzalloc(sizeof(*blk), GFP_KERNEL);
526
static int srcimp_mgr_put_ctrl_blk(void *blk)
528
kfree((struct srcimp_mgr_ctrl_blk *)blk);
533
static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
535
struct srcimp_mgr_ctrl_blk *ctl = blk;
537
set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
538
ctl->dirty.bf.srcimap = 1;
542
static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
544
struct srcimp_mgr_ctrl_blk *ctl = blk;
546
set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
547
ctl->dirty.bf.srcimap = 1;
551
static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
553
struct srcimp_mgr_ctrl_blk *ctl = blk;
555
set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
556
ctl->dirty.bf.srcimap = 1;
560
static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
562
struct srcimp_mgr_ctrl_blk *ctl = blk;
564
ctl->srcimap.idx = addr;
565
ctl->dirty.bf.srcimap = 1;
569
static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
571
struct srcimp_mgr_ctrl_blk *ctl = blk;
573
if (ctl->dirty.bf.srcimap) {
574
hw_write_20kx(hw, SRCIMAP+ctl->srcimap.idx*0x100,
575
ctl->srcimap.srcaim);
576
ctl->dirty.bf.srcimap = 0;
583
* AMIXER control block definitions.
586
#define AMOPLO_M 0x00000003
587
#define AMOPLO_X 0x0003FFF0
588
#define AMOPLO_Y 0xFFFC0000
590
#define AMOPHI_SADR 0x000000FF
591
#define AMOPHI_SE 0x80000000
593
/* AMIXER resource register dirty flags */
603
/* AMIXER resource control block */
604
struct amixer_rsc_ctrl_blk {
607
union amixer_dirty dirty;
610
static int amixer_set_mode(void *blk, unsigned int mode)
612
struct amixer_rsc_ctrl_blk *ctl = blk;
614
set_field(&ctl->amoplo, AMOPLO_M, mode);
615
ctl->dirty.bf.amoplo = 1;
619
static int amixer_set_iv(void *blk, unsigned int iv)
621
/* 20k1 amixer does not have this field */
625
static int amixer_set_x(void *blk, unsigned int x)
627
struct amixer_rsc_ctrl_blk *ctl = blk;
629
set_field(&ctl->amoplo, AMOPLO_X, x);
630
ctl->dirty.bf.amoplo = 1;
634
static int amixer_set_y(void *blk, unsigned int y)
636
struct amixer_rsc_ctrl_blk *ctl = blk;
638
set_field(&ctl->amoplo, AMOPLO_Y, y);
639
ctl->dirty.bf.amoplo = 1;
643
static int amixer_set_sadr(void *blk, unsigned int sadr)
645
struct amixer_rsc_ctrl_blk *ctl = blk;
647
set_field(&ctl->amophi, AMOPHI_SADR, sadr);
648
ctl->dirty.bf.amophi = 1;
652
static int amixer_set_se(void *blk, unsigned int se)
654
struct amixer_rsc_ctrl_blk *ctl = blk;
656
set_field(&ctl->amophi, AMOPHI_SE, se);
657
ctl->dirty.bf.amophi = 1;
661
static int amixer_set_dirty(void *blk, unsigned int flags)
663
((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
667
static int amixer_set_dirty_all(void *blk)
669
((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
673
static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
675
struct amixer_rsc_ctrl_blk *ctl = blk;
677
if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
678
hw_write_20kx(hw, AMOPLO+idx*8, ctl->amoplo);
679
ctl->dirty.bf.amoplo = 0;
680
hw_write_20kx(hw, AMOPHI+idx*8, ctl->amophi);
681
ctl->dirty.bf.amophi = 0;
687
static int amixer_get_y(void *blk)
689
struct amixer_rsc_ctrl_blk *ctl = blk;
691
return get_field(ctl->amoplo, AMOPLO_Y);
694
static unsigned int amixer_get_dirty(void *blk)
696
return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
699
static int amixer_rsc_get_ctrl_blk(void **rblk)
701
struct amixer_rsc_ctrl_blk *blk;
704
blk = kzalloc(sizeof(*blk), GFP_KERNEL);
713
static int amixer_rsc_put_ctrl_blk(void *blk)
715
kfree((struct amixer_rsc_ctrl_blk *)blk);
720
static int amixer_mgr_get_ctrl_blk(void **rblk)
722
/*amixer_mgr_ctrl_blk_t *blk;*/
725
/*blk = kzalloc(sizeof(*blk), GFP_KERNEL);
734
static int amixer_mgr_put_ctrl_blk(void *blk)
736
/*kfree((amixer_mgr_ctrl_blk_t *)blk);*/
742
* DAIO control block definitions.
745
/* Receiver Sample Rate Tracker Control register */
746
#define SRTCTL_SRCR 0x000000FF
747
#define SRTCTL_SRCL 0x0000FF00
748
#define SRTCTL_RSR 0x00030000
749
#define SRTCTL_DRAT 0x000C0000
750
#define SRTCTL_RLE 0x10000000
751
#define SRTCTL_RLP 0x20000000
752
#define SRTCTL_EC 0x40000000
753
#define SRTCTL_ET 0x80000000
755
/* DAIO Receiver register dirty flags */
764
/* DAIO Receiver control block */
765
struct dai_ctrl_blk {
767
union dai_dirty dirty;
770
/* S/PDIF Transmitter register dirty flags */
779
/* S/PDIF Transmitter control block */
780
struct dao_ctrl_blk {
781
unsigned int spos; /* S/PDIF Output Channel Status Register */
782
union dao_dirty dirty;
785
/* Audio Input Mapper RAM */
786
#define AIM_ARC 0x00000FFF
787
#define AIM_NXT 0x007F0000
794
/* I2S Transmitter/Receiver Control register */
795
#define I2SCTL_EA 0x00000004
796
#define I2SCTL_EI 0x00000010
798
/* S/PDIF Transmitter Control register */
799
#define SPOCTL_OE 0x00000001
800
#define SPOCTL_OS 0x0000000E
801
#define SPOCTL_RIV 0x00000010
802
#define SPOCTL_LIV 0x00000020
803
#define SPOCTL_SR 0x000000C0
805
/* S/PDIF Receiver Control register */
806
#define SPICTL_EN 0x00000001
807
#define SPICTL_I24 0x00000002
808
#define SPICTL_IB 0x00000004
809
#define SPICTL_SM 0x00000008
810
#define SPICTL_VM 0x00000010
812
/* DAIO manager register dirty flags */
813
union daio_mgr_dirty {
825
/* DAIO manager control block */
826
struct daio_mgr_ctrl_blk {
830
struct daoimap daoimap;
831
union daio_mgr_dirty dirty;
834
static int dai_srt_set_srcr(void *blk, unsigned int src)
836
struct dai_ctrl_blk *ctl = blk;
838
set_field(&ctl->srtctl, SRTCTL_SRCR, src);
839
ctl->dirty.bf.srtctl = 1;
843
static int dai_srt_set_srcl(void *blk, unsigned int src)
845
struct dai_ctrl_blk *ctl = blk;
847
set_field(&ctl->srtctl, SRTCTL_SRCL, src);
848
ctl->dirty.bf.srtctl = 1;
852
static int dai_srt_set_rsr(void *blk, unsigned int rsr)
854
struct dai_ctrl_blk *ctl = blk;
856
set_field(&ctl->srtctl, SRTCTL_RSR, rsr);
857
ctl->dirty.bf.srtctl = 1;
861
static int dai_srt_set_drat(void *blk, unsigned int drat)
863
struct dai_ctrl_blk *ctl = blk;
865
set_field(&ctl->srtctl, SRTCTL_DRAT, drat);
866
ctl->dirty.bf.srtctl = 1;
870
static int dai_srt_set_ec(void *blk, unsigned int ec)
872
struct dai_ctrl_blk *ctl = blk;
874
set_field(&ctl->srtctl, SRTCTL_EC, ec ? 1 : 0);
875
ctl->dirty.bf.srtctl = 1;
879
static int dai_srt_set_et(void *blk, unsigned int et)
881
struct dai_ctrl_blk *ctl = blk;
883
set_field(&ctl->srtctl, SRTCTL_ET, et ? 1 : 0);
884
ctl->dirty.bf.srtctl = 1;
888
static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
890
struct dai_ctrl_blk *ctl = blk;
892
if (ctl->dirty.bf.srtctl) {
895
hw_write_20kx(hw, SRTSCTL+0x4*idx, ctl->srtctl);
898
hw_write_20kx(hw, SRTICTL, ctl->srtctl);
900
ctl->dirty.bf.srtctl = 0;
906
static int dai_get_ctrl_blk(void **rblk)
908
struct dai_ctrl_blk *blk;
911
blk = kzalloc(sizeof(*blk), GFP_KERNEL);
920
static int dai_put_ctrl_blk(void *blk)
922
kfree((struct dai_ctrl_blk *)blk);
927
static int dao_set_spos(void *blk, unsigned int spos)
929
((struct dao_ctrl_blk *)blk)->spos = spos;
930
((struct dao_ctrl_blk *)blk)->dirty.bf.spos = 1;
934
static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
936
struct dao_ctrl_blk *ctl = blk;
938
if (ctl->dirty.bf.spos) {
941
hw_write_20kx(hw, SPOS+0x4*idx, ctl->spos);
943
ctl->dirty.bf.spos = 0;
949
static int dao_get_spos(void *blk, unsigned int *spos)
951
*spos = ((struct dao_ctrl_blk *)blk)->spos;
955
static int dao_get_ctrl_blk(void **rblk)
957
struct dao_ctrl_blk *blk;
960
blk = kzalloc(sizeof(*blk), GFP_KERNEL);
969
static int dao_put_ctrl_blk(void *blk)
971
kfree((struct dao_ctrl_blk *)blk);
976
static int daio_mgr_enb_dai(void *blk, unsigned int idx)
978
struct daio_mgr_ctrl_blk *ctl = blk;
982
set_field(&ctl->spictl, SPICTL_EN << (idx*8), 1);
983
ctl->dirty.bf.spictl |= (0x1 << idx);
987
set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 1);
988
ctl->dirty.bf.i2sictl |= (0x1 << idx);
993
static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
995
struct daio_mgr_ctrl_blk *ctl = blk;
999
set_field(&ctl->spictl, SPICTL_EN << (idx*8), 0);
1000
ctl->dirty.bf.spictl |= (0x1 << idx);
1004
set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 0);
1005
ctl->dirty.bf.i2sictl |= (0x1 << idx);
1010
static int daio_mgr_enb_dao(void *blk, unsigned int idx)
1012
struct daio_mgr_ctrl_blk *ctl = blk;
1016
set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 1);
1017
ctl->dirty.bf.spoctl |= (0x1 << idx);
1021
set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 1);
1022
ctl->dirty.bf.i2soctl |= (0x1 << idx);
1027
static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
1029
struct daio_mgr_ctrl_blk *ctl = blk;
1033
set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 0);
1034
ctl->dirty.bf.spoctl |= (0x1 << idx);
1038
set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 0);
1039
ctl->dirty.bf.i2soctl |= (0x1 << idx);
1044
static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
1046
struct daio_mgr_ctrl_blk *ctl = blk;
1050
switch ((conf & 0x7)) {
1052
set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 3);
1055
set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 0);
1058
set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 1);
1061
set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 2);
1066
set_field(&ctl->spoctl, SPOCTL_LIV << (idx*8),
1067
(conf >> 4) & 0x1); /* Non-audio */
1068
set_field(&ctl->spoctl, SPOCTL_RIV << (idx*8),
1069
(conf >> 4) & 0x1); /* Non-audio */
1070
set_field(&ctl->spoctl, SPOCTL_OS << (idx*8),
1071
((conf >> 3) & 0x1) ? 2 : 2); /* Raw */
1073
ctl->dirty.bf.spoctl |= (0x1 << idx);
1081
static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1083
struct daio_mgr_ctrl_blk *ctl = blk;
1085
set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1086
ctl->dirty.bf.daoimap = 1;
1090
static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1092
struct daio_mgr_ctrl_blk *ctl = blk;
1094
set_field(&ctl->daoimap.aim, AIM_NXT, next);
1095
ctl->dirty.bf.daoimap = 1;
1099
static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1101
struct daio_mgr_ctrl_blk *ctl = blk;
1103
ctl->daoimap.idx = addr;
1104
ctl->dirty.bf.daoimap = 1;
1108
static int daio_mgr_commit_write(struct hw *hw, void *blk)
1110
struct daio_mgr_ctrl_blk *ctl = blk;
1113
if (ctl->dirty.bf.i2sictl || ctl->dirty.bf.i2soctl) {
1114
for (i = 0; i < 4; i++) {
1115
if ((ctl->dirty.bf.i2sictl & (0x1 << i)))
1116
ctl->dirty.bf.i2sictl &= ~(0x1 << i);
1118
if ((ctl->dirty.bf.i2soctl & (0x1 << i)))
1119
ctl->dirty.bf.i2soctl &= ~(0x1 << i);
1121
hw_write_20kx(hw, I2SCTL, ctl->i2sctl);
1124
if (ctl->dirty.bf.spoctl) {
1125
for (i = 0; i < 4; i++) {
1126
if ((ctl->dirty.bf.spoctl & (0x1 << i)))
1127
ctl->dirty.bf.spoctl &= ~(0x1 << i);
1129
hw_write_20kx(hw, SPOCTL, ctl->spoctl);
1132
if (ctl->dirty.bf.spictl) {
1133
for (i = 0; i < 4; i++) {
1134
if ((ctl->dirty.bf.spictl & (0x1 << i)))
1135
ctl->dirty.bf.spictl &= ~(0x1 << i);
1137
hw_write_20kx(hw, SPICTL, ctl->spictl);
1140
if (ctl->dirty.bf.daoimap) {
1141
hw_write_20kx(hw, DAOIMAP+ctl->daoimap.idx*4,
1143
ctl->dirty.bf.daoimap = 0;
1149
static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1151
struct daio_mgr_ctrl_blk *blk;
1154
blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1158
blk->i2sctl = hw_read_20kx(hw, I2SCTL);
1159
blk->spoctl = hw_read_20kx(hw, SPOCTL);
1160
blk->spictl = hw_read_20kx(hw, SPICTL);
1167
static int daio_mgr_put_ctrl_blk(void *blk)
1169
kfree((struct daio_mgr_ctrl_blk *)blk);
1174
/* Timer interrupt */
1175
static int set_timer_irq(struct hw *hw, int enable)
1177
hw_write_20kx(hw, GIE, enable ? IT_INT : 0);
1181
static int set_timer_tick(struct hw *hw, unsigned int ticks)
1184
ticks |= TIMR_IE | TIMR_IP;
1185
hw_write_20kx(hw, TIMR, ticks);
1189
static unsigned int get_wc(struct hw *hw)
1191
return hw_read_20kx(hw, WC);
1194
/* Card hardware initialization block */
1196
unsigned int msr; /* master sample rate in rsrs */
1200
unsigned int msr; /* master sample rate in rsrs */
1201
unsigned char input; /* the input source of ADC */
1202
unsigned char mic20db; /* boost mic by 20db if input is microphone */
1206
unsigned int msr; /* master sample rate in rsrs */
1210
unsigned long vm_pgt_phys;
1213
static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1218
/* Read I2S CTL. Keep original value. */
1219
/*i2sorg = hw_read_20kx(hw, I2SCTL);*/
1220
i2sorg = 0x94040404; /* enable all audio out and I2S-D input */
1221
/* Program I2S with proper master sample rate and enable
1222
* the correct I2S channel. */
1223
i2sorg &= 0xfffffffc;
1225
/* Enable S/PDIF-out-A in fixed 24-bit data
1226
* format and default to 48kHz. */
1227
/* Disable all before doing any changes. */
1228
hw_write_20kx(hw, SPOCTL, 0x0);
1231
switch (info->msr) {
1234
spdorg |= (0x0 << 6);
1238
spdorg |= (0x1 << 6);
1242
spdorg |= (0x2 << 6);
1249
hw_write_20kx(hw, I2SCTL, i2sorg);
1250
hw_write_20kx(hw, SPOCTL, spdorg);
1252
/* Enable S/PDIF-in-A in fixed 24-bit data format. */
1253
/* Disable all before doing any changes. */
1254
hw_write_20kx(hw, SPICTL, 0x0);
1256
spdorg = 0x0a0a0a0a;
1257
hw_write_20kx(hw, SPICTL, spdorg);
1263
/* TRANSPORT operations */
1264
static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1267
u32 ptp_phys_low, ptp_phys_high;
1269
/* Set up device page table */
1270
if ((~0UL) == info->vm_pgt_phys) {
1271
printk(KERN_ERR "Wrong device page table page address!\n");
1275
trnctl = 0x13; /* 32-bit, 4k-size page */
1276
ptp_phys_low = (u32)info->vm_pgt_phys;
1277
ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
1278
if (sizeof(void *) == 8) /* 64bit address */
1280
#if 0 /* Only 4k h/w pages for simplicitiy */
1281
#if PAGE_SIZE == 8192
1285
hw_write_20kx(hw, PTPALX, ptp_phys_low);
1286
hw_write_20kx(hw, PTPAHX, ptp_phys_high);
1287
hw_write_20kx(hw, TRNCTL, trnctl);
1288
hw_write_20kx(hw, TRNIS, 0x200c01); /* realy needed? */
1293
/* Card initialization */
1294
#define GCTL_EAC 0x00000001
1295
#define GCTL_EAI 0x00000002
1296
#define GCTL_BEP 0x00000004
1297
#define GCTL_BES 0x00000008
1298
#define GCTL_DSP 0x00000010
1299
#define GCTL_DBP 0x00000020
1300
#define GCTL_ABP 0x00000040
1301
#define GCTL_TBP 0x00000080
1302
#define GCTL_SBP 0x00000100
1303
#define GCTL_FBP 0x00000200
1304
#define GCTL_XA 0x00000400
1305
#define GCTL_ET 0x00000800
1306
#define GCTL_PR 0x00001000
1307
#define GCTL_MRL 0x00002000
1308
#define GCTL_SDE 0x00004000
1309
#define GCTL_SDI 0x00008000
1310
#define GCTL_SM 0x00010000
1311
#define GCTL_SR 0x00020000
1312
#define GCTL_SD 0x00040000
1313
#define GCTL_SE 0x00080000
1314
#define GCTL_AID 0x00100000
1316
static int hw_pll_init(struct hw *hw, unsigned int rsr)
1318
unsigned int pllctl;
1321
pllctl = (48000 == rsr) ? 0x1480a001 : 0x1480a731;
1322
for (i = 0; i < 3; i++) {
1323
if (hw_read_20kx(hw, PLLCTL) == pllctl)
1326
hw_write_20kx(hw, PLLCTL, pllctl);
1330
printk(KERN_ALERT "PLL initialization failed!!!\n");
1337
static int hw_auto_init(struct hw *hw)
1342
gctl = hw_read_20kx(hw, GCTL);
1343
set_field(&gctl, GCTL_EAI, 0);
1344
hw_write_20kx(hw, GCTL, gctl);
1345
set_field(&gctl, GCTL_EAI, 1);
1346
hw_write_20kx(hw, GCTL, gctl);
1348
for (i = 0; i < 400000; i++) {
1349
gctl = hw_read_20kx(hw, GCTL);
1350
if (get_field(gctl, GCTL_AID))
1353
if (!get_field(gctl, GCTL_AID)) {
1354
printk(KERN_ALERT "Card Auto-init failed!!!\n");
1361
static int i2c_unlock(struct hw *hw)
1363
if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1366
hw_write_pci(hw, 0xcc, 0x8c);
1367
hw_write_pci(hw, 0xcc, 0x0e);
1368
if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1371
hw_write_pci(hw, 0xcc, 0xee);
1372
hw_write_pci(hw, 0xcc, 0xaa);
1373
if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1379
static void i2c_lock(struct hw *hw)
1381
if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1382
hw_write_pci(hw, 0xcc, 0x00);
1385
static void i2c_write(struct hw *hw, u32 device, u32 addr, u32 data)
1390
ret = hw_read_pci(hw, 0xEC);
1391
} while (!(ret & 0x800000));
1392
hw_write_pci(hw, 0xE0, device);
1393
hw_write_pci(hw, 0xE4, (data << 8) | (addr & 0xff));
1396
/* DAC operations */
1398
static int hw_reset_dac(struct hw *hw)
1408
ret = hw_read_pci(hw, 0xEC);
1409
} while (!(ret & 0x800000));
1410
hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1412
/* To be effective, need to reset the DAC twice. */
1413
for (i = 0; i < 2; i++) {
1416
gpioorg = (u16)hw_read_20kx(hw, GPIO);
1418
hw_write_20kx(hw, GPIO, gpioorg);
1420
hw_write_20kx(hw, GPIO, gpioorg | 0x2);
1423
i2c_write(hw, 0x00180080, 0x01, 0x80);
1424
i2c_write(hw, 0x00180080, 0x02, 0x10);
1431
static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1437
if (hw->model == CTSB055X) {
1438
/* SB055x, unmute outputs */
1439
gpioorg = (u16)hw_read_20kx(hw, GPIO);
1440
gpioorg &= 0xffbf; /* set GPIO6 to low */
1441
gpioorg |= 2; /* set GPIO1 to high */
1442
hw_write_20kx(hw, GPIO, gpioorg);
1447
gpioorg = (u16)hw_read_20kx(hw, GPIO);
1449
hw_write_20kx(hw, GPIO, gpioorg);
1456
hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1458
ret = hw_read_pci(hw, 0xEC);
1459
} while (!(ret & 0x800000));
1461
switch (info->msr) {
1476
i2c_write(hw, 0x00180080, 0x06, data);
1477
i2c_write(hw, 0x00180080, 0x09, data);
1478
i2c_write(hw, 0x00180080, 0x0c, data);
1479
i2c_write(hw, 0x00180080, 0x0f, data);
1483
/* unmute outputs */
1484
gpioorg = (u16)hw_read_20kx(hw, GPIO);
1485
gpioorg = gpioorg | 0x40;
1486
hw_write_20kx(hw, GPIO, gpioorg);
1491
/* ADC operations */
1493
static int is_adc_input_selected_SB055x(struct hw *hw, enum ADCSRC type)
1498
static int is_adc_input_selected_SBx(struct hw *hw, enum ADCSRC type)
1502
data = hw_read_20kx(hw, GPIO);
1505
data = ((data & (0x1<<7)) && (data & (0x1<<8)));
1508
data = (!(data & (0x1<<7)) && (data & (0x1<<8)));
1510
case ADC_NONE: /* Digital I/O */
1511
data = (!(data & (0x1<<8)));
1519
static int is_adc_input_selected_hendrix(struct hw *hw, enum ADCSRC type)
1523
data = hw_read_20kx(hw, GPIO);
1526
data = (data & (0x1 << 7)) ? 1 : 0;
1529
data = (data & (0x1 << 7)) ? 0 : 1;
1537
static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1539
switch (hw->model) {
1541
return is_adc_input_selected_SB055x(hw, type);
1543
return is_adc_input_selected_hendrix(hw, type);
1545
return is_adc_input_selected_hendrix(hw, type);
1547
return is_adc_input_selected_SBx(hw, type);
1552
adc_input_select_SB055x(struct hw *hw, enum ADCSRC type, unsigned char boost)
1557
* check and set the following GPIO bits accordingly
1560
* Mic_Pwr_on = GPIO7
1561
* Digital_IO_Sel = GPIO8
1563
* Aux/MicLine_Sw = GPIO12
1565
data = hw_read_20kx(hw, GPIO);
1569
data |= (0x1<<7) | (0x1<<8) | (0x1<<9) ;
1570
data |= boost ? (0x1<<2) : 0;
1576
data |= (0x1<<8) | (0x1<<12);
1579
data |= (0x1<<12); /* set to digital */
1585
hw_write_20kx(hw, GPIO, data);
1592
adc_input_select_SBx(struct hw *hw, enum ADCSRC type, unsigned char boost)
1602
ret = hw_read_pci(hw, 0xEC);
1603
} while (!(ret & 0x800000)); /* i2c ready poll */
1604
/* set i2c access mode as Direct Control */
1605
hw_write_pci(hw, 0xEC, 0x05);
1607
data = hw_read_20kx(hw, GPIO);
1610
data |= ((0x1 << 7) | (0x1 << 8));
1611
i2c_data = 0x1; /* Mic-in */
1614
data &= ~(0x1 << 7);
1616
i2c_data = 0x2; /* Line-in */
1619
data &= ~(0x1 << 8);
1620
i2c_data = 0x0; /* set to Digital */
1626
hw_write_20kx(hw, GPIO, data);
1627
i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
1629
i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
1630
i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
1632
i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
1633
i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
1642
adc_input_select_hendrix(struct hw *hw, enum ADCSRC type, unsigned char boost)
1652
ret = hw_read_pci(hw, 0xEC);
1653
} while (!(ret & 0x800000)); /* i2c ready poll */
1654
/* set i2c access mode as Direct Control */
1655
hw_write_pci(hw, 0xEC, 0x05);
1657
data = hw_read_20kx(hw, GPIO);
1661
i2c_data = 0x1; /* Mic-in */
1664
data &= ~(0x1 << 7);
1665
i2c_data = 0x2; /* Line-in */
1671
hw_write_20kx(hw, GPIO, data);
1672
i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
1674
i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
1675
i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
1677
i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
1678
i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
1686
static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1688
int state = type == ADC_MICIN;
1690
switch (hw->model) {
1692
return adc_input_select_SB055x(hw, type, state);
1694
return adc_input_select_hendrix(hw, type, state);
1696
return adc_input_select_hendrix(hw, type, state);
1698
return adc_input_select_SBx(hw, type, state);
1702
static int adc_init_SB055x(struct hw *hw, int input, int mic20db)
1704
return adc_input_select_SB055x(hw, input, mic20db);
1707
static int adc_init_SBx(struct hw *hw, int input, int mic20db)
1714
input_source = 0x100; /* default to analog */
1718
input_source = 0x180; /* set GPIO7 to select Mic */
1731
input_source = 0x0; /* set to Digital */
1742
ret = hw_read_pci(hw, 0xEC);
1743
} while (!(ret & 0x800000)); /* i2c ready poll */
1744
hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1746
i2c_write(hw, 0x001a0080, 0x0e, 0x08);
1747
i2c_write(hw, 0x001a0080, 0x18, 0x0a);
1748
i2c_write(hw, 0x001a0080, 0x28, 0x86);
1749
i2c_write(hw, 0x001a0080, 0x2a, adcdata);
1752
i2c_write(hw, 0x001a0080, 0x1c, 0xf7);
1753
i2c_write(hw, 0x001a0080, 0x1e, 0xf7);
1755
i2c_write(hw, 0x001a0080, 0x1c, 0xcf);
1756
i2c_write(hw, 0x001a0080, 0x1e, 0xcf);
1759
if (!(hw_read_20kx(hw, ID0) & 0x100))
1760
i2c_write(hw, 0x001a0080, 0x16, 0x26);
1764
gpioorg = (u16)hw_read_20kx(hw, GPIO);
1766
gpioorg |= input_source;
1767
hw_write_20kx(hw, GPIO, gpioorg);
1772
static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1774
if (hw->model == CTSB055X)
1775
return adc_init_SB055x(hw, info->input, info->mic20db);
1777
return adc_init_SBx(hw, info->input, info->mic20db);
1780
static int hw_have_digit_io_switch(struct hw *hw)
1782
/* SB073x and Vista compatible cards have no digit IO switch */
1783
return !(hw->model == CTSB073X || hw->model == CTUAA);
1786
#define CTLBITS(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
1788
#define UAA_CFG_PWRSTATUS 0x44
1789
#define UAA_CFG_SPACE_FLAG 0xA0
1790
#define UAA_CORE_CHANGE 0x3FFC
1791
static int uaa_to_xfi(struct pci_dev *pci)
1793
unsigned int bar0, bar1, bar2, bar3, bar4, bar5;
1794
unsigned int cmd, irq, cl_size, l_timer, pwr;
1795
unsigned int is_uaa;
1796
unsigned int data[4] = {0};
1797
unsigned int io_base;
1800
const u32 CTLX = CTLBITS('C', 'T', 'L', 'X');
1801
const u32 CTL_ = CTLBITS('C', 'T', 'L', '-');
1802
const u32 CTLF = CTLBITS('C', 'T', 'L', 'F');
1803
const u32 CTLi = CTLBITS('C', 'T', 'L', 'i');
1804
const u32 CTLA = CTLBITS('C', 'T', 'L', 'A');
1805
const u32 CTLZ = CTLBITS('C', 'T', 'L', 'Z');
1806
const u32 CTLL = CTLBITS('C', 'T', 'L', 'L');
1808
/* By default, Hendrix card UAA Bar0 should be using memory... */
1809
io_base = pci_resource_start(pci, 0);
1810
mem_base = ioremap(io_base, pci_resource_len(pci, 0));
1814
/* Read current mode from Mode Change Register */
1815
for (i = 0; i < 4; i++)
1816
data[i] = readl(mem_base + UAA_CORE_CHANGE);
1818
/* Determine current mode... */
1819
if (data[0] == CTLA) {
1820
is_uaa = ((data[1] == CTLZ && data[2] == CTLL
1821
&& data[3] == CTLA) || (data[1] == CTLA
1822
&& data[2] == CTLZ && data[3] == CTLL));
1823
} else if (data[0] == CTLZ) {
1824
is_uaa = (data[1] == CTLL
1825
&& data[2] == CTLA && data[3] == CTLA);
1826
} else if (data[0] == CTLL) {
1827
is_uaa = (data[1] == CTLA
1828
&& data[2] == CTLA && data[3] == CTLZ);
1834
/* Not in UAA mode currently. Return directly. */
1839
pci_read_config_dword(pci, PCI_BASE_ADDRESS_0, &bar0);
1840
pci_read_config_dword(pci, PCI_BASE_ADDRESS_1, &bar1);
1841
pci_read_config_dword(pci, PCI_BASE_ADDRESS_2, &bar2);
1842
pci_read_config_dword(pci, PCI_BASE_ADDRESS_3, &bar3);
1843
pci_read_config_dword(pci, PCI_BASE_ADDRESS_4, &bar4);
1844
pci_read_config_dword(pci, PCI_BASE_ADDRESS_5, &bar5);
1845
pci_read_config_dword(pci, PCI_INTERRUPT_LINE, &irq);
1846
pci_read_config_dword(pci, PCI_CACHE_LINE_SIZE, &cl_size);
1847
pci_read_config_dword(pci, PCI_LATENCY_TIMER, &l_timer);
1848
pci_read_config_dword(pci, UAA_CFG_PWRSTATUS, &pwr);
1849
pci_read_config_dword(pci, PCI_COMMAND, &cmd);
1851
/* Set up X-Fi core PCI configuration space. */
1852
/* Switch to X-Fi config space with BAR0 exposed. */
1853
pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x87654321);
1854
/* Copy UAA's BAR5 into X-Fi BAR0 */
1855
pci_write_config_dword(pci, PCI_BASE_ADDRESS_0, bar5);
1856
/* Switch to X-Fi config space without BAR0 exposed. */
1857
pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x12345678);
1858
pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, bar1);
1859
pci_write_config_dword(pci, PCI_BASE_ADDRESS_2, bar2);
1860
pci_write_config_dword(pci, PCI_BASE_ADDRESS_3, bar3);
1861
pci_write_config_dword(pci, PCI_BASE_ADDRESS_4, bar4);
1862
pci_write_config_dword(pci, PCI_INTERRUPT_LINE, irq);
1863
pci_write_config_dword(pci, PCI_CACHE_LINE_SIZE, cl_size);
1864
pci_write_config_dword(pci, PCI_LATENCY_TIMER, l_timer);
1865
pci_write_config_dword(pci, UAA_CFG_PWRSTATUS, pwr);
1866
pci_write_config_dword(pci, PCI_COMMAND, cmd);
1868
/* Switch to X-Fi mode */
1869
writel(CTLX, (mem_base + UAA_CORE_CHANGE));
1870
writel(CTL_, (mem_base + UAA_CORE_CHANGE));
1871
writel(CTLF, (mem_base + UAA_CORE_CHANGE));
1872
writel(CTLi, (mem_base + UAA_CORE_CHANGE));
1879
static irqreturn_t ct_20k1_interrupt(int irq, void *dev_id)
1881
struct hw *hw = dev_id;
1882
unsigned int status;
1884
status = hw_read_20kx(hw, GIP);
1888
if (hw->irq_callback)
1889
hw->irq_callback(hw->irq_callback_data, status);
1891
hw_write_20kx(hw, GIP, status);
1895
static int hw_card_start(struct hw *hw)
1898
struct pci_dev *pci = hw->pci;
1900
err = pci_enable_device(pci);
1904
/* Set DMA transfer mask */
1905
if (pci_set_dma_mask(pci, CT_XFI_DMA_MASK) < 0 ||
1906
pci_set_consistent_dma_mask(pci, CT_XFI_DMA_MASK) < 0) {
1907
printk(KERN_ERR "architecture does not support PCI "
1908
"busmaster DMA with mask 0x%llx\n",
1915
err = pci_request_regions(pci, "XFi");
1919
if (hw->model == CTUAA)
1920
hw->io_base = pci_resource_start(pci, 5);
1922
hw->io_base = pci_resource_start(pci, 0);
1926
/* Switch to X-Fi mode from UAA mode if neeeded */
1927
if (hw->model == CTUAA) {
1928
err = uaa_to_xfi(pci);
1935
err = request_irq(pci->irq, ct_20k1_interrupt, IRQF_SHARED,
1938
printk(KERN_ERR "XFi: Cannot get irq %d\n", pci->irq);
1944
pci_set_master(pci);
1949
pci_release_regions(pci);
1952
pci_disable_device(pci);
1956
static int hw_card_stop(struct hw *hw)
1960
/* disable transport bus master and queueing of request */
1961
hw_write_20kx(hw, TRNCTL, 0x00);
1964
data = hw_read_20kx(hw, PLLCTL);
1965
hw_write_20kx(hw, PLLCTL, (data & (~(0x0F<<12))));
1967
/* TODO: Disable interrupt and so on... */
1969
synchronize_irq(hw->irq);
1973
static int hw_card_shutdown(struct hw *hw)
1976
free_irq(hw->irq, hw);
1981
iounmap((void *)hw->mem_base);
1983
hw->mem_base = (unsigned long)NULL;
1986
pci_release_regions(hw->pci);
1990
pci_disable_device(hw->pci);
1995
static int hw_card_init(struct hw *hw, struct card_conf *info)
2000
struct dac_conf dac_info = {0};
2001
struct adc_conf adc_info = {0};
2002
struct daio_conf daio_info = {0};
2003
struct trn_conf trn_info = {0};
2005
/* Get PCI io port base address and do Hendrix switch if needed. */
2006
err = hw_card_start(hw);
2011
err = hw_pll_init(hw, info->rsr);
2015
/* kick off auto-init */
2016
err = hw_auto_init(hw);
2020
/* Enable audio ring */
2021
gctl = hw_read_20kx(hw, GCTL);
2022
set_field(&gctl, GCTL_EAC, 1);
2023
set_field(&gctl, GCTL_DBP, 1);
2024
set_field(&gctl, GCTL_TBP, 1);
2025
set_field(&gctl, GCTL_FBP, 1);
2026
set_field(&gctl, GCTL_ET, 1);
2027
hw_write_20kx(hw, GCTL, gctl);
2030
/* Reset all global pending interrupts */
2031
hw_write_20kx(hw, GIE, 0);
2032
/* Reset all SRC pending interrupts */
2033
hw_write_20kx(hw, SRCIP, 0);
2036
/* Detect the card ID and configure GPIO accordingly. */
2037
switch (hw->model) {
2039
hw_write_20kx(hw, GPIOCTL, 0x13fe);
2042
hw_write_20kx(hw, GPIOCTL, 0x00e6);
2045
hw_write_20kx(hw, GPIOCTL, 0x00c2);
2048
hw_write_20kx(hw, GPIOCTL, 0x01e6);
2052
trn_info.vm_pgt_phys = info->vm_pgt_phys;
2053
err = hw_trn_init(hw, &trn_info);
2057
daio_info.msr = info->msr;
2058
err = hw_daio_init(hw, &daio_info);
2062
dac_info.msr = info->msr;
2063
err = hw_dac_init(hw, &dac_info);
2067
adc_info.msr = info->msr;
2068
adc_info.input = ADC_LINEIN;
2069
adc_info.mic20db = 0;
2070
err = hw_adc_init(hw, &adc_info);
2074
data = hw_read_20kx(hw, SRCMCTL);
2075
data |= 0x1; /* Enables input from the audio ring */
2076
hw_write_20kx(hw, SRCMCTL, data);
2082
static int hw_suspend(struct hw *hw, pm_message_t state)
2084
struct pci_dev *pci = hw->pci;
2088
if (hw->model == CTUAA) {
2089
/* Switch to UAA config space. */
2090
pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x0);
2093
pci_disable_device(pci);
2094
pci_save_state(pci);
2095
pci_set_power_state(pci, pci_choose_state(pci, state));
2100
static int hw_resume(struct hw *hw, struct card_conf *info)
2102
struct pci_dev *pci = hw->pci;
2104
pci_set_power_state(pci, PCI_D0);
2105
pci_restore_state(pci);
2107
/* Re-initialize card hardware. */
2108
return hw_card_init(hw, info);
2112
static u32 hw_read_20kx(struct hw *hw, u32 reg)
2115
unsigned long flags;
2118
&container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2119
outl(reg, hw->io_base + 0x0);
2120
value = inl(hw->io_base + 0x4);
2121
spin_unlock_irqrestore(
2122
&container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2127
static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2129
unsigned long flags;
2132
&container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2133
outl(reg, hw->io_base + 0x0);
2134
outl(data, hw->io_base + 0x4);
2135
spin_unlock_irqrestore(
2136
&container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2140
static u32 hw_read_pci(struct hw *hw, u32 reg)
2143
unsigned long flags;
2146
&container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2147
outl(reg, hw->io_base + 0x10);
2148
value = inl(hw->io_base + 0x14);
2149
spin_unlock_irqrestore(
2150
&container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2155
static void hw_write_pci(struct hw *hw, u32 reg, u32 data)
2157
unsigned long flags;
2160
&container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2161
outl(reg, hw->io_base + 0x10);
2162
outl(data, hw->io_base + 0x14);
2163
spin_unlock_irqrestore(
2164
&container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2167
static struct hw ct20k1_preset __devinitdata = {
2170
.card_init = hw_card_init,
2171
.card_stop = hw_card_stop,
2172
.pll_init = hw_pll_init,
2173
.is_adc_source_selected = hw_is_adc_input_selected,
2174
.select_adc_source = hw_adc_input_select,
2175
.have_digit_io_switch = hw_have_digit_io_switch,
2177
.suspend = hw_suspend,
2178
.resume = hw_resume,
2181
.src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk,
2182
.src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk,
2183
.src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk,
2184
.src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk,
2185
.src_set_state = src_set_state,
2186
.src_set_bm = src_set_bm,
2187
.src_set_rsr = src_set_rsr,
2188
.src_set_sf = src_set_sf,
2189
.src_set_wr = src_set_wr,
2190
.src_set_pm = src_set_pm,
2191
.src_set_rom = src_set_rom,
2192
.src_set_vo = src_set_vo,
2193
.src_set_st = src_set_st,
2194
.src_set_ie = src_set_ie,
2195
.src_set_ilsz = src_set_ilsz,
2196
.src_set_bp = src_set_bp,
2197
.src_set_cisz = src_set_cisz,
2198
.src_set_ca = src_set_ca,
2199
.src_set_sa = src_set_sa,
2200
.src_set_la = src_set_la,
2201
.src_set_pitch = src_set_pitch,
2202
.src_set_dirty = src_set_dirty,
2203
.src_set_clear_zbufs = src_set_clear_zbufs,
2204
.src_set_dirty_all = src_set_dirty_all,
2205
.src_commit_write = src_commit_write,
2206
.src_get_ca = src_get_ca,
2207
.src_get_dirty = src_get_dirty,
2208
.src_dirty_conj_mask = src_dirty_conj_mask,
2209
.src_mgr_enbs_src = src_mgr_enbs_src,
2210
.src_mgr_enb_src = src_mgr_enb_src,
2211
.src_mgr_dsb_src = src_mgr_dsb_src,
2212
.src_mgr_commit_write = src_mgr_commit_write,
2214
.srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk,
2215
.srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk,
2216
.srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc,
2217
.srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser,
2218
.srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt,
2219
.srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr,
2220
.srcimp_mgr_commit_write = srcimp_mgr_commit_write,
2222
.amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk,
2223
.amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk,
2224
.amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk,
2225
.amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk,
2226
.amixer_set_mode = amixer_set_mode,
2227
.amixer_set_iv = amixer_set_iv,
2228
.amixer_set_x = amixer_set_x,
2229
.amixer_set_y = amixer_set_y,
2230
.amixer_set_sadr = amixer_set_sadr,
2231
.amixer_set_se = amixer_set_se,
2232
.amixer_set_dirty = amixer_set_dirty,
2233
.amixer_set_dirty_all = amixer_set_dirty_all,
2234
.amixer_commit_write = amixer_commit_write,
2235
.amixer_get_y = amixer_get_y,
2236
.amixer_get_dirty = amixer_get_dirty,
2238
.dai_get_ctrl_blk = dai_get_ctrl_blk,
2239
.dai_put_ctrl_blk = dai_put_ctrl_blk,
2240
.dai_srt_set_srco = dai_srt_set_srcr,
2241
.dai_srt_set_srcm = dai_srt_set_srcl,
2242
.dai_srt_set_rsr = dai_srt_set_rsr,
2243
.dai_srt_set_drat = dai_srt_set_drat,
2244
.dai_srt_set_ec = dai_srt_set_ec,
2245
.dai_srt_set_et = dai_srt_set_et,
2246
.dai_commit_write = dai_commit_write,
2248
.dao_get_ctrl_blk = dao_get_ctrl_blk,
2249
.dao_put_ctrl_blk = dao_put_ctrl_blk,
2250
.dao_set_spos = dao_set_spos,
2251
.dao_commit_write = dao_commit_write,
2252
.dao_get_spos = dao_get_spos,
2254
.daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk,
2255
.daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk,
2256
.daio_mgr_enb_dai = daio_mgr_enb_dai,
2257
.daio_mgr_dsb_dai = daio_mgr_dsb_dai,
2258
.daio_mgr_enb_dao = daio_mgr_enb_dao,
2259
.daio_mgr_dsb_dao = daio_mgr_dsb_dao,
2260
.daio_mgr_dao_init = daio_mgr_dao_init,
2261
.daio_mgr_set_imaparc = daio_mgr_set_imaparc,
2262
.daio_mgr_set_imapnxt = daio_mgr_set_imapnxt,
2263
.daio_mgr_set_imapaddr = daio_mgr_set_imapaddr,
2264
.daio_mgr_commit_write = daio_mgr_commit_write,
2266
.set_timer_irq = set_timer_irq,
2267
.set_timer_tick = set_timer_tick,
2271
int __devinit create_20k1_hw_obj(struct hw **rhw)
2273
struct hw20k1 *hw20k1;
2276
hw20k1 = kzalloc(sizeof(*hw20k1), GFP_KERNEL);
2280
spin_lock_init(&hw20k1->reg_20k1_lock);
2281
spin_lock_init(&hw20k1->reg_pci_lock);
2283
hw20k1->hw = ct20k1_preset;
2290
int destroy_20k1_hw_obj(struct hw *hw)
2293
hw_card_shutdown(hw);
2295
kfree(container_of(hw, struct hw20k1, hw));