2
* mxc-ssi.c -- SSI driver for Freescale IMX
4
* Copyright 2006 Wolfson Microelectronics PLC.
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* Author: Liam Girdwood
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* liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com
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* Based on mxc-alsa-mc13783 (C) 2006 Freescale.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
13
* option) any later version.
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* Need to rework SSI register defs when new defs go into mainline.
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* Add support for TDM and FIFO 1.
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* Add support for i.mx3x DMA interface.
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/dma-mapping.h>
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#include <linux/clk.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <mach/dma-mx1-mx2.h>
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#include <asm/mach-types.h>
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#include "mx1_mx2-pcm.h"
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static int ssi_active[2] = {0, 0};
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/* DMA information for mx1_mx2 platforms */
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static struct mx1_mx2_pcm_dma_params imx_ssi1_pcm_stereo_out0 = {
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.name = "SSI1 PCM Stereo out 0",
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.transfer_type = DMA_MODE_WRITE,
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.per_address = SSI1_BASE_ADDR + STX0,
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.event_id = DMA_REQ_SSI1_TX0,
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.watermark_level = TXFIFO_WATERMARK,
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.per_config = IMX_DMA_MEMSIZE_16 | IMX_DMA_TYPE_FIFO,
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.mem_config = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
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static struct mx1_mx2_pcm_dma_params imx_ssi1_pcm_stereo_out1 = {
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.name = "SSI1 PCM Stereo out 1",
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.transfer_type = DMA_MODE_WRITE,
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.per_address = SSI1_BASE_ADDR + STX1,
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.event_id = DMA_REQ_SSI1_TX1,
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.watermark_level = TXFIFO_WATERMARK,
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.per_config = IMX_DMA_MEMSIZE_16 | IMX_DMA_TYPE_FIFO,
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.mem_config = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
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static struct mx1_mx2_pcm_dma_params imx_ssi1_pcm_stereo_in0 = {
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.name = "SSI1 PCM Stereo in 0",
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.transfer_type = DMA_MODE_READ,
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.per_address = SSI1_BASE_ADDR + SRX0,
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.event_id = DMA_REQ_SSI1_RX0,
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.watermark_level = RXFIFO_WATERMARK,
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.per_config = IMX_DMA_MEMSIZE_16 | IMX_DMA_TYPE_FIFO,
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.mem_config = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
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static struct mx1_mx2_pcm_dma_params imx_ssi1_pcm_stereo_in1 = {
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.name = "SSI1 PCM Stereo in 1",
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.transfer_type = DMA_MODE_READ,
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.per_address = SSI1_BASE_ADDR + SRX1,
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.event_id = DMA_REQ_SSI1_RX1,
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.watermark_level = RXFIFO_WATERMARK,
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.per_config = IMX_DMA_MEMSIZE_16 | IMX_DMA_TYPE_FIFO,
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.mem_config = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
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static struct mx1_mx2_pcm_dma_params imx_ssi2_pcm_stereo_out0 = {
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.name = "SSI2 PCM Stereo out 0",
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.transfer_type = DMA_MODE_WRITE,
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.per_address = SSI2_BASE_ADDR + STX0,
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.event_id = DMA_REQ_SSI2_TX0,
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.watermark_level = TXFIFO_WATERMARK,
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.per_config = IMX_DMA_MEMSIZE_16 | IMX_DMA_TYPE_FIFO,
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.mem_config = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
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static struct mx1_mx2_pcm_dma_params imx_ssi2_pcm_stereo_out1 = {
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.name = "SSI2 PCM Stereo out 1",
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.transfer_type = DMA_MODE_WRITE,
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.per_address = SSI2_BASE_ADDR + STX1,
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.event_id = DMA_REQ_SSI2_TX1,
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.watermark_level = TXFIFO_WATERMARK,
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.per_config = IMX_DMA_MEMSIZE_16 | IMX_DMA_TYPE_FIFO,
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.mem_config = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
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static struct mx1_mx2_pcm_dma_params imx_ssi2_pcm_stereo_in0 = {
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.name = "SSI2 PCM Stereo in 0",
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.transfer_type = DMA_MODE_READ,
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.per_address = SSI2_BASE_ADDR + SRX0,
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.event_id = DMA_REQ_SSI2_RX0,
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.watermark_level = RXFIFO_WATERMARK,
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.per_config = IMX_DMA_MEMSIZE_16 | IMX_DMA_TYPE_FIFO,
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.mem_config = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
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static struct mx1_mx2_pcm_dma_params imx_ssi2_pcm_stereo_in1 = {
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.name = "SSI2 PCM Stereo in 1",
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.transfer_type = DMA_MODE_READ,
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.per_address = SSI2_BASE_ADDR + SRX1,
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.event_id = DMA_REQ_SSI2_RX1,
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.watermark_level = RXFIFO_WATERMARK,
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.per_config = IMX_DMA_MEMSIZE_16 | IMX_DMA_TYPE_FIFO,
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.mem_config = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
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static struct clk *ssi_clk0, *ssi_clk1;
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int get_ssi_clk(int ssi, struct device *dev)
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ssi_clk0 = clk_get(dev, "ssi1");
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if (IS_ERR(ssi_clk0))
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return PTR_ERR(ssi_clk0);
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ssi_clk1 = clk_get(dev, "ssi2");
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if (IS_ERR(ssi_clk1))
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return PTR_ERR(ssi_clk1);
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EXPORT_SYMBOL(get_ssi_clk);
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void put_ssi_clk(int ssi)
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EXPORT_SYMBOL(put_ssi_clk);
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* SSI system clock configuration.
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* Should only be called when port is inactive (i.e. SSIEN = 0).
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static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq, int dir)
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if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) {
172
pr_debug("%s: SCR for SSI1 is %x\n", __func__, scr);
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pr_debug("%s: SCR for SSI2 is %x\n", __func__, scr);
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if (scr & SSI_SCR_SSIEN) {
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printk(KERN_WARNING "Warning ssi already enabled\n");
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case IMX_SSP_SYS_CLK:
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if (dir == SND_SOC_CLOCK_OUT) {
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scr |= SSI_SCR_SYS_CLK_EN;
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pr_debug("%s: clk of is output\n", __func__);
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scr &= ~SSI_SCR_SYS_CLK_EN;
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pr_debug("%s: clk of is input\n", __func__);
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if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) {
198
pr_debug("%s: writeback of SSI1_SCR\n", __func__);
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pr_debug("%s: writeback of SSI2_SCR\n", __func__);
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* Should only be called when port is inactive (i.e. SSIEN = 0).
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static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
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pr_debug("%s\n", __func__);
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if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) {
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if (SSI1_SCR & SSI_SCR_SSIEN)
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if (SSI2_SCR & SSI_SCR_SSIEN)
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case IMX_SSI_TX_DIV_2:
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stccr &= ~SSI_STCCR_DIV2;
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case IMX_SSI_TX_DIV_PSR:
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stccr &= ~SSI_STCCR_PSR;
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case IMX_SSI_TX_DIV_PM:
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stccr |= SSI_STCCR_PM(div);
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case IMX_SSI_RX_DIV_2:
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stccr &= ~SSI_STCCR_DIV2;
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case IMX_SSI_RX_DIV_PSR:
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stccr &= ~SSI_STCCR_PSR;
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case IMX_SSI_RX_DIV_PM:
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stccr |= SSI_STCCR_PM(div);
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if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) {
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* SSI Network Mode or TDM slots configuration.
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* Should only be called when port is inactive (i.e. SSIEN = 0).
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static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
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unsigned int mask, int slots)
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u32 stmsk, srmsk, stccr;
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if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) {
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if (SSI1_SCR & SSI_SCR_SSIEN) {
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printk(KERN_WARNING "Warning ssi already enabled\n");
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if (SSI2_SCR & SSI_SCR_SSIEN) {
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printk(KERN_WARNING "Warning ssi already enabled\n");
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stmsk = srmsk = mask;
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stccr &= ~SSI_STCCR_DC_MASK;
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stccr |= SSI_STCCR_DC(slots - 1);
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if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) {
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SSI1_SRCCR = SSI1_STCCR = stccr;
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SSI2_SRCCR = SSI2_STCCR = stccr;
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* SSI DAI format configuration.
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* Should only be called when port is inactive (i.e. SSIEN = 0).
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* Note: We don't use the I2S modes but instead manually configure the
315
static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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u32 stcr = 0, srcr = 0, scr;
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* This is done to avoid this function to modify
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* previous set values in stcr
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if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2)
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scr = SSI1_SCR & ~(SSI_SCR_SYN | SSI_SCR_NET);
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scr = SSI2_SCR & ~(SSI_SCR_SYN | SSI_SCR_NET);
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if (scr & SSI_SCR_SSIEN) {
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printk(KERN_WARNING "Warning ssi already enabled\n");
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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/* data on rising edge of bclk, frame low 1clk before data */
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stcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
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srcr |= SSI_SRCR_RFSI | SSI_SRCR_REFS | SSI_SRCR_RXBIT0;
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case SND_SOC_DAIFMT_LEFT_J:
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/* data on rising edge of bclk, frame high with data */
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stcr |= SSI_STCR_TXBIT0;
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srcr |= SSI_SRCR_RXBIT0;
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case SND_SOC_DAIFMT_DSP_B:
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/* data on rising edge of bclk, frame high with data */
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stcr |= SSI_STCR_TFSL;
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srcr |= SSI_SRCR_RFSL;
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case SND_SOC_DAIFMT_DSP_A:
354
/* data on rising edge of bclk, frame high 1clk before data */
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stcr |= SSI_STCR_TFSL | SSI_STCR_TEFS;
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srcr |= SSI_SRCR_RFSL | SSI_SRCR_REFS;
360
/* DAI clock inversion */
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
362
case SND_SOC_DAIFMT_IB_IF:
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stcr |= SSI_STCR_TFSI;
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stcr &= ~SSI_STCR_TSCKP;
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srcr |= SSI_SRCR_RFSI;
366
srcr &= ~SSI_SRCR_RSCKP;
368
case SND_SOC_DAIFMT_IB_NF:
369
stcr &= ~(SSI_STCR_TSCKP | SSI_STCR_TFSI);
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srcr &= ~(SSI_SRCR_RSCKP | SSI_SRCR_RFSI);
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case SND_SOC_DAIFMT_NB_IF:
373
stcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP;
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srcr |= SSI_SRCR_RFSI | SSI_SRCR_RSCKP;
376
case SND_SOC_DAIFMT_NB_NF:
377
stcr &= ~SSI_STCR_TFSI;
378
stcr |= SSI_STCR_TSCKP;
379
srcr &= ~SSI_SRCR_RFSI;
380
srcr |= SSI_SRCR_RSCKP;
384
/* DAI clock master masks */
385
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
386
case SND_SOC_DAIFMT_CBS_CFS:
387
stcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR;
388
srcr |= SSI_SRCR_RFDIR | SSI_SRCR_RXDIR;
390
case SND_SOC_DAIFMT_CBM_CFS:
391
stcr |= SSI_STCR_TFDIR;
392
srcr |= SSI_SRCR_RFDIR;
394
case SND_SOC_DAIFMT_CBS_CFM:
395
stcr |= SSI_STCR_TXDIR;
396
srcr |= SSI_SRCR_RXDIR;
401
if (!(fmt & SND_SOC_DAIFMT_ASYNC))
404
/* tdm - only for stereo atm */
405
if (fmt & SND_SOC_DAIFMT_TDM)
408
if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) {
421
static int imx_ssi_startup(struct snd_pcm_substream *substream,
422
struct snd_soc_dai *dai)
424
struct snd_soc_pcm_runtime *rtd = substream->private_data;
425
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
427
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
428
/* set up TX DMA params */
429
switch (cpu_dai->id) {
431
cpu_dai->dma_data = &imx_ssi1_pcm_stereo_out0;
434
cpu_dai->dma_data = &imx_ssi1_pcm_stereo_out1;
437
cpu_dai->dma_data = &imx_ssi2_pcm_stereo_out0;
440
cpu_dai->dma_data = &imx_ssi2_pcm_stereo_out1;
442
pr_debug("%s: (playback)\n", __func__);
444
/* set up RX DMA params */
445
switch (cpu_dai->id) {
447
cpu_dai->dma_data = &imx_ssi1_pcm_stereo_in0;
450
cpu_dai->dma_data = &imx_ssi1_pcm_stereo_in1;
453
cpu_dai->dma_data = &imx_ssi2_pcm_stereo_in0;
456
cpu_dai->dma_data = &imx_ssi2_pcm_stereo_in1;
458
pr_debug("%s: (capture)\n", __func__);
462
* we cant really change any SSI values after SSI is enabled
463
* need to fix in software for max flexibility - lrg
465
if (cpu_dai->active) {
466
printk(KERN_WARNING "Warning ssi already enabled\n");
470
/* reset the SSI port - Sect 45.4.4 */
471
if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) {
476
if (ssi_active[SSI1_PORT]++) {
477
pr_debug("%s: exit before reset\n", __func__);
484
SSI1_SFCSR = SSI_SFCSR_RFWM1(RXFIFO_WATERMARK) |
485
SSI_SFCSR_RFWM0(RXFIFO_WATERMARK) |
486
SSI_SFCSR_TFWM1(TXFIFO_WATERMARK) |
487
SSI_SFCSR_TFWM0(TXFIFO_WATERMARK);
493
if (ssi_active[SSI2_PORT]++) {
494
pr_debug("%s: exit before reset\n", __func__);
501
SSI2_SFCSR = SSI_SFCSR_RFWM1(RXFIFO_WATERMARK) |
502
SSI_SFCSR_RFWM0(RXFIFO_WATERMARK) |
503
SSI_SFCSR_TFWM1(TXFIFO_WATERMARK) |
504
SSI_SFCSR_TFWM0(TXFIFO_WATERMARK);
510
int imx_ssi_hw_tx_params(struct snd_pcm_substream *substream,
511
struct snd_pcm_hw_params *params)
513
struct snd_soc_pcm_runtime *rtd = substream->private_data;
514
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
515
u32 stccr, stcr, sier;
517
pr_debug("%s\n", __func__);
519
if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) {
520
stccr = SSI1_STCCR & ~SSI_STCCR_WL_MASK;
524
stccr = SSI2_STCCR & ~SSI_STCCR_WL_MASK;
529
/* DAI data (word) size */
530
switch (params_format(params)) {
531
case SNDRV_PCM_FORMAT_S16_LE:
532
stccr |= SSI_STCCR_WL(16);
534
case SNDRV_PCM_FORMAT_S20_3LE:
535
stccr |= SSI_STCCR_WL(20);
537
case SNDRV_PCM_FORMAT_S24_LE:
538
stccr |= SSI_STCCR_WL(24);
542
/* enable interrupts */
543
if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2)
544
stcr |= SSI_STCR_TFEN0;
546
stcr |= SSI_STCR_TFEN1;
547
sier |= SSI_SIER_TDMAE;
549
if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) {
562
int imx_ssi_hw_rx_params(struct snd_pcm_substream *substream,
563
struct snd_pcm_hw_params *params)
565
struct snd_soc_pcm_runtime *rtd = substream->private_data;
566
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
567
u32 srccr, srcr, sier;
569
pr_debug("%s\n", __func__);
571
if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) {
572
srccr = SSI1_SRCCR & ~SSI_SRCCR_WL_MASK;
576
srccr = SSI2_SRCCR & ~SSI_SRCCR_WL_MASK;
581
/* DAI data (word) size */
582
switch (params_format(params)) {
583
case SNDRV_PCM_FORMAT_S16_LE:
584
srccr |= SSI_SRCCR_WL(16);
586
case SNDRV_PCM_FORMAT_S20_3LE:
587
srccr |= SSI_SRCCR_WL(20);
589
case SNDRV_PCM_FORMAT_S24_LE:
590
srccr |= SSI_SRCCR_WL(24);
594
/* enable interrupts */
595
if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2)
596
srcr |= SSI_SRCR_RFEN0;
598
srcr |= SSI_SRCR_RFEN1;
599
sier |= SSI_SIER_RDMAE;
601
if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) {
615
* Should only be called when port is inactive (i.e. SSIEN = 0),
616
* although can be called multiple times by upper layers.
618
int imx_ssi_hw_params(struct snd_pcm_substream *substream,
619
struct snd_pcm_hw_params *params,
620
struct snd_soc_dai *dai)
622
struct snd_soc_pcm_runtime *rtd = substream->private_data;
623
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
627
/* cant change any parameters when SSI is running */
628
if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) {
629
if (SSI1_SCR & SSI_SCR_SSIEN) {
630
printk(KERN_WARNING "Warning ssi already enabled\n");
634
if (SSI2_SCR & SSI_SCR_SSIEN) {
635
printk(KERN_WARNING "Warning ssi already enabled\n");
641
* Configure both tx and rx params with the same settings. This is
642
* really a harware restriction because SSI must be disabled until
643
* we can change those values. If there is an active audio stream in
644
* one direction, enabling the other direction with different
645
* settings would mean disturbing the running one.
647
ret = imx_ssi_hw_tx_params(substream, params);
650
return imx_ssi_hw_rx_params(substream, params);
653
int imx_ssi_prepare(struct snd_pcm_substream *substream,
654
struct snd_soc_dai *dai)
656
struct snd_soc_pcm_runtime *rtd = substream->private_data;
657
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
660
pr_debug("%s\n", __func__);
662
/* Enable clks here to follow SSI recommended init sequence */
663
if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) {
664
ret = clk_enable(ssi_clk0);
666
printk(KERN_ERR "Unable to enable ssi_clk0\n");
668
ret = clk_enable(ssi_clk1);
670
printk(KERN_ERR "Unable to enable ssi_clk1\n");
676
static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
677
struct snd_soc_dai *dai)
679
struct snd_soc_pcm_runtime *rtd = substream->private_data;
680
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
683
if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2)
689
case SNDRV_PCM_TRIGGER_START:
690
case SNDRV_PCM_TRIGGER_RESUME:
691
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
692
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
693
scr |= SSI_SCR_TE | SSI_SCR_SSIEN;
695
scr |= SSI_SCR_RE | SSI_SCR_SSIEN;
697
case SNDRV_PCM_TRIGGER_SUSPEND:
698
case SNDRV_PCM_TRIGGER_STOP:
699
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
700
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
709
if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2)
717
static void imx_ssi_shutdown(struct snd_pcm_substream *substream,
718
struct snd_soc_dai *dai)
720
struct snd_soc_pcm_runtime *rtd = substream->private_data;
721
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
723
/* shutdown SSI if neither Tx or Rx is active */
724
if (!cpu_dai->active) {
726
if (cpu_dai->id == IMX_DAI_SSI0 ||
727
cpu_dai->id == IMX_DAI_SSI2) {
729
if (--ssi_active[SSI1_PORT] > 1)
733
clk_disable(ssi_clk0);
735
if (--ssi_active[SSI2_PORT])
738
clk_disable(ssi_clk1);
744
static int imx_ssi_suspend(struct platform_device *dev,
745
struct snd_soc_dai *dai)
750
static int imx_ssi_resume(struct platform_device *pdev,
751
struct snd_soc_dai *dai)
757
#define imx_ssi_suspend NULL
758
#define imx_ssi_resume NULL
761
#define IMX_SSI_RATES \
762
(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | \
763
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
764
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
765
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | \
766
SNDRV_PCM_RATE_96000)
768
#define IMX_SSI_BITS \
769
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
770
SNDRV_PCM_FMTBIT_S24_LE)
772
static struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
773
.startup = imx_ssi_startup,
774
.shutdown = imx_ssi_shutdown,
775
.trigger = imx_ssi_trigger,
776
.prepare = imx_ssi_prepare,
777
.hw_params = imx_ssi_hw_params,
778
.set_sysclk = imx_ssi_set_dai_sysclk,
779
.set_clkdiv = imx_ssi_set_dai_clkdiv,
780
.set_fmt = imx_ssi_set_dai_fmt,
781
.set_tdm_slot = imx_ssi_set_dai_tdm_slot,
784
struct snd_soc_dai imx_ssi_pcm_dai[] = {
786
.name = "imx-i2s-1-0",
788
.suspend = imx_ssi_suspend,
789
.resume = imx_ssi_resume,
793
.formats = IMX_SSI_BITS,
794
.rates = IMX_SSI_RATES,},
798
.formats = IMX_SSI_BITS,
799
.rates = IMX_SSI_RATES,},
800
.ops = &imx_ssi_pcm_dai_ops,
803
.name = "imx-i2s-2-0",
808
.formats = IMX_SSI_BITS,
809
.rates = IMX_SSI_RATES,},
813
.formats = IMX_SSI_BITS,
814
.rates = IMX_SSI_RATES,},
815
.ops = &imx_ssi_pcm_dai_ops,
818
.name = "imx-i2s-1-1",
820
.suspend = imx_ssi_suspend,
821
.resume = imx_ssi_resume,
825
.formats = IMX_SSI_BITS,
826
.rates = IMX_SSI_RATES,},
830
.formats = IMX_SSI_BITS,
831
.rates = IMX_SSI_RATES,},
832
.ops = &imx_ssi_pcm_dai_ops,
835
.name = "imx-i2s-2-1",
840
.formats = IMX_SSI_BITS,
841
.rates = IMX_SSI_RATES,},
845
.formats = IMX_SSI_BITS,
846
.rates = IMX_SSI_RATES,},
847
.ops = &imx_ssi_pcm_dai_ops,
850
EXPORT_SYMBOL_GPL(imx_ssi_pcm_dai);
852
static int __init imx_ssi_init(void)
854
return snd_soc_register_dais(imx_ssi_pcm_dai,
855
ARRAY_SIZE(imx_ssi_pcm_dai));
858
static void __exit imx_ssi_exit(void)
860
snd_soc_unregister_dais(imx_ssi_pcm_dai,
861
ARRAY_SIZE(imx_ssi_pcm_dai));
864
module_init(imx_ssi_init);
865
module_exit(imx_ssi_exit);
866
MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com");
867
MODULE_DESCRIPTION("i.MX ASoC I2S driver");
868
MODULE_LICENSE("GPL");