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- Committer: Bazaar Package Importer
- Author(s): Anibal Monsalve Salazar
- Date: 2010-06-26 14:17:57 UTC
- mfrom: (2.1.18 sid)
- Revision ID: james.westby@ubuntu.com-20100626141757-xsp7xqv15qotwels
Tags: 1:3.1.7-4
Update pci.ids with snapshot dated 2010-06-12
- files added:
- .pc
- .pc/01-Makefile.patch
- .pc/01-Makefile.patch/lib
- .pc/02-pcimodules.patch
- .pc/03-pci.ids.patch
- .pc/04-update-pciids.sh.patch
- debian/patches
- debian/source
- files modified:
- ChangeLog
added
removed
lib/header.h
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/*
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* The PCI Library -- PCI Header Structure (based on <linux/pci.h>)
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*
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* Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz>
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* Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
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*
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* Can be freely distributed and used under the terms of the GNU GPL.
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*/
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#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
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#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
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#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
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#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
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#define PCI_CAP_ID_MSI 0x05 /* Message Signaled Interrupts */
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#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
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#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
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#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
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#define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
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#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
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#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
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#define PCI_EXT_CAP_ID_VC2 0x09 /* Virtual Channel (2nd ID) */
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#define PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
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#define PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
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#define PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
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#define PCI_EXT_CAP_ID_ARI 0x0e /* Alternative Routing-ID Interpretation */
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#define PCI_EXT_CAP_ID_ATS 0x0f /* Address Translation Service */
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#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
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/*** Definitions of capabilities ***/
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/* Power Management Registers */
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#define PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME can be asserted from D3cold */
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#define PCI_PM_CTRL 4 /* PM control and status register */
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#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
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#define PCI_PM_CTRL_NO_SOFT_RST 0x0008 /* No Soft Reset from D3hot to D0 */
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#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
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#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* PM table data index */
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#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* PM table data scaling factor */
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#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate (4x in AGP3 mode) */
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#define PCI_AGP_SIZEOF 12
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/* Vital Product Data */
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#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
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#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
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#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
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#define PCI_VPD_DATA 4 /* 32-bits of data returned here */
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/* Slot Identification */
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#define PCI_SID_ESR 2 /* Expansion Slot Register */
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#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
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#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
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/* Message Signalled Interrupts registers */
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/* Message Signaled Interrupts registers */
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#define PCI_MSI_FLAGS 2 /* Various flags */
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#define PCI_MSI_FLAGS_MASK_BIT 0x100 /* interrupt masking & reporting supported */
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#define PCI_HT_RM_CNT1 10 /* Retry Count 1 Register */
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#define PCI_HT_RM_SIZEOF 12
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/* Vendor-Specific Capability (see PCI_EVNDR_xxx for the PCIe version) */
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#define PCI_VNDR_LENGTH 2 /* Length byte */
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/* PCI Express */
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#define PCI_EXP_FLAGS 0x2 /* Capabilities register */
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#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
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#define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
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#define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
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#define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
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#define PCI_EXP_DEVCAP2 0x24 /* Device capabilities 2 */
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#define PCI_EXP_DEVCTL2 0x28 /* Device Control */
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#define PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */
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#define PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */
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#define PCI_EXP_DEV2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable Supported */
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#define PCI_EXP_DEV2_ARI 0x0020 /* ARI Forwarding */
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#define PCI_EXP_DEVSTA2 0x2a /* Device Status */
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#define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */
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#define PCI_EXP_LNKCTL2 0x30 /* Link Control */
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#define PCI_EXP_LNKCTL2_SPEED(x) ((x) & 0xf) /* Target Link Speed */
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#define PCI_EXP_LNKCTL2_CMPLNC 0x0010 /* Enter Compliance */
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#define PCI_EXP_LNKCTL2_SPEED_DIS 0x0020 /* Hardware Autonomous Speed Disable */
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#define PCI_EXP_LNKCTL2_DEEMPHASIS(x) (((x) >> 6) & 1) /* Selectable De-emphasis */
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#define PCI_EXP_LNKCTL2_MARGIN(x) (((x) >> 7) & 7) /* Transmit Margin */
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#define PCI_EXP_LNKCTL2_MOD_CMPLNC 0x0400 /* Enter Modified Compliance */
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#define PCI_EXP_LNKCTL2_CMPLNC_SOS 0x0800 /* Compliance SOS */
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#define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 1) /* Compliance De-emphasis */
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#define PCI_EXP_LNKSTA2 0x32 /* Link Status */
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#define PCI_EXP_LINKSTA2_DEEMPHASIS(x) ((x) & 1) /* Current De-emphasis Level */
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#define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities */
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#define PCI_EXP_SLTCTL2 0x38 /* Slot Control */
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#define PCI_EXP_SLTSTA2 0x3a /* Slot Status */
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/* MSI-X */
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#define PCI_MSIX_ENABLE 0x8000
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#define PCI_MSIX_MASK 0x4000
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#define PCI_MSIX_TABSIZE 0x03ff
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#define PCI_MSIX_TABSIZE 0x07ff
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#define PCI_MSIX_TABLE 4
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#define PCI_MSIX_PBA 8
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#define PCI_MSIX_BIR 0x7
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#define PCI_SSVID_VENDOR 4
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#define PCI_SSVID_DEVICE 6
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/* PCI Advanced Features */
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#define PCI_AF_CAP 3
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#define PCI_AF_CAP_TP 0x01
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#define PCI_AF_CAP_FLR 0x02
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#define PCI_AF_CTRL 4
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#define PCI_AF_CTRL_FLR 0x01
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#define PCI_AF_STATUS 5
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#define PCI_AF_STATUS_TP 0x01
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/* SATA Host Bus Adapter */
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#define PCI_SATA_HBA_BARS 4
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#define PCI_SATA_HBA_REG0 8
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/*** Definitions of extended capabilities ***/
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/* Advanced Error Reporting */
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#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
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#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
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#define PCI_ERR_UNC_TRAIN 0x00000001 /* Undefined in PCIe rev1.1 & 2.0 spec */
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#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
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#define PCI_ERR_UNC_SDES 0x00000020 /* Surprise Down Error */
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#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
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#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
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#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
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#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
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#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
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#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
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#define PCI_ERR_UNC_ACS_VIOL 0x00200000 /* ACS Violation */
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#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
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/* Same bits as above */
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#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
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#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
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#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
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#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
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#define PCI_ERR_COR_REP_ANFE 0x00002000 /* Advisory Non-Fatal Error */
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#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
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/* Same bits as above */
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#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
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#define PCI_PWR_CAP 12 /* Capability */
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#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
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/* Root Complex Link */
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#define PCI_RCLINK_ESD 4 /* Element Self Description */
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#define PCI_RCLINK_LINK1 16 /* First Link Entry */
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#define PCI_RCLINK_LINK_DESC 0 /* Link Entry: Description */
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#define PCI_RCLINK_LINK_ADDR 8 /* Link Entry: Address (64-bit) */
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#define PCI_RCLINK_LINK_SIZE 16 /* Link Entry: sizeof */
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/* PCIe Vendor-Specific Capability */
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#define PCI_EVNDR_HEADER 4 /* Vendor-Specific Header */
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#define PCI_EVNDR_REGISTERS 8 /* Vendor-Specific Registers */
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/* Access Control Services */
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#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
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#define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */
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#define PCI_ACS_CAP_BLOCK 0x0002 /* ACS Translation Blocking */
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#define PCI_ACS_CAP_REQ_RED 0x0004 /* ACS P2P Request Redirect */
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#define PCI_ACS_CAP_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect */
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#define PCI_ACS_CAP_FORWARD 0x0010 /* ACS Upstream Forwarding */
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#define PCI_ACS_CAP_EGRESS 0x0020 /* ACS P2P Egress Control */
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#define PCI_ACS_CAP_TRANS 0x0040 /* ACS Direct Translated P2P */
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#define PCI_ACS_CAP_VECTOR(x) (((x) >> 8) & 0xff) /* Egress Control Vector Size */
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#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
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#define PCI_ACS_CTRL_VALID 0x0001 /* ACS Source Validation Enable */
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#define PCI_ACS_CTRL_BLOCK 0x0002 /* ACS Translation Blocking Enable */
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#define PCI_ACS_CTRL_REQ_RED 0x0004 /* ACS P2P Request Redirect Enable */
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#define PCI_ACS_CTRL_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect Enable */
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#define PCI_ACS_CTRL_FORWARD 0x0010 /* ACS Upstream Forwarding Enable */
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#define PCI_ACS_CTRL_EGRESS 0x0020 /* ACS P2P Egress Control Enable */
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#define PCI_ACS_CTRL_TRANS 0x0040 /* ACS Direct Translated P2P Enable */
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#define PCI_ACS_EGRESS_CTRL 0x08 /* Egress Control Vector */
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/* Alternative Routing-ID Interpretation */
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#define PCI_ARI_CAP 0x04 /* ARI Capability Register */
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#define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */
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#define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */
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#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */
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#define PCI_ARI_CTRL 0x06 /* ARI Control Register */
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#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */
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#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
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#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */
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/* Address Translation Service */
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#define PCI_ATS_CAP 0x04 /* ATS Capability Register */
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#define PCI_ATS_CAP_IQD(x) ((x) & 0x1f) /* Invalidate Queue Depth */
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#define PCI_ATS_CTRL 0x06 /* ATS Control Register */
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#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */
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#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */
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/* Single Root I/O Virtualization */
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#define PCI_IOV_CAP 0x04 /* SR-IOV Capability Register */
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#define PCI_IOV_CAP_VFM 0x00000001 /* VF Migration Capable */
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#define PCI_IOV_CAP_IMN(x) ((x) >> 21) /* VF Migration Interrupt Message Number */
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#define PCI_IOV_CTRL 0x08 /* SR-IOV Control Register */
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#define PCI_IOV_CTRL_VFE 0x0001 /* VF Enable */
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#define PCI_IOV_CTRL_VFME 0x0002 /* VF Migration Enable */
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#define PCI_IOV_CTRL_VFMIE 0x0004 /* VF Migration Interrupt Enable */
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#define PCI_IOV_CTRL_MSE 0x0008 /* VF MSE */
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#define PCI_IOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */
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#define PCI_IOV_STATUS 0x0a /* SR-IOV Status Register */
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#define PCI_IOV_STATUS_MS 0x0001 /* VF Migration Status */
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#define PCI_IOV_INITIALVF 0x0c /* Number of VFs that are initially associated */
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#define PCI_IOV_TOTALVF 0x0e /* Maximum number of VFs that could be associated */
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#define PCI_IOV_NUMVF 0x10 /* Number of VFs that are available */
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#define PCI_IOV_FDL 0x12 /* Function Dependency Link */
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#define PCI_IOV_OFFSET 0x14 /* First VF Offset */
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#define PCI_IOV_STRIDE 0x16 /* Routing ID offset from one VF to the next one */
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#define PCI_IOV_DID 0x1a /* VF Device ID */
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#define PCI_IOV_SUPPS 0x1c /* Supported Page Sizes */
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#define PCI_IOV_SYSPS 0x20 /* System Page Size */
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#define PCI_IOV_BAR_BASE 0x24 /* VF BAR0, VF BAR1, ... VF BAR5 */
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#define PCI_IOV_NUM_BAR 6 /* Number of VF BARs */
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#define PCI_IOV_MSAO 0x3c /* VF Migration State Array Offset */
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#define PCI_IOV_MSA_BIR(x) ((x) & 7) /* VF Migration State BIR */
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#define PCI_IOV_MSA_OFFSET(x) ((x) & 0xfffffff8) /* VF Migration State Offset */
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/*
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* The PCI interface treats multi-function devices as independent
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* devices. The slot/function address of each device is encoded
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Version: 2.0.1