166
188
scan_ops(struct op *op)
170
if (op->num_values >= 0)
171
195
pacc->writeable = 1;
176
200
struct reg_name {
177
202
unsigned int offset;
178
203
unsigned int width;
179
204
const char *name;
182
207
static const struct reg_name pci_reg_names[] = {
183
{ 0x00, 2, "VENDOR_ID", },
184
{ 0x02, 2, "DEVICE_ID", },
185
{ 0x04, 2, "COMMAND", },
186
{ 0x06, 2, "STATUS", },
187
{ 0x08, 1, "REVISION", },
188
{ 0x09, 1, "CLASS_PROG", },
189
{ 0x0a, 2, "CLASS_DEVICE", },
190
{ 0x0c, 1, "CACHE_LINE_SIZE", },
191
{ 0x0d, 1, "LATENCY_TIMER", },
192
{ 0x0e, 1, "HEADER_TYPE", },
193
{ 0x0f, 1, "BIST", },
194
{ 0x10, 4, "BASE_ADDRESS_0", },
195
{ 0x14, 4, "BASE_ADDRESS_1", },
196
{ 0x18, 4, "BASE_ADDRESS_2", },
197
{ 0x1c, 4, "BASE_ADDRESS_3", },
198
{ 0x20, 4, "BASE_ADDRESS_4", },
199
{ 0x24, 4, "BASE_ADDRESS_5", },
200
{ 0x28, 4, "CARDBUS_CIS", },
201
{ 0x2c, 4, "SUBSYSTEM_VENDOR_ID", },
202
{ 0x2e, 2, "SUBSYSTEM_ID", },
203
{ 0x30, 4, "ROM_ADDRESS", },
204
{ 0x3c, 1, "INTERRUPT_LINE", },
205
{ 0x3d, 1, "INTERRUPT_PIN", },
206
{ 0x3e, 1, "MIN_GNT", },
207
{ 0x3f, 1, "MAX_LAT", },
208
{ 0x18, 1, "PRIMARY_BUS", },
209
{ 0x19, 1, "SECONDARY_BUS", },
210
{ 0x1a, 1, "SUBORDINATE_BUS", },
211
{ 0x1b, 1, "SEC_LATENCY_TIMER", },
212
{ 0x1c, 1, "IO_BASE", },
213
{ 0x1d, 1, "IO_LIMIT", },
214
{ 0x1e, 2, "SEC_STATUS", },
215
{ 0x20, 2, "MEMORY_BASE", },
216
{ 0x22, 2, "MEMORY_LIMIT", },
217
{ 0x24, 2, "PREF_MEMORY_BASE", },
218
{ 0x26, 2, "PREF_MEMORY_LIMIT", },
219
{ 0x28, 4, "PREF_BASE_UPPER32", },
220
{ 0x2c, 4, "PREF_LIMIT_UPPER32", },
221
{ 0x30, 2, "IO_BASE_UPPER16", },
222
{ 0x32, 2, "IO_LIMIT_UPPER16", },
223
{ 0x38, 4, "BRIDGE_ROM_ADDRESS", },
224
{ 0x3e, 2, "BRIDGE_CONTROL", },
225
{ 0x10, 4, "CB_CARDBUS_BASE", },
226
{ 0x14, 2, "CB_CAPABILITIES", },
227
{ 0x16, 2, "CB_SEC_STATUS", },
228
{ 0x18, 1, "CB_BUS_NUMBER", },
229
{ 0x19, 1, "CB_CARDBUS_NUMBER", },
230
{ 0x1a, 1, "CB_SUBORDINATE_BUS", },
231
{ 0x1b, 1, "CB_CARDBUS_LATENCY", },
232
{ 0x1c, 4, "CB_MEMORY_BASE_0", },
233
{ 0x20, 4, "CB_MEMORY_LIMIT_0", },
234
{ 0x24, 4, "CB_MEMORY_BASE_1", },
235
{ 0x28, 4, "CB_MEMORY_LIMIT_1", },
236
{ 0x2c, 2, "CB_IO_BASE_0", },
237
{ 0x2e, 2, "CB_IO_BASE_0_HI", },
238
{ 0x30, 2, "CB_IO_LIMIT_0", },
239
{ 0x32, 2, "CB_IO_LIMIT_0_HI", },
240
{ 0x34, 2, "CB_IO_BASE_1", },
241
{ 0x36, 2, "CB_IO_BASE_1_HI", },
242
{ 0x38, 2, "CB_IO_LIMIT_1", },
243
{ 0x3a, 2, "CB_IO_LIMIT_1_HI", },
244
{ 0x40, 2, "CB_SUBSYSTEM_VENDOR_ID", },
245
{ 0x42, 2, "CB_SUBSYSTEM_ID", },
246
{ 0x44, 4, "CB_LEGACY_MODE_BASE", },
208
{ 0, 0x00, 2, "VENDOR_ID" },
209
{ 0, 0x02, 2, "DEVICE_ID" },
210
{ 0, 0x04, 2, "COMMAND" },
211
{ 0, 0x06, 2, "STATUS" },
212
{ 0, 0x08, 1, "REVISION" },
213
{ 0, 0x09, 1, "CLASS_PROG" },
214
{ 0, 0x0a, 2, "CLASS_DEVICE" },
215
{ 0, 0x0c, 1, "CACHE_LINE_SIZE" },
216
{ 0, 0x0d, 1, "LATENCY_TIMER" },
217
{ 0, 0x0e, 1, "HEADER_TYPE" },
218
{ 0, 0x0f, 1, "BIST" },
219
{ 0, 0x10, 4, "BASE_ADDRESS_0" },
220
{ 0, 0x14, 4, "BASE_ADDRESS_1" },
221
{ 0, 0x18, 4, "BASE_ADDRESS_2" },
222
{ 0, 0x1c, 4, "BASE_ADDRESS_3" },
223
{ 0, 0x20, 4, "BASE_ADDRESS_4" },
224
{ 0, 0x24, 4, "BASE_ADDRESS_5" },
225
{ 0, 0x28, 4, "CARDBUS_CIS" },
226
{ 0, 0x2c, 4, "SUBSYSTEM_VENDOR_ID" },
227
{ 0, 0x2e, 2, "SUBSYSTEM_ID" },
228
{ 0, 0x30, 4, "ROM_ADDRESS" },
229
{ 0, 0x3c, 1, "INTERRUPT_LINE" },
230
{ 0, 0x3d, 1, "INTERRUPT_PIN" },
231
{ 0, 0x3e, 1, "MIN_GNT" },
232
{ 0, 0x3f, 1, "MAX_LAT" },
233
{ 0, 0x18, 1, "PRIMARY_BUS" },
234
{ 0, 0x19, 1, "SECONDARY_BUS" },
235
{ 0, 0x1a, 1, "SUBORDINATE_BUS" },
236
{ 0, 0x1b, 1, "SEC_LATENCY_TIMER" },
237
{ 0, 0x1c, 1, "IO_BASE" },
238
{ 0, 0x1d, 1, "IO_LIMIT" },
239
{ 0, 0x1e, 2, "SEC_STATUS" },
240
{ 0, 0x20, 2, "MEMORY_BASE" },
241
{ 0, 0x22, 2, "MEMORY_LIMIT" },
242
{ 0, 0x24, 2, "PREF_MEMORY_BASE" },
243
{ 0, 0x26, 2, "PREF_MEMORY_LIMIT" },
244
{ 0, 0x28, 4, "PREF_BASE_UPPER32" },
245
{ 0, 0x2c, 4, "PREF_LIMIT_UPPER32" },
246
{ 0, 0x30, 2, "IO_BASE_UPPER16" },
247
{ 0, 0x32, 2, "IO_LIMIT_UPPER16" },
248
{ 0, 0x38, 4, "BRIDGE_ROM_ADDRESS" },
249
{ 0, 0x3e, 2, "BRIDGE_CONTROL" },
250
{ 0, 0x10, 4, "CB_CARDBUS_BASE" },
251
{ 0, 0x14, 2, "CB_CAPABILITIES" },
252
{ 0, 0x16, 2, "CB_SEC_STATUS" },
253
{ 0, 0x18, 1, "CB_BUS_NUMBER" },
254
{ 0, 0x19, 1, "CB_CARDBUS_NUMBER" },
255
{ 0, 0x1a, 1, "CB_SUBORDINATE_BUS" },
256
{ 0, 0x1b, 1, "CB_CARDBUS_LATENCY" },
257
{ 0, 0x1c, 4, "CB_MEMORY_BASE_0" },
258
{ 0, 0x20, 4, "CB_MEMORY_LIMIT_0" },
259
{ 0, 0x24, 4, "CB_MEMORY_BASE_1" },
260
{ 0, 0x28, 4, "CB_MEMORY_LIMIT_1" },
261
{ 0, 0x2c, 2, "CB_IO_BASE_0" },
262
{ 0, 0x2e, 2, "CB_IO_BASE_0_HI" },
263
{ 0, 0x30, 2, "CB_IO_LIMIT_0" },
264
{ 0, 0x32, 2, "CB_IO_LIMIT_0_HI" },
265
{ 0, 0x34, 2, "CB_IO_BASE_1" },
266
{ 0, 0x36, 2, "CB_IO_BASE_1_HI" },
267
{ 0, 0x38, 2, "CB_IO_LIMIT_1" },
268
{ 0, 0x3a, 2, "CB_IO_LIMIT_1_HI" },
269
{ 0, 0x40, 2, "CB_SUBSYSTEM_VENDOR_ID" },
270
{ 0, 0x42, 2, "CB_SUBSYSTEM_ID" },
271
{ 0, 0x44, 4, "CB_LEGACY_MODE_BASE" },
272
{ 0x10001, 0, 0, "CAP_PM" },
273
{ 0x10002, 0, 0, "CAP_AGP" },
274
{ 0x10003, 0, 0, "CAP_VPD" },
275
{ 0x10004, 0, 0, "CAP_SLOTID" },
276
{ 0x10005, 0, 0, "CAP_MSI" },
277
{ 0x10006, 0, 0, "CAP_CHSWP" },
278
{ 0x10007, 0, 0, "CAP_PCIX" },
279
{ 0x10008, 0, 0, "CAP_HT" },
280
{ 0x10009, 0, 0, "CAP_VNDR" },
281
{ 0x1000a, 0, 0, "CAP_DBG" },
282
{ 0x1000b, 0, 0, "CAP_CCRC" },
283
{ 0x1000c, 0, 0, "CAP_HOTPLUG" },
284
{ 0x1000d, 0, 0, "CAP_SSVID" },
285
{ 0x1000e, 0, 0, "CAP_AGP3" },
286
{ 0x1000f, 0, 0, "CAP_SECURE" },
287
{ 0x10010, 0, 0, "CAP_EXP" },
288
{ 0x10011, 0, 0, "CAP_MSIX" },
289
{ 0x10012, 0, 0, "CAP_SATA" },
290
{ 0x10013, 0, 0, "CAP_AF" },
291
{ 0x20001, 0, 0, "ECAP_AER" },
292
{ 0x20002, 0, 0, "ECAP_VC" },
293
{ 0x20003, 0, 0, "ECAP_DSN" },
294
{ 0x20004, 0, 0, "ECAP_PB" },
295
{ 0x20005, 0, 0, "ECAP_RCLINK" },
296
{ 0x20006, 0, 0, "ECAP_RCILINK" },
297
{ 0x20007, 0, 0, "ECAP_RCECOLL" },
298
{ 0x20008, 0, 0, "ECAP_MFVC" },
299
{ 0x2000a, 0, 0, "ECAP_RBCB" },
300
{ 0x2000b, 0, 0, "ECAP_VNDR" },
301
{ 0x2000d, 0, 0, "ECAP_ACS" },
302
{ 0x2000e, 0, 0, "ECAP_ARI" },
303
{ 0x2000f, 0, 0, "ECAP_ATS" },
304
{ 0x20010, 0, 0, "ECAP_SRIOV" },
250
static void NONRET PCI_PRINTF(1,2)
251
usage(char *msg, ...)
311
const struct reg_name *r;
313
printf("cap pos w name\n");
314
for (r = pci_reg_names; r->name; r++)
257
fprintf(stderr, "setpci: ");
258
vfprintf(stderr, msg, args);
259
fprintf(stderr, "\n\n");
316
if (r->cap >= 0x20000)
317
printf("%04x", r->cap - 0x20000);
319
printf(" %02x", r->cap - 0x10000);
322
printf(" %02x %c %s\n", r->offset, "-BW?L"[r->width], r->name);
262
330
"Usage: setpci [<options>] (<device>+ <reg>[=<values>]*)*\n"
422
parse_err("Option -%c requires an argument", *e);
344
427
if (!parse_generic_option(*e, pacc, arg))
428
parse_err("Unable to parse option -%c", *e);
433
parse_err("Invalid or misplaced option -%c", *c);
442
static int parse_filter(int argc, char **argv, int i, struct pci_filter *filter)
447
if (!c[1] || !strchr("sd", c[1]))
448
parse_err("Invalid option -%c", c[1]);
450
d = (c[2] == '=') ? c+3 : c+2;
454
parse_err("Option -%c requires an argument", c[1]);
458
if (d = pci_filter_parse_slot(filter, d))
459
parse_err("Unable to parse filter -s %s", d);
462
if (d = pci_filter_parse_id(filter, d))
463
parse_err("Unable to parse filter -d %s", d);
466
parse_err("Unknown filter option -%c", c[1]);
472
static const struct reg_name *parse_reg_name(char *name)
474
const struct reg_name *r;
476
for (r = pci_reg_names; r->name; r++)
477
if (!strcasecmp(r->name, name))
482
static int parse_x32(char *c, char **stopp, unsigned int *resp)
489
unsigned long int l = strtoul(c, &stop, 16);
509
static void parse_register(struct op *op, char *base)
511
const struct reg_name *r;
514
op->cap_type = op->cap_id = 0;
515
if (parse_x32(base, NULL, &op->addr) > 0)
517
else if (r = parse_reg_name(base))
519
switch (r->cap & 0xff0000)
522
op->cap_type = PCI_CAP_NORMAL;
525
op->cap_type = PCI_CAP_EXTENDED;
528
op->cap_id = r->cap & 0xffff;
529
op->addr = r->offset;
530
if (r->width && !op->width)
531
op->width = r->width;
534
else if (!strncasecmp(base, "CAP", 3))
536
if (parse_x32(base+3, NULL, &cap) > 0 && cap < 0x100)
538
op->cap_type = PCI_CAP_NORMAL;
544
else if (!strncasecmp(base, "ECAP", 4))
546
if (parse_x32(base+4, NULL, &cap) > 0 && cap < 0x1000)
548
op->cap_type = PCI_CAP_EXTENDED;
554
parse_err("Unknown register \"%s\"", base);
557
static void parse_op(char *c, struct pci_dev **selected_devices)
559
char *base, *offset, *width, *value;
564
/* Split the argument */
566
if (value = strchr(base, '='))
568
if (width = strchr(base, '.'))
570
if (offset = strchr(base, '+'))
573
/* Look for setting of values and count how many */
578
parse_err("Missing value");
580
for (e=value; *e; e++)
585
/* Allocate the operation */
586
op = xmalloc(sizeof(struct op) + n*sizeof(struct value));
587
op->dev_vector = selected_devices;
590
/* What is the width suffix? */
594
parse_err("Invalid width \"%s\"", width);
595
switch (*width & 0xdf)
598
op->width = 1; break;
600
op->width = 2; break;
602
op->width = 4; break;
604
parse_err("Invalid width \"%c\"", *width);
610
/* Find the register */
611
parse_register(op, base);
613
parse_err("Missing width");
619
if (parse_x32(offset, NULL, &off) <= 0 || off >= 0x1000)
620
parse_err("Invalid offset \"%s\"", offset);
625
if (op->addr >= 0x1000 || op->addr + op->width*(n ? n : 1) > 0x1000)
626
parse_err("Register number %02x out of range", op->addr);
627
if (op->addr & (op->width - 1))
628
parse_err("Unaligned register address %02x", op->addr);
630
/* Parse the values */
633
unsigned int ll, lim;
634
e = strchr(value, ',');
637
if (parse_x32(value, &f, &ll) < 0 || f && *f != ':')
638
parse_err("Invalid value \"%s\"", value);
639
lim = max_values[op->width];
640
if (ll > lim && ll < ~0UL - lim)
641
parse_err("Value \"%s\" is out of range", value);
642
op->values[j].value = ll;
645
if (parse_x32(f+1, NULL, &ll) <= 0)
646
parse_err("Invalid mask \"%s\"", f+1);
647
if (ll > lim && ll < ~0UL - lim)
648
parse_err("Mask \"%s\" is out of range", f+1);
649
op->values[j].mask = ll;
650
op->values[j].value &= ll;
653
op->values[j].mask = ~0U;
662
static void parse_ops(int argc, char **argv, int i)
664
enum { STATE_INIT, STATE_GOT_FILTER, STATE_GOT_OP } state = STATE_INIT;
665
struct pci_filter filter;
666
struct pci_dev **selected_devices = NULL;
373
if (!c[1] || !strchr("sd", c[1]))
376
d = (c[2] == '=') ? c+3 : c+2;
385
674
if (state != STATE_GOT_FILTER)
387
pci_filter_init(pacc, &filter);
388
state = STATE_GOT_FILTER;
393
if (d = pci_filter_parse_slot(&filter, d))
397
if (d = pci_filter_parse_id(&filter, d))
675
pci_filter_init(pacc, &filter);
676
i = parse_filter(argc, argv, i-1, &filter);
677
state = STATE_GOT_FILTER;
404
else if (state == STATE_INIT)
681
if (state == STATE_INIT)
682
parse_err("Filter specification expected");
408
683
if (state == STATE_GOT_FILTER)
409
684
selected_devices = select_devices(&filter);
410
685
if (!selected_devices[0] && !force)
411
fprintf(stderr, "setpci: Warning: No devices selected for `%s'.\n", c);
686
fprintf(stderr, "setpci: Warning: No devices selected for \"%s\".\n", c);
687
parse_op(c, selected_devices);
412
688
state = STATE_GOT_OP;
413
/* look for setting of values and count how many */
419
usage("Missing value");
420
for(e=d, n=1; *e; e++)
423
op = xmalloc(sizeof(struct op) + n*sizeof(struct value));
428
op = xmalloc(sizeof(struct op));
430
op->dev_vector = selected_devices;
437
usage("Missing width");
441
op->width = 1; break;
443
op->width = 2; break;
445
op->width = 4; break;
447
usage("Invalid width \"%c\"", *e);
452
ll = strtol(c, &f, 16);
455
const struct reg_name *r;
456
for(r = pci_reg_names; r->name; r++)
457
if (!strcasecmp(r->name, c))
460
usage("Unknown register \"%s\"", c);
461
if (e && op->width != r->width)
462
usage("Explicit width doesn't correspond with the named register \"%s\"", c);
464
op->width = r->width;
466
if (ll > 0x1000 || ll + op->width*((n < 0) ? 1 : n) > 0x1000)
467
die("Register number out of range!");
468
if (ll & (op->width - 1))
469
die("Unaligned register address!");
471
/* read in all the values to be set */
477
ll = strtoul(d, &f, 16);
478
lim = max_values[op->width];
479
if (f && *f && *f != ':')
480
usage("Invalid value \"%s\"", d);
481
if (ll > lim && ll < ~0UL - lim)
482
usage("Value \"%s\" is out of range", d);
483
op->values[i].value = ll;
487
ll = strtoul(d, &f, 16);
489
usage("Invalid mask \"%s\"", d);
490
if (ll > lim && ll < ~0UL - lim)
491
usage("Mask \"%s\" is out of range", d);
492
op->values[i].mask = ll;
493
op->values[i].value &= ll;
496
op->values[i].mask = ~0U;
506
691
if (state == STATE_INIT)
507
usage("No operation specified");
692
parse_err("No operation specified");
696
main(int argc, char **argv)
702
i = parse_options(argc, argv);
707
parse_ops(argc, argv, i);
509
708
scan_ops(first_op);
510
709
execute(first_op);