957
976
; superseded by the CONFIG directive. The following settings
958
977
; are available for this device.
960
; Oscillator Selection:
965
; OSC = EC EC-OSC2 as Clock Out
966
; OSC = ECIO6 EC-OSC2 as RA6
967
; OSC = HSPLL HS-PLL Enabled
968
; OSC = RCIO6 RC-OSC2 as RA6
969
; OSC = INTIO67 INTRC-OSC2 as RA6, OSC1 as RA7
970
; OSC = INTIO7 INTRC-OSC2 as Clock Out, OSC1 as RA7
972
; Fail Safe Clock Monitor:
973
; FCMEN = OFF Disabled
976
; Internal External Osc. Switch Over:
977
; IESO = OFF Disabled
982
; PWRT = OFF Disabled
985
; BOREN = OFF Disabled
986
; BOREN = ON SBOREN Enabled
987
; BOREN = NOSLP Enabled except SLEEP, SBOREN Disabled
988
; BOREN = SBORDIS Enabled, SBOREN Disabled
1000
; Watchdog Postscaler:
979
; Oscillator Selection bits:
980
; OSC = LP LP oscillator
981
; OSC = XT XT oscillator
982
; OSC = HS HS oscillator
983
; OSC = RC External RC oscillator, CLKO function on RA6
984
; OSC = EC EC oscillator, CLKO function on RA6
985
; OSC = ECIO6 EC oscillator, port function on RA6
986
; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
987
; OSC = RCIO6 External RC oscillator, port function on RA6
988
; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
989
; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
991
; Fail-Safe Clock Monitor Enable bit:
992
; FCMEN = OFF Fail-Safe Clock Monitor disabled
993
; FCMEN = ON Fail-Safe Clock Monitor enabled
995
; Internal/External Oscillator Switchover bit:
996
; IESO = OFF Oscillator Switchover mode disabled
997
; IESO = ON Oscillator Switchover mode enabled
999
; Power-up Timer Enable bit:
1000
; PWRT = ON PWRT enabled
1001
; PWRT = OFF PWRT disabled
1003
; Brown-out Reset Enable bits:
1004
; BOREN = OFF Brown-out Reset disabled in hardware and software
1005
; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
1006
; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
1007
; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
1009
; Brown-out Voltage bits:
1010
; BORV = 0 Maximum setting
1013
; BORV = 3 Minimum setting
1015
; Watchdog Timer Enable bit:
1016
; WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
1017
; WDT = ON WDT enabled
1019
; Watchdog Timer Postscale Select bits:
1001
1020
; WDTPS = 1 1:1
1002
1021
; WDTPS = 2 1:2
1003
1022
; WDTPS = 4 1:4
1015
1034
; WDTPS = 16384 1:16384
1016
1035
; WDTPS = 32768 1:32768
1019
; MCLRE = OFF Disabled
1020
; MCLRE = ON Enabled
1022
; T1 Oscillator Enable:
1023
; LPT1OSC = OFF Disabled
1024
; LPT1OSC = ON Enabled
1026
; Port B A/D Enable:
1027
; PBADEN = OFF Port B<4:0> digital on RESET
1028
; PBADEN = ON Port B<4:0> analog on RESET
1031
; CCP2MX = PORTBE Muxed with RB3
1032
; CCP2MX = PORTC Muxed with RC1
1034
; Stack Overflow Reset:
1035
; STVREN = OFF Disabled
1036
; STVREN = ON Enabled
1039
; LVP = OFF Disabled
1043
; XINST = OFF Disabled
1044
; XINST = ON Enabled
1046
; Background Debugger Enable:
1047
; DEBUG = ON Enabled
1048
; DEBUG = OFF Disabled
1050
; Code Protection Block 0:
1052
; CP0 = OFF Disabled
1054
; Code Protection Block 1:
1056
; CP1 = OFF Disabled
1058
; Code Protection Block 2:
1060
; CP2 = OFF Disabled
1062
; Code Protection Block 3:
1064
; CP3 = OFF Disabled
1066
; Boot Block Code Protection:
1068
; CPB = OFF Disabled
1070
; Write Protection Block 0:
1072
; WRT0 = OFF Disabled
1074
; Write Protection Block 1:
1076
; WRT1 = OFF Disabled
1078
; Write Protection Block 2:
1080
; WRT2 = OFF Disabled
1082
; Write Protection Block 3:
1084
; WRT3 = OFF Disabled
1086
; Boot Block Write Protection:
1088
; WRTB = OFF Disabled
1090
; Configuration Register Write Protection:
1092
; WRTC = OFF Disabled
1094
; Table Read Protection Block 0:
1095
; EBTR0 = ON Enabled
1096
; EBTR0 = OFF Disabled
1098
; Table Read Protection Block 1:
1099
; EBTR1 = ON Enabled
1100
; EBTR1 = OFF Disabled
1102
; Table Read Protection Block 2:
1103
; EBTR2 = ON Enabled
1104
; EBTR2 = OFF Disabled
1106
; Table Read Protection Block 3:
1107
; EBTR3 = ON Enabled
1108
; EBTR3 = OFF Disabled
1110
; Boot Block Table Read Protection:
1111
; EBTRB = ON Enabled
1112
; EBTRB = OFF Disabled
1037
; MCLR Pin Enable bit:
1038
; MCLRE = OFF MCLR pin enabled; RE3 input pin disabled
1039
; MCLRE = ON RE3 input pin enabled; MCLR disabled
1041
; Low-Power Timer1 Oscillator Enable bit:
1042
; LPT1OSC = OFF Timer1 configured for higher power operation
1043
; LPT1OSC = ON Timer1 configured for low-power operation
1045
; PORTB A/D Enable bit:
1046
; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
1047
; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
1050
; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3
1051
; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
1053
; Stack Full/Underflow Reset Enable bit:
1054
; STVREN = OFF Stack full/underflow will not cause Reset
1055
; STVREN = ON Stack full/underflow will cause Reset
1057
; Single-Supply ICSP Enable bit:
1058
; LVP = OFF Single-Supply ICSP disabled
1059
; LVP = ON Single-Supply ICSP enabled
1061
; Extended Instruction Set Enable bit:
1062
; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
1063
; XINST = ON Instruction set extension and Indexed Addressing mode enabled
1065
; Background Debugger Enable bit:
1066
; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
1067
; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
1069
; Code Protection bit Block 0:
1070
; CP0 = ON Block 0 (000800-001FFFh) code-protected
1071
; CP0 = OFF Block 0 (000800-001FFFh) not code-protected
1073
; Code Protection bit Block 1:
1074
; CP1 = ON Block 1 (002000-003FFFh) code-protected
1075
; CP1 = OFF Block 1 (002000-003FFFh) not code-protected
1077
; Code Protection bit Block 2:
1078
; CP2 = ON Block 2 (004000-005FFFh) code-protected
1079
; CP2 = OFF Block 2 (004000-005FFFh) not code-protected
1081
; Code Protection bit Block 3:
1082
; CP3 = ON Block 3 (006000-007FFFh) code-protected
1083
; CP3 = OFF Block 3 (006000-007FFFh) not code-protected
1085
; Boot Block Code Protection bit:
1086
; CPB = ON Boot block (000000-0007FFh) code-protected
1087
; CPB = OFF Boot block (000000-0007FFh) not code-protected
1089
; Write Protection bit Block 0:
1090
; WRT0 = ON Block 0 (000800-001FFFh) write-protected
1091
; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
1093
; Write Protection bit Block 1:
1094
; WRT1 = ON Block 1 (002000-003FFFh) write-protected
1095
; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
1097
; Write Protection bit Block 2:
1098
; WRT2 = ON Block 2 (004000-005FFFh) write-protected
1099
; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected
1101
; Write Protection bit Block 3:
1102
; WRT3 = ON Block 3 (006000-007FFFh) write-protected
1103
; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected
1105
; Boot Block Write Protection bit:
1106
; WRTB = ON Boot block (000000-0007FFh) write-protected
1107
; WRTB = OFF Boot block (000000-0007FFh) not write-protected
1109
; Configuration Register Write Protection bit:
1110
; WRTC = ON Configuration registers (300000-3000FFh) write-protected
1111
; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
1113
; Table Read Protection bit Block 0:
1114
; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
1115
; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
1117
; Table Read Protection bit Block 1:
1118
; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
1119
; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
1121
; Table Read Protection bit Block 2:
1122
; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks
1123
; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
1125
; Table Read Protection bit Block 3:
1126
; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks
1127
; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
1129
; Boot Block Table Read Protection bit:
1130
; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
1131
; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
1114
1133
;==========================================================================
1115
1134
;==========================================================================
1146
1165
_CONFIG7H EQU H'30000D'
1148
1167
;----- CONFIG1H Options --------------------------------------------------
1149
_OSC_LP_1H EQU H'F0' ; LP
1150
_OSC_XT_1H EQU H'F1' ; XT
1151
_OSC_HS_1H EQU H'F2' ; HS
1152
_OSC_RC_1H EQU H'F3' ; RC
1153
_OSC_EC_1H EQU H'F4' ; EC-OSC2 as Clock Out
1154
_OSC_ECIO6_1H EQU H'F5' ; EC-OSC2 as RA6
1155
_OSC_HSPLL_1H EQU H'F6' ; HS-PLL Enabled
1156
_OSC_RCIO6_1H EQU H'F7' ; RC-OSC2 as RA6
1157
_OSC_INTIO67_1H EQU H'F8' ; INTRC-OSC2 as RA6, OSC1 as RA7
1158
_OSC_INTIO7_1H EQU H'F9' ; INTRC-OSC2 as Clock Out, OSC1 as RA7
1160
_FCMEN_OFF_1H EQU H'BF' ; Disabled
1161
_FCMEN_ON_1H EQU H'FF' ; Enabled
1163
_IESO_OFF_1H EQU H'7F' ; Disabled
1164
_IESO_ON_1H EQU H'FF' ; Enabled
1168
_OSC_LP_1H EQU H'F0' ; LP oscillator
1169
_OSC_XT_1H EQU H'F1' ; XT oscillator
1170
_OSC_HS_1H EQU H'F2' ; HS oscillator
1171
_OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6
1172
_OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6
1173
_OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6
1174
_OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
1175
_OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6
1176
_OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7
1177
_OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7
1179
_FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled
1180
_FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled
1182
_IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled
1183
_IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled
1166
1185
;----- CONFIG2L Options --------------------------------------------------
1167
_PWRT_ON_2L EQU H'FE' ; Enabled
1168
_PWRT_OFF_2L EQU H'FF' ; Disabled
1170
_BOREN_OFF_2L EQU H'F9' ; Disabled
1171
_BOREN_ON_2L EQU H'FB' ; SBOREN Enabled
1172
_BOREN_NOSLP_2L EQU H'FD' ; Enabled except SLEEP, SBOREN Disabled
1173
_BOREN_SBORDIS_2L EQU H'FF' ; Enabled, SBOREN Disabled
1175
_BORV_46_2L EQU H'E7' ; 4.6V
1176
_BORV_43_2L EQU H'EF' ; 4.3V
1177
_BORV_28_2L EQU H'F7' ; 2.8V
1178
_BORV_21_2L EQU H'FF' ; 2.1V
1186
_PWRT_ON_2L EQU H'FE' ; PWRT enabled
1187
_PWRT_OFF_2L EQU H'FF' ; PWRT disabled
1189
_BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software
1190
_BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
1191
_BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
1192
_BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
1194
_BORV_0_2L EQU H'E7' ; Maximum setting
1195
_BORV_1_2L EQU H'EF' ;
1196
_BORV_2_2L EQU H'F7' ;
1197
_BORV_3_2L EQU H'FF' ; Minimum setting
1180
1199
;----- CONFIG2H Options --------------------------------------------------
1181
_WDT_OFF_2H EQU H'FE' ; Disabled
1182
_WDT_ON_2H EQU H'FF' ; Enabled
1200
_WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit)
1201
_WDT_ON_2H EQU H'FF' ; WDT enabled
1184
1203
_WDTPS_1_2H EQU H'E1' ; 1:1
1185
1204
_WDTPS_2_2H EQU H'E3' ; 1:2
1199
1218
_WDTPS_32768_2H EQU H'FF' ; 1:32768
1201
1220
;----- CONFIG3H Options --------------------------------------------------
1202
_MCLRE_OFF_3H EQU H'7F' ; Disabled
1203
_MCLRE_ON_3H EQU H'FF' ; Enabled
1205
_LPT1OSC_OFF_3H EQU H'FB' ; Disabled
1206
_LPT1OSC_ON_3H EQU H'FF' ; Enabled
1208
_PBADEN_OFF_3H EQU H'FD' ; Port B<4:0> digital on RESET
1209
_PBADEN_ON_3H EQU H'FF' ; Port B<4:0> analog on RESET
1211
_CCP2MX_PORTBE_3H EQU H'FE' ; Muxed with RB3
1212
_CCP2MX_PORTC_3H EQU H'FF' ; Muxed with RC1
1221
_MCLRE_OFF_3H EQU H'7F' ; MCLR pin enabled; RE3 input pin disabled
1222
_MCLRE_ON_3H EQU H'FF' ; RE3 input pin enabled; MCLR disabled
1224
_LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation
1225
_LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation
1227
_PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset
1228
_PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset
1230
_CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3
1231
_CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1
1214
1233
;----- CONFIG4L Options --------------------------------------------------
1215
_STVREN_OFF_4L EQU H'FE' ; Disabled
1216
_STVREN_ON_4L EQU H'FF' ; Enabled
1218
_LVP_OFF_4L EQU H'FB' ; Disabled
1219
_LVP_ON_4L EQU H'FF' ; Enabled
1221
_XINST_OFF_4L EQU H'BF' ; Disabled
1222
_XINST_ON_4L EQU H'FF' ; Enabled
1224
_DEBUG_ON_4L EQU H'7F' ; Enabled
1225
_DEBUG_OFF_4L EQU H'FF' ; Disabled
1234
_STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset
1235
_STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset
1237
_LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled
1238
_LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled
1240
_XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
1241
_XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled
1243
_DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
1244
_DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
1227
1246
;----- CONFIG5L Options --------------------------------------------------
1228
_CP0_ON_5L EQU H'FE' ; Enabled
1229
_CP0_OFF_5L EQU H'FF' ; Disabled
1231
_CP1_ON_5L EQU H'FD' ; Enabled
1232
_CP1_OFF_5L EQU H'FF' ; Disabled
1234
_CP2_ON_5L EQU H'FB' ; Enabled
1235
_CP2_OFF_5L EQU H'FF' ; Disabled
1237
_CP3_ON_5L EQU H'F7' ; Enabled
1238
_CP3_OFF_5L EQU H'FF' ; Disabled
1247
_CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected
1248
_CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected
1250
_CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected
1251
_CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected
1253
_CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected
1254
_CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected
1256
_CP3_ON_5L EQU H'F7' ; Block 3 (006000-007FFFh) code-protected
1257
_CP3_OFF_5L EQU H'FF' ; Block 3 (006000-007FFFh) not code-protected
1240
1259
;----- CONFIG5H Options --------------------------------------------------
1241
_CPB_ON_5H EQU H'BF' ; Enabled
1242
_CPB_OFF_5H EQU H'FF' ; Disabled
1260
_CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected
1261
_CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected
1244
1263
;----- CONFIG6L Options --------------------------------------------------
1245
_WRT0_ON_6L EQU H'FE' ; Enabled
1246
_WRT0_OFF_6L EQU H'FF' ; Disabled
1248
_WRT1_ON_6L EQU H'FD' ; Enabled
1249
_WRT1_OFF_6L EQU H'FF' ; Disabled
1251
_WRT2_ON_6L EQU H'FB' ; Enabled
1252
_WRT2_OFF_6L EQU H'FF' ; Disabled
1254
_WRT3_ON_6L EQU H'F7' ; Enabled
1255
_WRT3_OFF_6L EQU H'FF' ; Disabled
1264
_WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected
1265
_WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected
1267
_WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected
1268
_WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected
1270
_WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected
1271
_WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected
1273
_WRT3_ON_6L EQU H'F7' ; Block 3 (006000-007FFFh) write-protected
1274
_WRT3_OFF_6L EQU H'FF' ; Block 3 (006000-007FFFh) not write-protected
1257
1276
;----- CONFIG6H Options --------------------------------------------------
1258
_WRTB_ON_6H EQU H'BF' ; Enabled
1259
_WRTB_OFF_6H EQU H'FF' ; Disabled
1277
_WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected
1278
_WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected
1261
_WRTC_ON_6H EQU H'DF' ; Enabled
1262
_WRTC_OFF_6H EQU H'FF' ; Disabled
1280
_WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected
1281
_WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected
1264
1283
;----- CONFIG7L Options --------------------------------------------------
1265
_EBTR0_ON_7L EQU H'FE' ; Enabled
1266
_EBTR0_OFF_7L EQU H'FF' ; Disabled
1268
_EBTR1_ON_7L EQU H'FD' ; Enabled
1269
_EBTR1_OFF_7L EQU H'FF' ; Disabled
1271
_EBTR2_ON_7L EQU H'FB' ; Enabled
1272
_EBTR2_OFF_7L EQU H'FF' ; Disabled
1274
_EBTR3_ON_7L EQU H'F7' ; Enabled
1275
_EBTR3_OFF_7L EQU H'FF' ; Disabled
1284
_EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks
1285
_EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
1287
_EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks
1288
_EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
1290
_EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks
1291
_EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
1293
_EBTR3_ON_7L EQU H'F7' ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks
1294
_EBTR3_OFF_7L EQU H'FF' ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
1277
1296
;----- CONFIG7H Options --------------------------------------------------
1278
_EBTRB_ON_7H EQU H'BF' ; Enabled
1279
_EBTRB_OFF_7H EQU H'FF' ; Disabled
1297
_EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks
1298
_EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks
1282
1301
_DEVID1 EQU H'3FFFFE'
added
removed
header/p18f4510.inc
